MEMORY CELL CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF

Abstract

Memory cell (100C) comprising: a first pull-up transistor (PU0) having a first active region (302a) extending in a first direction (X) and arranged on a first plane; a first pass-gate transistor (PG2) having a second active region (301a) extending in the first direction (X), the second active region being disposed on the first plane and being spaced from the first active region (302a) in a second direction (Y) different from the first direction, and the second active region being adjacent to the first active region (302a); a second pull-up transistor (PU1); a second pass-gate transistor (PG3) coupled to the second pull-up transistor (PU1); and a first metal contact (310e) extending in the second direction (Y) and extending from the first active region (302a) to the second active region (301a), the first metal contact being arranged on a second level different from the first level, the first metal contact electrically connecting a drain (303a2) of the first pull-up transistor (PU0) to a drain (305a2) of the first pass-gate transistor (PG2); wherein the first pass-gate transistor (PG2), the second pass-gate transistor (PG3), the first pull-up transistor (PU0) and the second pull-up transistor (PU1) are part of a four-transistor (4T) memory cell; and wherein the memory cell (100C) further comprises: a group of gates (304a, 304b) comprising a first gate (304a) and a second gate (304b); wherein the first gate (304a) extends in the second direction (Y), overlaps the first active region (302a) or the second active region (301a) and is arranged on the second level.

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has manufactured a variety of digital devices to solve problems in a number of different areas. Some of these digital devices, such as memory macros, are configured to store data. As ICs have become smaller and more complex, the resistance of the conductive lines within these digital devices has also changed, affecting the operating voltages of these digital devices and overall IC performance.

[0002] US 2005 / 0 063 238 A1 describes a layout for a 4-transistor memory cell, wherein the memory cell comprises a first and a second access PMOS transistor and a first and a second driver NMOS transistor. The four transistors are arranged rectangularly relative to one another, wherein the active regions of the four transistors extend in a first direction, and the two access PMOS transistors and the two driver NMOS transistors are each arranged in the first direction relative to one another. A drain of the first access PMOS transistor is connected to a drain of the first driver NMOS transistor.

[0003] DE 103 16 567 A1 describes an SRAM comprising first and second access PMOS transistors and first and second driver NMOS transistors. Active regions extend in a first direction, polysilicon wirings for forming gates of each of the MOS transistors extend orthogonally to the first direction, and drains of the first and second access PMOS transistors are connected to drains of the first and second driver NMOS transistors, respectively, using first metal wirings without interposing the polysilicon wirings forming the gates of the first and second driver NMOS transistors. BRIEF DESCRIPTION OF THE CHARACTERS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various elements are not shown to scale. Indeed, the dimensions of the various elements may be arbitrarily enlarged or reduced for clarity of discussion. Fig. 1A is a circuit diagram of a memory macro according to some embodiments. Fig. 1B is a circuit diagram of a memory cell according to some embodiments. Fig. 1C is a circuit diagram of a memory cell according to some embodiments. The Fig. 2A, Fig. 2B and Fig. 2C are diagrams of a layout design according to some embodiments. The Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 3G, Fig. 3H and Fig. 3I are diagrams of at least one integrated circuit according to some embodiments. The Fig. 4A and Fig. 4B are diagrams of a layout design in accordance with some embodiments. Fig. 5 is a diagram of an integrated circuit according to some embodiments. Fig. 6A is a flowchart of a method of manufacturing an integrated circuit according to some embodiments. Fig. 6B is a flowchart of a method for generating a layout design of a memory array circuit according to some embodiments. Fig. 7 is a block diagram of a system for designing a layout for integrated circuits in accordance with some embodiments. Fig. 8 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow coupled thereto, according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure contains various embodiments or examples of implementing elements of the described subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations.

[0006] In addition, spatially related terms such as "bottom," "down," "down," "down," "down," "up," "up," "up," and the like may be used herein for convenience to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0007] According to some embodiments, a memory cell includes first and second pull-up transistors, first and second pass-gate transistors, and a first metal contact. In some embodiments, the first pass-gate transistor, the second pass-gate transistor, the first pull-up transistor, and the second pull-up transistor are part of a four-transistor (4T) memory cell. In some embodiments, the second pass-gate transistor is coupled to the second pull-up transistor.

[0008] In some embodiments, the first pull-up transistor has a first active region extending in a first direction and disposed on a first level. In some embodiments, the first pass-gate transistor has a second active region extending in the first direction. In some embodiments, the second active region is disposed on the first level and is spaced from the first active region in a second direction different from the first direction. In some embodiments, the second active region is adjacent to the first active region.

[0009] In some embodiments, the first metal contact extends in the second direction from the first active region to the second active region. In some embodiments, the first metal contact is arranged on a second level that is different from the first level. In some embodiments, the first metal contact electrically couples a drain of the first pull-up transistor to a drain of the first pass-gate transistor. MEMORY MACRO

[0010] Fig. 1A is a circuit diagram of a memory macro 100A, according to some embodiments. In the embodiment of Fig. 1, memory macro 100A is a static random access memory (SRAM) macro. SRAM is used for illustration, and other types of memory are within the scope of various embodiments.

[0011] Memory macro 100A includes an array of cells 102 having M rows and N columns, where N is a positive integer corresponding to the number of columns in the array of cells 102 and M is a positive integer corresponding to the number of rows in the array of cells 102. The rows of cells in the array of cells 102 are arranged in a first direction X. The columns of cells in the array of cells 102 are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction extends perpendicular to the first direction. In some embodiments, the array of cells 102 includes one or more single-port (SP) SRAM cells. In some embodiments, the array of cells 102 includes one or more dual-port (DP) SRAM cells.Various types of memory cells in an array of cells 102 are within the intended scope of the present disclosure.

[0012] The memory macro 100A further includes N bitlines BL[1], .... BL[N] (collectively referred to as "bitline BL") and N bitline bars BLB[1], .... BLB[N] (collectively referred to as "bitline bar BLB"). Each column 1, ...., N in the array of cells 102 is overlapped by a corresponding bitline BL[1], ...., BL[N] and a corresponding bitline bar BLB[1], ...., BLB[N]. Each bitline BL or bitline bar BLB extends in the second direction Y and across a cell column (e.g., column 1, ...., N).

[0013] The memory macro 100A further includes M word lines WL[1], ...., WL[M] (collectively referred to as "word line WL"). Each row 1, ...., M in the array of cells 102 is overlapped by a corresponding word line WL[1], ...., WL[M]. Each word line WL extends in the first direction X and across a corresponding cell row (e.g., row 1, ...., M).

[0014] Various configurations of memory macro 100A are within the intended scope of the present disclosure. A MEMORY CELL

[0015] Fig. 1B is a circuit diagram of a memory cell 100B used in Fig. 1A is usable according to some embodiments.

[0016] The memory cell 100B is configured as one or more memory cells in the memory macro 100A of Fig. 1A usable.

[0017] Memory cell 100B is a four-transistor (4T) single-port (SP) SRAM memory cell used for illustration purposes. In some embodiments, memory cell 100B includes a number of transistors other than four. Other types of memory are possible within various embodiments.

[0018] The memory cell 100B includes two P-type metal-oxide-semiconductor (PMOS) transistors PG0 and PG1 and two N-type metal-oxide-semiconductor (NMOS) transistors PD0 and PD1. The PMOS transistors PG0 and PG1 are configured as pass-gate transistors, and the NMOS transistors PD0 and PD1 are configured as pull-down transistors.

[0019] A drain terminal of NMOS transistor PD0, a gate terminal of NMOS transistor PD1, and a source terminal of PMOS transistor PG0 are coupled together at a node configured as storage node ND. A drain terminal of NMOS transistor PD1, a gate terminal of NMOS transistor PD0, and a source terminal of PMOS transistor PG1 are coupled together at a node configured as storage node NDB.

[0020] A source terminal of each of the NMOS transistors PD0 and PD1 is configured as a supply reference voltage node (not shown) with a supply reference voltage VSS. The source terminal of each of the NMOS transistors PD0 and PD1 is also coupled to the supply reference voltage VSS.

[0021] A word line WL is coupled to a gate terminal of each of the PMOS transistors PG0 and PG1. The word line WL is also called a write control line because the PMOS transistors PG0 and PG1 are configured to be controlled by a signal on the word line WL to transfer data between the bit lines BL, BLB and the corresponding nodes ND, NDB.

[0022] A drain terminal of PMOS transistor PG0 is coupled to a bit line BL. A drain terminal of PMOS transistor PG1 is coupled to a bit line BLB. Bit lines BL and BLB are configured as both data inputs and outputs for memory cell 100B. In some embodiments, applying a logical value to a first bit line BL and the opposite logical value to the other bit line BLB in a write operation enables the logical values ​​on the bit lines to be written to memory cell 100B. Each of bit lines BL and BLB is referred to as a data line because the data on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0023] Various configurations of memory cell 100B are within the intended scope of the present disclosure. For example, source or drain terminals of PMOS transistor PG0, PMOS transistor PG1, NMOS transistor PD0, or NMOS transistor PD1 may be exchanged for corresponding drain or source terminals of PMOS transistor PG0, PMOS transistor PG1, NMOS transistor PD0, or NMOS transistor PD1, and vice versa. ANOTHER MEMORY CELL

[0024] Fig. 1C is a circuit diagram of a memory cell 100C used in Fig. 1A is usable according to some embodiments.

[0025] The memory cell 100C is configured as one or more memory cells in the memory macro 100A of Fig. 1A usable.

[0026] Memory cell 100C is a 4T SP SRAM memory cell for illustrative purposes. In some embodiments, memory cell 100C includes a number of transistors other than four. Other types of memory are possible within various embodiments.

[0027] The memory cell 100C comprises two PMOS transistors PU0 and PU1 and two NMOS transistors PG2 and PG3. The NMOS transistors PG2 and PG3 are configured as pass-gate transistors, and the PMOS transistors PU0 and PU1 are configured as pull-up transistors.

[0028] A drain terminal of PMOS transistor PU0, a gate terminal of PMOS transistor PU1, and a source terminal of NMOS transistor PG2 are coupled together at a node configured as storage node ND. A drain terminal of PMOS transistor PU1, a gate terminal of PMOS transistor PU0, and a source terminal of NMOS transistor PG3 are coupled together at a node configured as storage node NDB.

[0029] A source terminal of each of the PMOS transistors PU0 and PU1 is configured as a supply voltage node (not shown) with a supply voltage VDD. The source terminal of each of the PMOS transistors PU0 and PU1 is also coupled to the supply voltage VDD.

[0030] A word line WL is coupled to a gate terminal of each of the NMOS transistors PG2 and PG3. The NMOS transistors PG2 and PG3 are configured to be controlled by a signal on the word line WL to transfer data between the bit lines BL, BLB and the corresponding nodes ND, NDB.

[0031] A drain terminal of NMOS transistor PG2 is coupled to a bit line BL. A drain terminal of NMOS transistor PG3 is coupled to a bit line BLB. Bit lines BL and BLB are configured as both data inputs and outputs for memory cell 100C. In some embodiments, applying a logical value to one bit line BL and the opposite logical value to the other bit line BLB in a write operation enables the logical values ​​on the bit lines to be written to memory cell 100C. Each of bit lines BL and BLB is referred to as a data line because the data on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0032] Various configurations of memory cell 100C are within the intended scope of the present disclosure. For example, the source or drain terminals of NMOS transistor PG2, NMOS transistor PG3, PMOS transistor PU0, or PMOS transistor PU1 may be exchanged for corresponding drain or source terminals of NMOS transistor PG2, NMOS transistor PG3, PMOS transistor PU0, or PMOS transistor PU1, and vice versa. LAYOUT DESIGN

[0033] Fig. 2A-2C are diagrams of a layout design 200, in accordance with some embodiments. The layout design 200 is a layout diagram of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C. The layout design 200 can be used to fabricate the memory cell 100B or 100C.

[0034] The layout design 200 includes a section 200A ( Fig. 2A) and a section 200B ( Fig. 2B). For better illustration, the layout design contains 200 of Fig. 2A does not include section 200B. Likewise, the layout design 200 of Fig. 2B does not include section 200A for clarity.

[0035] The layout design 200, as in Fig. 2C, includes section 200A of Fig. 2A and section 200B of Fig. 2B. In other words, the layout design of Fig. 2C is the combination of layout section 200A of Fig. 2A and layout section 200B of Fig. 2B, when the cell borders of Section 200A and Section 200B are aligned. For clarity, some of the labeled elements of the Fig. 2A-2B in Fig. 2C. In some embodiments, the layout design 200 of the Fig. 2A-2C additional elements included in the Fig. 2A-2C are not shown.

[0036] The layout design 200 of Fig. 2A includes section 200A. Section 200A includes elements of the active (OD) level, the poly (Poly) level, the metal-on-diffusion (MD) level, the via-on-diffusion (VD) level, and the via-on-gate (VG) level of the layout design 200.

[0037] The layout design 200 of Fig. 2B includes section 200B. Section 200B includes elements of the metal 1 (M1) level, the metal 2 (M2) level, the via 0 (V0) level, and the via 1 (V1) level of the layout design 200.

[0038] The layout design 200 includes the active area layout designs 202a and 202b (collectively referred to as the “group of active area layout designs 202”).

[0039] The active area layout design 202a can be used to manufacture the active area 303a1, 303a2, 303b1 and 303b2 of the integrated circuit 300 ( Fig. 3A-3I). The active area layout design 202b can be used to fabricate active areas 305a1, 305a2, 305b1, and 305b2 of the integrated circuit 300 ( Fig. 3A-3I).

[0040] The active area layout design 202a includes an active area layout design 202a1 and an active area layout design 202a2. In some embodiments, the active area layout design 202a1 is usable to fabricate the active areas 303a1 and 303a2 of the integrated circuit 300 ( Fig. 3A-3I). In some embodiments, the active area layout design 202a2 of the active area may be used to fabricate the active areas 303b1 and 303b2 of the integrated circuit 300 ( Fig. 3A-31).

[0041] The active area layout design 202b includes an active area layout design 202b1 and an active area layout design 202b2. In some embodiments, the active area layout design 202b1 is usable to fabricate the active areas 305a1 and 305a2 of the integrated circuit 300 ( Fig. 3A-3I). In some embodiments, the active area layout design 202a2 is usable to fabricate the active areas 305b1 and 305b2 of the integrated circuit 300 ( Fig. 3A-3I).

[0042] Each of the layout designs of the group of active area layout designs 202a extends in a first direction X and is arranged on a first layout level. In some embodiments, the first layout level corresponds to the active area of ​​the layout design 200 or 400 ( Fig. 4). The layout designs 202a and 202b of the group of active area layout designs 202 are spaced apart from each other in a second direction Y. In some embodiments, the second direction Y differs from the first direction X. In some embodiments, the group of active area layout designs 202 is referred to as an oxide definition (OD) layout design, which defines source or drain diffusion layout designs of the layout design 200 or 400. In some embodiments, the group of active area layout designs 202 extends continuously through the cell edges of the layout design 200 to other adjacent cells.

[0043] The layout design 200 further includes the gate layout designs 204a, 204b and 204c (collectively referred to as “group of gate layout designs 204”). In some embodiments, the gate layout designs 204a and 204b are usable to form corresponding gate structures 304a and 304b of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5). The gate layout design 204c is located between 204a and 204b. In some embodiments, the gate layout design 204c is usable to form a dummy gate structure (not shown) of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5). In some embodiments, a dummy gate structure is a non-functional gate structure. At least the group of gate layout designs 204 of the layout design 200 or 400 ( Fig. 4A-4B) or the group of gates 304 of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) have a contact poly pitch (CPP) of 3, wherein in some embodiments, a width of the cell boundary of the layout design 200 in the first direction X is equal to the CPP (e.g., 3). In some embodiments, the layout design 200 or 400 ( Fig. 4A-4B) or the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) has a higher density than other solutions due to a CPP of 3.

[0044] In some embodiments, the gate layout design 204a can be used to form gate regions of the PMOS transistor PG0 and the NMOS transistor PD0, or gate regions of the PMOS transistor PU0 and the NMOS transistor PG2. In some embodiments, the gate layout design 204b can be used to form gate regions of the PMOS transistor PG1 and the NMOS transistor PD1, or gate regions of the PMOS transistor PU1 and the NMOS transistor PG3.

[0045] In some embodiments, each gate layout design of the group of gate layout designs 204 extends in the second direction Y and overlaps the group of active area layout designs 202. In some embodiments, each gate layout design of the group of gate layout designs 204 is spaced in the first direction X from an adjacent gate layout design of the group of gate layout designs 204. In some embodiments, an adjacent element is adjacent to or directly adjacent to another element. For example, in some embodiments, gate layout design 204a is adjacent to gate layout design 204c. In some embodiments, active area layout design 202a is adjacent to active area layout design 202b.

[0046] The group of gate layout designs 204 is arranged in a second layout level that is different from the first layout level. In some embodiments, the second layout level corresponds to the POLY level of the layout design 200 or 400 ( Fig. 4). The group of active area layout designs 202 is below the group of gate layout designs 204. Other quantities or configurations of the group of gate layout designs 204 are within the scope of the present disclosure.

[0047] The layout design 200 further includes a continuous polysilicon on oxide diffusion edge (OD) (CPODE) layout design 206. The CPODE layout design 206 extends in the second direction Y and covers the gate layout design 204c. In some embodiments, the CPODE layout design 206 is usable to indicate that a dummy gate structure (gate structure 304c, fabricated by the gate layout design 204c) of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) is removed, and a trench is formed and connected to an insulating section 330 in the first trough 301 ( Fig. 3A-3I) and the second trough 302 ( Fig. 3A-3I). In some embodiments, a dummy gate structure is a non-functional gate structure. In some embodiments, the gate layout design 204c is the CPODE layout design 206. In some embodiments, the CPODE layout design 206 is used to indicate that the gate layout design 204c is a dummy gate layout design. Other configurations or sets of patterns in the CPODE layout design 206 are within the scope of the present disclosure.

[0048] The layout design 200 further includes the poly-cut element layout design 208a and 208b (collectively referred to as “group of cut element layout designs 208”). The group of poly-cut element layout designs 208 extends in the first direction X. The poly-cut element layout design 208b overlaps the group of gate layout designs 204 in a central portion of the layout design 200. The poly-cut element layout design 208a overlaps the group of gate layout designs 204 along the cell edge 250 of the layout design 200. In some embodiments, each poly-cut element layout design (208a or 208b) of the group of poly-cut element layout designs 208 is separated in the second direction Y from another Poly-cut element layout design (208b or 208a) of the group of poly-cut element layout designs 208.In some embodiments, the group of poly-cut element layout designs 208 extends continuously through the cell edges of the layout design 200 to other adjacent cells.

[0049] The group of poly-cut element layout designs 208 has a pattern width W1V (no reference number) in the second direction Y and a pattern length L (no reference number) in the first direction X. In some embodiments, the poly-cut element layout designs 208a and 208b are usable to define a corresponding position of a portion of the corresponding gate structure 304a and 304b of the integrated circuit 300 or 500 ( Fig. 5) identified during process 604 of method 600A ( Fig. 6A) is removed.

[0050] In some embodiments, the pattern width W1V (without reference number) corresponds to the cutting width DV(no reference number) of one or more of the gate structures 304a1, 304a2, 304b1, and 304b2. In some embodiments, the pattern length L (no reference number) corresponds to the cut length LV (not shown) of one or more of the gate structures 304a1, 304a2, 304b1, and 304b2. In some embodiments, at least one of the gate layout design 204, the CPODE layout design 206, and / or the poly-cut element layout design 210 is arranged in a poly gate layout plane (POLY). Other configurations or sets of patterns in the poly-cut function layout design 210 are within the scope of the present disclosure.

[0051] The layout design 200 further comprises conductive structure layout designs 210a, 210b, 210c, 210e and 210f (collectively referred to as “group of conductive structure layout designs 210”). In some embodiments, the conductive structure layout designs 210a, 210b, 210c, 210d, 210e and 210f are for the fabrication of corresponding conductive structures 310a, 310b, 310c, 310d, 310e and 310f of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) can be used.

[0052] In some embodiments, the group of conductive structure layout designs 210 extends in the second direction Y and is arranged above the group of active area layout designs 202. The conductive structure layout designs 210a and 210b overlap the active area layout design 202a. In some embodiments, the conductive structure layout designs 210a and 210b overlap the cell edge 250. The conductive structure layout designs 210c and 210d overlap the active area layout design 202b. In some embodiments, at least the conductive structure layout design 210e or 210f overlaps the active area layout design 202a. In some embodiments, at least the conductive structure layout design 210e or 210f overlaps the active area layout design 202b.

[0053] In some embodiments, at least the conductive structure layout design 210e or 210f extends from the active area layout design 202a to the active area layout design 202b. In some embodiments, at least one side of the conductive structure layout design 210e or 210f directly contacts or touches one side of the active area layout design 202b. In some embodiments, at least the conductive structure layout design 210e or 210f extends from the active area layout design 202a to one side of the active area layout design 202b.

[0054] In some embodiments, each conductive structure layout design of the group of conductive structure layout designs 210 is spaced apart in at least the first direction X or the second direction Y from an adjacent layout design of the group of conductive structure layout designs 210. The group of conductive structure layout designs 210 is arranged in a third layout level that is different from the first layout level and the second layout level. In some embodiments, the third layout level corresponds to the metal-over-diffusion (MD) level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of conductive structure layout designs 210 are within the scope of the present disclosure.

[0055] The layout design 200 further comprises the conductive structure layout designs 212a, 212b, 212c, 212d, 212e and 212f (collectively referred to as “group of conductive structure layout designs 212”). In some embodiments, the conductive structure layout designs 212a, 212b, 212c, 212d, 212e and 212f are for the fabrication of corresponding conductive structures 312a, 312b, 312c, 312d, 312e and 312f of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) can be used.

[0056] In some embodiments, the group of conductive structure layout designs 212 extends in the first direction X and is arranged at least above the group of active area layout designs 210 or the group of gate layout designs 204.

[0057] The conductive structure layout design 212a overlaps the conductive structure layout designs 210a and 210b, the poly-cut element layout design 208a, and the CPODE layout design 206. Each of the conductive structure layout designs 212b and 212c overlaps the conductive structure layout designs 210e and 210f and the CPODE layout design 206. The conductive structure layout designs 212d and 212e overlap the corresponding conductive structure layout designs 210c and 210d. The conductive structure layout design 212b overlaps the conductive structure layout designs 210a and 210b, the poly-cut element layout design 208a, and the CPODE layout design 206.

[0058] The conductive structure layout design 212a overlaps the gate layout designs 204a, 204b, and 204c. The conductive structure layout design 212b overlaps the gate layout designs 204a and 204c. The conductive structure layout design 212c overlaps the gate layout designs 204b and 204c. The conductive structure layout designs 212d and 212e overlap the corresponding gate layout designs 204a and 204b. The conductive structure layout design 212f overlaps the gate layout designs 204a, 204b, and 204c and the CPODE layout design 206.

[0059] In some embodiments, each conductive structure layout design of the group of conductive structure layout designs 212 is spaced in the first direction X and / or the second direction Y from an adjacent layout design of the group of conductive structure layout designs 212. The group of conductive structure layout designs 212 is arranged on a fourth layout level that is different from the first layout level, the second layout level, and the third layout level. In some embodiments, the fourth layout level corresponds to the metal zero (M0) level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of conductive structure layout designs 212 are within the scope of the present disclosure.

[0060] The layout design 200 further includes the via layout designs 214a, 214b, 214c, 214d, 214e, 214f, 214g, and 214h (collectively referred to as “group of via layout designs 214”). In some embodiments, the layout designs 214a, 214b, 214c, 214d, 214e, 214f, 214g, and 214h are usable to form corresponding vias 314a, 314b, 314c, 314d, 314e, 314f, 314g, and 314h of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) to produce.

[0061] In some embodiments, the via layout designs 214c and 214i of the via layout design 214 are arranged where the corresponding conductive structure layout designs 212b and 212f of the group of conductive structure layout designs 212 overlap the gate layout design 204a of the group of gate layout designs 204.

[0062] In some embodiments, the layout designs 214f ​​and 214j of the group of via layout designs 214 are arranged where the corresponding conductive structure layout designs 212c and 212f of the group of conductive structure layout designs 212 overlap the gate layout design 204b of the group of gate layout designs 204.

[0063] In some embodiments, one or more of the via layout designs 214 are arranged between one or more of the conductive structure layout designs 212 and one or more of the gate layout designs 204.

[0064] In some embodiments, layout designs 214a and 214b of group of via layout designs 214 are arranged where conductive structure layout design 212a of group of conductive structure layout designs 212 overlaps corresponding conductive structure layout designs 210a and 210b of group of conductive structure layout designs 210.

[0065] In some embodiments, the via layout designs 214d and 214e of the group of via layout designs 214 are arranged where the corresponding conductive structure layout designs 212b and 212c of the group of conductive structure layout designs 212 overlap corresponding conductive structure layout designs 210f and 210e of the group of conductive structure layout designs 210.

[0066] In some embodiments, the via layout designs 214g and 214h of the group of via layout designs 214 are arranged where the corresponding conductive structure layout designs 212d and 212e of the group of conductive structure layout designs 212 overlap corresponding conductive structure layout designs 210c and 210d of the group of conductive structure layout designs 210.

[0067] In some embodiments, one or more of the via layout designs 214 are between one or more of the conductive structure layout designs 212 and one or more of the active area layout designs 210.

[0068] In some embodiments, the via layout designs 214c, 214f, 214i, and 214j of the group of via layout designs 214 are at least at the via-over-gate (VG) level of the layout design 200 or 400 ( Fig. 4). In some embodiments, the VG level is located between the fourth layout level and the second layout level of the layout design 200 or 400 ( Fig. 4).

[0069] In some embodiments, the via layout designs 214a, 214b, 214d, 214e, 214g, and 214h of the group of via layout designs 214g and 214h are at least on the via-over-diffusion (VD) level of the layout design 200 or 400 ( Fig. 4). In some embodiments, the VD level is arranged between the fourth layout level and the third layout level of the layout design 200 or 400 ( Fig. 4) arranged.

[0070] Other quantities or configurations of the group of via layout designs 214 are within the scope of the present disclosure.

[0071] The layout design 200 further includes the conductive structure layout designs 218a, 218b, 218c, and 218e (collectively referred to as “group of conductive structure layout designs 218”) as shown in Fig. 2B. In some embodiments, the conductive structure layout designs 218a, 218b, 218c, 218d, and 218e are used for the fabrication of corresponding conductive structures 318a, 318b, 318c, and 318e of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) can be used.

[0072] In some embodiments, the group of conductive structure layout designs 218 extends in the second direction Y and is arranged at least above the group of active area layout designs 210, the group of gate layout designs 204, or the group of conductive structure layout designs 212.

[0073] The conductive structure layout design 218a overlaps the active area layout designs 202a and 202b, the poly-cut element layout design 208b, the conductive structure layout design 212d, and at least a portion of the conductive structure layout designs 210a and 210c.

[0074] The conductive structure layout design 218b overlaps the active area layout designs 202a and 202b, the poly-cut element layout designs 208a and 208b, the conductive structure layout designs 212a, 212b, 212c, 212d and 212f, the gate layout design 204a and at least a portion of the conductive structure layout design 210e.

[0075] The conductive structure layout design 218c overlaps the active area layout designs 202a and 202b, the poly-cut element layout designs 208a and 208b, the CPODE layout design 206, the conductive structure layout designs 212a, 212b, 212c and 212f, and the gate layout design 204b.

[0076] The conductive structure layout design 218d overlaps the active area layout designs 202a and 202b, the poly-cut element layout designs 208a and 208b, the conductive structure layout designs 212a, 212b, 212c, 212e and 212f, the gate layout design 204c and at least a portion of the conductive structure layout design 210f.

[0077] The conductive structure layout design 218e overlaps the active area layout designs 202a and 202b, the poly-cut element layout design 208b, the conductive structure layout design 212e, and at least a portion of the conductive structure layout designs 210b and 210d.

[0078] In some embodiments, each conductive structure layout design of the group of conductive structure layout designs 218 is spaced at least in the first direction X from an adjacent layout design of the group of conductive structure layout designs 218. The group of conductive structure layout designs 218 is arranged in a fifth layout level that is different from the first layout level, the second layout level, the third layout level, and the fourth layout level. In some embodiments, the fifth layout level corresponds to the metal one (M1) level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of conductive structure layout designs 218 are within the scope of the present disclosure.

[0079] The layout design 200 further comprises the via layout designs 220a, 220b, 220c, 220d and 220e (collectively referred to as “group of via layout designs 220”). In some embodiments, the layout designs 220a, 220b, 220c, 220d and 220e are usable to form corresponding vias 320a, 320b, 320c, 320d and 320e of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) to produce.

[0080] In some embodiments, one or more of the via layout designs 220 are arranged between one or more of the conductive structure layout designs 218 and one or more of the conductive structure layout designs 212.

[0081] In some embodiments, the via layout designs 220a and 220e of the group of via layout designs 220 are arranged where the corresponding conductive structure layout designs 218a and 218e of the group of conductive structure layout designs 218 overlap corresponding conductive structure layout designs 212b and 212e of the group of conductive structure layout designs 212.

[0082] In some embodiments, the via layout designs 220b and 220c of the group of via layout designs 220 are arranged where the corresponding conductive structure layout designs 218b and 218d of the group of conductive structure layout designs 218 overlap the conductive structure layout design 212f of the group of conductive structure layout designs 212.

[0083] In some embodiments, the via layout design 220d of the group of via layout designs 220 is arranged where the conductive structure layout design 218c of the group of conductive structure layout designs 218c overlaps the conductive structure layout design 212a of the group of conductive structure layout designs 212.

[0084] In some embodiments, the group of via layout designs 220 is at least in the via zero (V0) level of the layout design 200 or 400 ( Fig. 4). In some embodiments, the V0 level is located between the fourth layout level and the fifth layout level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of via layout designs 220 are within the scope of the present disclosure.

[0085] The layout design 200 further comprises the conductive structure layout designs 222a, 222b, 222c, 222d and 222e (collectively referred to as “group of conductive structure layout designs 222”). In some embodiments, the conductive structure layout designs 222a, 222b, 222c, 222d and 222e are usable to form corresponding conductive structures 322a, 322b, 322c, 322d and 322e of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) to produce.

[0086] In some embodiments, the group of conductive structure layout designs 222 extends in the first direction X and over at least the group of active area layout designs 210, the group of gate layout designs 204, the group of conductive structure layout designs 212, or the group of conductive structure layout designs 218.

[0087] The conductive structure layout design 222a overlaps the poly-cut element layout design 208a, the conductive structure layout design 212a, the conductive structure layout designs 210a and 210b, the gate layout designs 204a, 204b and 204c, the CPODE layout design 206 and the conductive structure layout designs 218b, 218c and 218d.

[0088] The conductive structure layout design 222b overlaps the active area layout design 202a, the conductive structure layout design 212b, the gate layout designs 204a, 204b and 204c, the CPODE layout design 206, the conductive structure layout designs 218a, 218b, 218c, 218d and 218e and at least a portion of the conductive structure layout designs 210a, 210b, 210e and 210f.

[0089] The conductive structure layout design 222c overlaps the conductive structure layout design 212c, the gate layout designs 204a, 204b and 204c, the CPODE layout design 206, the conductive structure layout designs 218a, 218b, 218c, 218d and 218e, and at least a portion of the conductive structure layout designs 210e and 210f.

[0090] The conductive structure layout design 222d overlaps the conductive structure layout designs 212d and 212e, the gate layout designs 204a, 204b, and 204c, the CPODE layout design 206, the conductive structure layout designs 218a, 218b, 218c, and 218e, and at least a portion of the conductive structure layout designs 210c, 210d, 210e, and 210f. In some embodiments, the conductive structure layout design 222d overlaps at least a portion of the active area layout design 202b.

[0091] The conductive structure layout design 222e overlaps the conductive structure layout design 212f, the gate layout designs 204a, 204b and 204c, the CPODE layout design 206 and the conductive structure layout designs 218b, 218c and 218d.

[0092] In some embodiments, each conductive structure layout design of the group of conductive structure layout designs 222 is spaced apart in at least the second direction Y from an adjacent layout design of the group of conductive structure layout designs 222. The group of conductive structure layout designs 222 is arranged in a sixth layout level that is different from the first layout level, the second layout level, the third layout level, the fourth layout level, and the fifth layout level. In some embodiments, the sixth layout level corresponds to the metal two (M2) level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of conductive structure layout designs 222 are within the scope of the present disclosure.

[0093] The layout design 200 further includes the via layout designs 226a, 226b, 226c, and 226e (collectively referred to as “group of via layout designs 226”). In some embodiments, the layout designs 226a, 226b, 226c, 226d, and 226e are usable to form corresponding vias 326a, 326b, 326c, 326d, and 326e of the integrated circuit 300 ( Fig. 3A-3I) and 500 ( Fig. 5) to produce.

[0094] In some embodiments, one or more of the via layout designs 226 are disposed between one or more of the conductive structure layout designs 222 and one or more of the conductive structure layout designs 218.

[0095] In some embodiments, the via layout design 226a of the group of via layout designs 226 is arranged where the corresponding conductive structure layout design 222b of the group of conductive structure layout designs 222b overlaps the conductive structure layout design 218a of the group of conductive structure layout designs 218.

[0096] In some embodiments, the via layout designs 226b, 226c, and 226d of the group of via layout designs 226 are arranged where the corresponding conductive structure layout designs 222e, 222c, and 222a of the group of conductive structure layout designs 222 overlap the conductive structure 218c of the group of conductive structure layout designs 218.

[0097] In some embodiments, the via layout design 226e of the group of via layout designs 226 is arranged where the corresponding conductive structure layout design 222d of the group of conductive structure layout designs 222d overlaps the conductive structure layout design 218e of the group of conductive structure layout designs 218.

[0098] In some embodiments, each center of the via layout designs 220d and 220e is aligned with a corresponding center of the corresponding via layout designs 226d and 226e.

[0099] In some embodiments, at least one center of the via layout designs 220e, 226e, or 214h is aligned with at least one other center of the via layout designs 220e, 226e, or 214h.

[0100] In some embodiments, a center of the group of via layout designs 220a is aligned with a center of the via layout design 214g.

[0101] In some embodiments, the group of via layout designs 226 is in at least one (V1) level of the layout design 200 or 400 ( Fig. 4). In some embodiments, the V1 level is arranged between the fifth layout level and the sixth layout level of the layout design 200 or 400 ( Fig. 4). Other quantities or configurations of the group of via layout designs 226 are within the scope of the present disclosure.

[0102] In some embodiments, the use of conductive structure layout designs 222b and 222d between the conductive structure layout designs 222a, 222c, 222e of layout design 200 results in a layout design 200 or 400 with better electromagnetic shielding compared to other solutions. In some embodiments, providing better electromagnetic shielding results in a layout design 200 or 400 with less crosstalk than other solutions. INTEGRATED CIRCUIT - CROSS-SECTION VIEWS

[0103] The Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 3G, Fig. 3H and Fig. 3I are diagrams of an integrated circuit 300, in accordance with some embodiments.

[0104] Fig. 3A is a cross-sectional view of an integrated circuit 300 according to the layout design 200, cut in plane AA'. Fig. 3B is a cross-sectional view of an integrated circuit 300 according to layout design 200, cut in plane BB'. Fig. 3C is a cross-sectional view of an integrated circuit 300 according to layout design 200, cut in plane CC'. Fig. 3D is a cross-sectional view of an integrated circuit 300 according to the layout design 200, cut in the plane DD'. Fig. 3E is a cross-sectional view of an integrated circuit 300 according to layout design 200, cut in plane EE'. Fig. 3F is a cross-sectional view of an integrated circuit 300 according to layout design 200, cut in plane FF'. Fig. 3G is a cross-sectional view of an integrated circuit 300 according to the layout design 200, cut in the plane GG'. Fig. 3H is a cross-sectional view of an integrated circuit 300 according to layout design 200, cut in plane HH'. Fig. 3I is a cross-sectional view of an integrated circuit 300 according to the layout design 200, cut in plane II'.

[0105] The integrated circuit 300 is manufactured according to the layout design 200. The integrated circuit 300 is a structural implementation of the memory cell 100B or 100C.

[0106] Structural relationships including alignment, lengths and widths, and configurations of the integrated circuit 300 or 500 are similar to the structural relationships and configurations of the layout design 200 of the Fig. 2A-2B and the layout design 400 of the Fig. 4A-4B and are in the Fig. 3A-3I not described.

[0107] The integrated circuit 300 includes a first well 301 and a second well 302. The first well 301 and the second well 302 are arranged at least in the first plane of the integrated circuit 300 and extend at least in the first direction X or the second direction Y. In some embodiments, the first well 301 and the second well 302 are adjacent to each other and spaced apart from each other in the second direction Y.

[0108] The first trough 301 comprises a first section 301a and a second section 301b.

[0109] The second trough 302 comprises a first portion 302a and a second portion 302b.

[0110] The first portion 301a and the second portion 301b of the first well 301 of the integrated circuit 300 comprise dopants of a first type. The first portion 302a and the second portion 302b of the second well 302 of the integrated circuit 300 comprise dopants of a second type that differs from the first type.

[0111] In some embodiments, the first type is an N-type dopant and the second type is a P-type dopant. In some embodiments, the first type is a P-type dopant and the second type is an N-type dopant.

[0112] The first portion 301a and the second portion 301b of the first well 301 of the integrated circuit 300 extend in the first direction X. In some embodiments, the first portion 301a and the second portion 301b are a continuous part of the first well 301. In some embodiments, the first portion 301a and the second portion 301b are separated by an insulating portion 330.

[0113] The first portion 302a and the second portion 302b of the second well 302 of the integrated circuit 300 extend in the first direction X. In some embodiments, the first portion 302a and the second portion 302b are a continuous part of the second well 302. In some embodiments, the first portion 302a and the second portion 302b are separated by the insulating portion 330. In some embodiments, the insulating portion 330 extends in the second direction Y.

[0114] Other quantities or configurations of the first well 301 or the second well 302 are within the scope of the present disclosure.

[0115] The integrated circuit 300 further comprises a group of active regions 303 and a group of active regions 305. The group of active regions 303 and the group of active regions 305 extend in the second direction Y. The group of active regions 303 and the group of active regions 305 are arranged in the first level of the integrated circuit 300.

[0116] The group of active regions 303 includes one or more of the active regions 303a1, 303a2, and 303b2. Each of the active regions 303a1, 303a2, and 303b2 of the group of active regions 303 is separated in the first direction X from an adjacent active region of the group of active regions 303 by a first pitch distance (not specified).

[0117] The active regions 303a1 and 303a2 of the group of active regions 303 are embedded in the first section 301a of the second well 302 of the integrated circuit 300. The active regions 303b1 and 303b2 of the group of active regions 303 are embedded in the second section 301b of the second well 302 of the integrated circuit 300. The active regions 303a1, 303a2, 303b1, and 303b2 comprise dopants of the first type.

[0118] The active region group 305 includes one or more of the active regions 305a1, 305a2, and 305b2. Each of the active regions 305a1, 305a2, and 305b2 of the active region group 305 is separated in the first direction X from an adjacent active region of the active region group 305 by a second pitch distance (not specified).

[0119] The active regions 305a1 and 305a2 of the group of active regions 305 are embedded in the first section 301a of the first well 301 of the integrated circuit 300. The active regions 305b1 and 305b2 of the group of active regions 305 are embedded in the second section 301b of the first well 301 of the integrated circuit 300. The active regions 305a1, 305a2, 305b1, and 305b2 comprise dopants of the second type.

[0120] In some embodiments, the integrated circuit 300 corresponds to the memory cell 100B of Fig. 1B, and the first type is an N-type dopant and the second type is a P-type dopant, so that the first well 301 of the integrated circuit 300 is an N-well, the second well 302 of the integrated circuit 300 is a P-well, the active regions 303a1, 303a2, 303b1, and 303b2 are n-type dopants embedded in the second well 302 (P-well), and the active regions 305a1, 305a2, and 305b2 are p-type dopants embedded in the first well 301 (N-well). In these embodiments, the first well 301 corresponds to the N-well of the PMOS transistors PG0 and PG1 of the memory cell 100B of Fig. 1B, and the second well 302 corresponds to the P-well of the NMOS transistors PDo and PD1 of the memory cell 100B of Fig. 1B. In these embodiments, the active regions 303a1 and 303b2 correspond to the source regions of the respective NMOS transistors PD0 and PD1 of the memory cell 100B of Fig. 1B and the active regions 303a2 and 303b1 correspond to the drain regions of the respective NMOS transistors PDo and PD1 of the memory cell 100B of Fig. 1B. In these embodiments, the active regions 305a1 and 305b2 correspond to the source or drain regions of the corresponding PMOS transistors PGo and PG1 of the memory cell 100B of Fig. 1B, and the active regions 305a2 and 305b1 correspond to the drain or source regions of the corresponding PMOS transistors PGo and PG1 of the memory cell 100B of Fig. 1B.

[0121] In some embodiments, the integrated circuit 300 corresponds to the memory cell 100C of Fig. 1C, and the first type is a P-type dopant and the second type is an N-type dopant, so that the first well 301 of the integrated circuit 300 is a P-well, and the second well 302 of the integrated circuit 300 is an N-well, the active regions 303a1, 303a2, 303b1, and 303b2 are p-type dopants embedded in the second well 302 (N-well), and the active regions 305a1, 305a2, and 305b2 are n-type dopants embedded in the first well 301 (P-well). In these embodiments, the integrated circuit 300 corresponds to the memory cell 100C of Fig. 1C, and the first well 301 corresponds to the P-well of the NMOS transistors PG2 and PG3, and the second well 302 corresponds to the N-well of the PMOS transistors PUo and PU1 of the memory cell 100C of Fig. 1C. In these embodiments, the active regions 303a1 and 303b2 correspond to the source regions of the respective PMOS transistors PUo and PU1 of the memory cell 100C of Fig. 1C and the active regions 303a2 and 303b1 correspond to the drain regions of the corresponding PMOS transistors PUo and PU1 of the memory cell 100C of Fig. 1C. In these embodiments, the active regions 305a1 and 305b2 correspond to the source or drain regions of the corresponding NMOS transistors PG2 and PG3 of the memory cell 100C of Fig. 1C and the active regions 305a2 and 305b1 correspond to the drain or source regions of the corresponding NMOS transistors PG2 and PG3 of the memory cell 100C of Fig. 1C.

[0122] Other quantities or configurations of the group of active regions 303 or 305 are within the scope of the present disclosure.

[0123] The integrated circuit 300 further includes a group of gates 304 extending in the second direction Y. The group of gates 304 is arranged above the group of active areas 302 and 303 of the integrated circuit 300. The group of gates 304 is arranged on a second level of the integrated circuit 300 or 500. The second level is above the first level of the integrated circuit 300 or 500. In some embodiments, the second level of the integrated circuit 300 or 500 is referred to as a POLY level.

[0124] The group of gates 304 includes one or more of the gate structures 304a or 304b. The gate structures 304a and 304b are spaced apart from each other in the first direction X. The insulating portion 330 is disposed between the gate structures 304a and 304b and is spaced from each gate structure 304a or 304b by a gate pitch distance (not shown).

[0125] The gate structure 304a comprises the gate structures 304a1 and 304a2. The gate structures 304a1 and 304a2 are separated in the second direction Y by the cutting width D V (not shown) spaced apart.

[0126] The gate structure 304b comprises the gate structures 304b1 and 304b2. The gate structures 304b1 and 304b2 are separated in the second direction Y by the cutting width D V (not shown) spaced apart.

[0127] In some embodiments, the integrated circuit 300 corresponds to the memory cell 100B of Fig. 1B, such that the gate structures 304a1 and 304b1 are the respective gates of the NMOS transistors PDo and PD1, and the gate structures 304a2 and 304b2 are the respective gates of the PMOS transistors PGo and PG1. In some embodiments, the integrated circuit 300 corresponds to the memory cell 100C of Fig. 1C, such that the gate structures 304a1 and 304b1 are the corresponding gates of the PMOS transistors PUo and PU1, and the gate structures 304a2 and 304b2 are the corresponding gates of the NMOS transistors PG2 and PG3.

[0128] Other quantities or configurations of at least the group of gates 304, the gate structures 304a1, 304a2, 304b1 or 304b2 are within the scope of the present disclosure.

[0129] The integrated circuit 300 further comprises the conductive structures 310b, 310c, 310d, 310e, and 310f (collectively referred to as “group of contacts 310”). The group of contacts 310 extends in the second direction Y. The group of contacts 310 lies above the group of active areas 303, the group of active areas 305, the first well 301, and the second well 302. The group of contacts 310 is arranged on the second level of the integrated circuit 300 or 500. In some embodiments, the second level of the integrated circuit 300 or 500 is referred to as a metal diffusion (MD) level.

[0130] The group of vias 310 is electrically coupled to the group of active areas 303 or 305 of the integrated circuit 300 or 500. In some embodiments, the group of vias 310 electrically couples the group of active areas 303 or 305 of the integrated circuit 300 or 500 to the upper levels (e.g., M0, M1, or M2) of the integrated circuit 300 or 500.

[0131] The conductive structures 310a, 310b, 310c, 310d electrically couple corresponding vias 314a, 314b, 314g, 314h, 314h to the corresponding active areas 303a1, 303b2, 305a1, 305b2. The conductive structures 310e, 310f electrically couple corresponding active areas 303a2, 303b1 to corresponding active areas 305a2, 305b1. The conductive structures 310e, 310f electrically couple corresponding vias 314e, 314d to corresponding conductive structures 312c, 312b (M0 level). Other quantities or configurations of the group of vias 310 are within the scope of the present disclosure.

[0132] The integrated circuit 300 further comprises the conductive structures 312a, 312b, 312c, 312d, 312e, and 312f (collectively referred to as “group of conductive structures 312”). The group of conductive structures 312 extends in the first direction X. The group of conductive structures 312 is arranged above the group of contacts 310, the group of gate structures 304, the group of active areas 303, the group of active areas 305, the first well 301, and the second well 302 of the integrated circuit 300 or 500. The group of conductive structures 312 is arranged on a third level of the integrated circuit 300 or 500. The third level of the integrated circuit 300 or 500 is above the first level and the second level of the integrated circuit 300 or 500. In some embodiments, the third level of the integrated circuit 300 or 500 is referred to as the metal zero (M0) level.

[0133] The group of conductive structures 312 electrically couples the group of active areas 303 or 305 to the upper levels (e.g., M1 or M2) of the integrated circuit 300 or 500. In some embodiments, the group of conductive structures 312 electrically couples the group of gates 304 to upper levels (e.g., M1 or M2) of the integrated circuit 300 or 500.

[0134] Conductive structure 312a electrically couples conductive structure 310a to conductive structure 310b via vias 314a and 314b. Conductive structure 312b electrically couples conductive structure 310f to gate structure 304a1 via vias 314c and 314d. Conductive structure 312c electrically couples conductive structure 310e to gate structure 304b1 via vias 314e and 314f.

[0135] The conductive structure 312d electrically couples the conductive structure 310c to the upper layers (e.g., the conductive structure 318a) via the vias 314g and 320a. The conductive structure 312e electrically couples the conductive structure 310d to the upper layers (e.g., the conductive structure 318e) through the vias 314h and 320e.

[0136] The conductive structure 312f electrically couples the gate structure 304a2 to the gate structure 304b2 via the vias 314i and 314j. Other quantities or configurations of the group of conductive structures 312 are within the scope of the present disclosure.

[0137] The integrated circuit 300 further includes vias 314a, 314b, 314c, 314d, 314e, 314f, 314g, 314h, 314i, and 314j (collectively referred to as “group of vias 314”) between the group of conductive structures 312 and either the group of conductive structures 310 or the group of gate structures 304 of the integrated circuit 300 or 500. The group of vias 314 electrically couples the group of conductive structures 312 to the group of conductive structures 310 or the group of gate structures 304 of the integrated circuit 300 or 500.

[0138] In some embodiments, one or more of the vias of the group of vias 314 are arranged where one or more conductive structures of the group of conductive structures 312 overlie one or more conductive structures of the group of conductive structures 310 or one or more gate structures of the group of gate structures 304 of the integrated circuit 300 or 500.

[0139] Vias 314a, 314b electrically couple conductive structure 312a to corresponding conductive structures 310a, 310b. Vias 314c, 314f electrically couple corresponding conductive structures 312b, 312c to corresponding gate structures 304a2, 304b2. Vias 314d, 314e electrically couple corresponding conductive structures 312b, 312c to corresponding conductive structures 310f, 310e. Vias 314g, 314h electrically couple corresponding conductive structures 312d, 312e to corresponding conductive structures 310c, 310d.

[0140] The group of vias 314 is arranged in the via-over-diffusion (VD) level or in the via-over-gate (VG) level of the integrated circuit 300 or 500. The VG or VD level of the integrated circuit 300 or 500 is arranged between the second and third levels. In some embodiments, the vias 314c, 314f, 314i, and 314j are arranged in the VG level of the integrated circuit 300 or 500. In some embodiments, the vias 314a, 314b, 314d, 314e, 314e, 314g, and 314h are arranged in the VD level of the integrated circuit 300 or 500. Other quantities or configurations of the group of vias 314 are within the scope of the present disclosure.

[0141] The integrated circuit 300 further comprises the conductive structures 318a, 318b, 318c, and 318e (collectively referred to as "group of conductive structures 318"). The group of conductive structures 318 extends in the second direction Y. The group of conductive structures 318 is arranged above the group of vias 320, the group of conductive structures 312, the group of contacts 310, the group of gate structures 304, the group of active areas 303, the group of active areas 305, the first well 301, and the second well 302 of the integrated circuit 300 or 500. The group of conductive structures 318 is arranged in a fourth level of the integrated circuit 300 or 500. The fourth level of the integrated circuit 300 or 500 is above the first level, the second level and the third level of the integrated circuit 300 or 500.In some embodiments, the fourth level of the integrated circuit 300 or 500 is referred to as the metal zero (M0) level.

[0142] The group of conductive structures 318 electrically couples the group of conductive structures 312 to upper levels (e.g., the group of conductive structures 322 (M1)) of the integrated circuit 300 or 500.

[0143] The conductive structure 318a corresponds to at least a part of the bit line BL of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C.

[0144] The conductive structures 318b and 318d together correspond to the word line WL of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C.

[0145] The conductive structure 318e corresponds to at least a part of the bit line bar BLB of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C.

[0146] In some embodiments, the integrated circuit 300 corresponds to the memory cell 100B of Fig. 1B, and the conductive structure 318c is electrically coupled to a reference supply voltage VSS. In some embodiments, the integrated circuit 300 corresponds to the memory cell 100C of Fig. 1C, and the conductive structure 318c is electrically coupled to a supply voltage VDD. Other quantities or configurations of the group of conductive structures 318 are within the scope of the present disclosure.

[0147] The integrated circuit 300 further includes vias 320a, 320b, 320c, 320d, and 320e (collectively referred to as “group of vias 320”) between the group of conductive structures 318 and the group of conductive structures 312 of the integrated circuit 300 or 500. The group of vias 320 electrically couples the group of conductive structures 318 to the group of conductive structures 312 of the integrated circuit 300 or 500. In some embodiments, one or more vias of the group of vias 320 are arranged where one or more conductive structures of the group of conductive structures 318 overlie one or more conductive structures of the group of conductive structures 312 of the integrated circuit 300 or 500.

[0148] Vias 320a, 320e electrically couple the corresponding conductive structures 318a, 318e to the corresponding conductive structures 312d, 312e. Vias 320b, 320c electrically couple the corresponding conductive structures 318b, 318d to the corresponding conductive structures 312f. Via 320d electrically couples the conductive structure 318c to the conductive structure 312a.

[0149] The group of vias 320 is arranged in the via zero (V0) level of the integrated circuit 300 or 500. The V0 level of the integrated circuit 300 or 500 is arranged between the third and fourth levels. Other quantities or configurations of the group of vias 320 are within the scope of the present disclosure.

[0150] The integrated circuit 300 further includes the conductive structures 322a, 322b, 322c, and 322e (collectively referred to as the "group of conductive structures 322"). The group of conductive structures 322 extends in the first direction X. The group of conductive structures 322 is arranged over the group of vias 326, the group of vias 320, the group of conductive structures 318, the group of conductive structures 312, the group of contacts 310, the group of gate structures 304, the group of active areas 303, the group of active areas 305, the group of active areas 305, the first well 301, and the second well 302 of the integrated circuit 300 or 500. The group of conductive structures 322 is arranged in a fifth level of the integrated circuit 300 or 500.The fifth level of the integrated circuit 300 or 500 is above the first level, the second level, the third level, and the fourth level of the integrated circuit 300 or 500. In some embodiments, the fifth level of the integrated circuit 300 or 500 is referred to as the Metal 1 (M1) level.

[0151] The group of conductive structures 322 is electrically coupled to the group of conductive structures 312 and the other lower levels (e.g., MO, Poly, OD, etc.) of the integrated circuit 300 or 500. In some embodiments, the group of conductive structures 322 is electrically coupled to other upper levels (not shown) of the integrated circuit 300 or 500.

[0152] The conductive structure 322b and 318a corresponds to at least a part of the bit line BL of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C. The conductive structure 322d and 318e corresponds to at least a part of the bit line bar BLB of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C.

[0153] In some embodiments, the integrated circuit 300 corresponds to the memory cell 100B of Fig. 1B, and the conductive structures 322a, 322c, and 318c are electrically coupled to the reference voltage VSS. In some embodiments, the integrated circuit 300 corresponds to the memory cell 100C of Fig. 1C, and the conductive structures 322a, 322c, and 318c are electrically coupled to the supply voltage VDD. Other quantities or configurations of the group of conductive structures 322 are within the scope of the present disclosure.

[0154] The integrated circuit 300 further includes vias 326a, 326b, 326c, 326d, and 326e (collectively referred to as “group of vias 326”) between the group of conductive structures 322 and the group of conductive structures 318 of the integrated circuit 300 or 500. The group of vias 326 electrically couples the group of conductive structures 322 to the group of conductive structures 318 of the integrated circuit 300 or 500. In some embodiments, one or more of the vias of the group of vias 326 are arranged where one or more conductive structures of the group of conductive structures 322 overlie one or more of the conductive structures 318 of the integrated circuit 300 or 500.

[0155] Vias 326a, 326e electrically couple the corresponding conductive structures 322b, 322d to the corresponding conductive structures 318a, 318e. Vias 326b, 326c, 326d electrically couple the corresponding conductive structures 322e, 322c, 322a to the conductive structure 318c.

[0156] The group of vias 326 is arranged in via level 1 (V1) of the integrated circuit 300 or 500. The V1 level of the integrated circuit 300 or 500 is arranged between the fourth level and the fifth level. Other quantities or configurations of the group of vias 326 are within the scope of the present disclosure.

[0157] In some embodiments, at least one conductive structure of the group of vias 310 or at least one conductive structure of the group of conductive structures 312, 318 or 322 is a conductive material comprising copper, aluminum, alloys thereof, or other suitable conductive materials, and is formed in one or more metallization layers by one or more physical vapor deposition processes, a chemical vapor deposition process, a plating process, or other suitable processes.

[0158] In some embodiments, at least one of the group of vias 314, 320, or 326 is a metal line, a via, a through-silicon via (TSV), an interlevel via (ILV), a slot via, an array of vias, or another suitable line. In some embodiments, at least one of the group of vias 314, 320, or 326 comprises copper, aluminum, nickel, titanium, tungsten, cobalt, carbon, alloys thereof, or another suitable conductive material formed in one or more metallization layers by one or more physical vapor deposition processes, a chemical vapor deposition process, a plating process, or other suitable processes.In some embodiments, at least one via from the group of vias 314, 320, or 326 includes one or more conductive line segments. Other configurations, materials, or quantities of the group of vias 314, 320, or 326 are within the scope of the present disclosure.

[0159] In some embodiments, the integrated circuit occupies 300 or 500 ( Fig. 5) occupies less area than other integrated circuits. In some embodiments, integrated circuit 300 or 500 is used as part of a memory macro 100A, which is denser than other configurations by occupying less area than other integrated circuits. In some embodiments, memory macro 100A has a larger storage capacity than other configurations by being used as part of a denser memory macro 100A or memory cell array.

[0160] In some embodiments, the use of conductive structures 322b and 322d between conductive structures 322a, 322c, 322e results in an integrated circuit 300 with better electromagnetic shielding than other configurations. In some embodiments, providing better electromagnetic shielding results in the integrated circuit 300 having less crosstalk than other configurations. LAYOUT DESIGN

[0161] Fig. 4A-4B are diagrams of a layout design 400, in accordance with some embodiments.

[0162] The layout design 400 is a variant of the layout design 200 of the Fig. 2A-2C. For example, layout design 400 has bitline layout designs and bitline bar layout designs with a greater width than layout design 200. Components that are the same or similar to those in one or more of the Fig. 2A-2C, are given the same reference numerals, so a detailed description is omitted.

[0163] The layout design 400 is a layout diagram of the memory cell 100B of Fig. 1B or the memory cell 100C Fig. 1C. The layout design 400 can be used to fabricate the memory cell 100B or 100C. The layout design 400 includes the section 200A ( Fig. 2A) and a section 400A ( Fig. 4A). For better illustration, the layout design contains 400 of Fig. 4A does not apply to Section 200A. The layout design 400, as shown in Fig. 4B, includes section 200A of Fig. 2A and section 400A of Fig. 4A.

[0164] Compared to the layout design 200 of the Fig. 2A-2C, the layout design 400 does not include conductive structure layout designs 222a and 222e and via layout designs 226b and 226d.

[0165] Compared to the layout design 200 of the Fig. 2A-2C, conductive structure layout design 422d of layout design 400 replaces conductive structure layout design 222a, and conductive structure layout design 422b of layout design 400 replaces conductive structure layout design 222b.

[0166] The conductive structure layout designs 422d and 422b are similar to the corresponding conductive structure layout designs 222d and 222b, so a similar detailed description is omitted. In some embodiments, the conductive structure layout designs 422d and 422b can be used to fabricate corresponding conductive structures 522d and 522b ( Fig. ).

[0167] The conductive structure layout design 422d or 422b has a greater width in the second direction Y than a width of the corresponding conductive structure layout design 222d or 222b in the second direction Y. By increasing the width of the conductive structure layout design 422d, 422b, the conductive structure layout designs 422d, 422b are usable to produce corresponding bit lines BL (e.g., conductive structure 522b in Fig. 5) and bit line bars BLB (e.g. conductive structure 522d in Fig. 5) with less resistance than configurations with a smaller width in the second direction Y. In some embodiments, by removing conductive structure layout designs 222a and 222e and via layout designs 226b and 226d, layout design 400 has increased routing resources usable for other metal layers.

[0168] Other configurations of the conductive structure layout design 422d or 422b are within the scope of the present disclosure. For example, in some embodiments, the width or length of at least the conductive structure layout designs 422d or 422b is changed so that they overlap or have different layout designs than those in Fig. 4 shown. INTEGRATED CIRCUIT - CROSS-SECTION VIEWS

[0169] Fig. 5 is a cross-sectional view of an integrated circuit 500 according to layout design 400, cut in plane JJ'. Fig. 5 is a variation of Fig. 3H of the integrated circuit 300.

[0170] The integrated circuit 500 is manufactured according to the layout design 400. The integrated circuit 500 is a structural implementation of the memory cell 100B or 100C.

[0171] The integrated circuit 500 is a variant of the integrated circuit 300. Compared to the integrated circuit 300, the integrated circuit 500 does not include conductive structures 322a and 322e and no vias 326b and 326d.

[0172] Compared to the integrated circuit 300 of Fig. 3A-3I, conductive structure 522b of integrated circuit 500 replaces conductive structure 322b and conductive structure 522d of integrated circuit 500 replaces conductive structure 322d.

[0173] The conductive structures 522b and 522d are similar to the corresponding conductive structures 322b and 322d, so a similar detailed description is omitted.

[0174] The conductive structures 522b or 522d have a greater width in the second direction Y than a width of corresponding conductive structures 322b or 322d in the second direction Y. By increasing the width of the conductive structures 522b and 522d, the bit line BL (e.g. conductive structure 522b in Fig. 5) and the bit line bar BLB (e.g. conductive structure 522b in the Fig. 5) have less resistance than configurations with a smaller width in the second direction Y. In some embodiments, by removing the conductive structures 322a and 322e and the vias 326b and 326d, the integrated circuit 500 has an increased routing resource that can be used for other metal layers.

[0175] Other configurations of conductive structures 522b or 522d are within the scope of the present disclosure. For example, in some embodiments, the width or length of at least one conductive structure 522b or 522d is changed to overlap or expose different portions of the integrated circuit 500 than in Fig. 5 shown.

[0176] For brevity, a single cross-sectional drawing (e.g. Fig. 5) of the integrated circuit 500. However, it should be understood that the integrated circuit 500 includes additional cross-sectional drawings (not shown) that correspond to the cross-sectional drawings of the integrated circuit 300 in the Fig. 3A-3I. For example, each of the cross-sectional views of the integrated circuit 300 may be similar to Fig. 5 may be modified to exclude conductive structures 322a and 322e and vias 326b and 326d, and conductive structure 522b replaces conductive structure 322b, and conductive structure 522d replaces conductive structure 322d. PROCEDURE

[0177] Fig. 6A is a flowchart of a method 600A for forming or manufacturing an IC according to some embodiments. It is understood that additional operations may be performed before, during, and / or after the Fig. 6A, and that some other processes may only be briefly described herein. In some embodiments, the method 600A is for forming integrated circuits, such as memory macro 100A ( Fig. 1A), memory cell 100B ( Fig. 1B), memory cell 100C ( Fig. 1C), IC structure 300 ( Fig. 3A-3I) or IC structure 500 ( Fig. 5). In some embodiments, the method 600A is usable to form integrated circuits having similar relationships as one or more of the layout designs 200 or 400 ( Fig. 2A-2C or 4A-4B).

[0178] In operation 602 of method 600A, a layout design 200 or 400 of a memory array circuit (e.g., memory cell 100B, 100C) is generated. The operation 602 is performed by a processor device (e.g., processor 702 ( Fig. 7)) which is configured to execute instructions to generate a layout design 200, 400 or 716 ( Fig. 7). In some embodiments, the layout design 200, 400, or 716 is a Graphics Database Information System (GDSII) file format.

[0179] In operation 604 of method 600A, the memory array circuit (e.g., memory macro 100A, memory cell 100B, or 100C) is generated based on layout design 200, 400, or 716. In some embodiments, operation 604 of method 600A includes fabricating at least one mask based on layout design 200, 400, or 716 and fabricating the memory array circuit based on the at least one mask. In some embodiments, the memory array circuit of process 602 or 604 includes memory cell 100B ( Fig. 1B), the memory cell 100C ( Fig. 1C), the IC structure 300 ( Fig. 3A-3I) or the IC structure 500 ( Fig. 5).

[0180] Fig. 6B is a flowchart of a method 600B for generating a layout design of a memory array circuit according to some embodiments. It is understood that before, during, and / or after the Fig. 6B, additional operations may be performed, and some other processes may only be briefly described herein. In some embodiments, method 600B is usable to configure one or more of layout designs 200 or 400 ( Fig. 2A-2C & 4A-4B) of the memory cell 100B ( Fig. 1B), the memory cell 100C ( Fig. 1C), the IC structure 300 ( Fig. 3A-3I) or the IC structure 500 ( Fig. 5) to generate.

[0181] In process 610 of method 600B, a group of layout designs for active areas 212a or 212b is generated. In some embodiments, generating the group of layout designs for active areas 212a or 212b is usable or corresponds to fabricating a group of active areas 303 or 305 of integrated circuit 300 or 500.

[0182] In some embodiments, the group of active regions 303 or 305 of the integrated circuit 300 or 500 comprises the active regions of a first pull-down transistor (NMOS transistor PD0), a second pull-down transistor (NMOS transistor PD1), a first pass-gate transistor (PMOS transistor PG0), and a second pass-gate transistor (PMOS transistor PG1). In some embodiments, the group of active regions 303 or 305 of the integrated circuit 300 or 500 comprises the active regions of a first pull-up transistor (PMOS transistor PU0), a second pull-up transistor (PMOS transistor PU1), a first pass-gate transistor (NMOS transistor PG2), and a second pass-gate transistor (NMOS transistor PG3).

[0183] In some embodiments, each of the layout designs of the group of layout designs 212a, 212b is spaced from an adjacent layout design of the group of layout designs 212a, 212b in the second direction Y by a first pitch distance. In some embodiments, the group of active area layout designs 212a, 212b extends in the first direction X, which is different from the first direction and is arranged on a first layout level (e.g., active region or well).

[0184] In some embodiments, generating the set of active area layout designs 312a, 412a of process 610 includes generating active area layout designs 202a1, active area layout designs 202a2, active area layout designs 202b1, and active area layout designs 202b2.

[0185] In some embodiments, process 610 includes placing the group of layout designs for active areas 312a, 412a, or at the first layout level (e.g., active areas or wells). In some embodiments, the first layout level corresponds to the active area of ​​layout design 200 or 400.

[0186] In process 612, a group of gate layout designs 204 is generated. In some embodiments, the group of gate layout designs 204 corresponds to the fabrication of a group of gate structures 304 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0187] In some embodiments, the group of gate layout designs 204 of method 1000 includes one or more of the gate layout designs 204a, 204b, or 204c. In some embodiments, the process 612 includes placing the group of gate layout designs 202 on the second layout level (e.g., POLY).

[0188] In process 614, a group of metal contact layout designs 210 is generated. In some embodiments, the group of metal contact layout designs 210 corresponds to the fabrication of a group of metal contacts 310 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0189] In some embodiments, in process 614, the metal contact layout design 210a and 210b overlaps the cell boundary of the active area layout design 200 or 400 and the active area layout design 202a.

[0190] In some embodiments, metal contact layout designs 210a, 210b, 210c, and 210d are used in operation 614 to form corresponding metal contacts 310a, 310b, 310c, and 310d. In some embodiments, metal contact 310a is electrically coupled to a source of the first pull-down transistor (NMOS transistor PD0). In some embodiments, metal contact 310b is electrically coupled to a source of the second pull-down transistor (NMOS transistor PD1).

[0191] In some embodiments, metal contact 310a is electrically coupled to a source of the first pull-up transistor (PMOS transistor PU0). In some embodiments, metal contact 310b is electrically coupled to a source of the second pull-up transistor (PMOS transistor PU1).

[0192] In some embodiments, metal contact 310c is electrically coupled to a source or drain of the first pass-gate transistor (PMOS transistor PG0). In some embodiments, metal contact 310d is electrically coupled to a source or drain of the second pass-gate transistor (PMOS transistor PG1).

[0193] In some embodiments, metal contact 310c is electrically coupled to a source or drain of the first pass-gate transistor (NMOS transistor PG2). In some embodiments, metal contact 310d is electrically coupled to a source or drain of the second pass-gate transistor (NMOS transistor PG3).

[0194] In some embodiments, the group of metal contact layout designs 210 of method 600B includes one or more of the conductive structure layout designs 210a, 210b, 210c, 210d, 210e, or 210f. In some embodiments, operation 614 includes placing the group of metal contact layout designs 210 on the third layout level (e.g., MD).

[0195] In process 616, a first group of conductive pattern layout designs 212 is generated. In some embodiments, the first group of conductive pattern layout designs of process 616 comprises the group of conductive pattern layout designs 212. In some embodiments, the group of conductive pattern layout designs 212 corresponds to the fabrication of a group of conductive patterns 312 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0196] In some embodiments, the group of conductive structure layout designs 212 of method 600B includes one or more of the conductive structure layout designs 212a, 212b, 212c, 212d, 212e, or 212f. In some embodiments, process 616 includes placing the group of conductive structure layout designs 212 on the fourth layout level (e.g., M0).

[0197] In process 618, a first group of via layout designs is generated. In some embodiments, the first group of via layout designs of process 618 includes the group of via layout designs 214. In some embodiments, the group of via layout designs 214 corresponds to the fabrication of a group of vias 314 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0198] In some embodiments, the group of via layout designs 214 of method 600B comprises one or more of the via layout designs 214a, 214b, 214c, 214d, 214e, 214f, 214g, 214h, 214h, or 214i. In some embodiments, process 618 comprises placing the group of vias between the group of metal via layout designs 210 and the group of conductive structure layout designs 212. In some embodiments, process 618 comprises placing the group of vias between the third layout level (e.g., MD) and the fourth layout level (e.g., M0). In some embodiments, process 618 comprises placing the group of vias 214 on the VG or VD layout level.

[0199] In process 620, a second group of conductive structure layout designs is generated. In some embodiments, the second group of conductive structure layout designs of process 620 includes the group of conductive structure layout designs 218. In some embodiments, the group of conductive structure layout designs 218 corresponds to the fabrication of a group of conductive structures 318 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0200] In some embodiments, the group of conductive structure layout designs 218 of method 600B includes one or more of the conductive structure layout designs 218a, 218b, 218c, 218d, or 218e. In some embodiments, process 620 includes placing the group of conductive structure layout designs 218 on the fifth layout level (e.g., M1).

[0201] In process 622, a second group of via layout designs is generated. In some embodiments, the second group of via layout designs of process 622 includes the group of via layout designs 220. In some embodiments, the group of via layout designs 220 corresponds to the fabrication of a group of vias 320 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0202] In some embodiments, the group of via layout designs 220 of method 600B includes one or more of the via layout designs 220a, 220b, 220c, 220d, or 220e. In some embodiments, process 622 includes placing the group of via layout designs 220 between the group of conductive structure layout designs 218 and the group of conductive structure layout designs 212.

[0203] In some embodiments, process 622 includes placing the group of vias between the fourth layout level (e.g., M0) and the fifth layout level (e.g., M1). In some embodiments, process 622 includes placing the group of vias 220 on the V0 layout level.

[0204] In process 624, a third group of conductive structure layout designs is generated. In some embodiments, the third group of conductive structure layout designs of process 624 includes the group of conductive structure layout designs 222. In some embodiments, the group of conductive feature layout designs 222 corresponds to the fabrication of a group of conductive structures 322 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0205] In some embodiments, the group of conductive structure layout designs 222 of method 600B includes one or more of the conductive structure layout designs 222a, 222b, 222c, 222d, 222e, 222e, 422b, or 422d. In some embodiments, process 624 includes placing the group of conductive structure layout designs 222 on the sixth layout level (e.g., M2).

[0206] In process 626, a third group of via layout designs is generated. In some embodiments, the third group of via layout designs of process 626 includes the group of via layout designs 226. In some embodiments, the group of via layout designs 226 corresponds to the fabrication of a group of vias 326 of the memory cell 100B-100C or the integrated circuit 300 or 500.

[0207] In some embodiments, the group of via layout designs 226 of method 600B comprises one or more of the via layout designs 226a, 226b, 226c, 226d, or 226e. In some embodiments, the process 626 comprises placing the group of via layout designs 226 between the group of conductive structure layout designs 218 and the group of conductive structure layout designs 222. In some embodiments, the process 626 comprises placing the group of vias between the fifth layout level (e.g., M1) and the sixth layout level (e.g., M2). In some embodiments, the process 626 comprises placing the group of vias 226 on the V1 layout level.

[0208] In some embodiments, one or more of layout designs 200 or 400 is a standard cell. In some embodiments, one or more of processes 610-626 are not performed.

[0209] One or more of the processes of methods 600A-600B are performed by a processor device configured to execute instructions for manufacturing a memory array circuit, such as memory macro 100A, a memory cell, such as memory cell 100B or 100C, or an IC, such as IC structure 300 or 500. In some embodiments, one or more processes of methods 600A-600B are performed with the same processor device that is also used in one or more other operations of methods 600A-600B. In some embodiments, a different processor device is used to perform one or more operations of methods 600A-600B than the one used to perform one or more different processes of methods 600A-600B.

[0210] Fig. 7 is a schematic view of a system 700 for designing an IC layout design, according to some embodiments. In some embodiments, the system 700 generates or places one or more IC layout designs described herein. The system 700 includes a hardware processor 702 and a non-volatile memory 704 encoded with, i.e., storing, computer program code 706, i.e., storing a group of executable instructions. The memory 704 is configured to work with manufacturing machines for producing the integrated circuit. The processor 702 is electrically coupled to the memory 704 via a bus 708. The processor 702 is also electrically coupled to an I / O interface 710 via the bus 708. A network interface 712 is also electrically coupled to the processor 702 via the bus 708.The network interface 712 is coupled to a network 714 such that the processor 702 and the memory 704 are adapted to connect to external elements via the network 714. The processor 702 is configured to execute the computer program code 706 encoded in the memory 704 to cause the system 700 to be usable for performing some or all of the processes described in methods 600A or 600B.

[0211] In some embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a decentralized processor system, an application-specific integrated circuit (ASIC), and / or any suitable processing device.

[0212] In some embodiments, storage 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage 704 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments, storage 704 is a computer-readable storage medium. In some embodiments that utilize optical disks, storage 704 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0213] In some embodiments, storage medium 704 stores computer program code 706 configured to cause system 700 to perform method 600A or 600B. In some embodiments, storage medium 704 also stores information required to perform method 600A or 600B, as well as information generated during performance of method 600A or 600B, such as layout design 716 and user interface 718, and / or a set of executable instructions for performing the processes of method 600A or 600B. In some embodiments, layout design 716 comprises one or more of layout designs 200 or 400.

[0214] In some embodiments, storage medium 704 stores instructions (e.g., computer program code 706) for operating on manufacturing machines. The instructions (e.g., computer program code 706) enable processor 702 to generate manufacturing instructions that can be read by the manufacturing machines to effectively implement method 600A or 600B during a manufacturing process.

[0215] System 700 includes I / O interface 710. I / O interface 710 is coupled to external circuitry. In some embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, and / or arrow keys for transmitting information and commands to processor 702.

[0216] System 700 also includes network interface 712 coupled to processor 702. Network interface 712 enables system 700 to communicate with network 714 to which one or more other computer systems are connected. Network interface 712 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or wired network interfaces such as ETHERNET, USB, or IEEE-1394. In some embodiments, method 600A or 600B is implemented in two or more systems 700, and information such as layout design and user interface is exchanged between different systems 700 over network 714.

[0217] System 700 is configured to receive information related to a layout design via I / O interface 710 or network interface 712. The information is transmitted via bus 708 to processor 702 to determine a layout design for fabricating an IC structure, such as IC structure 300 or 500. The layout design is then stored in memory 704 as layout design 716. System 700 is configured to receive information related to a user interface via I / O interface 710 or network interface 712. The information is stored in memory 704 as user interface 718.

[0218] In some embodiments, method 600A or 600B is implemented as a stand-alone software application for execution by a processor. In some embodiments, method 600A or 600B is implemented as a software application that is part of an additional software application. In some embodiments, method 600A or 600B is implemented as a plug-in for a software application. In some embodiments, method 600A or 600B is implemented as a software application that is part of an EDA tool. In some embodiments, method 600A or 600B is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory, computer-readable medium or memory 704.In some embodiments, the layout is generated using a tool such as VIRTUOSO® from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool. In some embodiments, the layout is created based on a netlist created based on the schematic. In some embodiments, method 600A is implemented by a manufacturing device to fabricate an integrated circuit (e.g., memory cell 100B or 100C, IC structure 300 or 500) using a set of masks fabricated based on one or more layout designs (e.g., layout design 200 or 400) generated by system 700.

[0219] The System 700 from Fig. 7 generates layout designs (e.g. layout design 200 or 400) of memory macro 100A, memory cell 100B or 100C or IC structure 300 or 500 that are smaller than other approaches.

[0220] Fig. 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and an IC manufacturing flow coupled thereto, in accordance with at least one embodiment of the present disclosure.

[0221] In Fig. 8, the IC manufacturing system 800 includes entities, such as a design facility 820, a mask facility 830, and an IC manufacturer / fabricator (“fab”) 840, that interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing an IC device 860. The entities in the system 800 are coupled via a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a plurality of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides and / or receives services for one or more of the other entities.In some embodiments, two or more of the design facilities 820, 830, and 840 are owned by a single larger company. In some embodiments, two or more of the design facility 820, the mask facility 830, and the IC fab 840 coexist in a common facility and share common resources.

[0222] The design facility (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for an IC device 860. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 860. The various layers combine to form various IC elements. For example, a portion of the IC design layout 822 includes various IC elements, such as an active area, a gate electrode, a source and drain electrode, metal lines or vias of an interlayer connection, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate.The design facility 820 implements a suitable design process to form the IC design layout 822. The design process includes one or more of logic design, physical design, or location and route. The IC design layout 822 is represented in one or more data files containing information about the geometric patterns. For example, the IC design layout 822 can be expressed in a GDSII file format or DFII file format.

[0223] The mask facility 830 includes data preparation 832 and mask fabrication 834. The mask facility 830 uses the IC design layout 822 to create one or more masks used to fabricate the various layers of the IC device 860 according to the IC design layout 822. The mask facility 830 performs mask data preparation 832, translating the IC design layout 822 into a representative data file ("RDF"). The mask data preparation 832 provides the RDF for mask fabrication 834. The mask fabrication 834 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticular structure) or a semiconductor wafer. The IC design layout 822 is manipulated by the mask data preparation 832 to meet special properties of the mask writer and / or requirements of the IC fab 840. In Fig. 8, mask data preparation 832 and mask fabrication 834 are depicted as separate elements. In some embodiments, mask data preparation 832 and mask fabrication 834 may be collectively referred to as mask data preparation.

[0224] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also employed, which treats OPC as an inverse imaging problem.

[0225] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) for verifying the IC design layout subjected to OPC processes against a set of mask creation rules containing certain geometric and / or interconnect constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 822 to accommodate constraints during mask fabrication 834, which may undo some of the changes performed by OPC to satisfy the mask creation rules.

[0226] In some embodiments, mask data preparation 832 includes lithography process control (LPC), which simulates the processing implemented by IC fab 840 to fabricate IC device 860. LPC simulates this processing based on IC design layout 822 to create a simulated fabricated device, such as IC device 860. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device is created by LPC, OPC and / or MRC are repeated to further refine the IC design layout 822 if the simulated device is not close enough to the shape to conform to the design rules.

[0227] It should be understood that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional functions, such as a logic operation (LOP) to modify IC design layout 822 according to manufacturing rules. Furthermore, the processes applied to IC design layout 822 during data preparation 832 may be performed in a variety of different jobs.

[0228] After mask data preparation 832 and during mask fabrication 834, a mask or a group of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam (electron beam) or a multiple electron beam mechanism is used to form a pattern on a mask (photomask or reticular structure) based on the modified IC design layout. The mask can be formed using various technologies. In some embodiments, the mask is formed using the binary technique. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and penetrates the transparent regions.In one example, a binary mask includes a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, the mask is formed using a phase-shifting technology. In the phase-shifting mask (PSM), various elements in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase-shifting mask may be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 834 are used in a variety of processes. Such a mask(s) are used, for example, in an ion implantation process for forming various doped regions in the semiconductor wafer, in an etching process for forming various etched regions in the semiconductor wafer, and / or in other suitable processes.

[0229] IC fab 840 is an IC manufacturing facility that includes one or more manufacturing sites for producing a variety of different IC products. In some embodiments, IC fab 840 is a semiconductor foundry. For example, one manufacturing site may be dedicated to front-end manufacturing of a variety of IC products (front-end of line (FEOL) manufacturing), while a second manufacturing site may provide back-end manufacturing for interconnecting and packaging the IC products (back-end of line (BEOL) manufacturing), and a third manufacturing site may provide other services for the foundry business.

[0230] IC fab 840 uses the mask (or masks) produced by mask facility 830 to fabricate IC device 860. Thus, IC fab 840 at least indirectly uses IC design layout 822 to fabricate IC device 860. In some embodiments, a semiconductor wafer 842 is fabricated by IC fab 840 using the mask (or masks) to form IC device 860. Semiconductor wafer 842 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafers further include one or more of various doped regions, dielectric elements, multilayer interconnects, and the like (formed during subsequent fabrication steps).

[0231] Details of an integrated circuit (IC) manufacturing system (e.g. System 800 from Fig.8) and a linked IC manufacturing process can be found, for example, in US 9 256 709 B2, US 2015 / 0 278 429 A1, US 2014 / 0 040 838 A1 and US 7 260 442 B2.

[0232] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] Memory cell (100C) comprising: a first pull-up transistor (PU0) having a first active region (302a) extending in a first direction (X) and arranged on a first plane; a first pass-gate transistor (PG2) having a second active region (301a) extending in the first direction (X), the second active region being disposed on the first plane and being spaced from the first active region (302a) in a second direction (Y) different from the first direction, and the second active region being adjacent to the first active region (302a); a second pull-up transistor (PU1); a second pass-gate transistor (PG3) coupled to the second pull-up transistor (PU1); and a first metal contact (310e) extending in the second direction (Y) and extending from the first active region (302a) to the second active region (301a), the first metal contact being arranged on a second level different from the first level, the first metal contact electrically connecting a drain (303a2) of the first pull-up transistor (PU0) to a drain (305a2) of the first pass-gate transistor (PG2); wherein the first pass-gate transistor (PG2), the second pass-gate transistor (PG3), the first pull-up transistor (PU0) and the second pull-up transistor (PU1) are part of a four-transistor (4T) memory cell; and wherein the memory cell (100C) further comprises: a group of gates (304a, 304b) comprising a first gate (304a) and a second gate (304b); wherein the first gate (304a) extends in the second direction (Y), overlaps the first active region (302a) or the second active region (301a) and is arranged on the second level. [2] Memory cell (100C) according to claim 1, wherein: the second pull-up transistor (PU1) has a third active region (302b) extending in the first direction (X), the third active region being arranged on the first level and spaced from the first active region (302a) in the first direction; the second pass-gate transistor (PG3) has a fourth active region (301b) extending in the first direction (X), wherein the fourth active region is arranged on the first plane, is spaced from the third active region (302b) in the second direction (Y), and is spaced from the second active region (301a) in the first direction, and wherein the fourth active region is adjacent to the third active region; and wherein the memory cell (100C) further comprises a second metal contact (310f) extending in the second direction (Y) and extending from the third active region (302b) to the fourth active region (301b), the second metal contact being arranged on the second level and electrically connecting a drain (303b1) of the second pull-up transistor (PU1) to a drain (305b1) of the second pass-gate transistor (PG3). [3] The memory cell (100C) of claim 2, wherein the second gate (304b) extends in the second direction (Y), overlaps the third active region (302b) or the fourth active region (301b), and is arranged on the second level. [4] The memory cell (100C) of claim 3, further comprising: a first group of conductive structures (312a, ..., 312f) extending in the first direction (X) and overlapping at least the first active region (302a), the second active region (301a), the third active region (302b), the fourth active region (301b) or the group of gates (304a, 304b), wherein each conductive structure of the first group of conductive structures is spaced from an adjacent conductive structure of the first group of conductive structures in at least the first direction (X) or the second direction (Y) and is arranged on a third level that is different from the first level and the second level. [5] Memory cell (100C) according to claim 4, further comprising: a first group of vias (314a, ..., 314j) between the first group of conductive structures (312a, ..., 312f) and the first active region (302a) and the second active region (301a), wherein the first group of vias couples the first group of conductive structures to at least one of the first active region, the second active region, the third active region (302b), the fourth active region (301b), and the group of gates (304a, 304b); and wherein at least one via of the first group of vias is arranged where at least one conductive structure of the first group of conductive structures overlaps the first active region and / or the second active region. [6] The memory cell (100C) of claim 4, further comprising: a second group of conductive structures (318a, ..., 318e) extending in the second direction (Y) and overlapping at least the first active region (302a), the second active region (301a), the third active region (302b), the fourth active region (301b), or the first group of conductive structures (312a, ..., 312f), wherein each conductive structure of the second group of conductive structures is spaced in the first direction (X) from an adjacent structure of the second group of conductive structures and is arranged on a fourth level that is different from the first level, the second level, and the third level; and a second group of vias (320a, ..., 320e) between the second group of conductive structures (318a, ..., 318e) and the first group of conductive structures (312a, ..., 312f), wherein the second group of vias couples the second group of conductive structures to the first group of conductive structures, and wherein at least one via of the second group of vias is arranged where at least one conductive structure of the second group of conductive structures overlaps at least one conductive structure of the first group of conductive structures. [7] The memory cell (100C) of claim 6, further comprising: a third group of conductive structures (322a, ..., 322e) extending in the first direction (X) and overlapping at least the second group of conductive structures (318a, ..., 318e), wherein each conductive structure of the third group of conductive structures is spaced in the second direction (Y) from an adjacent structure of the third group of conductive structures and is arranged on a fifth level different from the first level, the second level, the third level, and the fourth level; and a third group of vias (326a, ..., 326e) between the third group of conductive structures (322a, ..., 322e) and the second group of conductive structures (318a, ..., 318e), wherein the third group of vias couples the third group of conductive structures to the second group of conductive structures, and wherein at least one via of the third group of vias is arranged where at least one conductive structure of the third group of conductive structures overlaps at least one conductive structure of the second group of conductive structures. [8] A method of forming a memory circuit (100B), the method comprising: Generating a layout design (200) of the memory circuit (100B) by a processor, the layout design having a cell edge (250), wherein generating the layout design comprises: Generating a first active area layout design (202a1) corresponding to the fabrication of a first active area (302a) of a first pull-down transistor (PDo), wherein the first active area layout design extends in a first direction (X) and is arranged on a first level; Generating a second active area layout design (202b1) corresponding to the fabrication of a second active area (301a) of a first pass-gate transistor (PG0), wherein the second active area layout design extends in the first direction (X), is arranged on the first level, and is spaced from the first active area layout design (202a1) in a second direction (Y) different from the first direction; Generating a third active area layout design (202a2) corresponding to the fabrication of a third active area (302b) of a second pull-down transistor (PD1), wherein the third active area layout design extends in the first direction (X), is arranged on the first level, and is coupled to the first active area layout design (202a1); Generating a fourth active area layout design (202b2) corresponding to the fabrication of a fourth active area (301b) of a second pass-gate transistor (PG1), wherein the fourth active area layout design extends in the first direction (X), is arranged on the first level, is coupled to the third active area layout design (202b1) in the second direction (Y), and is spaced from the second active area layout design (202a2) in the first direction (X); Generating a first metal contact layout design (210a) corresponding to the production of a first metal contact (310a), wherein the first metal contact layout design extends in the second direction (Y), the cell edge (250) of the memory circuit (100B) and the first active area layout design (202a1) overlap and is arranged on a second level different from the first level, and wherein the first metal contact is electrically connected to a source (303a1) of the first pull-down transistor (PDo); and Generating a second metal contact layout design (210b) corresponding to the production of a second metal contact (310b), wherein the second metal contact layout design extends in the second direction (Y), overlaps the cell edge (250) of the memory circuit (100B) and the third active area layout design (202a2) and is arranged on the second level, and wherein the second metal contact is electrically connected to a source (303b2) of the second pull-down transistor (PD1); Generating a third metal contact layout design (210e) corresponding to the production of a third metal contact (310e), wherein the third metal contact layout design extends in the second direction (Y) and extends from the first active area layout design (202a1) to the second active area layout design (202b1), wherein the third metal contact is arranged on the second level, and wherein the third metal contact electrically connects a drain (303a2) of the first pull-down transistor (PDo) to a drain (305a2) of the first pass-gate transistor; Generating a first gate layout design (204a) corresponding to the fabrication of a first gate (304a), extending in the second direction (Y), overlapping the first active area layout design (202a1) or the second active area layout design (202b1) and arranged on the second level; and Manufacturing the memory circuit (100B) based on the layout design, wherein the memory circuit is a four transistor (4T) memory cell including the first pass-gate transistor (PG0), the second pass-gate transistor (PG1), the first pull-down transistor (PDo), and the second pull-down transistor (PD1). [9] The method of claim 8, wherein generating the layout design (200) further comprises: Generating a fourth metal contact layout design (210f) corresponding to the production of a fourth metal contact (310f), wherein the fourth metal contact layout design extends in the second direction (Y) and extends from the third active area layout design (202a2) to the fourth active area layout design (202b2), wherein the fourth metal contact layout design is arranged on the second level, and wherein the fourth metal contact electrically connects a drain (303b1) of the second pull-down transistor (PD1) to a drain (305b1) of the second pass-gate transistor. [10] The method of claim 9, wherein generating the layout design comprises: Generating a group of gate layout designs (204a, 204b) corresponding to the fabrication of a group of gates (304a, 304b), the group of gate layout designs comprising the first gate layout design (204a) and a second gate layout design (204b); and wherein the second gate layout design (204b) extends in the second direction (Y), overlaps the third active area layout design (202a2) or the fourth active area layout design (202b2) and is arranged on the second level. [11] The method of claim 10, wherein generating the layout design (200) further comprises: Generating a first group of conductive structure layout designs (212a, ..., 212f) corresponding to the production of a first group of conductive structures (312a, ..., 312f), wherein the first group of conductive structure layout designs extends in the first direction (X) and overlaps at least the first active area layout design (202a1), the second active area layout design (202b1), the third active area layout design (202a2), the fourth active area layout design (202b2) or the group of gate layout designs (204a, 204b), wherein each conductive structure layout design of the first group of conductive structure layout designs is separated in at least the first direction or the second direction from an adjacent conductive structure layout design of the first group of conductive structure layout designs spaced apart and arranged on a third level different from the first level and the second level. [12] The method of claim 11, wherein generating the layout design (200) further comprises: Generating a first group of via layout designs (214a, ..., 214j) corresponding to the production of a first group of vias (314a, ..., 314j), wherein the first group of via layout designs lies between the first group of conductive structure layout designs (212a, ..., 212f) and the first active area layout design (202a1) and the second active area layout design (202b1), wherein the first group of vias comprises the first group of conductive structures (312a, ..., 312f) to at least the first active region (302a), the second active region (301a), the third active region (302b), the fourth active region (301b) or the group of gates, and at least one via layout design of the first group of via layout designs is arranged where at least one conductive structure layout design of the first group of conductive structure layout designs overlaps the first active region layout design and / or the second active region layout design. [13] The method of claim 12, wherein generating the layout design (200) further comprises: Generating a second group of conductive structure layout designs (218a, ..., 218e) corresponding to the production of a second group of conductive structures (318a, ..., 318e), wherein the second group of conductive structure layout designs extends in the second direction (Y) and overlaps at least the first active area layout design (202a1), the second active area layout design (202b1), the third active area layout design (202a2), the fourth active area layout design (202b2), or the first group of conductive structure layout designs (212a, ..., 212f), wherein each conductive structure layout design of the second group of conductive structure layout designs is spaced in the first direction (X) from an adjacent layout design of the second group of conductive structure layout designs and is arranged on a fourth level different from the first level, the second level and the third level; and Generating a second group of via layout designs (220a, ..., 220e) corresponding to the production of a second group of vias (320a, ..., 320e), wherein the second group of via layout designs is located between the second group of conductive structure layout designs (218a, ..., 218e) and the first group of conductive structure layout designs (212a, ..., 212f), wherein the second group of vias couples the second group of conductive structures (318a, ..., 318e) to the first group of conductive structures (312a, ..., 312f), and wherein at least one via layout design of the second group of via layout designs is arranged where at least one conductive structure layout design of the second group of conductive structure layout designs overlap at least one conductive structure layout design of the first group of conductive structure layout designs. [14] The method of claim 13, wherein generating the layout design (200) further comprises: Generating a third group of conductive structure layout designs (222a, ..., 222e) corresponding to the fabrication of a third group of conductive structures (322a, ..., 322e), wherein the third group of conductive structure layout designs extends in the first direction (X) and overlaps at least the second group of conductive structure layout designs, wherein each conductive structure layout design of the third group of conductive structure layout designs is spaced in the second direction (Y) from an adjacent layout design of the third group of conductive structure layout designs and is arranged on a fifth level that is different from the first level, the second level, the third level, and the fourth level; and Generating a third group of via layout designs (226a, ..., 226e) corresponding to the production of a third group of vias (326a, ..., 326e), wherein the third group of via layout designs is located between the third group of conductive structure layout designs (222a, ..., 222e) and the second group of conductive structure layout designs (218a, ..., 218e), wherein the third group of vias couples the third group of conductive structures (322a, ..., 322e) to the second group of conductive structures (318a, ..., 318e), and at least one via layout design of the third group of via layout designs is arranged where at least one conductive structure layout design of the third group of conductive structure layout designs overlap at least one conductive structure layout design of the second group of conductive structure layout designs (218a, ..., 218e). [15] Memory cell (100B) comprising: a first pull-down transistor (PD0) having a first active region (302a) extending in a first direction (X) and arranged on a first plane; a first pass-gate transistor (PG0) having a second active region (301a) extending in the first direction (X), the second active region being arranged on the first level and being spaced from the first active region (302a) in a second direction (Y) different from the first direction; a second pull-down transistor (PD1) having a third active region (302b) extending in the first direction (X), the third active region being arranged on the first plane and spaced from the first active region (302a) in the first direction; a second pass-gate transistor (PG1) having a fourth active region (301b) extending in the first direction (X), the fourth active region being arranged on the first level, being spaced from the third active region (302b) in the second direction (Y), and being spaced from the second active region (301a) in the first direction; a first metal contact (310e) extending in the second direction (Y) and extending from the first active region (302a) to the second active region (301a), wherein the first metal contact is arranged on a second level different from the first level, wherein the first metal contact electrically connects a drain (303a2) of the first pull-down transistor (PD0) to a drain (305a2) of the first pass-gate transistor; and a second metal contact (310f) extending in the second direction (Y) and extending from the third active region (302b) to the fourth active region (301b), the second metal contact being arranged on the second level, and electrically connecting a drain (303b1) of the second pull-down transistor (PD1) to a drain (305b1) of the second pass-gate transistor (PG1), wherein the first pass-gate transistor (PG0), the second pass-gate transistor (PG1), the first pull-down transistor (PD0), and the second pull-down transistor (PD1) are part of a four-transistor (4T) memory cell; and wherein the memory cell (100B) further comprises: a group of gates (304a, 304b) comprising: a first gate (304a) extending in the second direction (Y), overlapping the first active region (302a) or the second active region (301a) and arranged on the second level; and a second gate (304b) extending in the second direction (Y), overlapping the third active region (302b) or the fourth active region (301b) and arranged on the second level. [16] The memory cell (100B) of claim 15, further comprising: a first group of conductive structures (312a, ..., 312f) extending in the first direction (X) and overlapping at least the first active region (302a), the second active region (301a), the third active region (302b), the fourth active region (301b) or the group of gates (304a, 304b), wherein each conductive structure of the first group of conductive structures is spaced in at least the first direction or the second direction (Y) from an adjacent conductive structure of the first group of conductive structures and is arranged on a third level that is different from the first level and the second level; and a first group of vias (314a, ..., 314j) between the first group of conductive structures (312a, ..., 312f) and the first active region (302a) and the second active region (301a), wherein the first group of vias couples the first group of conductive structures to at least one of the first active region, the second active region, the third active region (302b), the fourth active region (301b), and the group of gates (304a, 304b); and wherein at least one via of the first group of vias is arranged where at least one conductive structure of the first group of conductive structures overlaps the first active region and / or the second active region. [17] The memory cell (100B) of claim 16, further comprising: a second group of conductive structures (318a, ..., 318e) extending in the second direction (Y) and overlapping at least the first active region (302a), the second active region (301a), the third active region (302b), the fourth active region (301b), or the first group of conductive structures (312a, ..., 312f), wherein each conductive structure of the second group of conductive structures is spaced in the first direction (X) from an adjacent structure of the second group of conductive structures and is arranged on a fourth level that is different from the first level, the second level, and the third level; and a second group of vias (320a, ..., 320e) between the second group of conductive structures (318a, ..., 318e) and the first group of conductive structures (312a, ..., 312f), wherein the second group of vias couples the second group of conductive structures to the first group of conductive structures, and wherein at least one via of the second group of vias is arranged where at least one conductive structure of the second group of conductive structures overlaps at least one conductive structure from the first group of conductive structures. [18] The memory cell (100B) of claim 17, further comprising: a third group of conductive structures (322a, ..., 322e) extending in the first direction (X) and overlapping at least the second group of conductive structures (318a, ..., 318e), wherein each conductive structure of the third group of conductive structures is spaced in the second direction (Y) from an adjacent structure of the third group of conductive structures and is arranged on a fifth level different from the first level, the second level, the third level, and the fourth level; and a third group of vias (326a, ..., 326e) between the third group of conductive structures (322a, ..., 322e) and the second group of conductive structures (318a, ..., 318e), wherein the third group of vias couples the third group of conductive structures to the second group of conductive structures, and wherein at least one via of the third group of vias is arranged where at least one conductive structure of the third group of conductive structures overlaps at least one conductive structure of the second group of conductive structures. [19] The memory cell (100B) of claim 18, wherein the first group of vias (314a, ..., 314j) comprises: a first via (314i) of the first group of vias (314a, ..., 314j) electrically coupling the first gate (304a) to a first conductive structure (312f) of the first group of conductive structures (312a, ..., 312f); and a second via (314j) of the first group of vias (314a, ..., 314j) electrically coupling the second gate (304b) to the first conductive structure (312f) of the first group of conductive structures (312a, ..., 312f); wherein the second group of vias (320a, ..., 320e) comprises: a first via (320b) of the second group of vias (320a, ..., 320e) electrically coupling the first conductive structure (312f) of the first group of conductive structures (312a, ..., 312f) to a first conductive structure (318b) of the second group of conductive structures (318a, ..., 318e); and a second via (320c) of the second group of vias (320a, ..., 320e) electrically coupling the first conductive structure (312f) of the first group of conductive structures (312a, ..., 312f) to a second conductive structure (318d) of the second group of conductive structures (318a, ..., 318e); and wherein the third group of vias (326a, ..., 326e) comprises: a first via (326b) of the third group of vias (326a, ..., 326e) electrically coupling a first conductive structure (322e) of the third group of conductive structures (322a, ..., 322e) to a third conductive structure (318c) of the second group of conductive structures (318a, ..., 318e), wherein the first conductive structure (322e) of the third group of conductive structures (322a, ..., 322e) corresponds to a power supply rail coupled to a voltage supply or a reference voltage.

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