COVER LAYERS IN METAL GATES OF TRANSISTORS AND ASSOCIATED MANUFACTURING METHODS

Abstract

A method of forming a semiconductor device, the method comprising: forming (218) a gate electrode (70) in a wafer (10) comprising: depositing a work function layer (120); performing a first treatment (304) on the wafer (10), wherein the first treatment (304) is performed using TiCl4, wherein the work function layer (120) is exposed to the TiCl4; after the first treatment (304), performing a second treatment (306) on the wafer (10), wherein the second treatment (306) is performed by soaking the wafer (10) using a first silicon-containing gas; after the second treatment (306), forming (310, 310') a first metal cap layer (126) over the work function layer (120); anddepositing (318) a filler metal (132) over the first metal cover layer (126).

Description

GENERAL STATE OF THE ARTMetal-oxide-semiconductor (MOS) devices are basic integrated circuit devices. An existing MOS device typically has a gate electrode formed of polysilicon doped with p-type or n-type impurities using doping operations such as ion implantation or thermal diffusion. The work function of the gate electrode may be adjusted to the band edge of silicon. For an n-type metal oxide semiconductor (NMOS) device, the work function may be adjusted close to the conduction band of silicon. For a p-type metal oxide semiconductor (NMOS) device, the work function may be adjusted close to the valence band of silicon. Adjusting the work function of the polysilicon gate electrode may be achieved by selecting appropriate impurities.MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as a poly depletion effect. The poly depletion effect occurs when the applied electric fields strip carriers from gate regions near gate dielectrics, thereby forming depletion layers. In an n-doped polysilicon layer, the depletion layer has ionized non-mobile donor sites, and in a p-doped polysilicon layer, the depletion layer has ionized non-mobile acceptor sites. The depletion effect leads to an increase in the effective gate dielectric thickness, making it difficult to form an inversion layer on the surface of the semiconductor.The poly depletion problem can be solved by forming metal gate electrodes, wherein the metal gates used in NMOS devices and PMOS devices may also have band edge work. Accordingly, the resulting metal gates include multiple layers to meet the requirements of the NMOS devices and PMOS devices.Forming metal gates typically includes depositing metal layers and then performing chemical mechanical polishing (CMP) to remove excess portions of the metal layers. The remaining portions of the metal layers form metal gates.US 2016 / 0118261 A1 relates to methods for depositing thin layers of TiAl or TaAl, wherein, after depositing such a thin layer, a protection treatment is carried out in order to deposit silicon or boron on the TiAl or TaAl layer.US 2018 / 0040620 A1 describes an integrated circuit having fins and a plurality of conductive stack structures extending transversely to the fins. The plurality of conductive stack structures includes a gate stack structure that includes a first conductive metal nitride layer and has a first effective work function. Further, the plurality of conductive stack structures includes an isolation stack structure adjacent to the gate stack structure and including a second conductive metal nitride layer and having a second effective work function different from the first effective work function, wherein the second conductive metal nitride layer includes the same metal nitride as a metal nitride included in the first conductive metal nitride layer and has a different thickness than the first conductive metal nitride layer.US 2014 / 0273428 A1 describes that the negative effect of oxygen on some metal layers can be reduced or prevented by contact of the layers with a treatment agent which comprises silane or borane. One or more layers in an NMOS gate stack are contacted with a treatment agent containing silane or borane during or after deposition.BRIEF DESCRIPTION OF THE DRAWINGSThe aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be appreciated that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.FIGS. 1-6, 7A, 7B, 8, 9A, 9B, 19, and 20 illustrate the perspective and cross-sectional views of intermediate stages in forming a fin field effect transistor (FinFET), in accordance with some embodiments.FIGS. 10-18 illustrate the perspective and cross-sectional views of intermediate stages in forming a gate stack of a transistor, in accordance with some embodiments.FIGS. 21 and 22 illustrate the experiment results according to some embodiments. FIG. 23 illustrates a process flow for forming a FinFET, in accordance with some embodiments. FIG. 24 illustrates a process flow for forming a gate stack, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "underlying", "below", "lower", "overlying", "upper", and the like may be used herein for convenience in description to describe the relationship of an element or feature to (another) element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise (rotated 90 degrees or oriented with other orientations) and the spatially relative descriptors used herein may accordingly be interpreted equally.Transistors having replacement gates and the methods of forming the same are provided according to various embodiments. The intermediate stages of forming the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. In the illustrated embodiments, forming fin field effect transistors (FinFETs) is used as an example for explaining the concept of the present disclosure. Planar transistors may also take on the concept of the present disclosure. According to some embodiments of the present disclosure, a silicon-containing soak (treatment) process is performed after forming a work function layer and before the fill metal of the metal gate is deposited. The silicon-containing layer resulting from the silicon-containing soak process has the function of preventing the metal from propagating upward in the work function layer to affect the work function and preventing oxygen from propagating downward into the work function layer.FIGS. 1-8, 9A, 9B, 19, and 20 illustrate the cross-sectional and perspective views of intermediate stages in forming a fin field effect transistor (FinFET), in accordance with some embodiments of the present disclosure. The processes shown in these figures are also schematically illustrated in the process flow 200 shown in FIG. 23.In FIG. 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The semiconductor substrate 20 may be a part of a wafer 10, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer substrate or gradient substrate may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, Al-GaAs GaInAs, GaInP, and / or GaInAsP; or combinations thereof.With continued reference to FIG. 1, a well region 22 is formed in the substrate 20. The respective process is illustrated as process 202 in process flow 200 shown in FIG. 23. According to some embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting an n-type impurity, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting a p-type impurity, which may be boron, indium, or the like, into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type impurity or p-type impurity concentration may be 1018 cm -3 or less, such as in the range between about 1017 cm -3 and about 1018 cm -3.Referring to FIG. 2, isolation regions 24 are formed to extend from a top surface of the substrate 20 into the substrate 20. The isolation regions 24 are alternatively referred to below as shallow trench isolation (STI) regions. The respective process is illustrated as process 204 in process flow 200 shown in FIG. 23. The portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein a top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 functions as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. the pad oxide layer 28 may also function as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitriding of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etch mask to form the hard masks 30, as shown in FIG. 2.Next, the patterned hard mask layer 30 is used as an etch mask for etching the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with (a) dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric materials, and the remaining portions of the dielectric material / materials are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material over the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like. The dielectric material over the liner dielectric may include silicon oxide, in accordance with some embodiments.The top surfaces of the hard masks 30 and the top surfaces of the STI regions 24 may be at substantially the same height. The semiconductor strips 26 are between adjacent STI regions 24. In some embodiments of the present disclosure, the semiconductor strips 26 are portions of the original substrate 20 and thus the material of the semiconductor strips 26 is the same as that of the substrate 20. Accordingly, the semiconductor strips 26 are formed of a semiconductor material different from that of the substrate 20. In some embodiments, the semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.Referring to FIG. 3, the STI regions 24 are recessed such that the top portions of the semiconductor strips 26 protrude higher than the top surfaces 24A of the remaining portions of the STI regions 24 to form protruding fins 36. The respective process is illustrated as process 206 in process flow 200 shown in FIG. 23. The etching may be performed using a dry etching process, wherein HF 3 and NH 3 are used as the etching gases, for example. Plasma may be generated during the etching process. Argon can also be absorbed. According to alternative embodiments of the present disclosure, the recessing of the STI regions 24 is performed using a wet etching process. The etching chemical may include, for example, HF.In the embodiments illustrated above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, enabling patterns to be generated having, for example, slopes that are smaller than what otherwise can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the fins.Referring to FIG. 4, the dummy gate stacks 38 are formed to extend on the top surfaces and the sidewalls of the (protruding) fins 36. The respective process is illustrated as process 208 in process flow 200 shown in FIG. 23. Dummy gate stacks 38 may include dummy gate dielectrics 40 and dummy gate electrodes 42 over dummy gate dielectrics 40. The dummy gate electrodes 42 may be formed using polysilicon, for example, and other materials may also be used. Each of the dummy gate stacks 38 may also include one (or more) hard mask layer 44 over the dummy gate electrodes 42. The hard mask layers 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multilayers thereof. Dummy gate stacks 38 may traverse a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stacks 38 also have longitudinal directions perpendicular to the longitudinal directions of the protruding fins 36.Next, gate spacers 46 are formed on the sidewalls of the dummy gate stacks 38. The respective process is also shown as process 208 in process flow 200 shown in FIG. 23. According to some embodiments of the present disclosure, the gate spacers 46 are formed of (a) dielectric material(s) such as silicon nitride, silicon carbonitride, or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers.An etching process is then performed to etch the portions of the protruding fins 36 not covered by the dummy gate stacks 38 and the gate spacers 46, resulting in the structure shown in FIG. 5. The respective process is illustrated as process 210 in process flow 200 shown in FIG. 23. The recess may be anisotropic, and thus the portions of the fins 36 that are directly below the dummy gate stacks 38 and the gate spacers 46 are protected and not etched. The top surfaces of the recessed semiconductor strips 26 may be lower than the top surfaces 24A of the STI regions 24, in accordance with some embodiments. The recesses 50 are accordingly formed. The recesses 50 include portions that are on the opposing sides of the dummy gate stacks 38 and portions between remaining portions of the protruding fins 36.Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) a semiconductor material in the recesses 50, resulting in the structure in FIG. 6. The respective process is illustrated as process 212 in process flow 200 shown in FIG. 23. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be doped in situ with the progress of epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP) may be grown. According to alternative embodiments of the present disclosure, epitaxy regions 54 include III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the recesses 50 are filled with the epitaxy regions 54, further epitaxially growing the epitaxy regions 54 causes the epitaxy regions 54 to extend horizontally, and facets may be formed. Further growing the epitaxy regions 54 may also cause adjacent epitaxy regions 54 to merge with each other. Gaps (air gaps) 56 may be created. According to some embodiments of the present disclosure, the formation of the epitaxy regions 54 may be finished when the upper surface of the epitaxy regions 54 is still wavy, or when the upper surface of the merged epitaxy regions 54 has become planar, which is achieved by further growing on the epitaxy regions 54, as shown in FIG. 6.After the epitaxy step, the epitaxy regions 54 may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral 54. According to alternative embodiments of the present disclosure, the implantation step is skipped when the epitaxial regions 54 are on-site doped with the p-type or n-type impurity during epitaxy.FIG. 7A illustrates a perspective view of the structure after forming the contact etch stop layer (CESL) 58 and the inter-layer dielectric (ILD) 60. The CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 60 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or other deposition process. The ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as tetraethylorthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, may be performed to level the top surfaces of the ILD 60, dummy gate stacks 38, and gate spacers 46.FIG. 7B illustrates the reference cross-section 7B- 7B in FIG. 7A, in which the dummy gate stacks 38 are illustrated. Next, the dummy gate stacks 38 including the hard mask layers 44, the dummy gate electrodes 42, and the dummy gate dielectrics 40 are etched, forming trenches 62 between the gate spacers 46, as shown in FIG. 8. The respective process is illustrated as process 216 in process flow 200 shown in FIG. 23. The top surfaces and the sidewalls of the protruding fins 36 are exposed to the trenches 62. Next, as shown in FIGS. 9A and 9B, the replacement gate stacks 72 are formed in the trenches 62 (FIG. 8 ). FIG. 9B illustrates the reference cross-section 9B- 9B in FIG. 9A. The respective process is illustrated as process 218 in process flow 200 shown in FIG. 23. The replacement gate stacks 72 include gate dielectrics 68 and the corresponding gate electrodes 70.According to some embodiments of the present disclosure, a gate dielectric 68 includes an interface layer (IL) 64 as its lower portion. The IL 64 is formed on the exposed surfaces of the protruding fins 36. The IL 64 may include an oxide layer, such as a silicon oxide layer, formed by the thermal oxidation of the protruding fins 36, a chemical oxidation process, or a deposition process. The gate dielectric 68 may also include a high-k dielectric layer 66 formed over the IL 64. The high-k dielectric layer 66 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, and may sometimes have a height of 21.0 or more. The high-k dielectric layer 66 overlies and may contact the IL 64. The high-k dielectric layer 66 is formed as a conformal layer and extends on the sidewalls of the protruding fins 36 and the top surface and sidewalls of the gate spacers 46. In accordance with some embodiments of the present disclosure, the high-k dielectric layer 66 is formed using ALD, CVD, PECVD, molecular-beam deposition (MBD), or the like.With continued reference to FIG. 9B, the gate electrode 70 is formed on the gate dielectric 68. The gate electrode 70 may include a plurality of metal-containing layers 74, which may be formed as conformal layers, and a fill metal region 76 that fills the remainder of the trenches not filled by the plurality of metal-containing layers 74. The metal-containing layers 74 may include a barrier layer, a work function layer over the barrier layer, and one or more metal capping layers over the work function layer. The detailed structure of the metal-containing layers 74 will be discussed with reference to Figures 10 through 18.FIG. 9B schematically illustrates the region 78 in which a portion of the fin 36, a portion of the gate dielectric 68, a portion of the metal-containing layers 74, and a portion of the fill metal region 76 are included. FIGS. 10-17 illustrate forming the features extending into region 78, in accordance with some embodiments. The respective process flow is illustrated as process flow 300 as shown in FIG. 24.It will be appreciated that the processes as shown in FIGS. 10-17 include the possible processes that may be implemented in forming gate stacks. According to some embodiments of the present disclosure, some, but not all, of these processes are performed and the resulting structure includes some, but not all, of the illustrated features as shown in FIG. 17. The possible combinations will be discussed. If a process is not formed, a respective overlying layer that is directly over the skipped process / layer / s will contact a respective underlying layer that is directly under the skipped process / layer / s.Referring to FIG. 10, IL 64 is formed on protruding fin 36. High-k dielectric layer 66 is formed over IL 64. In some embodiments, an adhesion layer (which is also a diffusion barrier layer) 119 is formed over the high-k dielectric layer 66. The adhesion layer 119 may be formed of TiN or titanium silicon nitride (TSN). The TiN layer may be formed using ALD or CVD, and the TSN layer may include TiN layers and SiN layers deposited alternately, which are formed using, for example, ALD. Since the TiN layers and the SiN layers are very thin, these layers may not be distinguished from each other and are thus referred to as a TSN layer.The work function layer 120 is formed over the adhesion layer 119. The work function layer 120 determines the work function of the gate and includes at least one layer or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer 120 may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work function layer 120 may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. It is understood that the work function layers may include different materials, which are also considered.According to some embodiments of the present disclosure, a metal capping layer 122 is formed over the work function layer 120, as shown in FIG. 11. The respective process is illustrated as process 302 in process flow 300 shown in FIG. 24. The metal capping layer 122 may be formed of a metal nitride such as TiN, in accordance with some embodiments, and other materials such as TaN may be used. According to other embodiments, the metal capping layer 122 comprises the metal nitride and is free of the TaN. According to some embodiments, the metal capping layer 122 is formed using ALD. The thickness of the metal capping layer 122 may be in the range of between about 0.5 nm and about 6 nm. According to alternative embodiments, forming the metal capping layer 122 is skipped and the impregnation steps may be performed directly on the work function layer 120 as shown in FIGS. 11 and 12. Accordingly, the metal capping layer 122 is illustrated using dashed lines to indicate that it may or may not be formed.FIG. 11 illustrates a metal or chlorine-containing gas soaking process using a gaseous precursor. According to some embodiments, the precursor comprises a titanium-containing gas and / or a chlorine-based gas. For example, the precursor may include TiCl 4 as a process gas. When the TiCl 4 is used, the corresponding impregnation process may also be referred to as a TiCl 4- impregnation process. The respective process is illustrated as process 304 in process flow 300 shown in FIG. 24. This process is advantageous when the metal capping layer 122 is not formed and the metal or chlorine-containing gas impregnation is performed on the work function layer 120 exposed to TiCl 4. According to some embodiments, TiCl 4, which is a gas, is provided to soak wafer 10, exposing either work function layer 120 or metal capping layer 122. During metal or chlorine-containing gas soaking, wafer 10 is heated, for example, to a temperature in the range of between about 200°C and about 500°C. No plasma is generated. The soaking time may be greater than about 5 seconds. The TiCl 4- impregnation results in the resulting molecules (such as TiCl 3- molecules) being bonded to the free bonds of the underlying work function layer 120. According to some embodiments in which the metal capping layer 122 is formed, the metal or chlorine-containing gas impregnation process may be performed or skipped. The metal or chlorine-containing gas soak process is used to improve the bonding of silicon to the underlying work function layer 120, as the silicon-containing gas as provided in the subsequent silicon-containing gas soak does not have good adhesion to the work function layer 120. In comparison, in the TiCl4 soak, Ti- and Cl-containing molecules are attached to the work function layer 120, and the silicon-containing molecules subsequently applied have a good bond to the Ti atoms in the TiCl 4. Accordingly, when the silicon-containing gas treatment discussed below is performed on the work function layer 120, the TiCl 4 is used to improve the bonding of the silicon-containing molecules to the work function layer 120.According to some embodiments in which the forming of the metal capping layer 122 is skipped, the precursor used for the impregnation process may be simultaneously performed when the work function layer 120 is formed, instead of being used after the forming of the work function layer 120.FIG. 12 illustrates a thermal soak process using a silicon-containing gas, which may be SiH4, Si2H6, or the like, or combinations thereof. The respective process is illustrated as process 306 in process flow 300 shown in FIG. 24. During silicon-containing gas soaking, wafer 10 is heated, for example, to a temperature in the range of between about 200°C and about 550°C when SiH4is used, and to a higher temperature in the range of between about 200°C and about 500°C when Si2H6is used. No plasma is generated. The soaking time may range from about 30 seconds to about 600 seconds. In the embodiments in which the metal or chlorine-containing gas soak process is performed using TiCl 4 a thin silicon and titanium-rich layer may be formed on the illustrated surface in FIG. 12. When the gas impregnation containing metal or chlorine is not performed, the Si atoms are fixed to the work function layers 120 or the metal capping layer 122.FIG. 12 schematically illustrates the silicon-containing layer 124 to depict the attached silicon-containing molecules that have silicon and hydrogen atoms and possible titanium and chlorine atoms when the TiCl 4- impregnation was performed.The forming of the work function layer 120, the forming of the metal capping layer 122, the metal or chlorine-containing gas soak process, and the silicon-containing gas soak process are performed in-situ so that no vacuum stop occurs between these processes. These processes may be performed in different process chambers residing in a same platform that has a same vacuum environment.Referring to FIG. 13, vacuum fracture may be performed after silicon-containing gas soaking. The respective process is illustrated as process 308 in process flow 300 shown in FIG. 24. Due to the silicon-containing layer 124 being exposed to air, the silicon-containing layer 124 is oxidized to form a silicon oxide layer 124', as shown in FIG. 13. It is understood that in subsequent thermal processes, the elements in adjacent layers may spread into the silicon oxide layer 124'. Accordingly, although referred to as a silicon oxide layer, layer 124' is actually a silicon and oxygen rich layer comprising other elements and may have its silicon and oxygen atoms higher than the corresponding silicon and oxygen atoms in the adjacent layer, which is initially free of silicon and / or oxygen.FIG. 14 illustrates the formation of the metal capping layer 126. The respective process is illustrated as process 310 in process flow 300 shown in FIG. 24. The formation method, the material, the thickness, etc. of the metal covering layer 126 may be selected from the candidate methods, candidate materials, candidate thicknesses of the metal covering layer 122. The details are thus not repeated.According to alternative embodiments, instead of performing a vacuum stop after the silicon-containing gas soak and before forming the metal capping layer 126, the vacuum stop may be performed after forming the metal capping layer 126 overlying and contacting the silicon-containing layer 124. The respective processes are shown as processes 310' and 308'. Because the metal capping layer 126 is very thin, for example, in the range of between about 0.5 nm and 6 nm, oxygen permeates through the metal capping layer 126 and the silicon-containing layer 124 is oxidized to form the silicon oxide layer 124'.FIG. 15 illustrates the optional second silicon-containing gas soaking process. The respective process is illustrated as process 312 in process flow 300 shown in FIG. 24. The second silicon-containing gas soak process may be performed using process conditions similar to those of the first silicon-containing gas soak process discussed with reference to FIG. 12. Accordingly, a silicon-containing layer 128 is formed to terminate the free bonds of the metal capping layer 126. The second SiH 4- soaking process is performed in a vacuum chamber. According to some embodiments of the present disclosure, a vacuum stop is performed after the second silicon-containing gas soak process (and before forming the metal capping layer 130) to convert the silicon-containing layer 128 into a silicon oxide layer (128' as shown in FIG. 16 ). The respective process is illustrated as process 314 in process flow 300 shown in FIG. 24.FIG. 16 illustrates the optional formation of the metal capping layer 130. The respective process is illustrated as process 316 in process flow 300 shown in FIG. 24. The formation method, the material, the thickness, etc. of the metal covering layer 130 may be selected from the candidate methods, candidate materials, candidate thicknesses, and the like for forming the metal covering layer 122. The details are thus not repeated. According to some embodiments, instead of performing the vacuum stop after the silicon-containing gas soaking process (FIG. 16 ) and before forming the metal capping layer 130, the vacuum stop may be performed after forming the metal capping layer 130. The respective processes are shown as processes 316' and 314' in the process flow 300 shown in FIG. 24. As a result of the vacuum stop, oxygen permeates through the metal capping layer 130 to convert the silicon-containing layer 128 (FIG. 15) into the silicon oxide layer 128' (FIG. 16). The silicon oxide layer 128' and the metal capping layer 130 are illustrated using dashed lines to indicate that these layers may or may not be formed. The layers 119, 120, 122, 124', 126, 128', and 130 in combination correspond to the stacked layers 74 in FIG. 9B.FIG. 17 illustrates the formation of the fill metal region 132 corresponding to the fill metal region 76 in FIG. 9B. The respective process is illustrated as process 318 in process flow 300 shown in FIG. 24. In some embodiments, the fill metal region 132 is formed of tungsten or cobalt, which may be formed using ALD, CVD, or the like. According to some embodiments, WF6and SiH 4 are used as process gases for depositing tungsten. After forming the fill metal region 132, a planarization process may be performed to remove excess portions of the deposited layers, as shown in FIG. 17, resulting in the gate stacks 72, as shown in FIGS. 9A and 9B. The respective planarization process is illustrated as process 320 in process flow 300 shown in FIG. 24. Throughout the specification, the layers between work function layer 120 and fill metal region 132, which may include layers 122, 124', 126, 128', and 130, are collectively referred to as a compound blocking layer.FIGS. 1-17 illustrate several possible processes, some of the processes being optional in some embodiments. Accordingly, multiple processes may be selected to form these candidate processes to implement multiple process flows. Thus, multiple gate stacks may be formed with different combinations of layers. Some of the possible processes are discussed below.In a first candidate process, the process sequence includes forming the metal capping layer 122 on the work function layer 120, performing a silicon-containing gas soak process (forming the silicon-containing layer 124), forming the metal capping layer 126, performing the vacuum stop, and forming the fill metal region 132. The respective gate stack may include the work function layer 120, the metal capping layer 122, the silicon oxide layer 124', the metal capping layer 126, and the fill metal region 132.In a second candidate process, the process sequence includes forming the metal capping layer 122 on the work function layer 120, performing a silicon-containing gas soak process (forming the silicon-containing layer 124), performing a vacuum stop, forming the metal capping layer 126, and forming the fill metal region 132. The respective gate stack is the same as the gate stack formed by the first candidate process and also includes the work function layer 120, the metal capping layer 122, the silicon oxide layer 124', the metal capping layer 126, and the fill metal region 132.In a third candidate process, the process sequence includes a metal or chlorine-containing gas soak process on the work function layer 120, performing a silicon-containing gas soak process (forming the silicon-containing layer 124), performing a vacuum stop, forming the metal capping layer 126, and forming the fill metal region 132. The respective gate stack may include work function layer 120, silicon oxide layer 124' (having Ti and Cl atoms therein), metal capping layer 126, and fill metal region 132.In a fourth candidate process, the process sequence includes performing a metal or chlorine-containing gas soak process on the work function layer 120, performing a silicon-containing gas soak process (forming the silicon-containing layer 124), forming the metal capping layer 126, performing a vacuum stop, and forming the fill metal region 132. The respective gate stack is the same as the gate stack formed by the third candidate process and also includes the work function layer 120, the silicon oxide layer 124' (having Ti and Cl atoms therein), the metal capping layer 126, and the fill metal region 132.In a fifth candidate process, the process sequence includes performing a metal or chlorine-containing gas soak process on the work function layer 120, performing a silicon-containing gas soak process, forming the metal capping layer 126, performing a vacuum stop, performing an additional silicon-containing gas soak process (forming the silicon-containing layer 128), forming the metal capping layer 130, performing a vacuum stop, and forming the fill metal region 132. The respective gate stack may include work function layer 120, silicon oxide layer 124' (having Ti and Cl atoms therein), metal capping layer 126, silicon oxide layer 128', metal capping layer 130, and fill metal region 132.FIG. 18 illustrates forming a gate stack according to alternative embodiments. According to some embodiments, a TSN layer 134 is formed over and may contact the work function layer 120. According to some embodiments, the TSN layer 134 is formed by performing one or more cycles, each of the cycles including forming a TiN layer by (one) ALD cycle / cycles, followed by forming a SiN layer by (one) ALD cycle / cycles. The TiN layer and the SiN layer are schematically illustrated as 134A and 134B, respectively, to schematically illustrate how the resulting TSN layer is formed. However, it should be understood that the TiN layer and the SiN are actually mixed together and cannot be distinguished from each other due to their small thickness and possibly cannot be distinguished from each other. There may be multiple alternating TiN layers and SiN layers, which are sometimes difficult to distinguish from each other due to inter-diffusion and thus are referred to in combination as TSN layer 134. The fill metal region 132 overlies and contacts the TSN layer 134. According to these embodiments, the silicon in the TSN layer 134 has the function of blocking downward oxygen spreading, upward metal spreading in the work function layer 120, and downward fluorine spreading (introduced during the formation of the fill metal region 132) in the work function layer 120.FIG. 19 illustrates the formation of hard masks 80 in accordance with some embodiments. The respective process is illustrated as process 220 in process flow 200 shown in FIG. 23. Forming the hard masks 80 may include performing an etching process to recess gate stacks 72 such that recesses are formed between gate spacers 46, filling the recesses with a dielectric material, and then performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the dielectric material. The hard masks 80 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.FIG. 20 illustrates the formation of source / drain contact plugs 82. Forming the source / drain contact plugs 82 includes etching the ILD 60 to expose the underlying portions of the CESL 58 and then etching the exposed portions of the CESL 58 to expose the source / drain regions 54. A metal nitride capping layer may be realized. An anneal process is then performed to react the metal layer with the top portion of the source / drain regions 54 to form silicide regions 84, as shown in FIG. 20. Next, either the previously formed metal nitride layer is left without being removed or the previously formed metal nitride layer is removed, followed by depositing a new metal nitride layer (such as a titanium nitride layer). A fill metal material, such as tungsten, cobalt, or the like, is then filled into the contact openings, followed by planarization to remove excess materials, resulting in the source / drain contact plugs 82. Gate contact plugs (not shown) are also formed to penetrate through a portion of each of the hard masks 80 to contact the gate electrodes 70. Thus, FinFETs 86 are formed that can be connected in parallel as a FinFET.FIGS. 21 to 24 illustrate the experiment results showing the effect of the composite blocking layer according to the embodiments of the present disclosure. The X-axes represent the binding energies. The Y-axes represent the signal strength values at different binding energies. FIG. 21 illustrates the bonding energies of aluminum, illustrating the characteristic bonding energies of Al-O and Al-C. Lines 140, 142, 144, and 146 are obtained when a capping layer is formed of a TSN thin layer, a 1 nm TiN layer, a 1.9 nm TiN layer, and a 3.7 nm TiN layer, respectively. The results indicate that line 140 has a strong Al-O signal, which indicates that oxygen penetrates through the thin TSN layer to form bonds with the aluminum in the work function layer (including TiAl). There is a noticeable Al-C signal, which indicates that the TSN thin film has an effect of blocking oxygen, although blocking ability is not suitable. For line 142, the Al-O signal is weaker and the Al-C signal is stronger. Lines 144 and 146 have an even weaker Al-O signal and an even stronger Al-C signal. This indicates that as the thickness of the TiN capping layers increases, less Al-O is formed due to less oxygen permeation and more Al-C remains. The results disclose that as the thickness of the TiN capping layers increases, the capping layers have an improved ability to prevent oxygen from penetrating therethrough to reach the work function layer.Figure 22 illustrates the bond energies of aluminum, lines 148 and 150 being obtained from a 1.9 nm TiN capping layer and a composite capping layer, respectively. The composite capping layer includes a thin TiN layer that passes through a silicon-containing gas soak. Lines 148 and 150 substantially overlap each other, with substantially no Al-O signal being detected. This indicates that the composite layer with the SiH 4- soak is as effective as the 1.9 nm TiN capping layer in blocking oxygen.The embodiments of the present disclosure have some advantageous features. The silicon-containing gas soak forms a silicon-containing layer over the work function layer. The silicon-containing layer may be a silicon oxide layer. The silicon-containing layer is effective in preventing oxygen from entering downward to reach the work function layer, and thus can prevent oxidation of the work function layer. Further, the silicon-containing layer may prevent the metal in the work function layer from spreading upward, which may help to stably maintain the composition of the work function layer, and prevent the deviation in threshold voltage of the resulting FinFET.The invention is defined by the main claim and the subordinate claims. The dependent claims relate to embodiments of the invention.

Claims

A method of forming a semiconductor device, the method comprising: forming (218) a gate electrode (70) in a wafer (10) comprising: depositing a work function layer (120); performing a first treatment (304) on the wafer (10), wherein the first treatment (304) is performed using TiCl 4 exposing the work function layer (120) to the TiCl4; after the first treatment (304), performing a second treatment (306) on the wafer (10), wherein the second treatment (306) is performed by soaking the wafer (10) using a first silicon-containing gas; after the second treatment (306), forming (310, 310') a first metal capping layer (126) over the work function layer (120); and depositing (318) a fill metal (132) over the first metal capping layer (126).The method of claim 1, wherein the second treatment (306) is performed using silane or disilane.The method of claim 1 or 2, wherein when the second treatment (306) is performed, the work function layer (120) is exposed to the silicon-containing gas.The method of any preceding claim, further comprising: exposing a layer (124') formed by the second treatment (306) to air by a first vacuum stop (308, 308'), after the second treatment (306), and before depositing the fill metal (132).The method of claim 4, further comprising: after the first vacuum stop (308, 308'), and after forming (310, 310') the first metal capping layer (126), performing a third treatment (312) on the wafer (10), wherein the third treatment (312) is performed by soaking the wafer (10) using a second silicon-containing gas.The method of claim 5, further comprising: depositing (316, 316') a second metal capping layer (130) after the third treatment (312), wherein the second metal capping layer (130) overlies the first metal capping layer (126).The method of claim 6, further comprising a second vacuum stop (314') for exposing the second metal capping layer (130) to air.The method of any of claims 4 to 7, wherein in the second treatment (306), silicon-containing molecules in the silicon-containing gas are attached to the work function layer (120) and during the first vacuum stop (308, 308'), the silicon-containing molecules are oxidized to form a silicon oxide layer (124).The method of any preceding claim, wherein forming (310, 310') the first metal capping layer (126) comprises depositing a TiN layer.The method of any preceding claim, further comprising: prior to forming the gate electrode (70), removing (216) a dummy gate stack (38), the gate electrode (70) being formed to extend into a trench (62) left behind by the removed dummy gate stack (38), wherein forming (218) the gate electrode (70) comprises: performing a planarization process (320) to remove portions of the work function layer (120), the first metal capping layer (126), and the fill metal (132) outside of the trench (62).A method of forming a semiconductor device on a wafer (10), the method comprising: forming (206) a semiconductor fin (36) that protrudes higher than isolation regions (24) on opposite sides of the semiconductor fin (36); forming (208) a dummy gate stack (38) on a portion of the semiconductor fin (36); forming (212) a source / drain region (54) based on the semiconductor fin (36), the source / drain region (54) being on a side of the dummy gate stack (38); depositing (214) an interlayer dielectric layer (60) to cover the source / drain region (54); Removing (216) the dummy gate stack (38) to leave a trench (62) in the interlayer dielectric layer (60); forming a gate dielectric layer (68) extending into the trench (62); depositing a work function layer (120) over the gate dielectric layer (68); performing a first treatment (304), wherein the first treatment (304) is performed using a gaseous precursor, wherein the gaseous precursor comprises a chlorine-based gas, and wherein the work function layer (120) is exposed to the gaseous precursor; after performing the first treatment (304), performing a second treatment (306) on the work function layer (120), the second treatment (306) being performed by using a silicon-containing gas to soak the wafer (10), wherein silicon-containing molecules in the silicon-containing gas are attached to the work function layer (120); after the second treatment (306), forming (310') a metal capping layer (126) over the work function layer (120); and performing a vacuum stop (308') to expose the metal capping layer (126) to air.The method of claim 11, wherein the second treatment (306) is performed at a temperature in a range of between about 200°C and about 550°C.The method of claim 11 or 12, wherein forming (310') the metal capping layer (126) comprises depositing a TiN layer.The method of any of claims 11 to 13, wherein the second treatment (306) is performed without generating plasma from the silicon-containing gas.The method of any of claims 11 to 14, further comprising: depositing (318) a fill metal (132) over and contacting the metal capping layer (126); and performing a planarization process (320) to remove portions of the work function layer (120), the metal capping layer (126), and the fill metal (132) outside of the trench (62).A semiconductor device comprising: a semiconductor region (36); and a gate stack (72) on the semiconductor region (36), the gate stack (72) comprising: a gate dielectric (68); a work function layer (120) over the gate dielectric (68); a silicon-containing layer (124) over the work function layer (120); a first metal capping layer (126) over the silicon-containing layer (124); and a fill metal (132) over the first metal capping layer (126); wherein the silicon-containing layer (124) further comprises chlorine.The semiconductor device of claim 16, wherein both the work function layer (120) and the first metal capping layer (126) are free of silicon.The semiconductor device of claim 16 or 17, wherein the silicon-containing layer (124) comprises silicon oxide.The semiconductor device of any of claims 16 to 18, wherein the gate stack (72) further comprises a second metal capping layer (122) over and contacting the work function layer (120), the silicon-containing layer (124) overlying and contacting the second metal capping layer (122).

Images