Coated, printed electronic devices showing improved yield and several of the same, as well as methods for their manufacture and use

Abstract

Coated, printed electronic device comprising the following: several contact points (104) arranged in a pattern, several electrode tracks (106) arranged in a different pattern, the several electrode tracks comprising a set of lower electrode tracks (106f-j) and a set of upper electrode tracks (106a-e), each electrode track being electrically connected to an associated contact point (104a-j) of the several contact points, several memory cells (108), each memory cell being arranged at an intersection of a pair of electrode tracks of the several electrode tracks and comprising a lower electrode layer (112) formed from a region of one of the lower electrode tracks, an upper electrode layer (110) formed from a region of one of the upper electrode tracks and a ferroelectric layer between the lower and the upper electrode layer, and a protective layer (116) covering the multiple electrode tracks and extending laterally beyond each edge of each electrode track to provide a buffer zone surrounding each electrode track, the buffer zone extending from one end of each electrode track to cover a portion of each associated contact point in an overlap area, each contact point also having at least one uncovered edge.

Description

[0001] Memory cell-based printed electronics are used in a wide variety of applications, including labels, markers, and sensors. The memory cells are capacitor-like structures, each containing a layer of memory material sandwiched between a pair of electrode layers. The memory cells can be accessed via conductive traces that connect the electrodes to an electronic driver and sensing circuit, which may be located in the periphery of the memory cells or in a separate module, such as a read / write unit. Depending on the application, the printed electronic device can contain a few or up to several million memory cells. Regardless of the specific configuration of the printed electronic device, the device's yield is generally maximized to ensure the device operates as intended (e.g.,(to enable accurate and efficient reading and writing of the individual memory cells). Unfortunately, despite the advantages of the various printing processes (e.g., inkjet printing, screen printing, gravure printing, etc.) used to manufacture printed electronic devices, many factors in the manufacturing process can contribute to a reduced device yield.

[0002] Devices with corresponding memory cells are known from the publications US 2007 / 0 243 678 A1, WO 2006 / 135 247 A1, US 9 659 819 B2, EP 0 158 363 A2, EP 2 351 083 B1 and US 9 564 576 B2.

[0003] The task is to improve the yield of such devices.

[0004] The problem is solved by the coated, printed electronic device according to claim 1, the multiple coated, printed electronic devices according to claim 18, the method for manufacturing a coated, printed electronic device according to claim 19, and the method for using a coated, printed electronic device according to claim 20. Further embodiments are set forth in the dependent claims.

[0005] In embodiments, coated, printed electronic devices are provided comprising: multiple contact points arranged in one pattern; multiple electrode tracks arranged in another pattern, wherein the multiple electrode tracks comprise a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being electrically connected to an associated contact point of the multiple contact points; multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; and comprising a lower electrode layer formed from a region of one of the lower electrode tracks, an upper electrode layer formed from a region of one of the upper electrode tracks, a ferroelectric layer between the lower and upper electrode tracks, and a protective layer.which covers the multiple electrode tracks and extends laterally beyond each edge of each electrode track to provide a buffer zone surrounding each electrode track, the buffer zone extending from one end of each electrode track to cover a portion of each associated contact point in an overlap area, each contact point also having at least one uncovered edge.

[0006] In embodiments, methods for manufacturing coated, printed electronic devices are provided, comprising: printing multiple lower electrode tracks on a substrate; printing a layer of a ferroelectric material onto the multiple lower electrode tracks; printing multiple upper electrode tracks onto the layer of ferroelectric material, wherein the multiple lower and upper electrode tracks form multiple electrode tracks arranged in a pattern and define multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; printing multiple contact points onto the multiple electrode tracks, wherein the multiple contact points are arranged in a different pattern and each electrode track of the multiple electrode tracks is in electrical contact with an associated contact point of the multiple contact points;Printing a curable composition onto the multiple electrode tracks and the multiple contact points; and curing the curable composition to form a protective layer. The protective layer covers the multiple electrode tracks and extends laterally beyond each edge of each electrode track to provide a buffer zone surrounding each electrode track, the buffer zone extending from one end of each electrode track to cover a portion of each associated contact point in an overlap area, each contact point also having at least one uncovered edge.

[0007] In embodiments, methods for using coated, printed electronic devices are provided, comprising: bringing multiple contact points of a coated, printed electronic device into contact with multiple pins of a read / write unit, wherein the device comprises: the multiple contact points arranged in one pattern, multiple electrode tracks arranged in another pattern, the multiple electrode tracks comprising a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being electrically connected to an associated contact point of the multiple contact points, multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks, and comprising a lower electrode layer formed from a region of one of the lower electrode tracks.an upper electrode layer formed from a region of one of the upper electrode tracks, a ferroelectric layer between the lower and upper electrode layers, and a protective layer covering the multiple electrode tracks and extending laterally beyond each edge of each electrode track to provide a buffer zone surrounding each electrode track, the buffer zone extending from one end of each electrode track to cover a portion of each associated contact point in an overlap region, each contact point also having at least one uncovered edge. Fig. Figure 1A shows a top view of a coated, printed electronic device according to an illustrative embodiment. Fig. Figure 1B shows an enlarged view of section A of the coated, printed electronic device made of Fig. 1A. Fig. Figure 1C shows a cross-sectional view of a memory cell of the coated, printed electronic device made of Fig. 1A. Fig. Figure 2 shows a top view of a coated, printed electronic comparison device. Fig. Figure 3 shows a top view of a coated, printed electronic device according to an illustrative embodiment. Fig. Figure 4 shows a top view of the coated, printed electronic device made of Fig. 1A, in which, however, the protective layer was darkened to show its lateral dimensions more clearly. Fig. Figure 5 shows a top view of the coated, printed electronic device made of Fig. 3, in which, however, the protective layer was darkened to show its lateral dimensions more clearly.

[0008] Coated, printed electronic devices are provided, demonstrating improved yield and methods for manufacturing and using such devices.

[0009] The coated, printed electronic devices are based on arrays or matrices of memory cells, known as passive arrays or matrices. The devices are multilayer structures comprising stacked layers, each layer being made of a different material and / or configured in a different pattern, depending on the layer's function.The devices comprise multiple contact points arranged in a pattern; multiple electrode tracks arranged in another pattern, the multiple electrode tracks comprising a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being electrically connected to an associated contact point of the multiple contact points; multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; and a protective layer covering the multiple electrode tracks. Each memory cell comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer between the upper and lower electrode layers. The upper and lower electrode layers of the memory cells correspond to regions of the upper and lower electrode tracks, respectively.From bottom to top in the devices, the set of lower electrode tracks is one of the layers of the multilayer structure, the ferroelectric layer is a layer located above the set of lower electrode tracks, the set of upper electrode tracks is a layer located above the ferroelectric layer, the multiple contact points are a layer located above the set of upper electrode tracks, and the protective layer is a layer located above the multiple contact points. The protective layer can be the uppermost layer in the device.

[0010] The protective layer shields the underlying layers of the coated, printed electronic devices from a variety of external forces that can damage the devices, such as scratches, abrasion, chemicals, etc. Traditionally, the coverage of the protective layer over the underlying material layers has been maximized to maximize the level of protection for these underlying material layers. The present disclosure is based in part on the finding that the yield of coated, printed electronic devices is improved (i.e., increased) when protective layers are used that provide reduced coverage compared to conventional coated, printed electronic devices.This is surprising, since the protective layers themselves are not the electrically active components of the printed electronic devices and would otherwise be expected to have a minimal impact on the yield. The increased yield is further described below with reference to illustrative embodiments of coated, printed electronic devices (see ). Fig. 1A and Fig. 3) Reducing the coverage of the protective layer also has the advantage of reducing costs, as less material is used.

[0011] In the present coated, printed electronic devices, the protective layer covers the multiple electrode tracks underneath. From a top view of the device (e.g., see...) Fig. 1A and Fig. 3) This means that the lateral (i.e., in-plane) dimensions of the protective layer are at least equal to the lateral dimensions of each of the electrode tracks of the multiple electrode tracks lying beneath the protective layer. However, the protective layer also covers an area beyond the edges of each electrode track of the multiple electrode tracks; that is, it extends laterally beyond them. This extended area completely surrounds each electrode track and is referred to here as the 'buffer zone'. The buffer zone may be characterized by a width equal to the distance between an edge of a covered electrode track and an edge of the protective layer, the width being measured along an axis perpendicular to the longitudinal axis of the electrode track. At one end of an electrode track, the buffer zone may extend radially from each corner of the electrode track by a distance equal to the buffer zone width.Thus, the buffer zone effectively traces the perimeter of each electrode track of the multiple electrode tracks and therefore surrounds each electrode track of the multiple electrode tracks. The buffer zone width, i.e., the extent of the lateral extension beyond the edges of each electrode track, is at least 2*2*(row registration capability). "Line registration capability" refers to the registration error value associated with the printing device used to print the protective layer. The registration error value for a printing device can be provided by the printing device manufacturer or determined by monitoring the printed registration marks relative to a fixed reference point against which all printed layers are registered. At least at some lateral locations (i.e., locations within the plane of the protective layer), the buffer zone width is greater than 2*2*(row registration capability).

[0012] Since the protective layer extends laterally beyond the edges of each of the electrode tracks of the multiple electrode tracks, and each electrode track is in direct contact with an associated contact point, a portion of each contact point of the multiple contact points is also covered by the protective layer; that is, the protective layer overlaps each contact point. The area of ​​a contact point covered by the protective layer can be referred to here as the overlap area. However, in such overlap areas, the buffer zone width does not exceed 2*2*(row registration capability). This means that although the buffer zone width at some lateral points in the protective layer is more than 2*2*(row registration capability). The buffer zone width in the overlap areas may not exceed a certain amount. 2*2*(row registration capability). In various embodiments, the buffer zone width is 2*2*(row registration capability). in the overlap areas. In embodiments, the buffer zone width in the overlap areas is greater than zero but not more than 500 µm; greater than zero but not more than 400 µm; or greater than zero but not more than 300 µm. In embodiments, the buffer zone width in the overlap areas is in a range of more than 200 µm to 2*2*(row registration capability). In this embodiment, the buffer zone width in the overlap areas ranges from more than 200 µm to 500 µm. This includes buffer zone widths of 250 µm, 275 µm, 300 µm, 325 µm, and 350 µm. During the design phase, these distances can be calculated using CAD software. After production, these distances can be measured with a video measurement system.

[0013] Although the protective layer overlaps a portion of each of the multiple contact points, each contact point also has an uncovered portion, i.e., a portion over which the protective layer does not overlap. In embodiments, each contact point is covered by the protective layer in an overlap region and has a remaining uncovered portion, i.e., the rest of the contact point is not covered by the protective layer. This is useful for minimizing the wicking effect of the protective layer material on the contact point material.

[0014] Each of the multiple contact points can also have at least one edge that is uncovered by the protective layer, i.e., at least one edge that neither touches nor overlaps the protective layer. In embodiments, all edges of each contact point are uncovered by the protective layer, except for those that are covered due to the buffer zone / overlap area. In embodiments, the protective layer is further configured to define a gap between an edge of the protective layer and an adjacent, facing edge of each contact point. The gap can be characterized by a width corresponding to the distance between the edge of the protective layer and the adjacent, facing edge of the contact point, measured along an axis perpendicular to the edges. In embodiments, the gap width is at least 2 *(Line registration capability). In embodiments, the gap width is at least 80 µm, at least 100 µm, at least 300 µm, or lies in the range of 80 to 100 µm, 200 to 500 µm, or 100 to 600 µm. This is useful to further minimize the wicking effect of the protective layer material on the contact point material.

[0015] Apart from the guidelines described above, which describe the lateral extent of the protective layer relative to the multiple electrode tracks and contact points, the lateral extent of the protective layer may vary in other areas. This is due to Fig. 1A (a protective layer that defines two openings) and Fig. 3 (a continuous protective layer with an approximately rectangular shape) is shown.

[0016] The protective layer can be provided as a single layer or as multiple stacked (e.g., two) sublayers. Multiple sublayers offer the possibility of using different materials to achieve different functions. For example, a first sublayer can be made of a material that provides increased mechanical resistance to external forces such as scratches and abrasion (e.g., a hard coating), and a second sublayer, placed beneath the first, can be made of a more elastic material capable of absorbing lateral dimensional changes caused by the first sublayer. Illustrative materials are described below.

[0017] A top view of a representational coated, printed electronic device 100 is shown in Fig. 1A is shown. The process and cross-process directions that define the lateral dimensions of each of the layers of the device 100 are shown in Fig. 1A. An outline representing the edge of a substrate 102 on which the layers of the device 100 are printed is shown. However, the substrate 102 can be much larger, allowing many coated, printed electronic devices to be printed on it. The device 100 comprises multiple contact points 104a-j arranged in one pattern and multiple electrode tracks 106a-j arranged in another pattern. The pattern of the multiple contact points 104a-j is that of two linear arrays 105a, b extending parallel to each other and parallel to the process direction. The linear arrays 105a, b are spaced apart in the process direction to define a space between them. In this embodiment, each contact point 104a-j has a rectangular shape. In the present disclosure, the term "rectangular" includes rectangles with sharp corners as well as rectangles with rounded corners, such as those described in Fig. Figure 1A shows the contact points. However, other shapes can also be used for contact points 104a-j. Furthermore, not every contact point needs to have the same shape.

[0018] The multiple electrode tracks 106a-j are positioned in the space defined by the linear arrays 105a, b. Each electrode track of tracks 106a-j is electrically connected to an associated contact point of contact points 104a-j; for example, electrode track 106a and contact point 104f are an associated pair. The multiple electrode tracks 106a-j include both upper electrode tracks 106a-e and lower electrode tracks 106f-j. (Both are visible because a ferroelectric layer formed between the upper and lower electrode tracks 106a-e, 106f-j is not shown.)Portions of both the upper and lower electrode tracks 106a-e, 106f-j are configured as strips, with the strip portions of the upper electrode tracks 106a-e being aligned parallel to each other and the strip portions of the lower electrode tracks 106f-j being aligned parallel to each other and orthogonally to the upper electrode tracks 106a-e, thereby forming a grid pattern. The remaining portions of the upper and lower electrode tracks 106a-e, 106f-j extend linearly to their associated contact points. In this embodiment, the grid pattern is oriented at 45° with respect to the process direction and the cross-process direction.Although other orientations can be used, the 45° orientation is useful because it minimizes any shift in the physical position of the bit and the associated electrical response due to shifts in the straight-line operation or across-operation shifts during device registration. Compared to a device whose matrix is ​​oriented orthogonally to the printing direction, a matrix oriented at 45° minimizes the resulting offset in any registration error by a factor of 1 / square meter(2).

[0019] As mentioned above, each memory cell of the multiple memory cells is formed at an intersection of a pair of electrode tracks of the multiple electrode tracks 106a-j. Such an intersection and memory cell is designated 108. Although not in Fig. As shown in Figure 1A, the printed electronic device 100 comprises the ferroelectric layer between the upper and lower electrode tracks 106a-e, 106f-j. A cross-sectional view of the memory cell 108 is shown in Figure 1A. Fig. Figure 1C shows an upper electrode layer 110, a lower electrode layer 112, and a ferroelectric layer 114 between the upper and lower electrode layers 110 and 112. The upper electrode layer 110 corresponds to a region of the upper electrode track 106c. The lower electrode layer 112 corresponds to a region of the lower electrode track 106h at the intersection. Part of a protective layer 116 covers the upper electrode layer 110. To Fig. Returning to 1A, the device 100 includes 25 memory cells. Due to the configuration of the multiple electrode tracks 106a-j (i.e., grid pattern), the multiple memory cells are arranged as a 5×5 matrix of memory cells.

[0020] As in Fig. As shown in Figure 1A, the coated, printed electronic device 100 further comprises the protective layer 116. In this embodiment, the protective layer 116 is the uppermost material layer of the device 100. The protective layer 116 extends over each electrode track of the multiple electrode tracks 106a-j to a region beyond each edge of each electrode track, thereby providing a buffer zone surrounding each electrode track. Consequently, a portion of each contact point of the multiple contact points 104a-j is also covered by the protective layer 116 in an overlap region. As described above, in this overlap region, the buffer zone width is no more than 2*2* (Line registration capability). Fig. Figure 4 shows a top view of the coated, printed electronic device made of Fig. 1A, in which the protective layer 116 was darkened to show its lateral dimensions more clearly.

[0021] It will be on Fig. 1B referenced, which shows an enlarged view of section A from Fig. Figure 1A shows the buffer zone widths in the overlap areas of contact junction 104a and contact junction 104b, where solid white arrows are used to indicate the buffer zone widths. As indicated by the solid black arrows, the buffer zone width is of a similar size in other areas, particularly near contact junctions 104a-j, but not beyond. However, as indicated by the partially dashed black arrows, the buffer zone width is significantly larger in other areas, especially those closer to the memory cells.

[0022] In the embodiment from Fig. 1A defines the protective layer 116 as having two openings 118a, b, each positioned above one of the respective linear arrays 105a, b, such that each contact point of the contact points 104a-j is completely uncovered by the protective layer 116, except for those parts covered due to the buffer / overlap area. Additionally, all edges of each contact point of the contact points 104a-j are also uncovered by the protective layer 116, except for those covered due to the buffer / overlap area. Furthermore, areas between adjacent contact points are also uncovered by the protective layer 116, except for those covered due to the buffer zone. This is best illustrated in Fig. Figure 1B shows an uncovered area 117 between adjacent contact points 104a, b. Finally, the protective layer 116 is further configured to define a gap between its edge (in this embodiment an inner edge defining the openings 118a, b) and an adjacent, facing edge of each contact point. This is best illustrated in Fig. Figure 1B shows an inner edge 120 of the protective layer 116 and adjacent facing edges 122 of the contact point 104b marked and spaced apart to define gaps (indicated by sets of bold parallel lines). Fig. Returning to 1A, the openings 118a, b each have a rectangular shape due to the rectangular shape of the linear arrays 105a, b. However, other shapes can also be used, especially when other arrangements of the contact points 104a-j are used.

[0023] A top view of another illustrated coated printed electronic device 300 is shown in Fig. 3 shown. Device 300 is identical to device 100 from Fig. 1A configured, except when the device 300 has an alternatively configured protective layer 316. Fig. Figure 5 shows a top view of the coated, printed electronic device made of Fig. 3, in which, however, the protective layer 316 was darkened to show its lateral dimensions more clearly. In the embodiment from Fig. 3. The lateral dimensions of the protective layer 316 are further reduced to provide the layer 316 as a continuous, approximately rectangular area positioned over the multiple electrode tracks. The term "approximately" is used because surrounding each electrode track and overlapping each contact point with the buffer zone means that the perimeter of the protective layer 316 deviates from that of a rectangle with straight sides. All other areas of the device 300 are not covered by the protective layer 316. The embodiment from Fig. 3 uses even less material compared to the embodiment from Fig. 1A, providing additional cost savings. The embodiment from Fig. 3 is particularly useful for rigid, inflexible substrates, as the protective layer 316 can exert an additional voltage across the multiple electrode tracks underneath.

[0024] A roll of coated printed electronic devices configured as the embodiment of Device 300 was produced according to the method described below. In particular, a printing system comprising a printing device configured for gravure printing of silver (for the multiple electrode tracks), a printing device configured for extrusion coating of a ferroelectric material (for the ferroelectric layer), a printing device configured for rotary screen printing of carbon (for the multiple contact points), and a printing device configured for rotary screen printing of a curable composition (for the protective layer) was used. A roll of printed electronic comparison devices was produced using the same printing system and the same method, but the coverage of the protective layer was maximized, as in Device 200. Fig. 2 shown. In Fig. 2. The printed electronic comparison device 200 is identical to the device 300. Fig. 3 configured, with the exception of a comparator protection layer 216. The comparator protection layer 216 covers the entire printed electronic device except for an inner area of ​​each contact point. In the comparator device 200, the protection layer 216 overlaps each edge of each contact point by 200 µm.

[0025] The yields for the rolls were evaluated as follows. Both rolls were initially printed in the same production campaign and evaluated before the application of the protective layers. These rolls were then completed using either the reference protective layer 216 or the protective layer 316. A sample set (approximately 500,000 devices) from each roll was then evaluated by subtracting the chip yield measured in the complete device from the chip yield measured before the application of the protective layers. The complete device yield decreased by 2.60% using the reference protective layer 216. In comparison, the complete device yield decreased by only 1.27% using the protective layer 316. The yield improvement by a factor of 2 is economically significant.The yield was also evaluated for a roll of coated, printed electronic devices configured as embodiment of device 100 (protective layer 116). The results were similar to those for a roll of coated printed electronic devices configured as embodiment of device 300.

[0026] As described above, contact points arranged in linear arrays and electrode tracks arranged in a grid pattern can be used to form a matrix of memory cells. However, other arrangements and patterns can also be used. For example, contact points can be arranged in circular or matrix patterns and occupy multiple lateral positions over an underlying substrate with respect to the electrode tracks and memory cells. Additionally, by a suitable configuration of electrode tracks, memory cells can be arranged to form linear arrays, e.g., using a single (1) common lower electrode and N parallel upper electrodes oriented orthogonally to the lower electrode (i.e., a linear 1xN arrangement). The matrix arrays that are Fig. 1A and Fig.Figure 3 shows representative N×N matrix arrays with N upper electrode tracks and N lower electrode tracks. However, unequal numbers of upper and lower electrode tracks can be used, e.g., M lower electrode tracks and N upper electrode tracks to form an M×N matrix array. Additionally, as mentioned above, the orientation of the pattern of multiple electrode tracks relative to the multiple contact points can vary. Furthermore, the portions of the electrode tracks extending from the memory cells to their associated contact points can take a variety of paths.

[0027] The materials used for the various layers of the coated printed electronic device depend on the device's application and the specific function of each layer. Illustrative materials for the substrate include silicon, glass, polymers, paper, etc. Illustrative materials for the electrode tracks / electrode layers include metals, e.g., silver, or conductive polymers, e.g., polyethylene dioxythiophene. Illustrative materials for the ferroelectric layer include ferroelectric polymers, e.g., a copolymer of polyvinylidene fluoride and trifluoroethylene. Illustrative materials for an underlayer (e.g., a top layer) of the protective coating include UV-curable polymer compositions. (e.g., polyester, polyether). Illustrative materials for an underlayer (e.g., a sublayer) of the protective layer include polypropylene glycol (PPG), silicone rubber, natural rubber, polyvinyl acetate, and acrylate-based resins. In coated, printed electronic devices, other layers, e.g., insulating layers of insulating polymers, such as acrylic-based polymers, may be included between the substrate and the lower electrode traces to improve planarization and promote adhesion. Other illustrative materials include those described in US 9,412,705 B2, WO 2006 / 135246 A1, and WO 2006 / 135247 A1, to which full reference is hereby made.

[0028] Apart from the above-described requirements regarding buffer zone widths and gap widths, other dimensions of the features of the coated, printed electronic devices, the thicknesses of the material layers, and the overall dimensions of the devices can be selected depending on the function of the material layers, the application for the devices, and the number of memory cells.

[0029] The coated, printed electronic devices can be used in a variety of applications, including product authentication applications for print cartridges, event tickets, credit cards, etc.

[0030] Methods for manufacturing the disclosed coated, printed electronic devices are also provided. The methods are performed on printing systems comprising one or more printing devices configured to print layers of material using a thin-film printing technique, such as inkjet printing, screen printing, flexographic printing, offset printing, electrographic printing, gravure printing, extrusion coating, etc. Since different material layers can be printed using different techniques, the printing system may include several different types of printing devices. The printing devices used in the printing system may be characterized by line registration capability.The line registration capability can be at least 50 pm, at least 75 pm, at least 100 pm, at least 150 pm, at least 200 pm, at least 250 pm, or in the range of 50 to 300 pm. The methods involve the sequential printing of the material layers of the desired printed electronic device in a bottom-up, layer-by-layer manner.

[0031] In embodiments, a method for manufacturing a coated, printed electronic device comprises printing multiple lower electrode tracks onto a substrate; printing a layer of a ferroelectric material onto the multiple lower electrode tracks; printing multiple upper electrode tracks onto the layer of ferroelectric material, wherein the multiple lower and upper electrode tracks form multiple electrode tracks arranged in a pattern and define multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; printing multiple contact points onto the multiple electrode tracks, wherein the multiple contact points are arranged in another pattern and each electrode track of the multiple electrode tracks is in electrical contact with an associated contact point of the multiple contact points;The process involves printing a curable composition onto the multiple electrode tracks and contact points; and curing the curable composition to provide a protective layer. In the process, the multiple electrode tracks, contact points, and memory cells being printed can be arranged in any of the appropriate patterns described above. The protective layer is configured as described above.

[0032] Curing can be achieved by exposing the curable composition to radiation under conditions designed to induce free radical polymerization reactions between components of the curable composition. Curing conditions include, for example, the wavelength of the radiation, the curing temperature, the curing time (which can be adjusted by the curing rate, e.g., by scanning the radiation source across the printed curable composition), and the curing atmosphere. Various wavelengths can be used. In embodiments, the wavelength is in the range of 200 nm to 800 nm, 250 nm to approximately 750 nm, or 300 nm to 700 nm. Any light source providing wavelengths within these ranges can be used, e.g., mercury arc lamps. In embodiments, the curing temperature is room temperature.from approximately 20 °C to approximately 25 °C. In various embodiments, the curing time ranges from 1 second to 10 minutes, 1 second to 1 minute, or approximately 1 second. Curing can be carried out in an ambient atmosphere (i.e., air at atmospheric pressure).

[0033] Methods for using a coated printed electronic device are also provided. In embodiments, such a method comprises bringing multiple contact points of a coated printed electronic device into contact with multiple pins of a read / write unit. This contact enables the application of voltage waveforms to control the reading / writing of the multiple memory cells and to detect the state of the memory cells during the reading process. Any of the coated printed electronic devices disclosed herein can be used. The configuration of the read / write unit is not particularly restricted, provided that the multiple pins are arranged in a pattern that corresponds to the pattern of the multiple contact points of the printed electronic device. Commercially available read / write units can be used.

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