Multiplexer

Abstract

Multiplexer, which includes the following: a monolithic stack (ST) of - a carrier substrate (SU), - a piezoelectric layer (PL) above the substrate with a main surface, - at least one dielectric layer (DL) positioned between the piezoelectric layer and the substrate, a metallization on the main surface, which includes the following: - an antenna connector (AT) for connecting to an antenna, - three signal contact points (SP), - three SAW filter circuits (FC) each connected in parallel between the antenna connection and a respective signal contact point, each of the filter circuits comprising a series signal line (SSL) and a number of SAW resonators (RP, RS) connected in series with the series signal line or in parallel with it, a package which provides a cavity on the stack, wherein the SAW resonators are enclosed in the cavity formed between the main surface of the piezoelectric layer and a lid and / or cover.

Description

[0001] At least three acoustic filters are arranged on a single chip. At least two of them are already electrically connected on the chip for multiplexing. This reduces the space requirement and results in a smaller device size.

[0002] In today's mobile communication devices, multiplexers are used to enable filter operation across a variety of frequency bands while using the same antenna connected to the multiplexer.

[0003] DE 11 2014 005 424 T5 discloses a splitter that implements simultaneous transmitting and receiving in multiple communication systems while reducing losses. In this splitter, a first duplexer, comprising a first transmit filter and a first receive filter at a first antenna connection, and a second duplexer, comprising a second transmit filter and a second receive filter at a second antenna connection, are connected. A second transmit band of the second transmit filter and a second receive band of the second receive filter are located in a frequency range between a first transmit band of the first transmit filter and a first receive band of the first receive filter. Both the second transmit filter and the second receive filter of the second duplexer are formed by an elastic wave filter.The elastic wave filter contains a high-speed sound film, which serves as a high-speed sound element, a low-speed sound film through which transverse waves propagate at a lower speed than those propagating through the high-speed sound film, a piezoelectric film arranged on the low-speed sound film, and IDT electrodes arranged on the piezoelectric film, stacked on top of each other in this order.

[0004] US 2018 0358951 A1 discloses an acoustic wave device comprising a first substrate having a first surface on which an acoustic wave element is located; a second substrate having a second surface on which a functional element is located; a third substrate having a third surface which is inclined towards the first and second surfaces, and a fourth surface which is opposite the third surface; a first metal layer which is separate from the acoustic wave element and a cable in the first substrate which connects the first and third substrates; a second metal layer which is separate from the functional element and a cable connection in the second substrate which connects the second and third surfaces;a first metal pattern located on the third surface, in contact with the first and second metal layers, and connecting the first and second metal layers; and a terminal located on the fourth surface, electrically connectable to the first metal pattern.

[0005] US 2018 0159498 A1 discloses a heterostructure, in particular a piezoelectric structure, which comprises a cover layer, in particular a layer of a piezoelectric material, wherein the material of the cover layer has a first thermal expansion coefficient, applied to a support substrate, wherein the support substrate has a second thermal expansion coefficient which differs substantially from the first thermal expansion coefficient at an interface layer, and wherein the cover layer includes at least one recess which extends from the interface layer into the cover layer.

[0006] Discrete electroacoustic components with more than two filter functions or multiplexers consist of a substrate, such as a laminate, and individual filter chips. Each filter function is implemented on separate chips. This has the advantage that a separately optimized layer stack can be used for each filter function, and different filter technologies can be employed. Additionally, the chip size used for individual filters remains small, which offers several advantages, for example, regarding mechanical stability, the failure of individual filters during manufacturing, or when the individual chips are tuned to the target frequency.

[0007] However, the substrate must be large enough to maintain minimum spacing at the chip edges and between the electro-acoustic chips. Furthermore, heat dissipation is not optimal, and cutting small chips from a wafer reduces the acoustically usable area and results in greater material loss when the wafer is disassembled.

[0008] When larger chips with more than two filter functions are combined on a single chip, the susceptibility to cracking and failure during operation due to thermal mismatch in an assembly or between the substrate and the chip is increased. Furthermore, simultaneous optimization of the different filter functions on the same chip is difficult to achieve.

[0009] One object of the present invention is to provide a multiplexer as a single-chip solution that is thermally matched and fully meets the specifications for various filter functions. A further object is to provide a multiplexer with improved heat dissipation properties.

[0010] At least one of these tasks is solved by a multiplexer according to independent claim 1. Advantageous features and embodiments can be found in the dependent claims.

[0011] A multiplexer is formed from a single monolithic stack comprising a silicon support substrate, a piezoelectric thin-film layer above the substrate with a main surface, and at least one dielectric layer positioned between the piezoelectric layer and the substrate. On the main surface, a structured metallization includes an antenna connector for connecting to an antenna, three signal contact points, and three SAW filter circuits. The filter circuits are each connected in parallel between the antenna connector and a respective signal contact point. Each filter circuit comprises a series signal line and a number of SAW resonators connected in series with the series signal line or in parallel with it. A package provides a cavity on the stack in which the SAW resonators are enclosed.The cavity is formed between the main surface of the piezoelectric layer and a lid and / or cover.

[0012] The multiplexer uses a single stack to perform all filter functions. With a suitable band combination, which is an appropriate combination of filter functions for those bands, all bands can be operated with the same antenna with sufficient isolation between the band channels and therefore without any crosstalk.

[0013] The stack uses a piezoelectric thin-film layer that does not generate any interference modes in any of the filter circuits combined at the antenna connector. Therefore, adjacent bands are not affected when the multiplexer is operating in one band.

[0014] Each filter circuit includes all the resonators necessary for the filter function. The multiplexer includes a separate filter circuit for each band that can be operated by the multiplexer. This offers several technical advantages: Wafer material can be saved. Instead of individually cutting out each small chip from a wafer, only a single large chip needs to be cut out. This significantly reduces the area loss on the wafers caused by cutting (for example, by one-third for three square individual chips or by half for four square individual chips).

[0015] Depending on the process, acoustic resonators must always maintain a minimum distance from the chip edges. Using a single chip instead of several smaller chips reduces the total chip edge area, which cannot be used acoustically and must remain free of any filter elements. Additionally, the acoustic resonators can be arranged more freely because they do not have to be aligned on a straight edge in the area between the individual filter functions, but can be positioned variably. This offers more degrees of freedom for the design of the existing acoustic surface and, consequently, more efficient use of space.

[0016] Additionally, the single-chip design offers the advantage of more effective heat dissipation. The resulting heat is distributed across a larger chip, radiated more efficiently, and can be dissipated through a greater number of contact points. This can have a positive impact on the functional compatibility and lifespan of the components.

[0017] Because normally only one filter circuit of the multiplexer is in operation, only that specific filter circuit can generate heat. The other, inactive filter circuits and the area they occupy within the stack provide sufficient volume to dissipate the heat effectively and prevent an excessive temperature rise.

[0018] It is preferred to use a substrate material for the stack whose thermal conductivity is at least ten times higher than that of the piezoelectric layer. Such a relationship can be achieved with a monocrystalline silicon support substrate and a piezoelectric layer consisting of lithium tantalate (LT) or lithium niobate (LN). Silicon exhibits a thermal conductivity approximately forty times better than the common SAW materials LiTaO3 or LiNbO3. The piezoelectric layer with its poor thermal conductivity is relatively thin and thus generates a correspondingly low thermal resistance, allowing heat to pass effectively through the layer. Therefore, most of the heat dissipation occurs in the highly conductive silicon substrate material and is thus an improvement over SAW devices or filter chips implemented on a commonly known thick piezoelectric substrate.

[0019] According to preferred embodiments, the piezoelectric layer is a monocrystalline thin-film layer of lithium tantalate or lithium niobate and has a thickness ranging from 400 to 2000 nm. Such a layer thickness is advantageous for TF-SAW filter circuits operating in the low-band, mid-band, and high-band regions. To minimize acoustic loss and enable wafer bonding, the piezoelectric layer preferably has a smooth top and bottom surface. In this context, a smooth surface is understood to have a roughness value Rq ≥ 0.5 nm, where Rq is the respective root mean square (RMS) value. The root mean square (RMS) value is defined as the square root of the mean square (the arithmetic mean of the squares of a set of deviations from a center line). A precise definition of roughness parameters can be found at https: / / en.wikipedia.can be found at org / wiki / Surface_roughness.

[0020] The dielectric layer beneath the piezoelectric layer is preferably a silicon oxide layer with a thickness of 300 nm to 2000 nm and a smooth upper surface with a roughness value Ra ≥ 0.5 µm, where Ra is the arithmetic mean deviation from a constant centerline of the profile under consideration. Such a dielectric layer can reduce the TCF (thermal frequency coefficient) of the multiplexer and compensate for or reduce the temperature drift of the filter circuits, which is due to the relatively high TCF of the piezoelectric material.

[0021] Between a direct interface of the Si substrate and a silicon oxide layer, fixed positive charges arise that attract mobile electrons, leading to a conductive layer subject to ohmic losses. To avoid these losses, it is advantageous to insert a trap-rich layer between the Si and SiO₂ layers. This trap-rich layer can, for example, consist of polycrystalline silicon with a thickness in the range of 100 nm to 2000 nm.

[0022] It is possible to use a multilayer circuit board with contact points on its bottom surface and integrated wiring within its multilayer structure for wiring and encapsulation. The circuit board's contact points are connected to corresponding external contacts on the top surface, opposite to the bottom surface, to enable connection to an external circuit arrangement of an electrical device, such as a mobile phone.

[0023] The multilayer circuit board is mounted onto the stack using an interconnection technique and electrically connected to it. The contact points are connected to the respective signal contact points and the antenna connection on the main surface, for example, via contact bumps. A sealant can be provided to seal the cavity formed between the multilayer circuit board and the main surface.

[0024] Alternatively, the SAW resonators can be enclosed in individual cavities that are integrally designed as an acoustic thin-film package (TFAP). Such a TFAP can enclose a single filter function, a portion of a filter function, or individual resonators. A TFAP can be created by applying and structuring a sacrificial material to pre-form the respective cavities. A mechanically stable thin film is then deposited over the entire surface of the chip to cover the sacrificial structures. The cavity is then released by removing the sacrificial material.

[0025] If an encapsulation technology with a circuit board (for example, CSSP) is used, the board area can be reduced because the spacing between the individual filter chips required for multi-chip multiplexers is eliminated by the single-chip multiplexer. Because the size of the single chip used for the single-chip variant significantly exceeds that of a single chip in the multi-chip variant, it is preferred with respect to the invention to use a circuit board material whose coefficient of thermal expansion is similar to that of the wafer material. This minimizes mechanical stresses during temperature cycling.

[0026] Suitable circuit board materials include laminate, HTCC, and LTCC. The latter is particularly advantageous in combination with a silicon-based TF-SAW wafer material because it allows for a good match between the thermal expansion coefficients of the stack / wafer and the circuit board. Overall, lower costs and the smaller size of the multiplexer result in competitive advantages.

[0027] The entire multiplexer interconnect can be measured at a very early stage of the manufacturing process, and interactions between the individual filters can therefore be detected. This allows manufacturing variations to be compensated for at an early stage, for example, by tuning.

[0028] During the fabrication of a single-chip multiplexer, process variations typically have a similar effect on all filters in the stack and can be corrected by a tuning process. This contrasts with the situation in multi-chip arrays, where significant statistical variations in device characteristics and a wide distribution of filter functions can occur. If two of the filter functions are close in frequency and therefore require a high degree of mutual selection of their respective opposing bands, they benefit from the single-chip arrangement of the new multiplexer because both filter functions are subject to parallel process variations; that is, critical passband edges of different filter circuits on the same stack are shifted in the same frequency direction.

[0029] This makes it easier to guarantee a critical duplex spacing during process design. This is not the case with multi-chip arrays.

[0030] Furthermore, processing times and associated costs can be reduced, for example during sawing or flip-chip bonding, because all required contact bump connections of all filter circuits of the multiplexer can be processed in one step.

[0031] The application of the invention is particularly attractive for multiplexers involving only a small number of filter circuits / filter functions whose frequency must be precisely matched due to high near-field selection requirements, and a larger number of filters with less stringent requirements. In such cases, the critical filters can be essentially tuned, and the filters can be designed to provide sufficient leeway to meet the less critical specifications.

[0032] According to one embodiment, the multiplexer comprises four SAW filter circuits to form a quadplexer. The four filter functions form two duplexers designed to allow the quadplexer to operate in a combination of bands B1 and B3 or in a combination of bands B25 and B66.

[0033] In this example, the filter functions for bands B3 and B25 need to be very precisely tuned, while the specifications for bands B1 or B66 are less critical.

[0034] However, a more complex selective multiple tuning can also be used for the individual filter units.

[0035] Initial tuning can be performed during stack fabrication. This measures and controls the thickness uniformity of the deposited or otherwise fabricated layers. If necessary, selective thickness reduction is achieved using a material-removing NF3 beam. The thicknesses of the dielectric and piezoelectric layers are most relevant for filter specifications.

[0036] The invention is explained in more detail with reference to embodiments and the accompanying drawings. The drawings are schematic only and may not be drawn to scale.

[0037] They show: Fig. 1 a known multiplexer arrangement of four separate chips on a common multilayer board with required chip-to-chip distances and a required edge boundary, Fig. 2 a single-chip multiplexer and the required edge confinement according to the invention, Fig. 3 a schematic block diagram of four filter circuits arranged on a single chip and connected to a common antenna connector, Fig. 4 a schematic filter circuit in further detail, Fig. 5 a schematic block diagram of a DMS filter that can be used as a resonator in an Rx filter circuit, Fig. 6 a cross-section through a monolithic stack provided with a structured metallization which includes contact points, electrode structures and terminals that can be used for the multiplexer and Fig. 7 a possible schematic assembly for the multiplexer.

[0038] Fig. Figure 1 shows an arrangement of four separate chips CH on a common multilayer board MLB with the required chip-to-chip spacing and edge boundaries. As a result of these required spacings, the acoustically usable area AA of a chip CH is smaller than the area of ​​the chips. Furthermore, the chips must maintain a distance from the edge of the multilayer board and between adjacent chips.

[0039] Fig. Figure 2 shows, to the same scale, the required area of ​​a multiplexer implemented on a single chip according to the invention. With such an arrangement, no chip-to-chip spacing is required, thus minimizing the size of the single chip compared to the arrangement shown in Figure 2. Fig. 1. A smaller chip area. The same applies to the limitation of the multilayer board (MLB). Therefore, up to 50% or even more wafer area can be saved, and a multiplexer device can be achieved whose area is correspondingly smaller than that of a known multi-chip arrangement according to [reference missing]. Fig. 1.

[0040] Fig. Figure 3 shows an exemplary schematic block diagram of four filter circuits FC1 to FC4, arranged on a single chip CH and connected to a common antenna connector AT. Each filter circuit FC comprises a series signal line SSL, which connects the respective signal contact points SP to the antenna connector AT and a number of SAW resonators. Series resonators RS are connected in series with the series signal line SSL, and parallel resonators RP are connected in parallel with the series signal line SSL.

[0041] The filter circuits are ladder-like arrangements and may include additional elements not shown in the figure for clarity. The number of resonators can be increased to achieve better selectivity. Some of the resonators may be cascaded to improve their power resistance, lifetime, and nonlinear behavior. The filter circuit may consist solely of series resonators (RS). Passive elements may be connected to the resonators or to the series signal line. Capacitors may be connected in parallel to individual resonators to modify their bandwidth. Parallel resonators (RP) may be grounded via an inductor. Some of the ground connections may be combined on-chip. The antenna connection is grounded via an inductor for phase shifting and impedance matching.

[0042] External circuit elements can be connected to signal terminals or to the series signal line.

[0043] Two filter circuits can be assigned to the same first mobile communication band, forming an Rx filter and a respective Tx filter for that band. The other two filter circuits can be assigned to a second mobile communication band to enable duplex operation in that second band. Preferably, the filter circuits are assigned to band combinations with a relatively small frequency separation. Preferably, the two bands lie within the same frequency range, which is selected from a high-band and / or a mid-band range.

[0044] Fig. Figure 4 shows a schematic example of a filter circuit FC of the type shown in Fig. Figure 3 shows further details. This filter circuit comprises five series resonators RS arranged in the series signal line SSL. Each node between two adjacent series resonators is connected to ground via a parallel branch, and a parallel resonator RP is arranged in each parallel branch. An inductor (not shown) may be connected between a parallel resonator and ground.

[0045] Fig. Figure 5 shows a schematic block diagram of an exemplary strain gauge filter that can be used as a series resonator in an Rx filter circuit of the multiplexer. A strain gauge filter comprises a first set of interdigital converters / resonators (IDTs) connected to the input terminal (EIN) of the strain gauge filter. A second set of interdigital converters (IDTs) is connected to the output terminal (OFF) of the strain gauge filter. All IDTs are arranged in an acoustic track extending between two reflectors (REFs) and are therefore acoustically coupled. The first and second sets can be placed higher than shown, depending on a required selectivity specification. The busbars of the IDTs not connected to the input or output can be grounded or floated. Two strain gauge filters can be connected in series within a filter circuit. Other elements of the filter circuit, as shown in the Fig. 3 and Fig. The four components shown complete the filter circuit.

[0046] Fig. Figure 6 shows a schematic cross-section through a monolithic stack, the top surface of which already has a structured metallization. From this metallization, contact points, electrode structures ES (such as interdigital converters), reflectors, conductors, terminals AT, and signal contact points SP1 and SP2 can be formed as needed, for example, to create the multiplexer. Fig. 3 will be formed.

[0047] The support substrate SU is a crystalline silicon material with sufficient thickness to provide the required mechanical stability. The stability must be high enough to allow handling of an entire wafer on which the stack ST is formed. The crystalline silicon material of the support substrate SU may have a top surface that is a crystallographic

[111] surface.

[0048] Optionally, a trap-rich layer TRL is arranged on the support substrate SU. This layer consists, for example, of a polycrystalline silicon layer with a thickness in the range of 100 nm to 2000 nm, in order to eliminate known free charges at a subsequent Si / SiO₂ junction. A dielectric layer DL of SiO₂ is formed or deposited to act as a TCF compensation layer. The thickness of the dielectric layer is controlled and set to a value of approximately 300 nm to 2000 nm, for example, 500 nm. All layer transitions can have smooth upper and lower surfaces with low surface roughness.

[0049] After smoothing the surface of the dielectric layer DL, for example by a CMP process, a piezoelectric wafer is bonded to the dielectric layer DL. Following atomic bonding, the thickness of the piezoelectric wafer is reduced to form a piezoelectric thin-film layer PL with a thickness of approximately 400 nm to 2000 nm, for example 600 nm. This is thin enough to allow rapid heat dissipation from the filter circuit to the underlying substrate and to prevent the excitation of interference modes in opposite bands or any other band that can be operated by the multiplexer. With a sufficiently thin piezoelectric layer, interference modes only occur at frequencies far above the bands used by the multiplexer.

[0050] After a thickness reduction process, the thickness of the piezoelectric layer is measured, and the entire layer is trimmed to achieve a desired thickness across the entire wafer with only a small tolerance. This is necessary because the frequency of a filter circuit formed on the piezoelectric layer can depend on its specific thickness, and excessive tolerance leads to frequency variation and a frequency distribution across the wafer depending on the remaining thickness deviation.

[0051] Lithium tantalate (LT) and lithium niobate (LN) are preferred piezoelectric materials. However, other materials can also be used.

[0052] It is important that the thermal conductivity of the substrate SU is at least ten times higher than the respective conductivity of the piezoelectric layer PL. The silicon substrate SU proposed above and the piezoelectric layer PL made of LT differ in conductivity by a factor of approximately 40.

[0053] The upper surface of the stack ST is the main surface on which electrode structures ES and signal contact points SP as well as the antenna connection AT are formed. Fig. Figure 6 shows the metallization in a very schematic representation. Further contact points, such as ground contact points for connecting the parallel branches to ground, are present on the main surface, but are not shown in the schematic figure.

[0054] Preferably, the electrode structures consist of a metallization based on aluminum or an aluminum alloy. Furthermore, copper and / or titanium can be additional components in the alloy or used as a discrete sublayer in a multilayer metallization. The surface of the metallization can be protected with a passivation layer. The contact points are thickened and provided with a solderable surface layer, for example, of gold or nickel.

[0055] To complete the multiplexer, a package is formed on the ST stack. A multilayer circuit board can be bonded to the main surface of the stack for this purpose.

[0056] Fig. Figure 7 shows a cross-section of such a multiplexer, which is already equipped with such a covering circuit board.

[0057] The multilayer PCB (MLB) can be made of any organic laminate such as FR4 or of a ceramic material such as LTCC or HTCC. A ceramic is preferred due to its higher thermal conductivity and its thermal expansion, which is matched to that of the silicon substrate. LTCC is the preferred choice for the multilayer PCB (MLB).

[0058] The multilayer circuit board incorporates wiring that includes vias through one or more of the ceramic or laminate layers and wiring levels. These vias connect different wiring levels located between two such ceramic or laminate layers, or a wiring level to a CP contact on the lower surface or to an external EC contact on the upper surface. The wiring serves to connect and link various signal contact points and / or terminals, and to provide a connection between the signal contact points, the antenna connector, and external EC contacts located on the multilayer circuit board (MLB).

[0059] Furthermore, the multilayer circuit board can include integrated passive components that can be formed from such integrated wiring. These passive components can support the filtering functions of the filter circuits. These integrated passive components can be used to form an inductor connected to the antenna terminal and inductors in series with parallel branches. Passive components requiring a higher quality factor, such as those used to match the terminals of a filter circuit, must be implemented as external discrete components that can be connected to the external contacts.

[0060] The assembly of the ST stack onto the MLB multilayer board can be performed at the wafer level. As a final step, individual devices can then be separated by disassembling the wafer-level package, for example by sawing.

[0061] Alternatively, a large multi-layer circuit board can be used to mount individual stacks that have already been separated.

[0062] Contact protrusions BU are preferred for connecting the multilayer circuit board to the respective contact points SP and terminals AT on the main surface of the stack ST. A maximum number of contact protrusions is preferred to promote heat dissipation from the filter circuit and the respective active piezoelectric layer to the multilayer circuit board.

[0063] In the example from Fig. 3. At least thirteen contact points and terminals must each be contacted by a separate contact prong. A higher number of parallel branches allows for assembly with a greater number of contact prongs. Contact prongs without any electrical function could also be used to provide better heat dissipation.

[0064] Within the package, the surfaces of the stack and the multilayer board can coincide. However, it can be advantageous for a boundary of one stack or board to extend beyond the edge of the other package layer. In this case, a sealing layer can be applied to the side of the layer or stack with the smaller surface area. The sealing layer can then more easily seal the protruding surface in the boundary area.

[0065] The sealing can be achieved with a resin, a laminate, or a film, and a hermetic seal can be achieved with a metal layer as the top sealing layer. The sealing layer must be structured to expose at least the external EC contacts of the assembly.

[0066] Because the invention has been described only with reference to some embodiments, the invention is not to be limited to a specific embodiment or figure. Features that have been described in more detail in writing or in a figure with reference to only one embodiment are not to be limited to these details, provided that the respective feature is disclosed in a more general form and is covered by the claims. List of terms and reference symbols used cavity Metallization Package Rx filter Tx-Filter AA acoustically usable area AT antenna connection BU contact bumps CH Chip CP Contact Point DL dielectric layer EC external contact ES electrode structure FC SAW filter circuit IDT Interdigital Converter IN input port of the DMS filter MLB multilayer circuit board OUT output terminal of the DMS filter PL piezoelectric layer REF Reflector RS, RP series and parallel SAW resonators SP signal contact points SSL serial signal line ST monolithic stack SU carrier substrate TRL layer with high fall rates

Claims

[1] Multiplexer, which includes the following: a monolithic stack (ST) of - a carrier substrate (SU), - a piezoelectric layer (PL) above the substrate with a main surface, - at least one dielectric layer (DL) positioned between the piezoelectric layer and the substrate, a metallization on the main surface, which includes the following: - an antenna connector (AT) for connecting to an antenna, - three signal contact points (SP), - three SAW filter circuits (FC) connected in parallel between the antenna connection and a respective signal contact point, each of the filter circuits comprising a series signal line (SSL) and a number of SAW resonators (RP, RS) connected in series with the series signal line or in parallel with it, a package which provides a cavity on the stack, wherein the SAW resonators are enclosed in the cavity formed between the main surface of the piezoelectric layer and a lid and / or cover. [2] Multiplexer according to the preceding claim, wherein the support substrate comprises Si, wherein the piezoelectric layer is a monocrystalline thin film layer of lithium tantalate or lithium niobate with a thickness of 400 nm to 2000 nm. [3] Multiplexer according to any of the preceding claims, wherein the dielectric layer is a silicon oxide layer with a thickness of 300 nm to 2000 nm and a smooth upper surface. [4] Multiplexer according to one of the preceding claims, wherein a trap-rich layer (TRL) is provided between the substrate and the piezoelectric layer, the trap-rich layer comprising a layer of polycrystalline silicon with a thickness of 300 nm to 2000 nm. [5] Multiplexer according to any of the preceding claims, wherein the substrate has a thermal conductivity that is at least ten times greater than the thermal conductivity of the piezoelectric layer. [6] Multiplexer according to one of the preceding claims, comprising a multilayer board (MLB) with contact points (CP) on a lower surface thereof and integrated wiring, wherein the contact points are connected to respective external contacts (EC) on the upper surface opposite the lower surface, wherein the multilayer board is mounted on the stack (ST) by a connection technique to electrically connect the contact points to respective signal contact points (SP) and the antenna connection (AT), the connection includes contact bumps (BU), wherein a sealing agent is provided for sealing the cavity formed between the multilayer board and the main surface. [7] Multiplexer according to any of the preceding claims, wherein the multilayer board is selected from the group consisting of a multilayer laminate, HTCC and LTCC. [8] Multiplexer according to one of the preceding claims, wherein the SAW resonators are enclosed in a cavity which is integrally designed as an acoustic thin-film package. [9] Multiplexer according to any of the preceding claims, wherein four SAW filter circuits (FC) are provided to form a quadplexer comprising two duplexers, the two duplexers being designed to operate in bands B1 and B3 or in bands B25 and B66. [10] Multiplexer according to any of the preceding claims, comprising a trimming layer on the stack, wherein one or more layers of the stack are tuned to meet the specifications of tape B3 or B25. [11] Multiplexer according to one of the preceding claims, comprising a filter circuit comprising an Rx filter with a strain gauge filter in the series signal line.

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