METHOD FOR PRODUCING A SEMI-CONDUCTOR ARRANGEMENT

Abstract

Method for manufacturing a semiconductor assembly (100) comprising the following: Performing a first etching of a semiconductor structure that is a hybrid fin (106b) to expose a first section (124) of a side wall (126, 128) of a dielectric layer (104) adjacent to the semiconductor structure when part of the hybrid fin (106b) is removed by the first etching, wherein: the first etching forms a first protective layer (406) on the first section (124) of the side wall (126, 128) of the dielectric layer (104), and the first protective layer (406) is formed from a first accumulation of by-product material formed from an etching agent of the first etching process, which interacts with the semiconductor structure; and Performing a first process to remove at least part of the first protective layer (406).

Description

BACKGROUND

[0001] During semiconductor manufacturing, various techniques are used to remove layers or sections of layers used in the construction of semiconductor devices. One technique for removing layers or sections of layers is etching. Etching is a process in which an etchant, such as a chemical, is applied to a layer or section of a layer that is to be removed. The layer or section of the layer is often removed to expose underlying layers or structural elements, or to define a specific structure within the layer. The layer or section of the layer to which the etchant is applied has a certain etch selectivity relative to the etchant, such that the layer or section of the layer is removed or etched away by the etchant.Other sections of the layer that are not to be removed are generally covered by a photoresist or a hard mask, which the etchant cannot affect or only minimally. The photoresist or hard mask thus protects these sections from the etchant. After the layer or section of the layer has been etched away, the photoresist or hard mask is removed to expose the structured layer or the remaining sections of the layer that were not etched away.

[0002] US 2007 / 0 202 700 A1 discloses a method for forming anisotropic features for high aspect ratio applications in an etching process. DE 10 2017 128 233 A1 describes a method for forming a semiconductor device. US 2004 / 0 072 430 A1 discloses a method for forming a dual damascene feature. US 2016 / 0 308 027 A1 discloses a method for fabricating a FinFET device. US 2015 / 0 249 127 A1 discloses an illustrative method for removing a rib from a plurality of ribs. Reference is also made to US 2016 / 0 359 043 A1 and US 2017 / 0 005 011 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figures 1 to 10 illustrate a semiconductor arrangement in various stages of manufacturing according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] In some embodiments, a semiconductor structure, such as a fin, with a relatively large aspect ratio is etched, while an adjacent dielectric layer experiences little to no etching during the etching process due to a protective layer formed on one or more faces of the dielectric layer. The etching process is performed cyclically, along with a flash process to remove the protective layer. A recess or trench, defined by the sidewalls of the dielectric layer and a top face of the semiconductor structure, is deepened during the cyclic etching process. An initial portion of the semiconductor structure is removed by the etching process, while the protective layer is simultaneously formed on the sidewalls of the dielectric layer. The protective layer prevents the accumulation of etching byproducts in the trench.The protective layer is then removed by a flash operation. The etching process is repeated to remove a second section of the semiconductor structure, further deepening the trench, while simultaneously reapplying the protective layer to surfaces of the dielectric layer to prevent etching byproducts from accumulating in the trench. Another flash operation is performed to remove the protective layer. The process is repeated cyclically as needed to remove a desired amount of the semiconductor structure. The protective layer also prevents the dielectric layer from being removed during the etching operations, ensuring that a top surface of the dielectric layer remains at a desired height, such that it is not lower than the top surface of an adjacent semiconductor structure, such as a neighboring fin.

[0007] Fig. Figure 1 illustrates a semiconductor arrangement 100 which, according to some embodiments, includes a first hybrid fin 106a and a second hybrid fin 106b formed on or from a substrate 102. Although two fins 106a, 106b are illustrated, some embodiments also consider one or fewer fins. According to some embodiments, the substrate 102 comprises at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, and a die formed from a wafer. In some embodiments, the substrate 102 is etched to form at least part of the first hybrid fin 106a and / or at least part of the second hybrid fin 106b. In some embodiments, the substrate 102 is doped before etching. In some embodiments, the substrate 102 is doped after etching.In some embodiments, at least a portion of the first hybrid fin 106a and / or at least a portion of the second hybrid fin 106b are grown from the substrate 102. In some embodiments, a germination layer is used to grow at least a portion of the first hybrid fin 106a and / or at least a portion of the second hybrid fin 106b.

[0008] In some embodiments, one or more layers are formed and structured on the substrate 102, for example by etching vias, to form at least part of the first hybrid fin 106a and / or at least part of the second hybrid fin 106b. In some embodiments, at least one of the first hybrid fin 106a and the second hybrid fin 106b comprises multiple layers. In some embodiments, at least one of the first hybrid fin 106a and the second hybrid fin 106b comprises at least one of a first silicon (Si) layer 108, a silicon germanium (SiGe) layer 110, a second Si layer 112, a pad oxide layer 114, a silicon carbide nitrogen (SiCN) layer 116, a pad Si layer 118, a silicon nitride (SiN) layer 120, or other suitable materials. Further embodiments are being considered, and the present disclosure is not limited to the layers mentioned above.In some embodiments, the first hybrid fin 106a and the second hybrid fin 106b have the same composition. In some embodiments, the first hybrid fin 106a and the second hybrid fin 106b do not have the same composition.

[0009] In some embodiments, a dielectric layer 104 is formed over a top surface and side walls of the first hybrid fin 106a and / or a top surface and side walls of the second hybrid fin 106b. In some embodiments, the first hybrid fin 106a is located adjacent to the second hybrid fin 106b. In some embodiments, there are no intermediate structures between the first hybrid fin 106a and the second hybrid fin 106b. In some embodiments, only the dielectric layer 104 is located between the first hybrid fin 106a and the second hybrid fin 106b. In some embodiments, the dielectric layer 104 comprises at least one of the following: a polymer, polybenzobisoxazole (PBO), a polyimide (PI), oxide, nitride, silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, silicon dioxide, sapphire, or other suitable materials.In some embodiments, the dielectric layer 104 is formed by at least one of the following: physical vapor deposition (PVD), spin sputtering, chemical vapor deposition (CVD), low-pressure phosphorylation (LPCVD), chemical atomic layer vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), pressure-reduced CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and other suitable methods.

[0010] Fig. Figure 2 illustrates the semiconductor arrangement 100 according to some embodiments, comprising a hard mask layer 202 and a photoresist layer 204 formed over the dielectric layer 104. In some embodiments, the photoresist layer 204 comprises a photosensitive material such that properties, such as solubility, of the photoresist layer 204 are influenced by light. The photoresist layer 204 is either a negative photoresist or a positive photoresist. With respect to a negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source, such that the application of a solvent to the negative photoresist during a subsequent development phase removes unilluminated regions of the negative photoresist.A structure formed in the negative photoresist is thus a negative of a structure defined by opaque regions of a stencil between the light source and the negative photoresist. In a positive photoresist, illuminated regions of the positive photoresist become soluble and are removed during development by the application of a solvent or etchant. Therefore, a structure formed in the positive photoresist is a positive image of opaque regions of the stencil between the light source and the positive photoresist.

[0011] In some embodiments, the photoresist layer 204 comprises several layers (not shown). According to some embodiments, the photoresist layer 204 comprises three layers: an upper layer, a middle layer below the upper layer, and a lower layer below the middle layer. In some embodiments, the uppermost layer comprises a photosensitive material as described above. In some embodiments, the middle layer comprises an anti-reflective material to aid in the exposure and / or focusing of the photosensitive material during processing. In some embodiments, the lower layer comprises a hard mask material, such as nitride and / or other suitable materials.In some embodiments, the photoresist layer 204 is formed by at least one of the following: physical vapor deposition (PVD), spin sputtering, chemical vapor deposition (CVD), low-pressure atomic layer vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), pressure-reduced CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and other suitable methods.

[0012] In some embodiments, the hard mask layer 202 comprises at least one of oxide, nitride, silicon, and other suitable materials. In some embodiments, the hard mask layer 202 is formed by at least one of the following: physical vapor deposition (PVD), spin sputtering, chemical vapor deposition (CVD), low-pressure atomic layer vapor deposition (LPCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), and other suitable processes.

[0013] In some embodiments, the photoresist layer 204 is in direct contact with the hard mask layer 202. In some embodiments, the photoresist layer 204 and the hard mask layer 202 have different etch selectivities, such that an etchant applied to the photoresist layer 204 and the hard mask layer 202 etches or removes the hard mask layer 202, but does not etch the photoresist layer 204 or etches it to a lesser extent. According to some embodiments, a structure formed in the photoresist layer 204 is thus transferred to the hard mask layer 202 by etching. In some embodiments, the photoresist layer 204 and the dielectric layer 104 have different etch selectivities, such that an etchant applied to the photoresist layer 204 and the dielectric layer 104 etches or removes the dielectric layer 104, but does not etch or etches the photoresist layer 204 to a lesser extent.According to some embodiments, a structure formed in the photoresist layer 204 is thus transferred to the dielectric layer 104 by etching to form a first recess 206. In some embodiments, the hard mask layer 202 and the dielectric layer 104 have different etch selectivities, such that an etchant applied to the hard mask layer 202 and the dielectric layer 104 etches or removes the dielectric layer 104, but does not etch the hard mask layer 202 or etches it to a lesser extent. According to some embodiments, a structure formed in the hard mask layer 202 is thus transferred to the dielectric layer 104 by etching to form the first recess 206.In some embodiments, the structure formed in the photoresist layer 204 is transferred to the hard mask layer 202, the photoresist layer 204 is removed, and then the structure in the hard mask layer 202 is transferred to the dielectric layer 104 to form the first recess 206. In some embodiments, the second hybrid fin 106b is exposed through the first recess 206. In some embodiments, at least one of etching with hydrogen chloride (HCl₂), etching with hydrogen sulfide (H₂S), dry etching, wet etching, plasma etching, and other suitable methods is implemented to form the first recess 206. In some embodiments, an etchant used to form the first recess 206 is a gas.

[0014] Fig. Figure 3 illustrates a second recess 208 formed in the dielectric layer 104 by removing at least part of the second hybrid fin 106b, according to some embodiments. In some embodiments, the photoresist layer 204 and / or the hard mask layer 202 are removed before the second recess 208 is formed. In some embodiments, the photoresist layer 204 and / or the hard mask layer 202 are not removed before the second recess 208 is formed.

[0015] In some embodiments, at least one of the following processes is implemented to form the second recess 208: silicon tetrafluoride (SiF4), hydrogen chloride (HCl2), hydrogen sulfide (H2S), silicon tetrachloride (SiCl4), oxygen (O2), nitrogen (N2), chlorine (Cl2), dry etching, wet etching, plasma etching, or other suitable methods. In some embodiments, the etchant used to form the second recess 208 is a gas. In some embodiments, more of the dielectric layer 104 is removed when the second recess 208 is formed, thereby deepening the first recess 206. In some embodiments, a top surface 122 of the dielectric layer 104, which defines the first recess 206, is protected, for example by the photoresist layer 204 and / or the hard mask layer 202, when the second recess 208 is formed.If the uppermost surface 122 of the dielectric layer 104 is protected, the overall height of the dielectric layer 104 experiences little to no reduction in some embodiments, even when the first recess 206 is deepened while the second recess 208 is formed.

[0016] In some embodiments, an initial etching is used to form the first recess 206. In some embodiments, a first etching is used to form the second recess 208. In some embodiments, the initial etching differs from the first etching in at least one of the following: etching time, etching pressure, etching temperature, etching bias / voltage, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc. In some embodiments, a first section 124 of a side wall 126 of the dielectric layer 104 is exposed when part of the second hybrid fin 106b is removed by the first etching.In some embodiments, at least one of the initial etching and the first etching is dynamic in that at least one of the etching pressure, etching temperature, etching preload / tension, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc., is varied during the initial etching and / or the first etching. In some embodiments, at least one of the initial etching and the first etching is performed in one or more stages, with the etching being stopped or almost stopped and then resumed in a subsequent stage. In some embodiments, at least one of the etching time, etching pressure, etching temperature, etching preload / tension, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc., is varied.during or between one or more stages of at least one of the original etching, the first etching or other etchings.

[0017] Fig. Figure 4 illustrates the semiconductor arrangement 100 with a first protective layer 406 formed over the top surface 122 of the dielectric layer 104, which defines the first recess 206, a side wall 128 of the dielectric layer 104, which defines the first recess 206, a top surface 130 of the dielectric layer 104, which defines the second recess 208, and the first section 124 of the side wall 126 of the dielectric layer 104, which defines the second recess, according to some embodiments. In some embodiments, the first protective layer 406 is formed during the first etching. In some embodiments, the first protective layer 406 is formed from a first accumulation of by-product material formed from an etchant of the first etching that interacts with the second hybrid fin 106b. In some embodiments, the first protective layer 406 comprises at least one of SiO2, Cl2, SiO x F y, where x and y are integers, an oxygen-rich formulation, and SiO x Cl y , where x and y are integers. In some embodiments, the SiO2 is a solid. In some embodiments, the SiO2 is formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the SiO2 is a gas. In some embodiments, the O2 that forms the SiO2 is a gas. In some embodiments, the Cl2 is a gas. In some embodiments, the Cl2 is formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the Cl2 is a gas. In some embodiments, the O2 that forms the Cl2 is a gas. In some embodiments, the SiO x F y formed from F radicals and oxygen. In some embodiments, the F radicals that form the SiO x F y form a gas. In some embodiments, the oxygen that forms the SiO₂ x F yforms a gas. In some embodiments, the oxygen-rich formulation is formed from SiF4 and O2. In some embodiments, the SiF4 forming the oxygen-rich formulation is a gas. In some embodiments, the O2 forming the oxygen-rich formulation is a gas. In some embodiments, the SiO x Cl y formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the SiO2 is... x Cl y forms a gas. In some embodiments, the O2 that forms the SiO2 is... x Cl y forms a gas.

[0018] In some embodiments, the formation of the first protective layer 406 while the second recess 208 is formed by the first etching prevents the unwanted removal of at least the dielectric layer 104 by one or more etchants of the first etching. Preventing such unwanted removal also prevents unwanted particles, material debris, etc., such as those from the dielectric layer 104, from falling into the second recess 208, clogging it, etc., when the first etching takes place. In some embodiments, such particles, material debris, etc., in the second recess 208 delay the progress of the first etching during the removal of the second hybrid fin 106b to form or deepen the second recess 208. In some embodiments, such particles, material debris, etc., in the second recess 208 delay the progress of the first etching because these particles, material debris, etc.exhibit a different etch selectivity than the materials of the second hybrid fin 106b. In some embodiments, if such particles, material debris, etc., are located in the second recess 208, one or more etchants from the first etching process etch laterally more than desired. In some embodiments, preventing such undesired removal also prevents undesired effects on the first hybrid fin 106a. In some embodiments, negative effects on the first hybrid fin 106a occur if not enough of the dielectric layer 104 remains around the first hybrid fin 106a, for example, if excessive lateral etching takes place.In some embodiments, where not enough of the dielectric layer 104 remains around the first hybrid fin 106a, the first hybrid fin 106a itself is affected by one or more etchants from the first etching process, for example, if at least one of the first recess 206 and the second recess 208 is designed to be too large or wide, potentially exposing the first hybrid fin 106a to one or more etchants from the first etching process. In some embodiments, the first hybrid fin 106a functions as a vertical transistor. In some embodiments, the operation of a vertical transistor is improved if the vertical transistor has a large aspect ratio. In some embodiments, the first hybrid fin 106a has a relatively large aspect ratio such that, when operated as a vertical transistor, the first hybrid fin 106a functions as desired.In some embodiments, the second hybrid fin 106b has a relatively large aspect ratio before the initial etching and / or the first etching. In some embodiments, the second recess 208 is designed to have a large aspect ratio that mirrors the large aspect ratio of the second hybrid fin 106b, in order to increase the likelihood that the first hybrid fin 106a will not be negatively affected by the first etching, for example, if the first etching is too laterally etched and the first hybrid fin 106a is exposed to one or more etchants of the first etching that alter, such as reduce, the aspect ratio of the first hybrid fin 106a.

[0019] Fig. Figure 5 illustrates the semiconductor arrangement 100 after a first flash has been performed, according to some embodiments, to remove at least a portion of the first protective layer 406. In some embodiments, the first flash removes at least a portion of the first protective layer 406 from at least a portion of the top surface 122 of the dielectric layer 104 defining the first recess 206, and / or at least a portion of the side wall 128 of the dielectric layer 104 defining the first recess 206, and / or at least a portion of the top surface 130 of the dielectric layer 104 defining the second recess 208, and / or at least a portion of the first section 124 of the side wall 126 of the dielectric layer 104 defining the second recess. In some embodiments, the first flash involves the use of at least one of oxygen, nitrogen, sulfur dioxide, and other suitable materials.In some embodiments, the first flash involves the use of plasma. In some embodiments, the first flash removes at least some particles, material debris, etc., located in the second recess 208. In some embodiments, chemical-mechanical polishing (CMP) is performed after the first flash to remove residual amounts of the first protective layer 406, such as from the top surface 122 of the dielectric layer 104. In some embodiments, one or more additional etching and flashing cycles are implemented to create the second recess 208 to a desired depth. In some embodiments, one or more additional etching and flashing cycles are implemented to create the second recess 208 to a desired aspect ratio.

[0020] Fig. Figure 6 illustrates the semiconductor arrangement 100 according to some embodiments after a second etching has been used to deepen the second recess 208. In some embodiments, the second etching incorporates at least one of the following techniques: silicon tetrafluoride (SiF4) etching, hydrogen chloride (HCl2) etching, hydrogen sulfide (H2S) etching, silicon tetrachloride (SiCl4) etching, oxygen (O2) etching, nitrogen (N2) etching, chlorine (Cl2) etching, dry etching, wet etching, plasma etching, or other suitable techniques. In some embodiments, the etchant used in the second etching is a gas. In some embodiments, more of the dielectric layer 104 is removed during the second etching, thereby deepening the first recess 206.In some embodiments, the top surface 122 of the dielectric layer 104, which defines the first recess 206, is protected, for example by a photoresist layer and / or a hard mask layer, when the second etching is performed. When the top surface 122 of the dielectric layer 104 is protected, the overall height of the dielectric layer 104 experiences little to no reduction in some embodiments, even when the first recess 206 is deepened during the second etching.

[0021] In some embodiments, the second etching differs from the initial etching and / or the first etching with respect to at least one of the following: etching time, etching pressure, etching temperature, etching bias / voltage, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc. In some embodiments, a second section 132 of the side wall 126 of the dielectric layer 104 is exposed because more of the second hybrid fin 106b is removed by the second etching. In some embodiments, the second etching is dynamic in that at least one of the following is varied during the second etching: etching pressure, etching temperature, etching bias / voltage, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc.In some embodiments, the second etching is performed in one or more stages, with the etching being stopped or almost stopped and then resumed in a subsequent stage. In some embodiments, at least one of the etching time, etching pressure, etching temperature, etching preload / tension, etchant composition, etchant concentration, etchant state (such as solid, liquid, plasma, or gas), or other etching conditions, parameters, etc., varies during or between one or more stages of the second etching.

[0022] Fig. Figure 7 illustrates the semiconductor arrangement 100 with a second protective layer 606 formed over the top surface 122 of the dielectric layer 104, which defines the first recess 206, the side wall 128 of the dielectric layer 104, which defines the first recess 206, the top surface 130 of the dielectric layer 104, which defines the second recess 208, the first section 124 of the side wall 126 of the dielectric layer 104, which defines the second recess 208, and the second section 132 of the side wall 126 of the dielectric layer 104, which defines the second recess 208, according to some embodiments. In some embodiments, the second protective layer 606 is formed during the second etching. In some embodiments, the second protective layer 606 is formed from a second accumulation of by-product material formed from an etchant of the second etching that interacts with the second hybrid fin 106b.In some embodiments, the second protective layer 606 comprises at least one of SiO2, Cl2, SiO. x F y , where x and y are integers, an oxygen-rich formulation, and SiO x Cl y , where x and y are integers. In some embodiments, the SiO2 is a solid. In some embodiments, the SiO2 is formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the SiO2 is a gas. In some embodiments, the O2 that forms the SiO2 is a gas. In some embodiments, the Cl2 is a gas. In some embodiments, the Cl2 is formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the Cl2 is a gas. In some embodiments, the O2 that forms the Cl2 is a gas. In some embodiments, the SiO x F y formed from F radicals and oxygen. In some embodiments, the F radicals that form the SiO x Fy form a gas. In some embodiments, the oxygen that forms the SiO₂ x F y forms a gas. In some embodiments, the oxygen-rich formulation is formed from SiF4 and O2. In some embodiments, the SiF4 forming the oxygen-rich formulation is a gas. In some embodiments, the O2 forming the oxygen-rich formulation is a gas. In some embodiments, the SiO x Cl y formed from SiCl4 and O2. In some embodiments, the SiCl4 that forms the SiO2 is... x Cl y forms a gas. In some embodiments, the O2 that forms the SiO2 is... x Cl y forms a gas. In some embodiments, the second protective layer 606 has the same composition as the first protective layer 406. In some embodiments, the second protective layer 606 does not have the same composition as the first protective layer 406.

[0023] In some embodiments, the formation of the second protective layer 606 during the formation of the second recess 208 by the second etching prevents the unwanted removal of at least the dielectric layer 104 by one or more etchants of the second etching. Preventing such unwanted removal also prevents unwanted particles, material debris, etc., such as those from the dielectric layer 104, from falling into the second recess 208, clogging it, etc., when the second etching takes place. In some embodiments, such particles, material debris, etc., in the second recess 208 delay the progress of the second etching during the removal of the second hybrid fin 106b to deepen the second recess 208. In some embodiments, such particles, material debris, etc., in the second recess 208 delay the progress of the second etching because these particles, material debris, etc.exhibit a different etch selectivity than the materials of the second hybrid fin 106b. In some embodiments, if such particles, material debris, etc., are located in the second recess 208, one or more etchants of the second etching process etch laterally more than desired. In some embodiments, preventing such undesired removal also prevents undesired effects on the first hybrid fin 106a. In some embodiments, negative effects on the first hybrid fin 106a occur if not enough of the dielectric layer 104 remains around the first hybrid fin 106a, for example, if excessive lateral etching takes place.In some embodiments where not enough of the dielectric layer 104 remains around the first hybrid fin 106a, the first hybrid fin 106a itself is affected by one or more etchants of the second etching, for example, if at least one of the first recess 206 and the second recess 208 is designed to be too large or wide, possibly exposing the first hybrid fin 106a to one or more etchants of the second etching.In some embodiments, the second recess 208 is designed to have the large aspect ratio of the second hybrid fin 106b in order to increase the probability that the first hybrid fin 106a is not negatively affected by the second etching, for example, if the first etching etches too much laterally and exposes the first hybrid fin 106a to one or more etchants of the second etching that change, such as reduce, the aspect ratio of the first hybrid fin 106a.

[0024] Fig. Figure 8 illustrates the semiconductor arrangement 100 after a second flash has been performed, according to some embodiments, to remove at least a portion of the second protective layer 606. In some embodiments, the second flash removes at least a portion of the second protective layer 606 from at least a portion of the top surface 122 of the dielectric layer 104 defining the first recess 206, and / or at least a portion of the side wall 128 of the dielectric layer 104 defining the first recess 206, and / or at least a portion of the top surface 130 of the dielectric layer 104 defining the second recess 208, and / or at least a portion of the first section 124 of the side wall 126 of the dielectric layer 104 defining the second recess 208, and / or at least a portion of the second section 132 of the side wall 126 of the dielectric layer 104 defining the second recess.In some embodiments, the second flash includes the use of at least one of oxygen, nitrogen, sulfur dioxide, and other suitable materials. In some embodiments, the second flash includes the use of plasma. In some embodiments, the second flash removes at least some particles, material debris, etc., located in the second recess 208. In some embodiments, a CMP is performed after the second flash to remove residual amounts of the second protective layer 606, for example, from the top surface 122 of the dielectric layer 104. In some embodiments, the second flash is implemented in the same way as the first flash. In some embodiments, the second flash is implemented differently from the first flash, for example, using one or more different chemicals.In some embodiments, one or more additional etching and flashing cycles are implemented to create the second recess 208 to a desired depth. In some embodiments, one or more additional etching and flashing cycles are implemented to create the second recess 208 to a desired aspect ratio. In some embodiments, one or more flashes are implemented in the same way as, or differently from, one or more other flashes. According to some embodiments, the cyclic etching / flashing is suitable for a variety of large aspect ratio applications, such as nanowires, and is not limited to the specific structures, materials, etc., described in this text.

[0025] In some embodiments, a desired minimum height of the top surface 130 of the dielectric layer 104, which defines the second recess 208, is located at a height above a top surface of an adjacent hybrid fin, such as the first hybrid fin 106a. In some embodiments, the top surface of the first hybrid fin 106a does not include at least one of the second Si layer 112, the pad oxide layer 114, the silicon carbide nitrogen (SiCN) layer 116, the pad Si layer 118, or the silicon nitride (SiN) layer 120. In some embodiments, the top surface of the first hybrid fin 106a corresponds to the silicon germanium (SiGe) layer 110, but the present disclosure is not limited to these.In some embodiments, the first hybrid fin 106a functions as a transistor or other suitable arrangement, and maintaining the desired minimum height of the top surface 130 of the dielectric layer 104, which defines the second recess 208, at a height above the top surface of the first hybrid fin 106a supports the desired functioning of the first hybrid fin 106a.

[0026] Fig. Figure 9 illustrates an enlarged view of the semiconductor arrangement 100 to show one or more critical dimensions (CDs) according to some embodiments. In some embodiments, the first recess 206 has a first width 804 of about 50 nm. In some embodiments, the second recess 208 has a second width 806 of about 10 nm. In some embodiments, the second width 806 is equal to or approximately equal to the width of the second hybrid fin 106b. In some embodiments, the first width 804 is greater than the second width 806. In some embodiments, the second recess 208 has a depth 808 of about 100 nm. In some embodiments, the second recess 208 has a relatively large depth-to-width aspect ratio of 100 nm / 10 nm or 10. Other aspect ratios are also considered according to some embodiments.In some embodiments, the second width 806 is reduced, and / or the depth 808 is increased to achieve a larger aspect ratio.

[0027] Fig. Figure 10 illustrates an electrical bias applied to the semiconductor arrangement 100 according to some embodiments, such as during the first etching, which is performed with respect to Fig. 3 and Fig.4 is described. According to some embodiments, an electrical bias is applied to all stages of one or more of the operations described in this text, such as etching and / or flashing. In some embodiments, etching is a chemical process that has a reaction rate, and the electrical bias 904 serves as a catalyst to modify, for example, increase the reaction rate. According to some embodiments, a voltage source 902, which generates a DC or AC electrical bias 904, is applied to the semiconductor arrangement 100. In some embodiments, the electrical bias 904 is applied to an etchant and one or more layers of the semiconductor arrangement 100, such as the substrate 102, to establish a potential difference between the etchant and the one or more layers.In some embodiments, the electrical bias is applied to an etchant by applying it to a cathode or anode located in a chamber into which the etchant is introduced, etc. In some embodiments, the electrical bias 904 is applied to one or more layers of the semiconductor arrangement 100 to establish a potential difference between a first layer and a second layer, wherein the first layer or the second layer may optionally be the substrate 102, and the first layer and the second layer may optionally be in contact with each other. According to some embodiments, other configurations are also considered. In some embodiments, the electrical bias is used to generate a plasma, such as for flashing.In some embodiments, the electrical bias generates a plasma by being applied to a cathode or anode located in a chamber containing one or more chemicals, agents, etc., and to one or more layers, such as the substrate 102, of the semiconductor arrangement 100, in order to establish a potential difference between the cathode or anode and the one or more layers. According to some embodiments, applying the electrical bias 904 during etching enables the formation of the protective layer. According to some embodiments, applying the electrical bias 904 during etching improves the efficiency of the etching and reduces the time required to form the first recess 206 and / or the second recess.In some embodiments, applying the electrical bias 904 during etching improves the uniformity of the etch depth and forms a more vertical first profile of the first recess 206 and / or a more vertical second profile of the second recess 208. In some embodiments, the electrical bias 904 is on the order of 1000 volts or more, depending on at least one of the desired depths of the first recess 206, the desired depth of the second recess 208, the desired etching time, the desired plasma to be developed, one or more materials to be etched, one or more materials to be flashed, and other suitable factors, considerations, etc.

[0028] According to some embodiments, a method for fabricating a semiconductor assembly includes performing a first etching of a semiconductor structure to expose a first portion of a sidewall of a first layer adjacent to the semiconductor structure. In some embodiments, the first etching forms a first protective layer on the first portion of the sidewall of the first layer. In some embodiments, the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching that interacts with the semiconductor structure. In some embodiments, the method includes performing a first flash to remove at least one portion of the first protective layer.

[0029] In some embodiments, the method includes performing a second etching of the semiconductor structure after the first flash to expose a second section of the sidewall of the first layer. In some embodiments, the second etching forms a second protective layer on the first section of the sidewall of the first layer and on the second section of the sidewall of the first layer. In some embodiments, the second protective layer is formed from a second accumulation of by-product material formed from a second etchant of the second etching, which interacts with the semiconductor structure.

[0030] In some embodiments, the method includes performing a second flash to remove at least one section of the second protective layer.

[0031] In some embodiments, the execution of the first flash involves the use of plasma.

[0032] In some embodiments, the execution of the first flash involves the use of at least one of oxygen, nitrogen, and sulfur dioxide.

[0033] In some embodiments, the first etching process includes applying an electrical bias to the semiconductor arrangement.

[0034] In some embodiments, the electrical bias voltage is at least 1000 volts.

[0035] In some embodiments, the first protective layer contains at least one of SiO₂. x F y and SiO x Cl y , where x is a positive integer and y is a positive integer.

[0036] In some embodiments, the method includes performing a chemical-mechanical polishing (CMP) process after the first flash to remove residual amounts of the first protective layer.

[0037] According to some embodiments, a method for fabricating a semiconductor assembly includes performing a first etching of a semiconductor structure to expose a first section of a sidewall of a first layer adjacent to the semiconductor structure. In some embodiments, performing the first etching includes contacting the semiconductor structure with a first etchant to remove a stack of materials comprising at least one silicon germanium layer, a silicon layer, an oxide layer, a silicon carbide nitrogen layer, and a silicon nitride layer, and forming a first protective layer on the first section of the sidewall of the first layer.

[0038] In some embodiments, the first protective layer is formed from a first accumulation of by-product material formed from the first etchant that interacts with the semiconductor structure.

[0039] In some embodiments, the method includes performing a first flash to remove at least one section of the first protective layer.

[0040] In some embodiments, the method includes performing a second etching of the semiconductor structure after the first flash to expose a second section of the sidewall of the first layer, wherein the second etching forms a second protective layer on the first section of the sidewall of the first layer and on the second section of the sidewall of the first layer.

[0041] In some embodiments, the first etchant contains at least one of SiCl4 and O2.

[0042] In some embodiments, performing the first etching includes applying an electrical bias voltage to form the first protective layer.

[0043] In some embodiments, the first protective layer contains at least one of SiO₂. x F yand SiO x Cl y , where x is a positive integer and y is a positive integer.

[0044] According to some embodiments, a method for fabricating a semiconductor assembly includes forming a first recess in a first layer to expose a first semiconductor structure located beneath the first layer. In some embodiments, the method includes forming a second recess in the first layer by removing at least a portion of the first semiconductor structure, wherein a top surface of the first layer defining the second recess lies above a top surface of a second semiconductor structure adjacent to the first semiconductor structure.

[0045] In some embodiments, forming the second recess includes performing a first etching of the first semiconductor structure to expose a first section of a sidewall of the first layer adjacent to the first semiconductor structure, wherein the first etching forms a first protective layer on the first section of the sidewall of the first layer and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching that interacts with the first semiconductor structure.

[0046] In some embodiments, the formation of the second recess includes performing a first flash to remove at least part of the first protective layer.

[0047] In some embodiments, the method includes performing a second etching of the first semiconductor structure after the first flash to expose a second section of the sidewall of the first layer, wherein the second etching forms a second protective layer on the first section of the sidewall of the first layer and on the second section of the sidewall of the first layer, and the second protective layer is formed from a second accumulation of by-product material formed from an etchant of the second etching that interacts with the first semiconductor structure.

[0048] The above outlines features of various embodiments to help the person skilled in the art better understand different aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

[0049] Although the subject matter has been described in terms specific to structural features and / or methodological actions, it is understood that the subject matter of the accompanying claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementation of at least some of the claims.

[0050] Various embodiments have been described in this text. The order in which some or all of the processes are described should not be interpreted as implying that these processes are necessarily sequential. Readers who have the opportunity to read this description will likely conceive of other sequences. Furthermore, it is understood that not all processes necessarily occur in every embodiment described in this text. It is also understood that not all processes are necessary in some embodiments.

[0051] It is understood that the layers, structural elements, components, etc., shown in this text have been illustrated with specific dimensions relative to each other, such as structural dimensions or orientations, for the sake of simplicity and clarity, and that their actual dimensions may differ considerably from those shown in this text in some embodiments. Furthermore, there are numerous techniques for forming the layers, regions, structural elements, components, etc., mentioned in this text, including at least one etching technique, planarization technique, implantation technique, doping technique, spin coating technique, sputtering technique, growth technique, and deposition technique, such as chemical vapor deposition (CVD).

[0052] Furthermore, the word "exemplary" in the context of this application means "serving as an example or for illustration" and not necessarily "advantageous". For the purposes of this application, "or" is to be understood as an inclusive "or" and not an exclusive "or". Moreover, "one" in the context of this application and the attached claims is generally to be understood as meaning "one or more", unless otherwise indicated or the context unambiguously requires a singular interpretation. In addition, "at least one of A and B" and / or the like generally means A or B or both A and B. Furthermore, to the extent that "contains", "has", "exhibits", "with", or variants thereof are used, these terms are to be understood as inclusive in a similar way to the term "comprising".Furthermore, unless otherwise specified, "first," "second," or the like are not intended to imply any temporal aspect, spatial aspect, sequence, etc. Rather, such terms are used merely as identifiers, names, etc., for structural elements, elements, things, etc. For example, a first element and a second element generally correspond to element A and element B, or to two different or two identical elements, or to the same element.

Claims

[1] A method of manufacturing a semiconductor device (100), comprising: Performing a first etch of a semiconductor structure that is a hybrid fin (106b) to expose a first portion (124) of a sidewall (126, 128) of a dielectric layer (104) adjacent to the semiconductor structure when a portion of the hybrid fin (106b) is removed by the first etch, wherein: the first etching forms a first protective layer (406) on the first portion (124) of the sidewall (126, 128) of the dielectric layer (104), and the first protective layer (406) is formed from a first collection of by-product material formed from an etchant of the first etch that interacts with the semiconductor structure; and Performing a first process for removing at least a portion of the first protective layer (406). [2] A method according to claim 1, comprising: Performing a second etch of the semiconductor structure after the first process to expose a second portion (132) of the sidewall (126, 128) of the first layer (104), wherein: the second etching forms a second protective layer (606) on the first portion (124) of the sidewall (126, 128) of the first layer (104) and on the second portion (132) of the sidewall (126, 128) of the first layer (104), and the second protective layer (606) is formed from a second collection of by-product material formed from a second etchant of the second etch that interacts with the semiconductor structure. [3] A method according to claim 2, comprising: Performing a second process to remove at least a portion of the second protective layer (606). [4] A method according to any one of the preceding claims, wherein performing the first process comprises using plasma. [5] A method according to any one of the preceding claims, wherein carrying out the first process comprises using at least one of oxygen, nitrogen and sulfur dioxide. [6] The method of any preceding claim, wherein performing the first etching comprises applying an electrical bias voltage (904) to the semiconductor device (100). [7] The method of claim 6, wherein the electrical bias voltage (904) is at least 1000 volts. [8] Method according to one of the preceding claims, wherein the first protective layer (406) comprises at least one of SiO x F y and SiO x Cl y where x is a positive integer and y is a positive integer. [9] A method according to any one of the preceding claims, comprising: Performing a chemical mechanical polishing, CMP, after the first process to remove residual amounts of the first protective layer (406). [10] A method of manufacturing a semiconductor device (100), comprising: Performing a first etch of a semiconductor structure that is a hybrid fin (106b) to expose a first portion (124) of a sidewall (126, 128) of a dielectric layer (104) adjacent to the semiconductor structure when a portion of the hybrid fin (106b) is removed by the first etch, wherein performing the first etch comprises: contacting the semiconductor structure with a first etchant to remove a stack of materials comprising at least one of a silicon germanium layer (110), a silicon layer (108, 112), an oxide layer (114), a silicon carbide nitrogen layer (116), and a silicon nitride layer (120); and Forming a first protective layer (406) on the first portion (124) of the sidewall (126, 128) of the first layer (104). [11] The method of claim 10, wherein the first protective layer (406) is formed from a first collection of by-product material formed from the first etchant interacting with the semiconductor structure. [12] A method according to claim 10 or 11, comprising: Performing a first process for removing at least a portion of the first protective layer (406). [13] A method according to claim 12, comprising: Performing a second etch of the semiconductor structure after the first process to expose a second portion (132) of the sidewall (126, 128) of the first layer (104), wherein the second etch forms a second protective layer (606) on the first portion (124) of the sidewall (126, 128) of the first layer (104) and on the second portion (132) of the sidewall (126, 128) of the first layer (104). [14] A method according to any one of the preceding claims 10 to 13, wherein the first etchant comprises at least one of SiCl4 and O2. [15] The method of any one of the preceding claims 10 to 14, wherein performing the first etching comprises applying an electrical bias (904) to form the first protective layer (406). [16] Method according to one of the preceding claims 10 to 15, wherein the first protective layer (406) comprises at least one of SiO x F y and SiO x Cl ywhere x is a positive integer and y is a positive integer. [17] A method of manufacturing a semiconductor device (100), comprising: Forming a first recess (206) in a first layer (104) to expose a first semiconductor structure, which is a hybrid fin (106b), beneath the first layer (104); and Forming a second recess (208) in the first layer (104) by removing at least a portion of the first semiconductor structure, wherein a top surface (130) of the first layer (104) defining the second recess (208) lies above a top surface (122) of a second semiconductor structure adjacent to the first semiconductor structure, wherein forming the second recess (208) comprises: Performing a first etch of the first semiconductor structure to expose a first portion (124) of a sidewall (126, 128) of the first layer (104) adjacent to the first semiconductor structure when a portion of the hybrid fin (106b) is removed by the first etch, wherein: the first etching forms a first protective layer (406) on the first portion (124) of the sidewall (126, 128) of the first layer (104), and the first protective layer (406) is formed from a first collection of by-product material formed from an etchant of the first etch that interacts with the first semiconductor structure. [18] The method of claim 17, wherein the first protective layer (406) is formed during the first etching. [19] The method of claim 17 or claim 18, wherein forming the second recess (208) comprises performing a first process for removing at least a portion of the first protective layer (406). [20] A method according to claim 19, comprising: Performing a second etch of the first semiconductor structure after the first process to expose a second portion (132) of the sidewall (126, 128) of the first layer (104), wherein: the second etching forms a second protective layer (606) on the first portion (124) of the sidewall (126, 128) of the first layer (104) and on the second portion (132) of the sidewall (126, 128) of the first layer (104), and the second protective layer (606) is formed from a second collection of by-product material formed from an etchant of the second etch that interacts with the first semiconductor structure.

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