DIRECT ACCESS STORAGE

Abstract

Memory cell (MC) comprising: a stack of memory cells; a first word line (WL0); a second word line (WLa0); a bit line (BL0) that is coupled to one end of the memory cell stack; a first unidirectional selector (US1) having one end coupled to another end of the memory cell stack and another end coupled to the first word line (WLo); and a second unidirectional selector (US2) which has one end coupled to the other end of the memory cell stack and another end coupled to the second word line (WLao), wherein the current flow directions of the first unidirectional selector (US1) and the second unidirectional selector (US2) are opposite, wherein the memory cell stack comprises an MTJ structure which has a cover layer (145) formed on a free magnetic layer (140) and a diffusion barrier layer (150) formed on the cover layer (145).

Description

TECHNICAL BACKGROUND

[0001] MRAM offers comparable performance to volatile static random-access memory (SRAM) and comparable density with lower power consumption than volatile dynamic random-access memory (DRAM). Compared to non-volatile (NVM) flash memory, MRAM offers much faster access times and exhibits minimal degradation over time, whereas flash memory can only be overwritten a limited number of times. An MRAM cell is formed by a magnetic tunnel junction (MTJ), which comprises two ferromagnetic layers separated by a thin insulating barrier, and operates by tunneling electrons between the two ferromagnetic layers through the insulating barrier.

[0002] Similarly, a resistive random access memory (ReRAM or RRAM) is a type of non-volatile random access memory that works by changing the resistance via a dielectric solid-state material.

[0003] Furthermore, a phase-change random-access memory (PCRAM) is a non-volatile storage device that utilizes different resistive phases and heat-induced phase transitions between the phases of the phase-change material. A PCRAM is composed of numerous cells that operate independently of one another. A PCRAM cell primarily comprises a heater and a resistor, which is a data storage element primarily composed of reversible phase-change material to provide at least two dramatically different resistance levels for the logical "o" state and the "1" state. To read a state (data) from the PCRAM cell, a sufficiently small current is applied to the phase-change material without causing the heater to generate heat. The resistivity of the phase-change material can be measured at this switch, and the states representing the resistivity, i.e.,An "o" state for high resistivity or a "1" state for low resistivity can be read. To write a state (data) to a PCRAM cell, such as a "1" state to represent a low resistivity phase of the phase-change material, a moderate electric current is applied to the heater, which generates heat long enough to anneal the phase-change material at a temperature above its crystallization temperature but below its melting temperature, thus achieving a crystalline phase.To write an "o" state, representing a phase of high resistivity of the phase-change material, a very large electric current is applied to the heater to generate heat to melt the phase-change material at a temperature above its melting point. The electric current is then abruptly cut off to lower the temperature below the crystallization temperature of the phase-change material, quenching and stabilizing its amorphous structure to create the high-resistance "o" logical state. The very large electric current can be in pulse form. A method and system for a programmable resistor memory, comprising a plurality of programmable resistor units, is known from US Publication 2012 / 0320657A1.Each programmable resistor unit can comprise at least one programmable resistor cell. Each programmable resistor cell can comprise a programmable resistor element coupled at one end to a first supply voltage line and at the other end to at least one diode serving as a program selector. Each diode can have at least one first and one second terminal with a first and a second type of dopant, the second terminal being connected to a second supply voltage line. The first and second terminals of the diode can be made from the source / drain of MOS in a well for MOS devices or on the same polysilicon structure. Similar methods and devices are also known from US 2018 / 0006213A1, DE 112005002818T5, and DE 102019113405A1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a circuit diagram of an MRAM cell array according to an embodiment of this disclosure. Fig. Figure 2 shows a read operation for an MRAM array cell according to one embodiment of this disclosure. Fig. Figure 3 shows a write operation for an MRAM array cell according to one embodiment of this disclosure. Fig. Figure 4 shows a write operation for an MRAM array cell according to one embodiment of this disclosure. Fig. Figure 5 shows a write operation for an MRAM array cell according to one embodiment of this disclosure. Fig. Figure 6 shows a write operation for an MRAM cell array according to an embodiment of this disclosure. Fig. Figure 7 shows a circuit diagram and a read operation for an MRAM cell array according to another embodiment of this disclosure. Fig. Figure 8 shows a write operation for an MRAM cell array according to one embodiment of this disclosure. Fig. Figure 9 shows a write operation for an MRAM cell array according to one embodiment of this disclosure. Fig. Figure 10 shows a structural configuration of an MRAM cell according to an embodiment of this disclosure. Fig. 11A and Fig. Figure 11B shows cross-sectional views of an MTJ film stack according to an embodiment of this disclosure. Fig. 12A, Fig. 12B and Fig. Figure 12C shows schematic cross-sectional views of the magnetic layers of the MTJ film stack according to an embodiment of this disclosure. Fig. Figure 13 shows a schematic cross-sectional view of the MRAM cell according to an embodiment of this disclosure. Fig. Figure 14 shows a schematic cross-sectional view of the MRAM cell according to an embodiment of this disclosure. Fig. Figure 15 shows a schematic cross-sectional view of the MRAM cell according to an embodiment of this disclosure. Fig. Figure 16 shows a schematic cross-sectional view of the MRAM cell according to an embodiment of this disclosure. Fig. Figure 17 shows a schematic cross-sectional view of the MRAM cell according to an embodiment of this disclosure. Fig. Figure 18 shows a circuit diagram of the MRAM cell according to an embodiment of this disclosure. DETAILED DESCRIPTION

[0004] It is understood that the following disclosure provides many different embodiments or examples for implementing various functions of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values ​​but may depend on process conditions and / or desired properties of the device.Furthermore, the embodiment of a first feature or a second feature in the following description may include embodiments in which the first and second features are in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features do not have to be in direct contact. For the sake of simplicity and clarity, various features may be arbitrarily designated at different scales. In the accompanying drawings, some layers / features may have been omitted for simplification.

[0005] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms should encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative designators used herein may be interpreted accordingly. Furthermore, the term "formed of" may mean either "comprising" or "consisting of."Furthermore, in the following manufacturing process, one or more operations may occur within or between the described operations, and the sequence of operations may be changed. In this disclosure, the term "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element of A, one element of B and one element of C, unless otherwise described.

[0006] Some embodiments of this disclosure are directed to an MRAM comprising memory cells, each containing an MTJ film stack. In other embodiments, an RRAM or a PCRAM may be used instead of an MRAM.

[0007] In a 1T1R MRAM configuration, each memory cell (MTJ bit cell) includes a selector transistor that controls when the bit cell is accessed. In advanced process nodes, the selector transistor is larger than the MTJ bit cell, thus limiting the density of a memory array. Furthermore, the transistor area is proportional to the fin spacing and / or metal gate spacing, and scaling these spacings slows down, further limiting density scaling. MRAM array density can be improved by replacing the transistor selector with a two-terminal selector. However, since the operation of the MRAM MTJ bit cells requires current flow in both directions, the selector must be bidirectional. This makes the selector more complex. A two-terminal selector, in conjunction with an MTJ bit cell, satisfies a set of constraints between the selector cutoff voltage and the MTJ cell voltage to minimize leakage via "sneak paths."

[0008] In the present disclosure, two unidirectional selectors (e.g., diodes) together with three terminals per cell are used to achieve a high-density MRAM array. Unidirectional selectors are easier to fabricate in a back-end-of-line (BEOL) than bidirectional selectors or transistors. Three terminals per unit cell allow the simultaneous writing of 0s and 1s to different bits along a word line.

[0009] Fig. Figure 1 is a circuit diagram of an MRAM cell array according to an embodiment of this disclosure. In this drawing, “FL” refers to a first magnetic layer as a free magnetic layer, and “PL” refers to a second magnetic layer as a reference layer or a pinned layer in an MTJ film stack. The MTJ film stack further comprises other layers, as described below with reference to Fig. 11 explained.

[0010] As in Fig. As shown in Figure 1, two unidirectional selectors (diodes) are provided for each MTJ bit cell. Each unidirectional diode is connected to a respective word line: a main word line, designated WLx, and an associated word line, designated WLax, thus comprising 3 connections per bit cell (x denotes an integer 0, 1, 2, 3, ...). The diodes are provided in opposite directions for WLx and WLax.

[0011] More precisely, in some embodiments of this disclosure, a storage device comprises multiple memory cells arranged in a matrix, multiple main word lines extending in one direction (e.g., the X-direction) and arranged parallel to each other in another direction (e.g., the Y-direction), multiple associated word lines extending in the X-direction and arranged parallel to each other in the Y-direction, and multiple bit lines extending in the Y-direction and arranged parallel to each other in the X-direction. As described in Fig. As shown in Figure 1, several cells (e.g., three cells) of the memory cell are coupled to one of the main word lines (e.g., WL0) and one of the associated word lines (e.g., WLa0). The number of memory cells coupled to the same word lines is not limited to three and can be more than three, e.g., 4, 8, 16, 32, 64, 128, 256, 512, or 1024 or more. As shown in Figure 1, Fig. As shown in Figure 1, each memory cell MC comprises a memory cell stack. In some embodiments, the memory cell stack comprises an MTJ film stack. The terminal (e.g., an electrode) located closer to the free layer FL is coupled to a corresponding bit line (e.g., BL0). Each memory cell further comprises a first unidirectional selector (first diode) US1 and a second unidirectional selector (second diode) US2. The first diode has a first end (e.g., anode) coupled to another terminal (e.g., electrode) of the memory cell stack located closer to the reference layer PL, and a second end (e.g., cathode) coupled to one of the main word lines (e.g., WL0). The second unidirectional selector has a first end (e.g., cathode) that is coupled to another terminal of the memory cell stack, and a second end (e.g.,Anode), which is coupled with the associated word lines (WLao). As in . Fig. As shown in Figure 1, the current flow directions of the first unidirectional selector and the second unidirectional selector are opposite (opposite to each other). In the following embodiments, the data "0" and "1" can be interchanged.

[0012] In some embodiments, the main word lines are formed from thicker and / or wider (i.e., with lower resistance) conducting wires than the associated word lines, as long as the associated word lines can tolerate thinner metal for an asymmetrically present time - or additional metal can be added to the bottom of the associated word lines.

[0013] Fig. Figure 2 shows a read operation for an MRAM cell according to one embodiment of this disclosure. When reading data from a target memory cell MC, voltages are applied such that only the first diode US1 of the target memory cell MC is activated, while the remaining diodes are deactivated. In some embodiments, a first read voltage Vr1 is applied to a main word line WLo coupled to the target memory cell MC, a second read voltage Vr2 is applied to the remaining main word lines (e.g., WL1, ...) except for the main word line WLo, and a third read voltage Vr3 is applied to a bit line BLo coupled to the target memory cell MC. In some embodiments, the voltage Vr2 is applied before the voltage Vr3 is applied to prevent memory cells coupled to a different bit line BLo than the target memory cell MC from being activated.The second read voltage, Vr2, is higher than the first read voltage, Vr1, and the third read voltage, Vr3, is higher than the first read voltage, Vr1. Thus, a read current flows through the target memory cell, MC, and the first diode, US1, from the bit line, BL0. In some embodiments, the voltage, Vr1, is the ground voltage (0 V). The voltage, Vr3, is higher than a threshold voltage of the first diode, US1 (Vt), and in some embodiments, the voltage, Vr3, is Vt + 50 mV to 200 mV. The voltage level (e.g., 50–200 mV) can vary depending on the memory cell materials and / or structures and is not limited to this range. In some embodiments, the voltage, Vr2, is equal to or higher than the voltage, Vr3. A fourth read voltage, Vr4, is applied to the remaining bit lines. In some embodiments, the voltage, Vr4, is equal to or lower than the voltage, Vr1. For the associated word lines WLao, WLa1, ..., a fifth reading voltage Vr5 is applied.In some embodiments, the voltage Vr5 is equal to or lower than the voltage Vr4. In some embodiments, Vr4-Vr5 is equal to or less than a limit voltage of the second diode US2 (Vt). In certain embodiments, Vr2=Vr3=Vt+ (50 to 200) mV and Vr1=Vr4=Vr5=0V.

[0014] Fig. Figure 3 shows a write operation for an MRAM cell according to one embodiment of this disclosure. When writing first-type data, e.g., "0", to a destination memory cell MC, voltages are applied such that only the first diode US1 of the destination memory cell MC is activated, while the remaining diodes are deactivated. In some embodiments, a first write voltage Vw1 is applied to a main word line WL0 coupled to the destination memory cell MC, a second write voltage Vw2 is applied to the remaining main word lines (e.g., WL1, ...) except for the main word line WL0, and a third write voltage Vw3 is applied to a bit line BLo coupled to the destination memory cell MC. In some embodiments, the voltage Vw2 is applied before the voltage Vw3 is applied. The second write voltage Vw2 is higher than the first write voltage Vw1, and the third write voltage Vw3 is higher than the first write voltage Vw1.A write current flows through the target memory cell MC and the first diode US1 from the bit line BL0. In some embodiments, the voltage Vw1 is the ground voltage (0 V). The voltage Vw3 is higher than a first diode's cutoff voltage (Vt), and in some embodiments, the voltage Vw3 is higher than Vr3 and is Vt + 700 mV to 1000 mV. In some embodiments, the voltage Vw2 is equal to or higher than the voltage Vw3. A fourth write voltage Vw4 is applied to the remaining bit lines BL1, Bl2, ... In some embodiments, the voltage Vw4 is equal to or lower than the voltage Vw1. A fifth write voltage Vw5 is applied to the associated word lines. In some embodiments, the voltage Vw5 is equal to or lower than the voltage Vw4. In some embodiments, Vw4-Vw5 is equal to or less than a second diode's cutoff voltage US2 (Vt).In certain embodiments, Vw2=Vw3=Vt+ (700 to 1000) mV and Vw1=Vw4=Vw5=0 V. In some embodiments, the third write voltage Vw3 is applied to the bit lines that are coupled to two or more memory cells in order to write data “0” simultaneously.

[0015] Fig. Figure 4 shows a write operation for an MRAM cell according to another embodiment of this disclosure. When writing the second type of data, e.g., "1", to a destination memory cell MC, voltages are applied such that the second diode US2, which is coupled to the destination memory cell MC, is activated (turned on), while the remaining diodes are deactivated (turned off). In some embodiments, a first write voltage Vw11 is applied to an associated word line WLa0, a second write voltage Vw12 is applied to the remaining associated word lines WLa1, ..., except for the associated word line WLa0, and a third write voltage Vw13 is applied to a bit line BLo, which is coupled to the destination memory cell MC. In some embodiments, Vw12 is applied before Vw11 and Vw13 are applied.The second write voltage Vw12 is lower than the first write voltage Vw11, and the third write voltage Vw13 is lower than the first write voltage Vw11. Thus, a write current flows through the destination memory cell MC from the first associated world line via the second diode US2. In some embodiments, the voltage Vw11 is higher than a cutoff voltage of the second diode (Vt), and in some embodiments, the voltage Vw11 is Vt + 700 mV to 1000 mV. In some embodiments, the voltage Vw12 is the ground voltage (0 V). In some embodiments, the voltage Vw12 is equal to or less than the voltage Vw13. A fourth write voltage Vw14 is applied to the remaining bit lines BL1, ...,. In some embodiments, the voltage Vw14 is equal to or higher than the voltage Vw11. A fifth write voltage Vw15 is applied to the main word lines. In some embodiments, Vw15 is equal to or higher than Vw14.In certain embodiments, Vw11=Vw15=Vt+ (700 to 1000) mV and VW12=Vwl3=Vwl4=0 V. In some embodiments, as in . Fig. 4. The third write voltage Vw13 is applied to two or more memory cells to write data “1” to two or more cells simultaneously.

[0016] Fig. Figure 5 shows a write operation for an MRAM cell according to another embodiment of this disclosure. When writing the second type of data, e.g., "1", to a destination memory cell MC, voltages are applied such that the second diode US2, which is coupled to the destination memory cell MC, is activated (turned on), while the remaining diodes are deactivated (turned off). In some embodiments, a first write voltage Vw21 is applied to an associated word line WLa0, a second write voltage Vw22 is applied to the remaining associated word lines WLa1, ..., except for the associated word line WLa0, and a third write voltage Vw23 is applied to a bit line BLo, which is coupled to the destination memory cell MC. In some embodiments, Vw22 is applied before Vw21 and Vw23 are applied.The second write voltage, Vw22, is lower than the first write voltage, Vw21, and the third write voltage, Vw23, is lower than the first write voltage, Vw21. Thus, a write current flows through the destination memory cell MC from the first associated world line via the second diode, US2. In some embodiments, Vw21 is the ground voltage (0 V). In some embodiments, the second voltage, Vw22, is lower than a limit voltage of the second diode (Vt), and in some embodiments, Vw22 is -(Vt + 700 mV to 1000 mV). In some embodiments, the voltage Vw22 is equal to or lower than the voltage Vw23. A fourth write voltage, Vw24, is applied to the remaining bit lines, BL1, BL2, ... In some embodiments, the voltage Vw24 is equal to or higher than the voltage Vw22. A fifth write voltage, Vw25, is applied to the main word lines. In some embodiments, the voltage Vw25 is equal to or higher than the voltage Vw24.In certain embodiments, Vw21=Vw24=0 V, Vw22=Vw23= -(Vt+ 700 to 1000 mV) and VW25=Vt+(700 to 1000) mV. In some embodiments, as in . Fig. As shown in Figure 5, the third write voltage Vw23 is applied to the bit lines BLo and BL2, which are coupled to two or more memory cells MC, in order to write the data “1” simultaneously.

[0017] Fig. Figure 6 shows a write operation for an MRAM cell according to another embodiment of this disclosure. In this embodiment, the data “0” and the data “1” are written simultaneously to two or more memory cells MC, for example, by writing data “1” to a first destination memory cell MC coupled to a bit line BLo and the word lines WLo, and WLa0 and data “0” to a second destination memory cell MC coupled to a bit line BL1 and the word lines WLo and WLa0. In some embodiments, voltages are applied such that the second diode US2 of the first destination memory cell MC is activated (turned on) to write the data “1” via the associated word line WLa0, and the first diode US1 of the second destination memory cell MC is activated (turned on) to write the data “0” via the main word line WLo, while the remaining first and second diodes are deactivated (turned off).

[0018] In some embodiments, a first write voltage Vw31 is applied to the main word line WLo, a second write voltage Vw32 is applied to the associated word line WLa0, a third write voltage Vw33 is applied to the bit line BLo, which is coupled to the first destination memory cell MC, and a fourth write voltage Vw34 is applied to the bit line BL1, which is coupled to the second destination memory cell MC, while a fifth write voltage Vw35 is applied to the remaining main word lines WL1, ..., and a sixth write voltage Vw36 is applied to the remaining associated word lines WLa1, ...In some embodiments, the first write voltage Vw31 is lower than the fourth write voltage Vw34, so that a write current flows from the bit line BL1 through the second target memory cell MC, and the second write voltage Vw32 is higher than the third write voltage Vw33, so that a write current flows from the associated word line WLa0 through the first target memory cell MC. In some embodiments, the fifth write voltage Vw35 is higher than the first write voltage Vw31, and equal to or higher than the third write voltage Vw33. In some embodiments, the sixth write voltage Vw36 is lower than the second write voltage Vw32 and equal to or higher than the fourth write voltage Vw34. In certain embodiments, Vw31 = Vw32 = 0 V, Vw33 = Vw36 = - (Vt + 700 to 1000 mV), and Vw34 = Vw35 = Vt + (700 to 1000) mV.

[0019] Fig. Figure 7 shows a circuit diagram and a read operation for an MRAM cell according to another embodiment of this disclosure. In this configuration, subword lines are each coupled to two or more memory cells and to a main word line.

[0020] When reading data from a target memory cell MC, voltages are applied such that only the first diode US1 of the target memory cell MC is activated, while the remaining diodes are deactivated. In some embodiments, a first read voltage Vr41 is applied to a main word line WLo coupled to the target memory cell MC, a second read voltage Vr42 is applied to the remaining main word lines (e.g., WL1, ...) except for the main word line WLo, and a third read voltage Vr43 is applied to a bit line BL0 coupled to the target memory cell MC. In some embodiments, voltage Vr42 is applied before voltage Vr43. The second read voltage Vr42 is higher than the first read voltage Vr41, and the third read voltage Vr43 is higher than the first read voltage Vr41. Thus, a read current flows through the target memory cell MC and the first diode US1 from bit line BL0.In some embodiments, the voltage Vr41 is the ground voltage (0 V). The voltage Vr43 is higher than a cutoff voltage of the first diode US1 (Vt), and in some embodiments, the voltage Vr43 is Vt + 50 mV to 200 mV. In some embodiments, the voltage Vr42 is equal to or higher than the voltage Vr43. A fourth read voltage Vr44 is applied to the remaining bit lines. In some embodiments, the voltage Vr44 is equal to or lower than the voltage Vr41. A fifth read voltage Vr45 is applied to the associated word lines WLa0, WLa1, ... In some embodiments, the voltage Vr45 is equal to or lower than the voltage Vr44. In some embodiments, Vr44 - Vr45 is equal to or less than a cutoff voltage of the second diode US2 (Vt). In certain embodiments, Vr42 = Vr43 = Vt + (50 to 200) mV and Vr41 = Vr44 = Vr45 = 0 V.

[0021] Fig. 8 and Fig. Figure 9 shows write operations for an MRAM cell according to one embodiment of this disclosure. Fig. Figure 8 illustrates the backflow problem in the configuration of these embodiments when writing the data “0” and Fig. Figure 9 illustrates the backflow problem in the configuration of these embodiments when writing data “1”.

[0022] In Fig. 8. In some embodiments, the voltages applied to the word lines and bit lines are the same as those in Fig. 3. In Fig. 9. In some embodiments, the voltages applied to the word lines and bit lines are the same as those in Fig. 5. In Fig. 8 can, assuming that the reverse bias resistance is sufficiently much larger than the resistance of the memory cell MC and the voltages as in Fig. As shown in Figure 8, the reverse bias current flows as indicated by the arrow with dashed lines. However, the magnitude of the reverse bias current is sufficiently small and does not cause any major problems apart from a small power loss. Similarly, in Fig. 9 assuming that the reverse bias resistance is sufficiently much larger than the resistance of the memory cell MC and the voltages are as in Fig. As shown in Figure 8, the reverse bias current flows as indicated by the arrow with dashed lines. However, the magnitude of the reverse bias current is sufficiently small and does not cause any major problems apart from a small power loss.

[0023] Fig. Figure 10 shows a structural configuration of an MRAM cell according to one embodiment of this disclosure. In some embodiments, one of the diodes 200 is located directly beneath the MTJ film stack 100, and another of the diodes 200 is located horizontally separated from one of the diodes. In some embodiments, the diode 200 and the MTJ film stack are connected by a metal film 190.

[0024] Fig. 11A and Fig. Figure 11B shows cross-sectional views of an MTJ film stack according to an embodiment of this disclosure. Fig. 12A, Fig. 12B and Fig. Figure 12C shows schematic cross-sectional views of the magnetic layers of the MTJ film stack according to an embodiment of this disclosure.

[0025] Fig. Figure 11A is a schematic view of an MTJ-MRAM cell according to an embodiment of this disclosure. The MTJ film stack 100 is arranged between a lower metal layer Mx and an upper metal layer My of a semiconductor device. The metal layers Mx and My are used to connect one element to another in a semiconductor device formed on a different layer above a substrate. Furthermore, the lower metal layer Mx is coupled to unidirectional selectors (diodes) that are coupled to an associated word line AWL and a main word line MWL, respectively. The upper metal layer My is coupled to a bit line.

[0026] The MTJ film stack 100 comprises a first electrode layer 110 coupled to the lower metal layer Mx, and a second electrode layer 155 coupled to the upper metal layer My. An MTJ functional layer 101 is arranged between the first electrode layer 110 and the second electrode layer 155, as shown in Fig. 11B shown.

[0027] The MTJ functional layer 101 comprises a second pinned magnetic layer 130, a free magnetic layer 140, and a tunnel barrier layer 135 made of a non-magnetic material, which is arranged between the second pinned magnetic layer 130 and the free magnetic layer 140. The free magnetic layer 140 and the second pinned magnetic layer 130 comprise one or more ferromagnetic materials, each of which may be magnetically oriented. The free magnetic layer 140 is configured so that its magnetic orientation can be changed or rotated by exposure to an external magnetic field. The second pinned magnetic layer 130 is configured so that its magnetic orientation is fixed and does not respond to a typical magnetic field. In some embodiments, the thickness of the free magnetic layer 140 is in the range of about 0.8 nm to about 1.5 nm.In some embodiments, the thickness of the second pinned layer 130 is in a range of about 0.8 nm to about 2.0 nm.

[0028] The tunnel barrier layer 135 comprises a relatively thin oxide layer capable of electrically isolating the free magnetic layer 140 from the second pinned magnetic layer 130 at low potentials and of conducting current by electron tunneling at higher potentials. In some embodiments, the tunnel barrier layer 135 is made of magnesium oxide (MgO) with a thickness in the range of about 0.5 nm to about 1.2 nm.

[0029] The MTJ functional layer 101 further comprises an antiferromagnetic layer 125 as in Fig. Figure 11B shows that the antiferromagnetic layer 125 is used to define the magnetic orientation of the second pinned magnetic layer 130. The antiferromagnetic layer 125 comprises ruthenium (Ru) or another suitable antiferromagnetic material. In some embodiments, the thickness of the antiferromagnetic layer 125 is in the range of about 0.4 nm to about 1.0 nm.

[0030] The MTJ functional layer 101 further comprises a first pinned magnetic layer 120, which includes one or more magnetic materials, as shown in Fig. 11B shown.

[0031] The second pinned magnetic layer 130 comprises several layers of magnetic materials. In some embodiments, as in Fig. In embodiment 12A, the second pinned magnetic layer 130 comprises four layers 1301, 1302, 1303, and 1304, wherein layer 1304 is in contact with the tunnel barrier layer 135 and layer 1301 is in contact with the antiferromagnetic layer 125. In some embodiments, layer 1301 (the bottom layer) comprises a multilayer structure of cobalt (Co) and platinum (Pt). In some embodiments, the thickness of the cobalt layer is in the range of about 0.3 nm to about 0.6 nm, and the thickness of the platinum layer is in the range of about 0.2 nm to about 0.5 nm. The thickness of the cobalt layer can be equal to or greater than that of the platinum layer. The cobalt and platinum layers are stacked alternately, so that the total thickness of layer 1301 in some embodiments is in the range of approximately 2.0 nm to approximately 5.0 nm. Layer 1302 comprises a cobalt layer with a thickness in the range of approximately 0.4 nm to approximately 0.6 nm.In certain embodiments, layer 1301 is the cobalt layer and layer 1302 comprises the multilayer cobalt layers and the platinum layers as described above. In this disclosure, an “element” layer generally means that the content of the “element” is greater than 99%.

[0032] Layer 1303 is a spacer layer. In some embodiments, the thickness of spacer layer 1303 ranges from approximately 0.2 nm to approximately 0.5 nm. Layer 1304 is a cobalt iron boron (CoFeB) layer, a cobalt / palladium (CoPd) layer, and / or a cobalt iron (CoFe) layer. In some embodiments, the thickness of layer 1304 ranges from approximately 0.8 nm to approximately 1.5 nm.

[0033] The first pinned magnetic layer 120 comprises several layers of magnetic materials. In some embodiments, as in Fig. As shown in Figure 12B, the first pinned magnetic layer 120 comprises two layers 1201 and 1202, with layer 1202 in contact with the antiferromagnetic layer 125. In some embodiments, layer 1201 comprises a multilayer structure of cobalt (Co) and platinum (Pt). In some embodiments, the thickness of the cobalt layer is in the range of about 0.3 nm to about 0.6 nm, and the thickness of the platinum layer is in the range of about 0.2 nm to about 0.5 nm. The thickness of the cobalt layer can be equal to or greater than that of the platinum layer. The cobalt and platinum layers are stacked alternately, so that the overall thickness of layer 1201 in some embodiments is in the range of about 5.0 nm to about 10.0 nm. Layer 1202 comprises a cobalt layer with a thickness in the range of approximately 0.4 nm to approximately 0.6 nm.

[0034] In some embodiments, the free magnetic layer 140 comprises a cobalt-iron-boron (CoFeB) layer, a cobalt-palladium (CoPd) layer, and / or a cobalt-iron (CoFe) layer with a thickness in the range of about 1.0 nm to about 2.0 nm. In other embodiments, the free magnetic layer 140 comprises multiple layers of magnetic materials. In some embodiments, as in Fig. In 12C, the free magnetic layer 140 comprises three layers 1401, 1402, and 1403, with layer 1401 being in contact with the tunnel barrier layer 135. Layers 1401 and 1403 are, in some embodiments, a cobalt-iron-boron (CoFeB) layer, a cobalt-palladium (CoPd) layer, and / or a cobalt-iron (CoFe) layer, with a thickness in the range of about 1.0 nm to about 2.0 nm. Layer 1402 is a spacer layer. The thickness of the spacer layer 1402 is, in some embodiments, in the range of about 0.2 nm to about 0.6 nm.

[0035] The MTJ functional layer 101 further comprises a nucleation layer 115 formed on the first electrode layer 110, a cover layer 145 formed on the free magnetic layer 140, and a diffusion barrier layer 150 formed on the cover layer 145, as shown in Fig. Figure 11B shows the cover layer 145, which is formed from a dielectric material such as magnesium oxide or aluminum oxide, and in some embodiments has a thickness in the range of approximately 0.5 nm to approximately 1.5 nm. The first electrode layer 110 is formed from a conductive material, such as a metal, to reduce the resistance of the first pinned magnetic layer 120, particularly for programming purposes. The second electrode layer 155 is also formed from a conductive material, such as a metal, to reduce the resistivity during reading.

[0036] Fig. Figure 13 is a schematic cross-sectional view of the MRAM cell according to one embodiment of this disclosure. Fig. In references 13 to 17, “Mx” (x=0, 1, 2, 3, ...) refers to a wiring layer at the respective levels arranged above a substrate, and “Vy” (y=0, 1, 2, 3, ...) refers to a via (a contact) connecting the metal wiring layer My to the metal wiring layer My+1. In some embodiments, even-numbered metal wiring layers extend in one direction, and odd-numbered metal wiring layers extend in another direction that intersects the first direction. In some embodiments, the spacing for metal wiring in M3 and M4 is equal, and the spacing for metal wiring in M5 or higher is equal to, and greater than, the spacing for metal wiring in M3 and M4.

[0037] In some embodiments, the MTJ film stack is arranged between the M5 and M7 layers. One of the diodes is arranged below the MTJ film stack between the M3 and M5 layers, and the other diode is arranged above the MTJ film stack between the M7 and M9 layers. In some embodiments, the main word line WL is arranged at the Mg layer, and the associated word line WLa is arranged at the M3 layer. In some embodiments, the bit line BL is arranged at the M4 layer. In other embodiments, the main word line WL is arranged at the M3 layer, and the associated word line WLa is arranged at the M3 layer. In some embodiments, the MTJ film stack is arranged above a lower via contact BEVA, which is located above the M4 layer. Similarly, the diodes are arranged above the lower via contacts.In some embodiments, the diodes are arranged in different wiring layers (e.g., one is a higher wiring layer and the other is a lower wiring layer than the MTJ) and have the same current flow direction as in . Fig. Figure 13 shows that this makes the manufacturing process simpler than manufacturing diodes with different current flow directions.

[0038] Fig. Figure 14 is a schematic cross-sectional view of the MRAM cell according to one embodiment of this disclosure. In some embodiments, the MTJ film stack is arranged between the M3 (or M4) layer and the M6 ​​layer, and the two diodes are arranged above the MTJ film stack between the M6 ​​layer and the M8 layer. In some embodiments, the main word line WL and the associated word line WLa are arranged at the M8 layer. In some embodiments, the bit line BL is arranged at the M3 layer.

[0039] Fig. Figure 15 is a schematic cross-sectional view of the MRAM cell according to one embodiment of this disclosure. In some embodiments, the MTJ film stack is arranged between the M3 (or M4) layer and the M6 ​​layer, and the two diodes are arranged above the MTJ film stack between the M6 ​​layer and the M8 layer. In some embodiments, the main word line WL is arranged at the M10 layer, and the associated word line WLa is arranged at the M8 layer. In other embodiments, the main word line WL is arranged at the M8 layer, and the associated word line WLa is arranged at the M10 layer. In some embodiments, the bit line BL is arranged at the M3 layer.

[0040] Fig. Figure 16 is a schematic cross-sectional view of the MRAM cell according to one embodiment of this disclosure. In some embodiments, the MTJ film stack is arranged between the M6 ​​layer and the M8 layer, and the two diodes are arranged under the MTJ film stack between the M3 (or M4) layer and the M6 ​​layer. In some embodiments, the main word line WL and the associated word line WLa are arranged at the M3 layer. In some embodiments, the bit line BL is arranged at the M8 layer.

[0041] Fig. Figure 17 is a schematic cross-sectional view of the MRAM cell according to one embodiment of this disclosure. In some embodiments, the MTJ film stack is arranged between the M4 layer and the M6 ​​layer, and the two diodes are arranged in the substrate. In some embodiments, the main word line WL and the associated word line WLa are arranged at the M0 layer and coupled to the diodes by a via VD and a contact MD, respectively. In some embodiments, the bit line BL is arranged at the M6 ​​layer. The M4 layer is coupled to the diodes by V3, M3, V2, M2, V1, M1, V0, M0, and MD.

[0042] Fig. Figure 18 shows a circuit diagram of the MRAM cell according to an embodiment of this disclosure.

[0043] As in Fig.As shown in Figure 18, a first word line driver WLD1 is coupled to the main word lines WL0, WL1, ... to apply voltages to the main word line as described above, and a second word line driver WLD2 is coupled to the associated word lines WLao, WLa1, ... to apply voltages to the associated word line as described above. In some embodiments, one word line driver is provided for the main word lines and associated word lines, and in other embodiments, more than one first word line driver and more than one second word line driver are provided. Furthermore, a bit line driver BLD1 is coupled to the bit lines BL0, BL1, ... to apply voltages to the bit line as described above. In some embodiments, more than one bit line driver is provided.

[0044] In some embodiments, the diodes are pn diodes formed from crystalline, polycrystalline, or amorphous semiconductors, or a Schottky barrier diode. In some embodiments, the diodes are a vertical interconnect diode or a lateral interconnect diode.

[0045] In the above embodiments, the memory cells are MRAM cells. In other embodiments, the memory cells are PCRAM cells or RRAM cells.

[0046] It is understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may offer different advantages.

[0047] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Memory cell (MC) comprising: a memory cell stack; a first word line (WL0); a second word line (WLa0); a bit line (BL0) coupled to one end of the memory cell stack; a first unidirectional selector (US1) having one end coupled to another end of the memory cell stack and another end coupled to the first word line (WLo); and a second unidirectional selector (US2) having one end coupled to the other end of the memory cell stack and another end coupled to the second word line (WLao), wherein the current flow directions of the first unidirectional selector (US1) and the second unidirectional selector (US2) are opposite, wherein the memory cell stack comprises an MTJ structure having a cap layer (145) formed on a free magnetic layer (140) and a diffusion barrier layer (150) formed on the cap layer (145). [2] The memory cell (MC) of claim 1, wherein the cap layer (145) is formed of a dielectric, such as magnesium oxide or aluminum oxide. [3] Memory cell (MC) according to claim 1 or 2, wherein the bit line (BL0) is coupled to a free magnetic layer side (FL) of the MTJ structure. [4] Memory cell (MC) according to one of the preceding claims, wherein the memory cell stack comprises a resistivity changing element (110). [5] Memory cell (MC) according to one of the preceding claims, wherein the memory cell stack comprises a phase change element. [6] Memory cell (MC) according to one of the preceding claims, wherein the first and second unidirectional selectors (US1, US2) are diodes. [7] Memory cell (MC) according to claim 6, wherein a cathode of the first unidirectional selector (US1) is coupled to the first word line (WLo), and an anode of the second unidirectional selector (US2) is coupled to the second word line (WLao). [8] Memory cell (MC) according to claim 6 or 7, wherein one of the first and second unidirectional selectors (US1, US2) is arranged above the memory cell stack, and another of the first and second unidirectional selectors (US1, US2) is arranged below the memory cell stack. [9] Memory cell (MC) according to claim 6 or 7, wherein the first unidirectional selector (US1) and the second unidirectional selector (US2) are arranged above the memory cell stack. [10] Memory cell (MC) according to claim 6 or 7, wherein the first unidirectional selector (US1) and the second unidirectional selector (US2) are arranged below the memory cell stack. [11] Memory cell (MC) according to one of the preceding claims, wherein no transistor is connected to the memory cell stack in the memory cell (MC). [12] A semiconductor device comprising: Memory cells (MC); Main word lines comprising a first main word line (WLo); associated word lines having a first associated word line (WLao); and Bit lines (BL), where: each of the memory cells (MC) includes: - a memory cell stack having one end coupled to a corresponding one of the bit lines, the memory cell stack comprising an MTJ structure having a cap layer (145) formed on a free magnetic layer (140) and a diffusion barrier layer (150) formed on the cap layer (145); - a first diode (US1) having an anode coupled to another end of the memory cell stack and a cathode coupled to the first word line (WLo); and - a second diode (US2) having a cathode coupled to the other end of the memory cell stack and an anode coupled to the first associated word line (WLao). [13] The semiconductor device according to claim 12, wherein the cap layer 145 is formed of a dielectric such as magnesium oxide or aluminum oxide. [14] A semiconductor device according to claim 12 or 13, further comprising: a first word line driver (WLD1) coupled to the main word lines (WLo); a second word line driver (WLD2) coupled to the associated word lines (WLao); and a bit line driver (BD) coupled to the bit lines (BL). [15] A semiconductor device according to claim 14, wherein, for reading data from a target memory cell (MC): the first word line driver (WLD1) is configured to apply a first read voltage (Vr1) to the first main word line (WL1) coupled to the target memory cell (MC) and to apply a second read voltage (Vr2) to the remaining main word lines (WL2...) except for the first main word line (WL1), wherein the second read voltage (Vr2) is higher than the first read voltage (Vr1); and the bit line driver (BLD) is configured to apply a third read voltage (Vr3) to one of the bit lines (BL0) coupled to the target memory cell (MC), wherein the third read voltage (Vr3) is higher than the first read voltage (Vr1). [16] A semiconductor device according to claim 14 or 15, wherein, for writing a first type of data to a target memory cell (MC): the first word line driver (WLD1) is configured to apply a first write voltage (Vw1) to the first main word line (WL1); the first word line driver (WLD1) is configured to apply a second write voltage (Vw2) to remaining word lines (WL2...) except for the first main word line (WL1), wherein the second write voltage (Vw2) is higher than the first write voltage (Vw1); and the bit line driver (BLD) is configured to apply a third write voltage (Vw3) to one of the bit lines (BL0) coupled to the target memory cell (MC), wherein the third write voltage (Vw3) is higher than the first write voltage (Vw1). [17] A method of operating a random access memory (RAM), the RAM comprising: Memory cells (MC); Main word lines comprising a first main word line (WLo); associated word lines comprising a first associated word line (WLao); and Bit lines (BL), where: each of the memory cells (MC) includes: - a memory cell stack having one end coupled to a corresponding one of the bit lines (BL1), the memory cell stack comprising an MTJ structure having a cap layer (145) formed on a free magnetic layer (140) and a diffusion barrier layer (150) formed on the cap layer (145); - a first diode (US1) having another end coupled to another end of the memory cell stack and a cathode coupled to the first word line (WLo); and - a second diode (US2) having a cathode coupled to the other end of the memory cell stack and an anode coupled to the first associated word line (WLao), the method includes reading data by: - applying a first read voltage (Vr1) to the first main word line (WL0); - applying a second read voltage (Vr2) to the remaining main word lines (WL1 ... ) except the first main word line (WL0), wherein the second read voltage (Vr2) is higher than the first read voltage (Vr1); and - applying a third read voltage (Vr3) to one of the bit lines (BL1), the third read voltage (Vr3) being higher than the first read voltage (Vr1), whereby the data is read from one of the memory cells (MC) coupled to the one of the bit lines (BL1) and the first main word line (WLo). [18] The method of claim 17, further comprising applying the second read voltage (Vr2) to the associated word lines (WLa0). [19] The method of claim 17 or 18, further comprising writing data of a first type by: Applying a first write voltage (Vw1) to the first main word line (WL0); Applying a second write voltage (Vw2) to the remaining word lines (WL1 ... ) except the first main word line (WL0), wherein the second write voltage (Vw2) is higher than the first write voltage (Vw1); and Applying a third write voltage (Vw3) to one or more of the bit lines (BL0), wherein the third write voltage (Vw3) is higher than the first write voltage (Vw1), whereby the data of the first type is written to one or more of the memory cells (MC) coupled to the one or more of the bit lines (BL1) and the first main word line (WLo), where the third write voltage (Vw3) is higher than the third read voltage (Vr3). [20] The method of claim 19, further comprising writing data of a second type by: Applying a fourth write voltage (Vw4) to the first associated word line (WLa0); Applying a fifth write voltage (Vw5) to the remaining associated word lines (WLa1...) except the first associated word line (WLa0), wherein the fifth write voltage (Vw5) is smaller than the fourth write voltage (Vw4); and Applying a sixth write voltage (Vw6) to one or more of the bit lines (BL1), wherein the sixth write voltage (Vw6) is less than the fourth write voltage (Vw4), whereby the data of the second type is written to one or more of the memory cells (MC) coupled to the one or more of the bit lines (BL1) and the first associated word line (WLao).

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