MAGNETIC DEVICE AND MAGNETIC DIRECT ACCESS STORAGE

Abstract

Magnetic storage, including: a first spin-orbital transfer-spin-torque transfer (SOT-STT) hybrid magnet device arranged over a substrate (100); and a second SOT-STT hybrid magnet device arranged above the substrate (100); a SOT conductor layer (10) connected to the first and second SOT-STT devices; and an upper electrode layer (5) arranged in contact with the SOT conducting layer (10) and having a recess over each of the first and second SOT-STT hybrid magnet devices, each of the first and second SOT-STT hybrid magnet devices comprises: - a first magnetic layer (20) as a magnetic free layer; - a spacer layer (30) arranged below the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer, which is arranged below the spacer layer, wherein the SOT conducting layer (10) is arranged above the first magnetic layer (20), the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device.

Description

BACKGROUND

[0001] Magnetic random-access memory (MRAM) offers comparable performance to volatile static random-access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random-access memory (DRAM). Compared to non-volatile memory (NVM) flash memory, MRAM offers much faster access times and minimal degradation over time, while flash memory has a limited number of rewrites. One type of MRAM is spin-transfer torque random-access memory (STT-RAM). STT-RAM uses a magnetic tunnel junction (MTJ) that is at least partially written by a current driven through the MTJ. Another type of MRAM is spin-orbit torque RAM (SOT-RAM).

[0002] WO 2018 / 101998 A1 discloses a hybrid magnetic random access memory (MRAM) consisting of spin-transfer torque (STT) and spin-orbit torque (SOT). The cells of the hybrid STT-SOT MRAM feature magnetic tunnel junctions (MTJs) with some ferromagnetic multilayers whose magnetization is aligned perpendicular to the plane of the substrate and some ferromagnetic multilayers whose magnetization is aligned within the plane of the substrate.

[0003] US 2018 / 0123031 A1 relates to semiconductor devices comprising a magnetic tunnel junction (MTJ). In one aspect, a method for forming a magnetoresistive random access memory (MRAM) comprises forming a layer stack over a substrate, the layer stack comprising a ferromagnetic reference layer, a tunnel barrier layer, a ferromagnetic free layer, and a spin-orbit layer. The method additionally comprises, after forming the layer stack, patterning the layer stack to form an MTJ column.

[0004] US 2011 / 0122674 A1 discloses devices and methods for a reverse-connected STT-MTJ element of an MRAM to overcome the source degeneration effect when the magnetization of the MTJ element is switched from the parallel to the antiparallel direction.

[0005] WO 2017 / 172209 A1 discloses devices, systems and methods, including a memory device having a plurality of bit cells, each of the plurality of bit cells corresponding to a respective weight value and comprising a switching device having a magnetic tunnel junction (MTJ) or other suitable resistive memory element to generate stochastic switching.

[0006] US 2017 / 0221541 A1 discloses a magnetic memory device comprising a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each of a magnetic resistance element and a switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, as is standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1 is a schematic view of a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure. 04] Fig. 2 shows a circuit diagram of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. 05] Fig. 3 shows a circuit diagram of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. 06] Fig. 4 is a schematic view of a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure. 07] Fig. 5A is a cross-sectional view of a cell of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. 08] Fig. 5B is a top view of a cell of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. 09] Fig. 6 illustrates an operation for writing data to a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure. 10] Fig. 7 shows a memory array structure of a SOT-STT hybrid MRAM device according to embodiments of the present disclosure. 1 Fig. 8A, Fig. 8B, Fig. 8C, Fig. 8D, Fig. 8E, Fig. 8F, Fig. 8G, Fig. 8H, Fig. 8I, Fig. 8 years and Fig. 8K illustrate a sequential fabrication process for a SOT-STT hybrid MRAM device according to the present disclosure. 1 Fig. 9A, Fig. 9B and Fig. 9C show various structures for an SOT induction wiring layer according to embodiments of the present disclosure. 13] Fig. 10 shows operations of an STT-MRAM and an SOT-MRAM. DETAILED DESCRIPTION

[0008] It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed range or values, but may depend on the process conditions and / or the desired characteristics of the device.Furthermore, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed disposed between the first and second features such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn at different scales for convenience and clarity. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0009] Furthermore, spatially relative terms such as "beneath," "below," "further down," "above," "above," and the like may be used for ease of description to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or oriented in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. Additionally, the term "formed of" can mean either "having" or "consisting of."Furthermore, in the subsequent manufacturing process, one or more additional operations may be present between the described operations, and the order of the operations may be changed. In the present disclosure, a term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C) and does not mean one of A, one of B, and one of C, unless otherwise described.

[0010] Spin-torque transfer magnetic random access memory (STT-MRAM) is one of the next-generation technologies for CMOS integrated circuits. It requires memory compatible with Si-CMOS technology due to its non-volatile nature, fast read and write speeds, high data endurance and retention, a relatively small bit cell size, and environmental robustness. A high-value, emerging application for STT-MRAM is a low-level cache for a central processing unit (CPU) or microcontroller unit (MCU), which offers the attractive advantage of increased system speed and faster power-up due to its non-volatility. However, this application places high demands on memory speed, especially write speed, which is much slower than read speed.The cache application for a CPU and / or an MCU additionally demands low power consumption, which is challenging for STT-MRAM because it requires significant power to change the magnetization state during the write operation. In current STT-MRAM technology, improving write speed through a film stack and optimizing the write scheme, as well as reducing write current through stack optimization and reducing the critical dimension (CD), may stall due to an unavoidable performance trade-off between endurance and storage. Novel ideas, such as high-frequency assisted write operation, have been proposed, but these may not be feasible.There is a significant gap between the best reported STT MRAM write speed and write power consumption and those required for cache applications, which can result in a show-stopper.

[0011] In contrast, magnetic switching through spin-orbital transfer (or spin-orbital torque) (SOT) is an emerging write concept that has the potential to achieve an order of magnitude improvement in write current and write speed. SOT is considered a solution for high-speed, low-power cache applications.

[0012] Fig. 10 shows operations of an STT-MRAM and an SOT-MRAM.

[0013] An STT-MRAM cell comprises a magnetic tunnel junction (MTJ) film stack 500 with a free magnetic layer 510 (FL), a reference or pinned magnetic layer 520 (RL), and a tunnel barrier layer 530. Magnetic layers can be either in-plane or perpendicular to the plane. The FL 510 is the magnetic layer that has two energetically equivalent magnetic states, with the magnetization in the FL 510 being parallel or antiparallel to the magnetization of the RL 520. By applying a current perpendicular to the MTJ film stack 500, the magnetic orientation (moment) of the free magnetic layer can be changed, thereby writing data to the STT-MRAM cell.

[0014] In contrast, in an SOT-MRAM, the magnetic moment of the free magnetic layer is switched using the spin-orbit interaction effect caused by a current flowing parallel to the MTJ film stack 500. The magnetic moment of the free magnetic layer is switched using only the spin-orbit interaction effect, or the magnetic moment of the free magnetic layer is switched using a combination of effects.

[0015] However, an SOT device structure has several problems. For example, since the SOT device writes data using an SOT current plus as a supporting magnetic field, a design-in magnetic field is undesirable for device manufacturing costs and scaling. Furthermore, an SOT design lacks a hard bias layer, resulting in insufficient data retention and insufficient durability. Since an SOT layer (a heavy metal wire) is generally located beneath the magnetic tunneling junction (MTJ) stack, a possible hard bias layer for the MTJ film stack can only be located on the MTJ film stack (top pin), and such a top-pin design can lead to poor performance. Furthermore, an SOT power line beneath the MTJ film stack can only be realized with a 2T1R (two transistors - one resistor) structure, resulting in a large cell footprint.

[0016] The present disclosure proposes an implementable SOT-controlled STT-MRAM design that can realize the high write speed and low power consumption advantage of SOT as well as the data endurance and retention of STT, requires no additional magnetic field, has a 1T1R (one-transistor-on-resistor) structure with a small cell footprint, has a common SOT power line enabling side-write operation, has an SOT layer above the MTJ film stack enabling the proven bottom-pin STT design, and has an efficient film stack design for SOT and STT.

[0017] Fig. 1 is a schematic view of a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure.

[0018] The SOT-STT hybrid magnet device includes an SOT inductive wiring layer 10 as an active spin-orbit interaction layer formed over an MTJ film stack. The MTJ film stack includes a first magnetic layer 20, which is a free magnetic layer or a data storage layer, disposed beneath the SOT inductive wiring layer 10, a non-magnetic spacer layer 30 disposed beneath the first magnetic layer 20, and a second magnetic layer 40 as a reference layer disposed beneath the non-magnetic spacer layer 30. In some embodiments, an interface layer 50 is disclosed as a support layer between the SOT inductive wiring layer 10 and the first magnetic layer 20. The MTJ film stack further includes a third magnetic layer 60 as a hard bias layer disposed beneath the second magnetic layer 40, and a bottom electrode layer 80.In some embodiments, a seed layer 70 is formed on the bottom electrode layer 80. In some embodiments, an antiferromagnetic layer, such as a Ru layer, is disposed between the second magnetic layer 40 and the third magnetic layer 60. Furthermore, in some embodiments, a top conductive layer 5, such as a top electrode, is disposed on the SOT induction wiring layer 10.

[0019] The magnetic moment of the free layer 20 (first magnetic layer) is switched using the spin-orbit interaction effect. In some embodiments, the magnetic moment of the first magnetic layer 20 is switched using only the spin-orbit interaction effect. In other embodiments, the magnetic moment of the first magnetic layer 20 is switched using a combination of effects. For example, the magnetic moment of the first magnetic layer 20 is switched using spin transfer torque as a primary effect, which may be assisted by the torque induced by the spin-orbit interaction. In other embodiments, the primary switching mechanism is a torque induced by the spin-orbit interaction.In such embodiments, another effect, including but not limited to spin transfer torque, may assist switching.

[0020] The SOT inductive wiring layer 10 is an active spin-orbit layer that exhibits a strong spin-orbit interaction and can be used to switch the magnetic moment of the first magnetic layer 20. The SOT inductive wiring layer 10 is used to generate the spin-orbit magnetic field H. In particular, a current driven in-plane through the SOT inductive wiring layer 10 and the associated spin-orbit interaction can result in the spin-orbit magnetic field H. This spin-orbit magnetic field H is equivalent to the spin-orbit torque T upon magnetization, where T = -γ[M×H] in the first magnetic layer 20. The torque and the magnetic field are therefore interchangeably referred to as the spin-orbit field and the spin-orbit torque. This reflects the fact that the spin-orbit interaction is the origin of the spin-orbit torque and the spin-orbit field.The spin-orbit torque occurs for a current driven in-plane in the SOT inductive wiring layer 10 and a spin-orbit interaction. In contrast, the spin-transfer torque relies on a current perpendicular to the plane that flows through the first magnetic layer 20, the non-magnetic spacer layer 30, and the second magnetic layer 40 (reference layer), injecting spin-polarized charge carriers into the first magnetic layer 20. The spin-orbit torque T can rapidly deflect the magnetic moment of the first magnetic layer 20 from its equilibrium state parallel to the easy axis. The spin-orbit torque T can flip the magnetization of the first magnetic layer 20 significantly faster than a conventional STT torque with a similar maximum amplitude. In some embodiments, the switching can be completed using a spin-orbit torque.In other embodiments, a different mechanism, such as spin transfer, may be used to complete the switching. The generated spin-orbit field / spin-orbit torque can thus be used to switch the magnetic moment of the first magnetic layer 20.

[0021] In some embodiments, the interaction of the SOT induction wiring layer comprises the spin Hall effect. For the spin Hall effect, a current Je is generated in the plane of the SOT induction wiring layer 10 (i.e., current-in-plane, substantially in the xy-plane in Fig. 1). In other words, the current Je is perpendicular to the stacking direction of the films including the SOT induction wiring layer 10 and the first magnetic layer 20 (ie, perpendicular to the normal to the surface, the z-direction in Fig. 1). Charge carriers with spins of a specific orientation perpendicular to the current direction and to the normal to the surface (z-direction) accumulate on the surfaces of the SOT induction wiring layer 10. A large portion of these spin-polarized charge carriers diffuse into the first magnetic layer 20 (free layer). This diffusion leads to the torque T during magnetization of the first magnetic layer 20. Since the torque during magnetization is equivalent to the effective magnetic field during magnetization, as explained above, the spin accumulation leads to the field H on the first magnetic layer 20. The spin-orbit field for the spin Hall effect is the cross product of the spin-orbit polarization and the magnetic moment of the first magnetic layer 20. The magnitude of the torque is therefore proportional to the in-plane current density Je and the spin polarization of the charge carriers. The spin Hall effect can be used to switch the Fig. 1 when the polarization induced by the spin Hall effect is parallel to the easy axis of the first magnetic layer 20. To obtain the spin-orbit torque T, the in-plane current pulse is driven through the SOT induction wiring layer 10. The resulting spin-orbit torque T counteracts the damping torque, which leads to switching the magnetization of the first magnetic layer 20 in a manner analogous to conventional STT switching.

[0022] As stated above, the SOT induction wiring layer 10 is an active spin-orbit layer that causes a strong spin-orbit interaction with the first magnetic layer 20 (free layer). In some embodiments, the SOT induction wiring layer 10 includes one or more heavy metals or materials doped with heavy metals. In certain embodiments, α-W, β-W, Mo, Ru, and / or β-Ta is used as the SOT induction wiring layer 10. A thickness of the SOT induction wiring layer 10 is in a range of about 2 nm to 20 nm in some embodiments and is in a range of about 5 nm to 15 nm in other embodiments. In some embodiments, an antiferromagnetic layer of, for example, IrMn is disposed between the SOT induction wiring layer 10 and the upper conductive layer 5.In other embodiments, instead of the heavy metal layer, the antiferromagnetic layer (e.g., IrMn) is used as the SOT induction wiring layer 10.

[0023] The first magnetic layer 20 as a data storage layer is a free layer with a switchable magnetic moment. In some embodiments, the first magnetic layer 20 is a cobalt-iron-boron (CoFeB) layer, a cobalt / palladium (CoPd) layer, and / or a cobalt-iron (CoFe) layer with a thickness in a range of about 0.6 nm to about 1.2 nm in some embodiments. In certain embodiments, the first magnetic layer 20 is Fe x Co y B 1-x-y , where 0.50 ≤ x ≤ 0.70 and 0.10 ≤ y ≤ 0.30. In other embodiments, 0.55 ≤ x ≤ 0.65 and 0.15 ≤ y ≤ 0.25.

[0024] The non-magnetic spacer layer 30 is formed from a dielectric material and functions as a tunnel barrier. In some embodiments, the non-magnetic spacer layer 30 comprises a crystalline or amorphous magnesium oxide (MgO) layer. In other embodiments, the non-magnetic spacer layer 30 is formed from aluminum oxide or a conductive material such as Cu. In some embodiments, the non-magnetic spacer layer 30 has a thickness in a range of about 0.3 nm to about 1.2 nm, and in other embodiments, the thickness of the non-magnetic layer 30 is in a range of about 0.5 nm to about 1.0 nm. In this disclosure, an "element layer" or a "composite layer" generally means that the content of the element or compound is greater than 99%.

[0025] The second magnetic layer 40 is a reference layer whose magnetic moment does not change. In some embodiments, the second magnetic layer 40 is formed of the same material as the first magnetic layer 20, as discussed above. In some embodiments, the second magnetic layer 40 comprises one or more layers of magnetic materials. In some embodiments, the second magnetic layer 40 comprises a layer of cobalt (Co), iron (Fe), and boron (B), or comprises a layer of Fe and B. In some embodiments, a thickness of the second magnetic layer 40 is in a range of about 0.2 nm to about 1.0 nm, and in other embodiments, is in a range of about 0.3 nm to about 0.5 nm.

[0026] The third magnetic layer 60 is a hard bias layer whose magnetic moment does not change. In some embodiments, the third magnetic layer 60 comprises a multilayer structure of cobalt (Co) and platinum (Pt). In some embodiments, a thickness of the third magnetic layer 60 is in a range from about 0.2 nm to about 2.0 nm, and in other embodiments, in a range from about 0.3 nm to about 1.0 nm.

[0027] In some embodiments, a seed layer 70 contains Ta. In some embodiments, the bottom electrode layer 80 comprises Ti, TiN, Ta, and / or TaN. In some embodiments, a CoHf buffer layer is disposed between the third magnetic layer 60 and the bottom electrode layer 80.

[0028] The upper conductive layer 5 is an electrode comprising one or more layers of Ta, TiN, TaN, Ru, Au and Al.

[0029] In some embodiments, the interface layer 50 comprises an MgO layer and / or a Co layer. The interface layer 50 can minimize magnetic interference between the first magnetic layer 20 and the SOT inductive wiring layer 10 while maintaining their magnetic coupling.

[0030] Fig. 2 shows a circuit diagram of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure.

[0031] In some embodiments of the present disclosure, multiple MTJ stacks are connected to an SOT induction wiring layer 10, as shown in Fig. 2. In other words, multiple MTJ stacks share the SOT induction wiring layer 10. As shown in Fig. As shown in Figure 2, the bottom electrode layer 80 of each of the MTJ stacks is connected to a switching device SW1, such as a MOS-FET. In some embodiments, a drain of the MOS-FET is connected to the bottom electrode layer 80, and a source of the MOS-FET is connected to a source line SL, which is connected to a source line driver circuit having a current source. A gate of the MOS-FET is connected to an STT word line WL-STT. Furthermore, one end of the SOT inductance wiring layer 10 is connected to a bit line BL-STT together with the upper conductive layer 5. In addition, another switching device SW2 (an SOT switching device), such as a MOS-FET, is arranged between the other end of the SOT inductance wiring layer 10 and the source line SL.In some embodiments, a drain of the SOT switching MOS-FET SW2 is connected to the SOT induction wiring layer 10, and a source of the SOT switching MOS-FET SW2 is connected to the source line SL. A gate of the SOT switching MOS-FET SW2 is connected to an SOT word line WL-SOT. The word lines WL-STT and WL-SOT are connected to a word line driver circuit in some embodiments. The bit line BL-STT is connected to a bit line driver in some embodiments.

[0032] In the configuration of Fig. 2, in an SOT-controlled STT-MRAM design, data is written to the MTJ film stack by conducting an in-plane SOT current by turning on the SOT-switching MOS-FET SW2 through the SOT induction wiring layer 10 adjacent to the first magnetic layer (free magnetic layer) 20 disposed on the MTJ film stack and conducting a vertical STT current by simultaneously turning on the MOS-FET SW1 through the MTJ film stack. Thus, the SOT-controlled STT-MRAM can write data without a supporting magnetic field. Furthermore, since multiple MTJ film stacks share the same SOT induction wiring layer 10, it is possible to perform side-by-side writing. As shown in Fig. As shown in Figure 2, the circuit structure is a 1T1R structure with a small cell footprint.

[0033] Fig. 3 shows a circuit diagram of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. Fig. 4 is a schematic view of a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure.

[0034] As in the Fig. 3 and Fig. As shown in Figure 4, the switching devices (MOS-FETs) SW1 and SW2 are located under the MTJ film stacks.

[0035] In some embodiments, the MOS-FETs are formed on a substrate 100. In some embodiments, the substrate 100 has a single-crystal semiconductor layer on at least its surface portion. The substrate 100 may comprise a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 100 is formed from crystalline Si.

[0036] Each of the MOS-FETs includes a gate, a source, and a drain, and the source and / or drain are electrically connected to the bottom electrode 80 of the MTJ film stack via one or more contacts and metal wirings. The other of the source and drain is electrically connected to the source line SL via one or more contacts and metal wirings. In some embodiments, the MOS-FETs are planar MOS-FETs, fin-FETs (Fin-FETs), and / or gate-all-around FETs (GAA-FETs).

[0037] In some embodiments, as shown in Fig. 4, the bottom electrode layer 80 is connected to an n-th metal layer or is formed by the n-th metal layer, where n is 0, 1, 2, ..., 10 or more. The upper conductive layer 5 is connected to an (n + 2)-th metal wiring Mn + 2x / y forming the bit line BL via an (n + 1)-th via contact Vn + 1. In this embodiment, the SOT induction wiring layer 10 and the upper conductive layer 5 are considered to be the (n + 1)-th metal layer. In some embodiments, n is 4, 5, 6, 7, 8, 9, or 10. In some embodiments, the upper conductive layer 5 and the SOT induction wiring layer 10 are located on the Mn + 1 metal wiring level.

[0038] In some embodiments, as shown in Fig. 4, a source of a MOS-FET is connected to a source line SL disposed on the 0th metal wiring layer Mox and extending in the X direction via a source / drain contact structure MD and VD. A drain of a MOS-FET is connected to the bottom electrode 80, which is the nth wiring Mnx / y extending in either the X or Y direction, via a source / drain contact structure MD and VD, a 0th (Vo) to an (n-1)th (Vn-1) via contact, and a 0th (Mox) to an (n-1)th metal wiring in some embodiments. In some embodiments, odd-numbered metal wirings (M1y,...) extend in the Y direction, and even-numbered metal wirings (Mox,...) extend in the X direction, which crosses the Y direction. In some embodiments, the word line WL is arranged in the first metal wiring layer M1y.In some embodiments, a top electrode via TEVA is arranged between the top conductive layer 5 and the (n+1)th contact Vn+1, and a bottom electrode via BEVA is arranged between the MTJ film stack MTJ and the bottom electrode 80 (Mnx / y).

[0039] Fig. 5A is a cross-sectional view of a cell of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure.

[0040] In some embodiments, the top conductive layer 5 has a recess (a thin portion) above the MTJ film stack, wherein a thickness of the top conductive layer 5 is smaller than the remaining portion of the top conductive layer 5. This structure allows for an increase in the current flowing through the SOT induction wiring layer 10 to cause a sufficient SOT effect while enabling a low resistance between adjacent cells. In some embodiments, a thickness of the top conductive layer 5 is in a range of about 2 nm to 20 nm in some embodiments and is in a range of about 5 nm to 15 nm in other embodiments, and the thickness of the thin portion of the top conductive layer 5 accounts for about 40% to about 80% of the thickness of the top conductive layer 5 at a location other than the thin portion.

[0041] Fig. 5B is a top view of a cell of a SOT-STT hybrid MRAM device according to an embodiment of the present disclosure. In other embodiments, in addition to or instead of the recess, a narrow portion is provided where the width of the upper conductive layer 5 above the MTJ film is narrower than the remaining portion of the upper conductive layer 5. The width of the narrow portion of the upper conductive layer 5 is about 50% to about 90% of the width of the upper conductive layer 5 at a location other than the narrow portion.

[0042] Fig. 6 illustrates an operation for writing data to a SOT-STT hybrid MRAM cell according to an embodiment of the present disclosure.

[0043] In some embodiments, an SOT current is applied to the SOT induction wiring layer 10 (and the upper conductive layer 5) by turning on the SOT switching device SW2, and then an STT current is applied to one of the cells by turning on the STT switching device SW1 connected to the one cell, thereby writing data to the one cell by operations of the word line driver, the bit line driver, and / or the source line driver. Further, the STT switching device connected to the one of the cells is turned off, and then the SOT switching device is turned off by operations of the word line driver, the bit line driver, and / or the source line driver.

[0044] In some embodiments, the SOT current and the STT current are pulse currents, as in Fig. 6. The amplitude of the SOT current is in some embodiments in a range of about 1 × 10-7 to about 1 × 10 -6 A / cm 2 and a pulse duration ranges from about 1 ns to about 20 ns. The amplitude of the STT current is larger than that of the SOT current and ranges from about 1 × 10 -6 up to about 1 × 10 -5 A / cm 2 and a pulse duration ranges from about 500 ps to about 10 ns in some embodiments. In a pure STT device case, the write current is about 1 × 10 -5 A / cm 2 for a duration of 50 ns to 500 ns and in a case of a pure SOT device, the write current is about 1 × 10 -6 A / cm 2for a duration of 100 ps to 10 ns. Accordingly, a lower operating current (i.e., lower power consumption) and a higher write speed can be achieved in the SOT-STT hybrid MRAM cell according to the embodiments of the present disclosure. Furthermore, by turning on a plurality of switches SW1, a side wiring operation is possible.

[0045] Fig. 7 shows a memory array structure according to embodiments of the present disclosure. The memory array includes a matrix of multiple memory cell sections, and each of the memory cell sections includes 2 to 32 memory cells connected to an SOT inductance wiring layer 10 and an SOT switching device. Each of the SOT inductance lines is connected to a corresponding bit line BL-1, BL-2, or BL-3. Each of the switching devices SW1 is connected to a corresponding source line SL-1, SL-2, or SL-3. In some embodiments, each of the memory cell sections includes 2, 4, 8, 16, 32, 64, or 128 memory cells. In some embodiments, each of the memory cell sections includes one or more redundant memory cells with which one or more defective memory cells can be replaced. In some embodiments, each of the memory cell sections includes one or more dummy memory cells.

[0046] Fig. 8A-8K illustrate a sequential manufacturing process for a hybrid SOT-MRAM according to the present disclosure. It should be understood that in the sequential manufacturing process, one or more additional operations may be performed before, during, and after the steps shown in Fig. 8A - 8K, and that some of the operations described below may be replaced or omitted for additional embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations described with reference to Fig. 1 - 7 can be used in the following embodiments, and detailed explanation thereof may be omitted.

[0047] As in Fig. As shown in Figure 8A, a hard mask structure 220 is formed over an n-th wiring layer having a metal wiring 210 embedded in an interlayer dielectric (ILD) layer 200. In some embodiments, n is 4, 5, or 6. In some embodiments, the metal wiring 210 is made of Cu or a Cu alloy. In some embodiments, the hard mask layer 220 includes a first layer 222, a second layer 224, and a third layer 226. In some embodiments, the first through third layers are formed of silicon oxide, silicon nitride, SiC, SiCN, or alumina, zirconium oxide, or any other suitable dielectric material. In certain embodiments, the first and third layers 222 and 226 are made of SiC, and the second layer 224 is made of silicon oxide.

[0048] Then, the hard mask layer 220 is patterned to form an opening to at least partially expose the top surface of the metal wiring 210 using one or more lithography and etching processes. A liner layer 230 is formed in the opening, and a conductive layer 240 is formed over the liner layer 230, as shown in Fig. 8B. In some embodiments, the liner layer 230 is formed from Ti, Ta, or TaN, and the conductive layer 240 is formed from TiN. After the conductive layer 240 is formed, a planarization process, such as chemical mechanical polishing (CMP), is performed to form an electrode 240, as shown in Fig. 8C. The electrode 240 corresponds to the bottom electrode via BEVA, which is shown in Fig. 4, in some embodiments.

[0049] Layers for the MTJ film stack are then formed over the electrode 240 as shown in Fig. 8D. In the Fig. 8D-8K, the electrode 240, the metal wiring 210, and the ILD layer 200 are omitted. The layer for the MTJ film stack includes layers for a bottom electrode BE, a seed or buffer layer Seed / Buff, a hard bias layer HB, a reference layer RL, an MgO layer MgO, a free layer FL, a keeper layer Keeper, in some embodiments, a CMP stop layer, and a hard mask layer HM. Each of the layers of the MTJ film stack can be formed by suitable film formation methods, including physical vapor deposition (PVD) including sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam epitaxy (E-beam epitaxy); chemical vapor deposition (CVD); or derivative CVD processes further including low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), vacuum CVD (RPCVD); electroplating, or any combination thereof.

[0050] Then, the stacked layers for the MTJ film are patterned into an MTJ film stack using one or more lithography and etching processes, as shown in Fig. 8E. According to one aspect, as shown in Fig. As shown in Figure 8E, the cross-sectional view of the MTJ film stack has a tapered (mesa) shape. Then, one or more ILD dielectric material layers, such as silicon oxide, SiOC, SiOCN, or SiCN, are formed to completely cover the MTJ film stack, as shown in Fig. 8F. A planarization operation, such as CMP, is performed to expose the top layer of the MTJ film stack, as shown in Fig. 8G. Then, a conductive layer 250 for the SOT induction wiring layer 10 and conductive layers 260 for the upper conductive layer 5 (see Fig. 1) trained as in Fig. 8H. In some embodiments, the conductive layers 260 include a first conductive layer 262, a second conductive layer 264 as an etch stop layer, and a third conductive layer 266. The second conductive layer 264 is formed from a different material than the first and third conductive layers. In some embodiments, no first conductive layer is formed.

[0051] Furthermore, as in Fig. 8I, a photoresist pattern 270 is formed over the conductive layers 260 and the conductive layers 260 are patterned using one or more lithography and etching processes, as shown in Fig. 8J. Then, the photoresist pattern 270 is removed as shown in Fig. 8K to see the Fig. 5A. In some embodiments, the etching stops at the second conductive layer 264. In other embodiments, an additional etch is performed such that the first conductive layer is partially etched. In some embodiments, before or after the steps shown in the Fig. 8I - 8K, the conductive layers 250 and 260 are patterned to form a line-shaped structure, and the thickness of the conductive layers 260 is determined by the operations of Fig. 8I - 8K reduced.

[0052] Fig. 9A-9C show various structures for the SOT induction wiring layer. In some embodiments, the SOT induction wiring layer 10 is a single heavy metal layer of W, Ta, and Mo, as shown in Fig. 9A. In other embodiments, the SOT induction wiring layer 10" is a single layer of antiferromagnetic material such as IrMn, as shown in Fig. 9B. In other embodiments, the SOT induction wiring layer 10" is a dual layer of a heavy metal layer 11 and an antiferromagnetic material layer 12, with the heavy metal layer 11 in contact with the MTJ film stack, as shown in Fig. 9C shown.

[0053] It should be understood that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0054] According to one aspect of the present disclosure, a magnetic memory device includes a first SOT-STT (spin-orbital-transfer-spin-torque-transfer) hybrid magnet device disposed over a substrate, a second SOT-STT hybrid magnet device disposed over the substrate, and an SOT conductive layer connected to the first and second SOT-STT devices. Each of the first and second SOT-STT hybrid magnet devices includes a first magnetic layer as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer as a magnetic reference layer disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnet devices.In one or more of the preceding and following embodiments, the conductive SOT layer comprises one or more layers of W, Ta, Mo, and IrMn. In one or more of the preceding and following embodiments, the conductive SOT layer comprises a lower layer made of W, Ta, or Mo and an upper layer made of IrMn. The magnetic memory further comprises an upper electrode layer arranged in contact with the conductive SOT layer.In one or more of the preceding and following embodiments, the upper electrode layer includes a narrow portion having a width narrower than a remaining portion, or a thin portion having a thickness smaller than the remaining portion, over each of the first and second SOT-STT hybrid magnet devices, and the remaining portion is disposed between the first SOT-STT hybrid magnet devices and the second SOT-STT hybrid magnet device. In one or more of the preceding and following embodiments, each of the first and second SOT-STT hybrid magnet devices further includes an interface layer disposed over the first magnetic layer and in contact with the SOT conductive layer. In one or more of the preceding and following embodiments, the first magnetic layer is Fe. x Co y B 1-x-y, where for x and y: 0.50 ≤ x ≤ 0.70 and 0.10 ≤ y ≤ 0.30. In one or more of the preceding and following embodiments, the second magnetic layer comprises at least one layer of Co, Fe and B and one layer of Fe and B. In one or more of the preceding and following embodiments, each of them comprises a layer of Co, Fe and B and / or a layer of Fe and B. The first and second SOT-STT hybrid magnet devices further comprise a third magnetic layer as a bias layer under the second magnetic layer, and the third magnetic layer comprises a layer of Co and Fe. In one or more of the preceding and following embodiments, each of the first and second SOT-STT hybrid magnet devices further comprises a bottom electrode layer disposed under the third magnetic layer.In one or more of the preceding and following embodiments, each of the first and second SOT-STT hybrid magnet devices further comprises an STT switching device, wherein one terminal of the STT switching device is connected to the bottom electrode and another terminal of the switching device is connected to a source line, wherein the magnetic memory further comprises an SOT switching device, one terminal of the SOT switching device is connected to the SOT conductive layer and another terminal of the SOT switching device is connected to the source line. In one or more of the preceding and following embodiments, the source line is connected to a power source. In one or more of the preceding and following embodiments, the STT switching device and the SOT switching device are located below the first and second SOT-STT hybrid magnet devices.

[0055] According to another aspect of the present disclosure, a magnetic memory device comprises first word lines, a second word line, a bit line, a source line, memory cells, and a conductive wire. Each of the memory cells comprises a magnetic tunnel junction (MTJ) film stack and a spin torque transfer (STT) transfer device. One terminal of the STT switching device is connected to one end of the MTJ film stack, another terminal of the STT switching device is connected to the source line, and a control terminal of the STT switching device is connected to a corresponding one of the first word lines. Another end of the MTJ film stack is connected to the conductive wire. The conductive wire is connected to the bit line. The magnetic memory device further comprises an SOT switching device.One terminal of the SOT switching device is connected to the conductive wire, another terminal of the SOT switching device is connected to the source line, and a control terminal of the SOT switching device is connected to the second word line. In one or more of the preceding and following embodiments, the source line is connected to a power source. In one or more of the preceding and following embodiments, a number of memory cells connected to the conductive wire is in a range from 2 to 32. In one or more of the preceding and following embodiments, the MTJ film stack comprises a first magnetic layer as a magnetic free layer, a spacer layer arranged below the first magnetic layer, and a second magnetic layer as a magnetic reference layer arranged below the spacer layer. The conductive wire is arranged above the first magnetic layer.In one or more of the preceding and following embodiments, the magnetic memory further comprises a driver circuit configured to apply an SOT current to the conductive wire by turning on the SOT switching device, and then apply an STT current to one of the memory cells by turning on the STT switching device connected to the one of the memory cells, thereby writing data to the one of the memory cells. In one or more of the preceding and following embodiments, the driver circuit is configured to turn off the STT switching device connected to the one of the memory cells and then turn off the SOT switching device.

[0056] According to another aspect of the present disclosure, in a method for manufacturing a magnetic memory device, a plurality of magnetic tunnel junction (MTJ) film stacks are formed. Each of the plurality of MTJ film stacks includes a first magnetic layer as a magnetic free layer, a spacer layer disposed beneath the first magnetic layer, and a second magnetic layer as a magnetic reference layer disposed beneath the spacer layer. An interlayer dielectric layer is formed to insulate the plurality of MTJ film stacks from each other. A conductive wire is formed over the plurality of MTJ film stacks to connect to the plurality of cell stacks. The conductive wire includes a narrow portion having a width that is narrower than a remaining portion over each of the plurality of MTJ film stacks, the remaining portion being disposed between adjacent MTJ film stacks.In one or more of the preceding and following embodiments, the conductive wire has a bottom layer comprising one or more layers of W, Ta, Mo, and IrMn, and a top layer made of one or more of TiN, Ru, Ti, TaN, and Al, and the method further comprises trimming a portion of the top layer located above each of the plurality of MTJ film stacks.

Claims

[1] Magnetic storage device comprising: a first spin-orbital transfer-spin-torque transfer (SOT-STT) hybrid magnet device disposed over a substrate (100); and a second SOT-STT hybrid magnet device disposed over the substrate (100); an SOT conductive layer (10) connected to the first and second SOT-STT devices; and an upper electrode layer (5) arranged in contact with the SOT conductive layer (10) and having a recess above each of the first and second SOT-STT hybrid magnet devices, wherein each of the first and second SOT-STT hybrid magnet devices comprises: - a first magnetic layer (20) as a magnetic free layer; - a spacer layer (30) arranged under the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer, which is arranged under the spacer layer, wherein the SOT conductive layer (10) is disposed over the first magnetic layer (20), the first SOT-STT hybrid magnet device, and the second SOT-STT hybrid magnet device. [2] A magnetic memory according to claim 1, wherein the SOT conductive layer (10) comprises one or more layers of W, Ta, Mo and IrMn. [3] A magnetic memory according to claim 1 or 2, wherein the SOT conductive layer (10) comprises a lower layer of W, Ta or Mo and an upper layer of IrMn. [4] A magnetic memory according to any one of the preceding claims, wherein the upper electrode layer (5) has a narrow portion having a width narrower than a remaining portion or a thin portion having a thickness smaller than the remaining portion over each of the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device, the remaining portion being arranged between the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device. [5] The magnetic memory device according to any preceding claim, wherein each of the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device further comprises an interface layer (50) disposed over the first magnetic layer (20) and in contact with the SOT conductive layer (10). [6] Magnetic memory according to one of the preceding claims, wherein the first magnetic layer Fe x Coy B 1-x-y where x and y satisfy 0.50 ≤ x ≤ 0.70 and 0.10 ≤ y ≤ 0.

30. [7] Magnetic memory according to claim 6, wherein the second magnetic layer (40) comprises at least one layer of Co, Fe and B and one layer of Fe and B. [8] Magnetic memory according to claim 7, wherein: each of the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device further comprises a third magnetic layer (60) as a bias layer under the second magnetic layer (40), and the third magnetic layer has a layer of Co and Fe. [9] The magnetic memory device according to claim 8, wherein each of the first and second SOT-STT hybrid magnet devices further comprises a bottom electrode layer (80) disposed under the third magnetic layer (60). [10] Magnetic storage according to claim 9, wherein: each of the first and second SOT-STT hybrid magnet devices further comprises an STT switching device, one terminal of the STT switching device is connected to the bottom electrode (80), and another terminal of the switching device is connected to a source line (SL), the magnetic memory further comprises an SOT switching device, and one terminal of the SOT switching device is connected to the SOT line layer (10), and another terminal of the SOT switching device is connected to the source line (SL). [11] Magnetic memory according to claim 10, wherein the source line (SL) is connected to a current source. [12] The magnetic memory device according to claim 10 or 11, wherein the STT switching device and the SOT switching device are arranged below the first SOT-STT hybrid magnet device and the second SOT-STT hybrid magnet device. [13] Magnetic storage device comprising: first word lines (WL-STT); a second word line (WL-SOT); a bit line (BL); a source line (SL); memory cells; and a conductive wire (10), wherein: each of the memory cells comprises a magnetic tunnel junction film stack (MTJ film stack) and a spin torque transfer switching device (STT switching device SW1), wherein the MTJ film stack has a tapered shape towards the conductive wire (10), a terminal of the STT switching device (SW1) is connected to one end of the MTJ film stack, another terminal of the STT switching device (SW1) is connected to the source line (SL), and a control terminal of the STT switching device (SW1) is connected to a corresponding one of the first word lines (WL-STT), another end of the MTJ film stack is connected to the conductive wire (10), the conductive wire is connected to the bit line (BL), the magnetic memory further comprises an SOT switching device (SW2), and one terminal of the SOT switching device (SW2) is connected to the conductive wire (10), another terminal of the SOT switching device (SW2) is connected to the source line (SL), and a control terminal of the SOT switching device (SW2) is connected to the second word line (WL-SOT). [14] Magnetic memory according to claim 13, wherein the source line (SL) is connected to a current source. [15] A magnetic memory according to claim 13 or 14, wherein a number of the memory cells connected to the conductive wire (10) is 2 to 32. [16] Magnetic storage device according to one of the preceding claims 13 to 15, wherein: The MTJ film stack includes: - a first magnetic layer (20) as a magnetic free layer; - a spacer layer (30) arranged under the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer, which is arranged below the spacer layer (30), and the conductive wire (10) is arranged above the first magnetic layer (20). [17] Magnetic memory according to one of the preceding claims 13 to 16, further comprising a driver circuit arranged to: Applying an SOT current to the conductive wire by turning on the SOT switching device (SW2); and then applying an STT current to one of the memory cells by turning on the STT switching device (SW1) connected to the one memory cell, thereby writing data into the one of the memory cells. [18] Magnetic memory according to claim 17, wherein the driver circuit is arranged to: Turning off the STT switching device (SW1) connected to one of the memory cells; and then turning off the SOT switching device (SW2). [19] A method of manufacturing a magnetic memory device, comprising: Forming a plurality of magnetic tunnel junction (MTJ) film stacks, each comprising: - a first magnetic layer (20) as a magnetic free layer; - a spacer layer (30) arranged under the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer arranged under the spacer layer; Forming an interlayer dielectric layer (ILD) to isolate the plurality of MTJ film stacks from each other; and Forming a conductive wire (250, 260) over the plurality of MTJ film stacks to be connected to the plurality of cell stacks, wherein the conductive wire (250, 260) has a narrow portion having a width that is narrower than a remaining portion above each of the plurality of MTJ film stacks, the remaining portion being disposed between adjacent MTJ film stacks.

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