SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Abstract

A method of manufacturing a semiconductor device, comprising: Forming a stacked structure comprising alternately stacked semiconductor layers (25) and sacrificial layers (20), wherein the sacrificial layers (20) comprise a metal nitride material; Forming a sacrificial gate structure (40) over the stack structure; Forming a dielectric layer (50) over the sacrificial gate structure (40); Removing the sacrificial gate structure (40) and thereby forming a gate space (52); Removing the sacrificial layers (20) in the gate space (52) and thereby releasing the semiconductor layers (25); and Forming a gate structure (80, 82) around channel regions of the semiconductor layers (25), Forming a contact opening (65) in the dielectric layer (50); Removing the sacrificial layers (20) in the contact opening (65) and thereby exposing source / drain regions of the semiconductor layers (25); and Forming a source / drain contact (70) around the source / drain regions of the semiconductor layers (25), wherein the semiconductor layers (25) are made of an oxide semiconductor material.

Description

BACKGROUND

[0001] As the size of semiconductor devices shrinks, so does the cell height of standard cells. Cell height is generally defined as a periodic distance (pitch) between two power supply lines, VDD and VSS, and is generally determined by the number and pitch of fin structures and / or metal lines. Cell height is also called trace height. Typical trace heights are 7.5T, 6.5T, or 5.5T, where T is a smallest pitch of metal lines running across the standard cell. Currently, downsizing to 4.5T or 4T is required to further minimize the size of semiconductor devices.

[0002] US 2018 / 0 366 587 describes methods for fabricating non-planar transistors with improved electrostatic properties. US 2017 / 0 140 996 A1 proposes a semiconductor device with improved electrical contacts, in which source / drain contacts are arranged around a semiconductor layer. US 2017 / 0 154 958 A1 shows a transistor with fin structures, in which a gate structure encloses the channel region of a semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 shows a circuit diagram of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 3 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 4 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 5 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 6A and Fig. 6B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 6A is an isometric view and Fig. 6B is a top view. Fig. 7A and Fig. 7B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 7A is an isometric view and Fig. 7B is a top view. Fig. 8A and Fig. 8B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 8A is an isometric view and Fig. 8B is a top view. Fig. 9A and Fig. 9B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 9A is an isometric view and Fig. 9B is a top view. Fig. 10A and Fig. 10B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 10A is an isometric view and Fig. 10B is a top view. Fig. 11A and Fig. 11B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 11A is an isometric view and Fig. 11B is a top view. Fig. 12A and Fig. 12B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 12A is an isometric view and Fig. 12B is a top view. Fig. 13A and Fig. 13B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 13A is an isometric view and Fig. 13B is a top view. Fig. 14A and Fig. 14B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 14A is an isometric view and Fig. 14B is a top view. Fig. 15A and Fig. 15B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 15A is an isometric view and Fig. 15B is a top view. Fig. 16A and Fig. 16B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 16A is an isometric view and Fig. 16B is a top view. Fig. 17A and Fig. 17B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 17A is an isometric view and Fig. 17B is a top view. The Fig. 18A and Fig. 18B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 18A is an isometric view and Fig. 18B is a top view. Fig. 19A and Fig. 19B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 19A is an isometric view and Fig. 19B is a top view. Fig. 20A and Fig. 20B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 20A is an isometric view and Fig. 20B is a top view Fig. 21A and Fig. 21B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 21A is an isometric view and Fig. 21B is a plan view Fig. 22A and Fig. 22B are schematic illustrations of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 22A is an isometric view and Fig. 22B is a top view. Fig. 23 shows a cross-sectional view of a semiconductor FET device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing different features of various embodiments of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired device characteristics.Furthermore, in the following description, the formation of a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements need not be in direct contact. Various elements may be arbitrarily drawn at different scales for simplicity and clarity. In the accompanying drawings, some layers / elements may be omitted for simplicity.

[0005] Further, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, the term "made of" can mean either "comprising" or "consisting of."Furthermore, in the subsequent manufacturing process, there may be one or more additional operations in / between the described operations, and the order of operations may be changed. In the following embodiments, the terms "over" and / or "above" are defined along directions with an increase in distance from the front surface and the back surface. Materials, configurations, dimensions, processes, and / or operations explained with respect to one embodiment may be employed in the other embodiments, and the detailed description thereof may be omitted.

[0006] Minimizing power consumption in a semiconductor device such as an integrated circuit (IC) is a critical problem in semiconductor devices for high-speed operations and / or semiconductor devices for mobile terminal devices. Various technologies have been proposed to reduce power consumption, but many of them require a larger chip area due to additional circuitry for controlling the current. One such technology involves providing a virtual power supply line (VVDD and / or VVSS) along with a header switch and / or a footer switch between a main power supply line (VDD and / or VSS) and the virtual power supply line. The virtual power supply line may be called a local power supply line, while the main power supply line may be called a global power supply line.Note that VDD generally has a higher potential (voltage) than VSS, and in some embodiments, VSS is coupled to ground (0 V). Power consumption is reduced by turning off (opening) the header / footer switch, which is coupled to an inactive functional circuit in the semiconductor device.

[0007] Fig. 1 shows a circuit diagram of a semiconductor device according to an embodiment of the present disclosure. As shown in Fig. 1, a p-MOSFET is used as a header switch and an n-MOSFET is used as a footer switch to turn off the power supply to the local VVDD, which continues to supply power to blocks comprising one or more standard cells STDC, each of which includes a functional circuit (e.g., CMOS inverter). In some embodiments, no footer switch is used and the standard cells are directly coupled to the VSS. In some embodiments, as shown in Fig. 1, a first main power supply line VDD is coupled to a VDD generation circuit (Vdd Source) that generates a voltage such as 0.5 V, 0.8 V, 1.0 V, 1.2 V, 1.8 V, 2.4 V, 3.3 V, or 5.0 V. A second main power supply line VSS is coupled to a VSS generation circuit (Vss Source), which in some embodiments generates a voltage lower than VDD or ground. As shown in Fig. 1, the local power supply lines VVDD are divided into a plurality of local power supply lines, each of which is connected to one or more standard cells STDC as a cell block. Accordingly, the power supply to the standard cells can be controlled on a block-by-block basis. In some embodiments, the standard cells STDC further include an internal power supply line (bus line) INT, and the local power supply line VVDD is coupled to the internal power supply line with or without a switch.

[0008] In embodiments of the present disclosure, in a semiconductor device, a power switch circuit (header and / or footer switch) is moved from the front-end-of-line (FEOL) circuit level to the back-end-of-line (BEOL) circuit level to provide, as shown in Fig. 2 to enable devices of reduced size. The FEOL circuit level includes MOS transistors formed on a semiconductor substrate. The MOS transistors include planar field-effect transistors (FETs), fin FETs, and / or gate-around (GAA) FETs. The FEOL circuit level, in some embodiments, further includes local coupling structures. The BEOL circuit level includes metal interconnect structures including one or more dielectric layers, metal interconnects, and vias embedded in the dielectric layer. Offsetting the power switch circuitry from the FEOL circuit level to the interconnect layers in the BEOL circuit level allows the device area to be reduced by approximately 10%.Placing the power switch circuitry in the BEOL circuit layer requires fewer vias, thus freeing up space for more routing to the logic block and thereby increasing device density in the logic block. TFTs with a non-crystalline semiconductor are suitable for a back-end-of-line process because a non-crystalline semiconductor can generally be formed at a low temperature, such as below 450 °C.

[0009] In some embodiments, the power switch circuit includes thin film transistors (TFTs) as shown in Fig. 2, since TFT manufacturing processes do not generally require high temperatures, for example, to form an epitaxial semiconductor channel, and are suitable for the BEOL circuit level. The power switch circuit is, for example, as shown in Fig. 2 arranged in the M1-M2 plane, the M4-M5 plane or the M8-M9 plane.

[0010] In some embodiments of the present disclosure, the channel region of the TFTs comprises oxide semiconductors such as amorphous indium gallium zinc oxide (IGZO), crystal c-axis aligned (CAAC) IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and ZnON.

[0011] Transistors in the power switch circuit generally require a low operating resistance R on = V ds / I d . For example, IGZO offers an extremely low off-current I off (low leakage current) and IGZO TFTs have a large ratio I on / Ioff. Since amorphous IGZO (a-IGZO) has a low electron mobility (~15 cm 2 Vs), a single-layer planar TFT made from an a-IGZO, but for the required R on -value is not sufficient for a circuit breaker circuit.

[0012] To compensate for this property, the channel width W eff in some embodiments increased to achieve a low R on > R eh = L g / (W eff -Mobility C ox (V g -V t )) to provide, since C ox usually cannot be increased due to gate current limitations and V g -V t is determined by the supply voltage. In embodiments of this disclosure, a multi-stack nanosheet gate wraparound oxide semiconductor device structure and a corresponding process flow are provided to increase the effective width per footprint and R on to reduce without changing the ratio I on / I off The advantages of using an oxide semiconductor such as IGZO include low leakage current, reasonable electron mobility, and high reliability.

[0013] Fig. 3 is a schematic cross-sectional illustration (XZ plane) across the oxide semiconductor nanosheet of a semiconductor device and Fig. 4 is a schematic cross-sectional illustration (YZ plane) across the gate electrode of the semiconductor device according to an embodiment of the disclosure.

[0014] In some embodiments, the semiconductor device is a gate-all-around (GAA) FET as shown in the Fig. 3 and Fig. 4. In some embodiments, the oxide semiconductor nanosheets 25 extend in the Y-direction (source-to-drain direction) and are stacked along the Z-direction (vertical direction). Although four oxide semiconductor nanosheets 25 are stacked in the Fig. 3 and Fig. 4, the number of oxide semiconductor nanosheets 25 can be as few as 2 and as many as 20, depending on a required current. In some embodiments, the number of oxide semiconductor nanosheets ranges from 4 to 10. A width W1 of the oxide semiconductor nanosheets 25 is in a range from about 10 nm to about 50 nm in some embodiments, and in a range from about 15 nm to about 30 nm in other embodiments, depending on the required current and / or the manufacturing process conditions. A thickness T1 of the oxide semiconductor nanosheets 25 is in a range from about 5 nm to about 30 nm in some embodiments, and in a range from about 10 nm to about 20 nm in other embodiments, depending on the required current and / or the manufacturing process conditions. In some embodiments, W1>T1.In some embodiments, an aspect ratio W1 / T1 ranges from about 1.2 to about 10, and in other embodiments, from about 2 to about 5. A space S1 between adjacent oxide semiconductor nanosheets 25 ranges from about 5 nm to about 30 nm in some embodiments, and from about 10 nm to about 20 nm in other embodiments, depending on the required current and / or manufacturing process conditions. In some embodiments, S1 ≥ T1, and in other embodiments, S1 < T1. If the space S1 is too narrow, it would be difficult to uniformly form layers (e.g., a gate dielectric layer and a gate electrode layer) to wrap around the oxide semiconductor nanosheet 25.

[0015] A gate dielectric layer 82 wraps around each of the oxide semiconductor nanosheets 25. In some embodiments, the gate dielectric layer is a high-k dielectric, such as silicon nitride, HfO 2 , La 2 O 3 , ZrO 2 , BaO, TiO 2 , Ta 2 O 5 , SrO, Y 2 O 3 , HfSiO 4 , ZrSiO 4 , Al 2 O 3, MgO, CaO, other suitable high-k dielectrics, and / or combinations thereof. A thickness of the gate dielectric layer 82, in some embodiments, ranges from approximately 2 nm to approximately 20 nm. The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process such as ALD to ensure the formation of a gate dielectric layer with a uniform thickness around each oxide semiconductor nanosheet.

[0016] A metal gate electrode 80 is formed on the gate dielectric layer 82 so that it wraps around each of the oxide semiconductor nanosheets 25. The metal gate electrode 80, in some embodiments, includes multiple conductive layers. In some embodiments, the metal gate electrode 80 includes one or more work function adjustment layers 84 and a body metal gate electrode layer 86. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The work function adjustment layer may be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process. Furthermore, the work function adjustment layer 84 may be formed separately for the nFET and the pFET, which may use different metal layers.The body gate electrode layer is formed to surround each oxide semiconductor nanosheet (channel region). The body gate electrode layer comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The body gate electrode layer may be formed by CVD, ALD, electroplating, or another suitable process.

[0017] The gate structure, which includes the gate dielectric layer 82 and the metal gate electrode 80, is as shown in Fig. 3 between gate sidewall spacers 48, and an interlayer dielectric (ILD) layer 50 is further disposed as shown in Fig. 3 arranged.

[0018] In some embodiments, as in Fig. 4, inner spacers 21 are disposed between the gate electrode layer 84 and the source / drain contact 70. The inner spacers 21 are remaining portions of a sacrificial layer 20, as described below.

[0019] The oxide semiconductor nanosheet 25 also has a source / drain region as shown in Fig. 4. A source / drain contact 70 is formed in contact therewith and wraps around the source / drain region of each of the oxide semiconductor nanosheets 25. In some embodiments, the source / drain contact 70 has a multilayer structure. The source / drain contact 70, in some embodiments, comprises, as shown in Fig. 4 a liner or barrier layer 72 and a body contact layer 74. In some embodiments, the liner layer 72 is made of one or more of Ti, TiN, Ta, and TaN, and the body contact layer 74 is made of one or more of W, Cu, Ti, Ag, Al, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr.

[0020] In some embodiments, the oxide semiconductor nanosheets 25 pass through the source / drain contact 70 and reach the ILD layer 50 as shown in Fig. 4. In other embodiments, the ends of the oxide semiconductor nanosheets 25 are located in the source / drain contact 70.

[0021] Fig. 5 is a schematic cross-sectional illustration (YZ plane) across the gate electrode of the semiconductor device according to another embodiment of the disclosure.

[0022] In this embodiment, the oxide semiconductor nanosheets 25 do not penetrate into or pass through the source / drain contact 70. The source / drain contact 70 covers, as shown in Fig. 5 end faces of the non-oxide semiconductor sheets 25.

[0023] The Fig. 6A to 20B illustrate sequential operations for manufacturing a semiconductor device according to an embodiment of the present disclosure. However, it should be understood that additional operations may be performed before, during, and after the processes described by the Fig. 6A to 20B, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable. The "A" figures show isometric views, and the "B" figures show plan views (top views).

[0024] The Fig. 6A and Fig. 6B are schematic illustrations of one of the stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. As shown in Fig. 6A, a substrate 5 is provided. In some embodiments, the substrate 5 comprises a single-crystal semiconductor layer on at least one surface portion. The substrate 5 may comprise a single-crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 5 is made of crystalline Si, SiGe, or Ge. The substrate 5, in some embodiments, may comprise one or more buffer layers (not shown) in its surface region. The buffer layers may serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers may be made of epitaxially grown single-crystal semiconductor materials such as, for example, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. B., but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP and InP.In a specific embodiment, the substrate 5 comprises silicon germanium (SiGe) buffer layers epitaxially grown on the silicon substrate 5. The germanium concentration of the SiGe buffer layers can increase from 30 atomic percent germanium for the very bottom buffer layer to 70 atomic percent germanium for the top buffer layer.

[0025] As shown in Fig. 6A, one or more first interlayer dielectric (ILD) layers 10 are formed over the substrate 5. In some embodiments, one or more electronic devices, such as transistors (e.g., FETs), memory (e.g., dynamic random access memory (DRAM), static RAM, magnetic MRAM, and / or phase change RAM), are formed on the substrate 5, and the one or more first interlayer dielectric layers 10 cover the electronic devices.

[0026] In some embodiments, one or more metal wiring structures are embedded in the ILD layers 10. The dielectric for the first ILD layers 10 comprises silicon oxide, silicon nitride, silicon oxynitride (SiON), SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD, or any other suitable film-forming process. An annealing process may be performed after the formation of the first ILD layer 10. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process and / or an etch-back process is performed to flatten the surface of the first ILD layer 10.

[0027] The Fig. 7A and Fig. 7B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. In some embodiments, semiconductor layers 25 and sacrificial layers 20 are alternately formed over the ILD layer 10.

[0028] In some embodiments, the semiconductor layers 25 are made of oxide semiconductor materials, such as amorphous indium gallium zinc oxide (IGZO), crystal with c-axis alignment (CAAC)-IGZO, ZnO, In 2 O 3 , Ga 2 O 3and ZnON. In some embodiments, amorphous IGZO is used. The semiconductor layers 25 are formed by CVD, atomic layer deposition (ALD), physical vapor deposition including sputtering, or any other suitable film formation method. In some embodiments, the semiconductor layers 25 are formed by CVD at a temperature in a range of approximately 50°C to 600°C. In other embodiments, the semiconductor layers 25 are formed by atomic layer deposition (ALD) at a temperature in a range of approximately 25°C to 400°C. In some embodiments, the semiconductor layers 25 are formed by physical vapor deposition including sputtering at a temperature in a range of approximately 25°C to 400°C.

[0029] In some embodiments, the sacrificial layers 20 are made of a different material than the semiconductor layers 25, so that the sacrificial layers 20 are removed selectively from the semiconductor layers 25 in the subsequent process. In some embodiments, the sacrificial layer 25 is made of one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide, or any other suitable insulating material. In some embodiments, the sacrificial layers 25 are made of one or more layers of semiconductor material, such as Si, SiGe, and Ge. In some embodiments, the semiconductor layer is amorphous or polycrystalline. In other embodiments, the sacrificial layers 25 are made of one or more layers of a metallic material, such as metal nitride, which includes TiN and TaN.

[0030] In some embodiments, the thickness of the semiconductor layers 25 is in a range from about 5 nm to about 30 nm, and in other embodiments, in a range from about 10 nm to about 20 nm. In some embodiments, the thickness of the sacrificial layers 20 is in a range from about 5 nm to about 30 nm, and in other embodiments, in a range from about 10 nm to about 20 nm. In some embodiments, the thickness of the semiconductor layers 25 is equal to the thickness of the sacrificial layers 20, and in other embodiments, the thickness of the semiconductor layers 25 is greater or less than the thickness of the sacrificial layers 20.

[0031] Although four semiconductor layers 25 and five sacrificial layers 20 are shown, in some embodiments, up to 20 layers each are formed. In some embodiments, the number of layers ranges from 4 to 10 layers each of the semiconductor and sacrificial layers. In some embodiments, a sacrificial layer 20 is formed directly on the first ILD layer 10, and the topmost layer of the alternative stack is a sacrificial layer 20. In other embodiments, the topmost layer of the alternative stack is a semiconductor layer 25.

[0032] The Fig. 8A and Fig. 8B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. In some embodiments, the alternating stack of semiconductor layers 25 and sacrificial layers 20 is patterned into fin structures 22.

[0033] The fin structures 22 may be patterned by any suitable method. The structures may be patterned, for example, using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for structures to be fabricated that have, for example, pitches smaller than what is otherwise achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer (a mandrel structure) is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process.The sacrificial layer (mandrel structure) is then removed and the remaining spacer elements can then be used to pattern the fin structure 22.

[0034] Although five fin structures 22 in Fig. 8B, the number of fin structures for a TFT is not limited to five. In some embodiments, the number of fin structures per TFT ranges from 1 to 10, and in other embodiments, depending on drive current requirements, is in a range of 2 to 5. A width of the fin structures 25 is in a range of about 10 nm to about 50 nm in some embodiments, and in a range of about 15 nm to about 30 nm in other embodiments.

[0035] The Fig. 9A and Fig. 9B are schematic illustrations of a sequential step for manufacturing a semiconductor device according to an embodiment of the present disclosure. In some embodiments, as shown in Fig. 9A, a sacrificial gate dielectric layer 42 is formed over the fin structures 22 and the ILD layer 20. In some embodiments, the sacrificial gate dielectric layer 42 is formed from an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide, or any other suitable insulating material. In other embodiments, no sacrificial gate dielectric layer is formed.

[0036] The Fig. 10A and Fig. 10B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. Then, a sacrificial gate structure 40 for a gate replacement technique is formed as shown in FIGS. Fig. 10A and Fig. 10B. In some embodiments, the sacrificial gate structure includes a sacrificial gate electrode layer 44 and a hard mask layer 46. In some embodiments, the sacrificial gate electrode layer 44 is polycrystalline or amorphous Si, SiGe, or Ge. The sacrificial gate electrode layer 44 is formed by chemical vapor deposition (CVD) or any other suitable film formation method, and a hard mask layer 46 is formed over the sacrificial gate electrode layer 44. In some embodiments, the hard mask layer 46 is formed from a silicon nitride-based material, such as silicon nitride, SiON, or SiCN, or a silicon oxide-based material, such as silicon oxide. After the hard mask layer 46 is formed using one or more lithography and etching processes, the hard mask layer 46 is patterned.Then, using the patterned hard mask layer 46 as an etch mask, the deposited sacrificial gate electrode layer 44 is patterned. In some embodiments, one or more dummy gate structures are formed to surround the sacrificial gate structures in favor of a functional transistor to suppress process variations and / or to improve the pattern fidelity of the structure.

[0037] The Fig. 11A and Fig. 11B are schematic illustrations of a sequential step for manufacturing a semiconductor device according to an embodiment of the present disclosure. Subsequently, as shown in the Fig. 11A and Fig. 11B Gate sidewall spacers 48 are formed on side surfaces of the sacrificial gate structure 40. A cap layer of an insulating material for the first sidewall spacers is conformally formed using CVD or other suitable methods. The cap layer is deposited in a conformal manner such that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top surface of the sacrificial gate structure 40. In some embodiments, the cap layer is deposited to a thickness in a range of about 2 nm to about 30 nm. In one embodiment, the insulating material of the cap layer is different from the materials of the sacrificial gate structure and is made of a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof. In some embodiments, the cap layer is made of silicon nitride.The sidewall spacers are formed on opposite side surfaces of the sacrificial gate structure by anisotropic etching. In some embodiments, the gate sidewall spacers 48 are formed on opposite side surfaces of the hard mask layer 46. In some embodiments, the sidewall spacers are formed on side surfaces of the fin structures 22.

[0038] The Fig. 12A and Fig. 12B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. Then, the sacrificial gate dielectric layer 42 is removed and the fin structures 22, as shown in the Fig. 12A and Fig. 12B exposed. As shown in Fig. 12A, the sacrificial gate dielectric layer 42 remains beneath the sacrificial gate structure 40 and the gate sidewall spacers 48.

[0039] The Fig. 13A and Fig. 13B are schematic illustrations of a sequential step for manufacturing a semiconductor device according to an embodiment of the present disclosure. Then, as shown in the Fig. 13A and Fig. 13B, a second ILD layer 50 is formed over the sacrificial gate structure 40 and the fin structures 22. The materials for the second ILD layer 50 include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the second ILD layer 50. In some embodiments, the second ILD layer 50 is made of the same material as the first ILD layer 10. After the second ILD layer 50 is formed, a planarization process such as CMP is performed so that the upper portion of the sacrificial gate electrode layer 44 is formed as shown in the Fig. 13A and Fig. 13B is exposed.

[0040] The Fig. 14A and Fig. 14B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. Subsequently, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed and thereby, as shown, in the Fig. 14A and Fig. 14B, a gate space 52 is formed. The sacrificial gate electrode layer 44 may be removed using plasma dry etching and / or wet etching. In some embodiments, when the sacrificial gate electrode layer 44 is formed from polycrystalline or amorphous Si, a tetramethylammonium hydroxide (TMAH) solution is used as a wet etchant. The sacrificial gate dielectric layer 42 is also removed by a suitable wet / dry etch.

[0041] Furthermore, as shown in the Fig. 14A and Fig. 14B, the sacrificial layers 20 are also removed under the gate space 52. If the sacrificial layers 20 and the sacrificial gate dielectric layer 42 are made of the same or similar materials, the removal process (e.g., wet etching) of the sacrificial gate dielectric layer 42 also removes the sacrificial layer 20. If the sacrificial layers 20 and the sacrificial gate dielectric layer 42 are made of different materials, two or more etching processes are performed to sequentially remove the sacrificial gate dielectric layer 42 and the sacrificial layers 20. By removing the sacrificial layers 20, channel regions of the semiconductor layers 25 in the gate space 52 are exposed as semiconductor nanosheets.

[0042] The Fig. 15A and Fig. 15B are schematic illustrations of a sequential step for manufacturing a semiconductor device according to an embodiment of the present disclosure. Then, as shown in the Fig. 15A and Fig. 15B, a gate dielectric layer 82 and a gate electrode layer 80 are formed in the gate space 52. In some embodiments, the gate dielectric layer 82 comprises one or more layers of a dielectric, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric, and / or combinations thereof. Examples of high-k dielectric materials include HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnia aluminum oxide (HfO 2 -Al 2 O 3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interlayer formed between the channel region and the dielectric. The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process such as ALD to ensure the formation of a gate dielectric layer with a uniform thickness around each channel region. The thickness of the gate dielectric layer 82 is in a range from about 1 nm to about 20 nm in some embodiments and in a range from about 2 nm to about 10 nm in other embodiments.

[0043] The metal gate electrode layer 80, in some embodiments, includes one or more work function adjustment layers 84 and a body metal gate electrode layer 86. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The work function adjustment layer may be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process. Furthermore, the work function adjustment layer 84 may be formed separately for the nFET and the pFET, which may use different metal layers. The body gate electrode layer is formed to surround each oxide semiconductor nanosheet (channel region).The body gate electrode layer comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The body gate electrode layer may be formed by CVD, ALD, electroplating, or another suitable process. The metals for the gate dielectric layer 82 and the gate electrode layer 80 are also deposited over the top surface of the second ILD layer 50. The material for the gate electrode layer 80 formed over the second ILD layer 50 is then planarized using, for example, CMP until the top surface of the second ILD layer 50 is as shown in FIGS. Fig. 15A and Fig. 15B. In some embodiments, after the planarization process, the metal gate electrode layer is recessed, and a cap insulating layer (not shown) is formed over the recessed gate electrode layer. The cap insulating layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The cap insulating layer may be formed by depositing an insulating material followed by a planarization process.

[0044] The Fig. 16A and Fig. 16B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. Furthermore, a third ILD layer 60 is formed over the second ILD layer 50, and the contact holes 65 for the source / drain contact are formed in the third and second ILD layers as shown in FIGS. Fig. 16A and Fig. 16B. The materials for the third ILD layer 60 include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the third ILD layer 60. In some embodiments, the third ILD layer 60 is formed from the same material as the second ILD layer and / or the first ILD layer 10. In some embodiments, the third ILD layer 60 functions as a hard mask layer for etching the second ILD layer.

[0045] The Fig. 17A and Fig. 17B are schematic illustrations of a sequential step for fabricating a semiconductor device according to an embodiment of the present disclosure. After the contact holes 65 are formed, the sacrificial layers 20 beneath the contact holes 65 are removed, thereby forming source / drain regions of the semiconductor layers 20 as shown in Fig. 17A will be released.

[0046] In some embodiments, a portion of the sacrificial layers 20 remain as inner spacers 21. If the sacrificial layers 20 remain as the inner spacers 21, the sacrificial layers 20 are made of an insulating material in some embodiments. In other embodiments, the sacrificial layers 20 are completely removed.

[0047] The Fig. 18A to 20B are schematic illustrations of a sequential step for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 18A shows a cross section along the source-to-drain direction (Y direction), Fig. 19A shows a cross section along the gate extension direction (X direction) of the gate electrode and Fig. Figure 20A shows a cross-section along the X direction of a source / drain contact.

[0048] As shown in the Fig. 18A to 20B, source / drain contacts 70 are formed in the contact holes 65. One or more layers of conductive materials are formed in and over the contact holes, and then a planarization process, such as a CMP operation, is performed to form the conductive contacts 70. In some embodiments, the source / drain contact 70 includes a liner or barrier layer 72 and a body contact layer 74 as shown in Fig. 4. In some embodiments, the liner layer 72 is made of one or more of Ti, TiN, Ta, and TaN, and the body contact layer 74 is made of one or more of W, Cu, Ti, Ag, Al, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. As shown in Fig. 20A, at least the liner layer 72 wraps around the source / drain regions of the semiconductor layers (nanosheet) 25. In other embodiments, the body contact layer 74 also wraps around the source / drain regions.

[0049] It is understood that the TFT undergoes further processes to form various features such as contacts / vias, coupling structure metal layers, dielectric layers, passivation layers, etc.

[0050] The Fig. 21A to 22B illustrate sequential operations for manufacturing a semiconductor device according to another embodiment of the present disclosure. However, it should be understood that additional operations may be performed before, during, and after the processes described by the Fig. 21A to 22B, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. Fig. 21A to 22B correspond to the manufacturing processes shown in Fig. TFT structure shown in Figure 5.

[0051] After the contact holes 65 for the source / drain contacts have been formed, both the semiconductor layer 25 and the sacrificial layers 20 in the contact holes 65 are deposited in the Fig. 21A and Fig. 21B. Then, similar to the Fig. 20A and Fig. 20B Source / Drain contacts 70, as shown in the Fig. 22A and Fig. 22B formed.

[0052] Fig. 23 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. As shown in Fig. 23, a bottom layer device 100 is formed over a substrate. The bottom layer devices 100 include one or more fin field-effect transistors (FinFETs), gate-around FETs (GAA FETs), planar FETs, vertical FETs, or any other electronic devices. Fig.23 also shows an upper layer device 200 disposed over the lower layer device 100. In some embodiments, one or more ILD layers, metal wiring layers, and / or via contacts are disposed between the lower layer device 100 and the upper layer device 200. In some embodiments, the upper layer device 200 includes one or more TFTs fabricated by the above-described embodiments of the present disclosure.

[0053] In the present embodiments, an on-off circuit for switching the power supply from the main power supply (VDD or VSS) to the local power supply (VVDD or VVSS) and power supply wiring are formed using an oxide semiconductor such as IGZO. Accordingly, it is possible to provide the on-off circuit at the BEOL circuit level.

[0054] It should be understood that not all advantages have necessarily been described herein, that no particular advantage is required for all embodiments or examples, and that different embodiments or examples may provide different advantages.

[0055] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a stack structure including semiconductor layers and sacrificial layers are alternately stacked, a sacrificial gate structure is formed over the stack structure, a dielectric layer is formed over the sacrificial gate structure, the sacrificial gate structure is removed, thereby forming a gate space, the sacrificial layers in the gate space are removed, thereby exposing the semiconductor layers, and a gate structure wrapping around the semiconductor layers is formed. The semiconductor layers are made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC) IGZO, ZnO, In 2 O 3 , Ga 2 O3and ZnON. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO). In one or more of the preceding and / or following embodiments, the sacrificial layer comprises one selected from the group consisting of an insulating material, an amorphous or polycrystalline semiconductor material, and a metal nitride material. In one or more of the preceding and / or following embodiments, the stack structure is formed on an insulating material layer. In one or more of the preceding and / or following embodiments, the insulating material layer covers transistors formed over a semiconductor substrate.In one or more of the preceding and / or following embodiments, the stack structure is formed by alternately forming the semiconductor layers and the sacrificial layers on an insulating material layer and patterning the semiconductor layers and the sacrificial layers into one or more fin structures.

[0056] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure including semiconductor layers and sacrificial layers are alternately stacked over a first dielectric layer, a sacrificial gate structure is formed over the fin structure, gate sidewall spacers are formed on opposite side surfaces of the sacrificial gate structure, a second dielectric layer is formed over the sacrificial gate structure and the fin structure, the sacrificial gate structure is removed, thereby forming a gate space, the sacrificial layers in the gate space are removed, thereby exposing channel regions of the semiconductor layers, a gate structure wrapping around the channel regions of the semiconductor layers is formed, a third dielectric layer is formed, a contact opening is formed in the third dielectric layer and the second dielectric layer,The sacrificial layers are removed in the contact opening, thereby exposing source / drain regions of the semiconductor layers, and a source / drain contact is formed that wraps around the source / drain regions of the semiconductor layers. The semiconductor layers are made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises one selected from the group consisting of indium gallium zinc oxide (IGZO), crystal with c-axis alignment (CAAC)-IGZO, ZnO, In, 2 O 3 , Ga 2 O 3and ZnON. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO). In one or more of the preceding and / or following embodiments, the sacrificial layer comprises one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide. In one or more of the preceding and / or following embodiments, the sacrificial layer comprises one selected from the group consisting of amorphous or polycrystalline Si, SiGe, and Ge. In one or more of the preceding and / or following embodiments, the sacrificial layer comprises one selected from the group consisting of TiN and TaN. In one or more of the preceding and / or following embodiments, the first dielectric layer covers transistors formed over a semiconductor substrate.In one or more of the preceding and / or following embodiments, when removing the sacrificial layers in the contact opening, parts of the sacrificial layers remain and, after the source / drain contact has been formed, the remaining parts of the sacrificial layers are arranged between the source / drain contact and the gate structure.

[0057] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure including semiconductor layers and sacrificial layers are alternately stacked over a first dielectric layer, a sacrificial gate structure is formed over the fin structure, gate sidewall spacers are formed on opposite side surfaces of the sacrificial gate structure, a second dielectric layer is formed over the sacrificial gate structure and the fin structure, the sacrificial gate structure is removed, thereby forming a gate space, the sacrificial layers are removed in the gate space, thereby exposing channel regions of the semiconductor layers, a gate structure wrapping around the channel regions of the semiconductor layers is formed, a third dielectric layer is formed, a contact opening is formed in the third dielectric layer and the second dielectric layer,The sacrificial layers and the semiconductor layer are removed in the contact opening, and a source / drain contact is formed in the contact opening. The semiconductor layers are made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC) IGZO, ZnO, In, 2 O 3 , Ga 2 O 3and ZnON. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO). In one or more of the preceding and / or following embodiments, the sacrificial layer comprises one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide. In one or more of the preceding and / or following embodiments, when removing the sacrificial layers in the contact opening, parts of the sacrificial layers remain and, after the source / drain contact has been formed, the remaining parts of the sacrificial layers are arranged between the source / drain contact and the gate structure.

[0058] According to one aspect of the present disclosure, a semiconductor device comprises a power switch circuit and a logic circuit. The semiconductor device comprises a first dielectric layer and a thin-film transistor (TFT) formed on the first dielectric layer. The TFT comprises a semiconductor nanosheet, a gate dielectric layer encapsulated around a channel region of the semiconductor nanosheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nanosheet is made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises one selected from the group consisting of indium gallium zinc oxide (IGZO), crystal c-axis aligned (CAAC) IGZO, ZnO, In 2 O 3 , Ga 2 O 3and ZnON. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO). In one or more of the preceding and / or following embodiments, a thickness T1 of the semiconductor nanosheet is in a range from 5 nm to 30 nm, and a width W1 of each of the semiconductor nanosheets along a gate extension direction is in a range from 10 nm to 50 nm. In one or more of the preceding and / or following embodiments, a ratio W1 / T1 is in a range from 1.2 to 10.

[0059] According to another aspect of the present disclosure, a semiconductor device comprises a power switch circuit and a logic circuit. The power switch circuit comprises a first dielectric layer and a thin-film transistor (TFT) formed on the first dielectric layer. The TFT comprises semiconductor nanosheets arranged vertically, a gate dielectric layer wrapping around a channel region of each of the semiconductor nanosheets, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nanosheets are made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC) IGZO, ZnO, In 2 O 3 , Ga 2 O 3and ZnON. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO). In one or more of the preceding and / or following embodiments, a thickness T1 of each of the semiconductor nanosheets is in a range from 5 nm to 30 nm, and a width W1 of each of the semiconductor nanosheets along a gate extension direction is in a range from 10 nm to 50 nm. In one or more of the preceding and / or following embodiments, a ratio W1 / T1 is in a range from 2 to 5. In one or more of the preceding and / or following embodiments, a number of the semiconductor nanosheets is in a range from 2 to 10. In one or more of the preceding and / or following embodiments, the TFT further comprises a source / drain contact wrapping around a source / drain region of each of the semiconductor nanosheets.In one or more of the preceding and / or following embodiments, the TFT further comprises internal spacers disposed between the source / drain contact and the gate electrode layer. In one or more of the preceding and / or following embodiments, the TFT further comprises a source / drain contact in contact with end surfaces of the semiconductor nanosheets. In one or more of the preceding and / or following embodiments, the TFT further comprises internal spacers disposed between the source / drain contact and the gate electrode layer.

[0060] According to another aspect of the present disclosure, a semiconductor device comprises a power switch circuit and a logic circuit, and the semiconductor device comprises a first dielectric layer and a thin-film transistor (TFT) formed on the first dielectric layer. The TFT comprises a plurality of groups of semiconductor nanosheets, the semiconductor nanosheets in each of the plurality of groups being perpendicularly arranged, a gate dielectric layer wrapping around a channel region of each of the semiconductor nanosheets of the plurality of groups of semiconductor nanosheets, and a gate electrode layer formed on the gate dielectric layer over the plurality of groups of semiconductor nanosheets. The semiconductor nanosheets are made of an oxide semiconductor material. In one or more of the preceding and / or following embodiments, the oxide semiconductor material comprises amorphous indium gallium zinc oxide (IGZO).In one or more of the preceding and / or following embodiments, a thickness T1 of each of the semiconductor nanosheets is in a range from 5 nm to 30 nm and a width W1 of each of the semiconductor nanosheets along a gate extension direction is in a range from 10 nm to 50 nm. In one or more of the preceding and / or following embodiments, a number of the semiconductor nanosheets is in a range from 2 to 10. In one or more of the preceding and / or following embodiments, a number of the plurality of groups is in a range from 2 to 5.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a stacked structure comprising alternately stacked semiconductor layers (25) and sacrificial layers (20), wherein the sacrificial layers (20) comprise a metal nitride material; Forming a sacrificial gate structure (40) over the stack structure; Forming a dielectric layer (50) over the sacrificial gate structure (40); Removing the sacrificial gate structure (40) and thereby forming a gate space (52); Removing the sacrificial layers (20) in the gate space (52) and thereby releasing the semiconductor layers (25); and Forming a gate structure (80, 82) around channel regions of the semiconductor layers (25), Forming a contact opening (65) in the dielectric layer (50); Removing the sacrificial layers (20) in the contact opening (65) and thereby exposing source / drain regions of the semiconductor layers (25); and Forming a source / drain contact (70) around the source / drain regions of the semiconductor layers (25), wherein the semiconductor layers (25) are made of an oxide semiconductor material. [2] The method of claim 1, wherein the oxide semiconductor material comprises a material selected from a group consisting of indium gallium zinc oxide, indium gallium zinc oxide crystal with c-axis aligned, ZnO, In 2 O 3 , Ga 2 O 3 and ZnON. [3] The method of claim 1 or 2, wherein the oxide semiconductor material comprises amorphous indium gallium zinc oxide. [4] A method according to any one of the preceding claims, wherein the stack structure is formed over an insulating material layer (10). [5] The method of claim 4, wherein the insulating material layer (10) covers transistors formed over a semiconductor substrate (5). [6] A method according to any one of the preceding claims, wherein the stack structure is formed by: alternately forming the semiconductor layers (25) and the sacrificial layers (20) on an insulating material layer (10); and Structuring the semiconductor layers (25) and the sacrificial layers (20) into one or more fin structures (22). [7] A method of manufacturing a semiconductor device, comprising: Forming a fin structure (22) comprising alternately stacked semiconductor layers (25) and sacrificial layers (20) over a first dielectric layer (10), wherein the sacrificial layers (20) comprise a material selected from a group consisting of TiN and TaN; Forming a sacrificial gate structure (40) over the fin structure (22); Forming gate sidewall spacers (48) on opposite side surfaces of the sacrificial gate structure (40); Forming a second dielectric layer (50) over the sacrificial gate structure (40) and the fin structure (22); Removing the sacrificial gate structure (40) and thereby forming a gate space (52); Removing the sacrificial layers (20) in the gate space (52) and thereby exposing channel regions of the semiconductor layers (25); Forming a gate structure (80, 82) around the channel regions of the semiconductor layers (25); Forming a third dielectric layer (60); Forming a contact opening (65) in the third dielectric layer (60) and the second dielectric layer (50); Removing the sacrificial layers (20) in the contact opening (65) and thereby exposing source / drain regions of the semiconductor layers (25); and Forming a source / drain contact (70) around the source / drain regions of the semiconductor layers (25), wherein the semiconductor layers (25) are made of an oxide semiconductor material. [8] The method of claim 7, wherein the oxide semiconductor material comprises a material selected from a group consisting of indium gallium zinc oxide, indium gallium zinc oxide crystal with c-axis aligned, ZnO, In 2 O 3 , Ga 2 O 3 and ZnON. [9] The method of claim 7, wherein the oxide semiconductor material comprises amorphous indium gallium zinc oxide. [10] A method according to any one of claims 7 to 9, wherein the first dielectric layer (10) covers transistors formed over a semiconductor substrate (5). [11] A method according to any one of claims 7 to 10, wherein: when removing the sacrificial layers (20) in the contact opening (65) parts of the sacrificial layers (20) remain, and after the source / drain contact (70) is formed, the remaining parts of the sacrificial layers (20) are arranged between the source / drain contact (70) and the gate structure (80, 82). [12] A semiconductor device comprising a power supply switch circuit and a logic circuit, wherein the power supply switch circuit comprises: a first dielectric layer (10); a thin film transistor formed on the first dielectric layer (10), the thin film transistor comprising: a fin structure (22) with vertically arranged semiconductor nanosheets (25); a gate dielectric layer (82) around a channel region of each of the semiconductor nanosheets (25); a gate electrode layer (80) formed on the gate dielectric layer (82), a second dielectric layer (50) formed on the fin structure (22), a source / drain contact (70) formed in a contact opening (65) of the second dielectric layer (50) and enclosing source / drain regions of the semiconductor nanosheets (25), and inner spacers (21) arranged between the gate electrode layer (80) and the source / drain contact (70) and being remaining portions of sacrificial layers (20), sacrificial layers (20) and remaining portions of sacrificial layers (20), wherein the sacrificial layers (20) comprise a metal nitride material, wherein the semiconductor nanosheets (25) are made of an oxide semiconductor material. [13] The semiconductor device according to claim 12, wherein the oxide semiconductor material comprises a material selected from a group consisting of indium gallium zinc oxide, indium gallium zinc oxide crystal with c-axis aligned, ZnO, In 2 O 3 , Ga 2 O 3 and ZnON. [14] The semiconductor device of claim 12, wherein the oxide semiconductor material comprises amorphous indium gallium zinc oxide. [15] A semiconductor device according to any one of claims 12 to 14, wherein: a thickness T1 of each of the semiconductor nanosheets (25) is in a range of 5 nm to 30 nm, and a width W1 of each of the semiconductor nanosheets (25) along a gate extension direction is in a range of 10 nm to 50 nm. [16] The semiconductor device according to claim 15, wherein a ratio W1 / T1 is in a range of 2 to 5.

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