Devices and methods for setting and clamping a node voltage

Abstract

Node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) with a controllable voltage operating range and a set voltage, the node control circuit comprising: a setting circuit (1) electrically connected to a node and configured to control a voltage of the node within a voltage range, wherein the setting circuit (1) is configured to set the voltage of the node based on a setting signal; and at least one clamping circuit (2) configured to control the voltage range, wherein the at least one clamping circuit comprises a follower transistor clamp (53, 54, 163, 164, 173, 174) configured to receive a clamping control signal operable to adjust a voltage limit at which the follower transistor clamp activates to clamp the voltage of the node; wherein the follower transistor clamp (53, 54, 163, 164, 173, 174) comprises at least one of a pair of cross-connected source-follower transistors (21, 22, 23, 24) or a pair of cross-connected emitter-follower transistors (181, 182, 183, 184).

Description

FIELD OF DISCLOSUREEmbodiments of the invention relate to electronic systems and, more particularly, to electronic circuits for controlling a voltage of a node.GENERAL STATE OF THE ARTCertain electronic devices use amplifiers to drive a load. For example, an amplifier may drive the load with a controlled voltage and / or a controlled current. Examples of amplifiers include, but are not limited to, operational amplifiers, transimpedance amplifiers, and transconductance amplifiers. Certain amplifiers are implemented in a multistage configuration to increase their gain and / or performance.WO 2018 / 106 600 A1 discloses a voltage clamp circuit.DE 10 2011 013 105 A1 relates to an electronic device, electronic device, including a first limiter including a first transistor configured to be coupled to a first side of a channel with a first output node of a non-ideal voltage source having an internal impedance greater than zero to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor to supply a current to the capacitor from the first output node if the voltage level at the output node reaches or exceeds an upper limit value.SUMMARY OF THE DISCLOSUREIn view of the foregoing, an object of aspects of the present invention may be to provide further improved apparatus and methods for clamping (English) a node voltage.The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims.In one aspect of the invention, a node control circuit having a controllable voltage operating range and a set voltage is provided. The node control circuit includes a setting circuit electrically connected to a node and operable to control a voltage of the node within a voltage range. The setting circuit is configured to set the voltage of the node on the basis of a setting signal. The node control circuit further comprises at least one clamping circuit configured to control the voltage range. The at least one clamping circuit includes a follower transistor clamp configured to receive a clamping control signal operable to adjust a voltage limit at which the follower transistor clamp activates to clamp the voltage of the node; wherein the follower transistor clamp includes at least one of a pair of cross-connected source follower transistors or a pair of cross-connected emitter follower transistors.In another aspect of the invention, an electronics module is provided. The electronics module has a module substrate and an amplifier die fastened to the module substrate. The amplifier die includes a sensing circuit coupled to a load pin, a driving circuit configured to control the load pin by the sensing circuit and controlled by a voltage of a node, and a node control circuit including a setting circuit and at least one clamping circuit. The setting circuit is configured to control the voltage of the node within a voltage range based on a setting signal. The at least one clamping circuit is configured to control the voltage range. The at least one clamping circuit includes a follower transistor clamp configured to receive a clamping control signal operable to adjust a voltage limit at which the follower transistor clamp activates to clamp the voltage of the node; wherein the follower transistor clamp includes at least one of a pair of cross-connected source follower transistors or a pair of cross-connected emitter follower transistors.In another aspect of the invention, a method of controlling a voltage operating range and a set voltage of a node is provided. The method includes: receiving a set signal indicative of a target operating voltage of a node; setting a voltage of the node within a voltage range based on the set signal using a set circuit; and controlling the voltage range of the node using at least one clamping circuit, including adjusting a voltage limit provided by a follower transistor clamp based on a clamping control signal and activating the follower transistor clamp to clamp the voltage of the node in response to the voltage of the node reaching the voltage limit; wherein the follower transistor clamp includes at least one of a pair of cross-connected source follower transistors or a pair of cross-connected emitter follower transistors.Apparatuses and methods for setting and clamping ("clamping") a node voltage are provided herein. In certain embodiments, a node control circuit controls a voltage of a node based on a set signal indicative of a target voltage of the node, an upper clamp control signal for controlling an upper voltage limit of the node, and a lower clamp control signal for controlling a lower voltage limit of the node. Thus, the upper and lower clamp control signals define a voltage range over which the node can operate without clamping, and the set signal controls the voltage at the node to a particular voltage level within the voltage range. When used in an impedance measurement application, the set signal controls a current or voltage applied to a device under test (DUT) to a target level for measurement, and the upper and lower clamp control signals protect the DUT from unintentional damage resulting from excessive bias conditions.Apparatus and methods for setting and clamping a node voltage are provided herein. In certain embodiments, a node control circuit includes a setting circuit for setting a voltage of a node based on a setting signal. For example, the voltage of the node may be set by the set signal to control driving of a device under test (DUT) or other load. The node control circuit further includes at least one of a p-type follower terminal for clamping the node to an upper voltage limit based on an upper clamping control signal and an n-type follower terminal for clamping the node to a lower voltage limit based on a lower clamping control signal. When both terminals are present, the node operates at a voltage level set by the set signal, but saturates at the upper voltage limit set by the upper clamping control signal and at the lower voltage limit set by the lower clamping control signal.In certain implementations, the set circuit is implemented such that the voltage of the node is linearly changed with the set signal. The setting circuit may include, for example, a current source that supplies a current to a resistor to thereby set the node voltage. In such implementations, the current source and / or the resistor may be controlled by the set signal to provide flexibility in setting the node to a target voltage.The upper clamp control signal and the lower clamp control signal control a voltage range over which the node can operate without clamps. However, when the node reaches the upper voltage limit set by the upper clamp control signal, the p-type follower clamp activates to clamp the node voltage to the upper voltage limit. In addition, when the node voltage reaches the lower voltage limit set by the lower clamp control signal, the n-type follower clamp activates to clamp the node voltage to the lower voltage limit.The p-type follower terminal includes one or more p-type transistors arranged as a follower. For example, the p-type follower terminal may include at least one p-type field effect transistor (PFET) arranged as a source follower and / or at least one PNP bipolar transistor arranged as an emitter follower. In addition, the n-type follower terminal includes one or more n-type transistors arranged as a follower. For example, the n-type follower terminal may include at least one n-type field effect transistor (NFET) arranged as a source follower and / or at least one NPN bipolar transistor arranged as an emitter follower.In certain implementations, the p-type follower terminal and / or the n-type follower terminal include one or more double diffused metal oxide semiconductor (DMOS) transistors arranged as source followers. Using p-type and n-type DMOS transistors to implement source-follower terminals allows the node to operate over a wide voltage range and / or allows the use of high voltage power supplies without the risk of transistor damage.In certain implementations, the p-type follower terminals include a pair of cross-connected p-type followers and / or the n-type follower terminal includes a pair of cross-connected n-type followers. Implementing the p-type follower terminal and / or the n-type follower terminal with cross-connected follower transistors provides increased robustness against overvoltage. For example, in the context of metal oxide semiconductor (MOS) transistors, cross-switching a pair of MOS transistor followers may limit gate-source voltages, thereby protecting the transistors from gate oxide breakdown.To provide increased control of the lower voltage limit and / or the upper voltage limit, the p-type follower terminal and / or the n-type follower terminal may be implemented with an error amplifier to drive the input to a follower transistor. Incorporating error amplifiers can provide precise control over the lower voltage limit and the upper voltage limit.For example, in the context of a conversion using MOS transistors, including the error amplifiers compensates the lower voltage limit and the upper voltage limit for an offset corresponding to the threshold voltage of the MOS transistors. Also, in the context of a conversion using bipolar transistors, including the error amplifiers compensates for the lower voltage limit and the upper voltage limit for an offset resulting from the base-emitter voltage (V BE) of the bipolar transistors.In certain implementations, the node voltage controls an input to a drive circuit, which in turn drives a load. For example, the node voltage may control a non-inverting input of an amplifier connected to negative feedback, such as a unity gain buffer. Thus, the node voltage may be used to control the bias voltage of the load, such as a DUT.In certain implementations, the node control circuit is connected using one or more feedback loops to provide control over the node voltage. For example, the node voltage may control biasing of a load, and feedback at the setting circuit and / or the follower terminals may be controlled based on the current and / or voltage of the load. In a first example, feedback is provided to the set circuit based on the current supplied to the load and feedback is provided to the follower terminals based on the voltage across the load. In a second example, feedback is provided to the set circuit based on the voltage across the load and feedback to the follower terminals is provided based on the current supplied to the load.When operating using feedback, the bandwidths of control loops used for the set circuit, the p-type follower terminal and / or the n-type follower terminal may be controlled separately. Independent control of loop bandwidth may provide flexibility in a wide range of applications including load control applications, among others.In certain implementations, the node control circuit is controlled by data received from an interface or bus, such as an I 2 C (Inter-Integrated Circuit) bus, a GPIO (General Purpose Input Output) bus, and / or another suitable interface. For example, the data may serve to control at least one of the set signal, the upper clamp control signal and / or the lower clamp control signal. In certain implementations, the node control circuit is fabricated on a semiconductor die or chip, and a user may digitally program set points of the set signal, the upper clamp control signal, and / or the lower clamp control signal using the bus. Implementing the node control circuit in this manner provides a convenient and flexible mechanism for user configurability.Apparatus and methods for setting and clamping a node voltage are provided herein. In certain embodiments, a node control circuit may include a setting circuit for setting a voltage of a node based on a setting signal. The node control circuit may further include at least one of a p-type follower terminal for clamping the node to an upper voltage limit based on an upper clamping control signal, or an n-type follower terminal for clamping the node to a lower voltage limit based on a lower clamping control signal. When both terminals are included, the node may operate with a voltage level set by the set signal, but may saturate at the upper voltage limit set by the upper clamping control signal and at the lower voltage limit set by the lower clamping control signal.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a schematic diagram of a node control circuit according to an embodiment. FIG. 1B is a schematic diagram of a node control circuit according to another embodiment. FIG. 2A is a schematic diagram of a node control circuit according to another embodiment. FIG. 2B is a schematic diagram of a node control circuit according to another embodiment. FIG. 3A is a schematic diagram of a node control circuit according to another embodiment. FIG. 3B is a schematic diagram of a node control circuit according to another embodiment. FIG. 4A is a schematic diagram illustrating a first example operating scenario of the node control circuit of FIG. 3B. FIG. 4B is a schematic diagram illustrating a second example operating scenario of the node control circuit of FIG. 3B. FIG. 4C is a schematic diagram illustrating a third example operating scenario of the node control circuit of FIG. 3B. FIG. 5 is a schematic diagram of a node control circuit according to another embodiment. FIG. 6 is a schematic diagram of a node control circuit according to another embodiment. FIG. 7A is a schematic diagram of an embodiment of a feedback-switched node control system. FIG. 7B is a schematic diagram of another embodiment of a feedback-switched node control system. FIG. 8A is a schematic diagram of another embodiment of a feedback-switched node control system. FIG. 8B is a diagram of an example of simulation results for the node control system of FIG. 8A. FIG. 9 is a schematic diagram of a module according to an embodiment.DETAILED DESCRIPTION OF EMBODIMENTSThe following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be embodied in a variety of different ways. In this specification, reference is made to the drawings, wherein like reference numerals may indicate identical or functionally similar elements. It is understood that elements shown in the figures are not necessarily drawn to scale. In addition, it should be appreciated that certain embodiments may include more elements than shown in a drawing and / or a subset of the elements shown in a drawing. In addition, some embodiments may include any suitable combination of features of two or more drawings.FIG. 1A is a schematic diagram of a node control circuit 10 according to an embodiment. The node control circuit 10 includes a setting circuit 1 and a follower terminal 2. As shown in FIG. 1A, the set circuit 1 and the follower terminal 2 are each electrically connected to a circuit node (NODE). Although an embodiment of the node control circuit is shown in FIG. 1A, the teachings herein are applicable to node control circuits implemented in a wide variety of ways.As shown in FIG. 1A, the setting circuit 1 receives a set signal (SET), and the follower terminal 2 receives a clamp control signal (LIMIT). The set signal operates to set a voltage level of the node, while the clamp control signal operates to control an upper or lower limit for the voltage range over which the node can operate.In certain implementations, follower terminal 2 is a p-type follower terminal, and the clamping control signal is used to control an upper limit of the voltage range of the node. For example, if the voltage level of the node is greater than or equal to the upper limit, the follower terminal 2 turns on to provide clamping and remains turned off otherwise. In other implementations, the follower terminal 2 is an n-type follower terminal, and the clamping control signal is used to control a lower limit of the voltage range of the node. For example, if the voltage level of the node is less than or equal to the lower limit, the follower terminal 2 turns on to provide clamping and remains turned off otherwise. Follower clamp 2 may be implemented according to any of the embodiments herein.In some implementations, the set signal controls the voltage level of the node to change substantially linearly with respect to the set signal. For example, the setting circuit 1 may include a current source that supplies a current to a resistor to thereby set the node voltage. In such implementations, the current source and / or resistor may be controllable by the set signal to provide flexibility when setting the node to a target voltage.Although an example implementation of the setting circuit has been described, the setting circuit 1 can be implemented in a wide variety of ways. In another example, the setting circuit 1 is implemented as a digital-to-analog converter (DAC).FIG. 1B is a schematic diagram of a node control circuit 20 according to another embodiment. The node control circuit 20 includes a setting circuit 1, a p-type follower terminal 3 and an n-type follower terminal 4. As shown in FIG. 1B, the set circuit 1, the p-type follower terminal 3, and the n-type follower terminal 4 are each electrically connected to a node (NODE). Although another embodiment of a node control circuit is shown in FIG. 1B, the teachings herein are applicable to node control circuits implemented in a wide variety of ways.As shown in FIG. 1B, the setting circuit 1 receives a set signal (SET). In addition, the p-type follower terminal 3 receives an upper clamping control signal (LIMIT UPPER), and the n-type follower terminal 4 receives a lower clamping control signal (LIMIT LOWER).The p-type follower terminal 3 comprises one or more p-type followers, such as at least one PFET source follower and / or at least one PNP emitter follower, operable to clamp the node to an upper limit controlled by the upper clamp control signal. The p-type follower terminal 3 is inactive when the voltage of the node is below the upper limit, and activated to clamp the node when the voltage of the node is equal to or higher than the upper limit. Thus, the upper clamp control signal controls an adjustable upper limit at which the p-type follower clamp 3 clamps the node.The n-type follower terminal 4 comprises one or more n-type followers, such as at least one NFET source follower and / or at least one NPN emitter follower, operable to clamp the node to a lower limit controlled by the lower clamping control signal. The n-type follower terminal 4 is inactive when the node voltage is above the lower limit, and activated to clamp the node when the node voltage is less than or equal to the lower limit. Thus, the lower clamp control signal controls an adjustable lower limit at which the n-type follower clamp 4 clamps the node.In the illustrated embodiment, the p-type follower terminal 3 is connected between the node and a first voltage (V 1) and the n-type follower terminal 4 is connected between the nodes and a second voltage (V 2). When the node control circuit 20 is energized, the second voltage is greater than the first voltage. The first voltage and the second voltage may be any suitable voltages. In one example, the first voltage is a low power supply or ground, and the second voltage is a high power supply. However, other implementations are possible.As shown in FIG. 1B, the setting circuit 1 receives the setting signal that controls the voltage level of the node. In certain implementations, the set signal controls the voltage level of the node to change substantially linearly with respect to the set signal. Thus, the set signal may be used to set the node voltage to a target voltage level within a voltage range between the lower limit controlled by the lower clamp control signal and the upper limit controlled by the upper clamp control signal.Although not shown in FIG. 1B, in certain implementations, a control circuit (e.g., control circuit 305 of FIG. 9 ) generates the set signal, the lower clamp control signal, and / or the upper clamp control signal. For example, the control circuit may control the set signal, the lower clamp control signal, and / or the upper clamp control signal based on data received via an interface and / or data stored in a memory.FIG. 2A is a schematic diagram of a node control circuit 30 according to another embodiment. The node control circuit 30 includes a setting circuit 1, a p-type follower terminal 13, and an n-type follower terminal 14.The node control circuit 30 of FIG. 2A is similar to the node control circuit 20 of FIG. 1B, except that the node control circuit 30 has a specific implementation of a p-type follower terminal and an n-type follower terminal.For example, the p-type follower terminal 13 of FIG. 2A includes a PFET source follower 21 having a gate receiving the upper clamping control signal (LIMIT UPPER) a drain electrically connected to a low power supply voltage (V SS) and a source electrically connected to a node (NODE). In addition, the n-type follower terminal 14 includes an NFET source follower 23 having a gate receiving the lower clamping control signal (LIMIT LOWER) a drain electrically connected to a high power supply voltage (V DD) and a source electrically connected to the node. In certain implementations, the PFET source follower 21 and / or the NFET source follower 23 are implemented as a MOS transistor, such as a DMOS transistor.Although an embodiment of a p-type follower terminal and an n-type follower terminal is shown in FIG. 2A, the teachings herein are applicable to follower terminals implemented in a wide variety of ways.FIG. 2B is a schematic diagram of a node control circuit 50 according to another embodiment. The node control circuit 50 includes a setting circuit 31, a p-type follower terminal 13, an n-type follower terminal 14, an upper limit control circuit 35, and a lower limit control circuit 36.The node control circuit 50 of FIG. 2B is similar to the node control circuit 30 of FIG. 2A, except that the node control circuit 50 illustrates an example of circuitry for setting the node voltage and controlling upper and lower voltage limits of the clamp.For example, the node control circuit 50 includes a setting circuit 31 including a setting current source 40 and a setting resistor 44. At least one of the set current source 40 or the set resistor 44 may be controlled to adjust the node voltage to a target voltage level.In the illustrated embodiment, the upper limit control circuit 35 includes an upper limit current source 41 and an upper limit resistor 45. At least one of the upper limit current source 41 or the upper limit resistor 45 may be controlled to adjust an upper clamping control voltage (V UPPER). In addition, the lower limit control circuit 36 includes a lower limit current source 42 and a lower limit resistor 46. At least one of the lower limit current source 42 or the lower limit resistor 46 may be controlled to adjust a lower terminal control voltage (V LOWER).Although FIG. 2B illustrates one embodiment of circuitry for setting the node voltage and controlling upper and lower voltage limits of the clamping, other implementations are possible.The node voltage may be actuatable over a voltage range extending from a lower voltage limit to an upper voltage limit. In this embodiment, the upper voltage limit of the voltage range is approximately V UPPER+ | V THP|, where V THP is the threshold voltage of the PFET source follower 21. The value of V UPPER is based on a product of a current of the upper limit current source 41 and a resistance value of the upper limit resistor 45, and thus can be set by controlling the upper limit current source 41 and / or the upper limit resistor 45.With continued reference to FIG. 2B, the lower voltage limit is approximately V LOWER- | VTHN|, where VTHNcorresponds to the threshold voltage of the NFET source follower 23. The value of V LOWER is based on a product of a current of the lower limit current source 42 and a resistance value of the lower limit resistor 46, and thus can be set by controlling the lower limit current source 42 and / or the lower limit resistor 46.When the voltage of the node operates within the voltage range set by the upper voltage limit and the lower voltage limit, both the PFET source follower 21 and the NFET source follower 23 are turned off. Thus, the node voltage can be set to a target voltage within the voltage range by the setting circuit 31. However, when the node voltage reaches an upper limit of the voltage range, the PFET source follower 21 turns on to clamp the node voltage to about V UPPER+ | V THP|. In addition, when the voltage of the node reaches a lower limit of the voltage range, the NFET source follower 23 turns on to clamp the node voltage to about V LOWER- | VTHN|.In this example, the node voltage is set to a certain voltage level within the voltage range by controlling a resistance value of the set resistor 44 and / or a current of the set current source 40. Although one embodiment of a set circuit is shown, the teachings herein are applicable to set circuits implemented in a wide variety of ways.In certain embodiments, a control circuit (e.g., control circuit 305 of FIG. 9 ) controls set circuit 31, upper limit control circuit 35, and / or lower limit control circuit 36. Such a control circuit may set the voltage levels of the node voltage, the upper clamp control voltage, and / or the lower clamp control voltage based on data received via an interface or a bus.The node control circuit 50 of FIG. 2B may have a greatest operating voltage limited by a greatest nominal gate-source voltage of the PFET source follower 21 and / or the NFET source follower 23. Thus, in one example, the transistors have a 5V gate-source rating and a 30V gate-drain rating, V DD is 15V, V SS is -15V, V UPPER is 10V, V LOWER is -10V, and the voltage of the node is 0V. In this example, the PFET source follower 21 receives a -15V source-gate voltage and fails when the node voltage is -5V.In certain embodiments herein, a p-type follower terminal and / or an n-type follower terminal is implemented using a pair of cross-connected follower transistors. When a follower terminal is thus implemented, this provides protection for the transistors from overvoltage, thereby expanding a maximum operating voltage of the node control circuit. For example, in the context of MOS transistors, cross-switching a pair of MOS transistor followers may limit gate-source voltages, thereby protecting the transistors from gate oxide breakdown.FIG. 3A is a schematic diagram of a node control circuit 60 according to another embodiment. Node control circuit 60 includes a set circuit 1, a p-type follower terminal 53, and an n-type follower terminal 54. Node control circuit 60 of FIG. 3A is similar to node control circuit 30 of FIG. 2A, except that node control circuit 60 represents a implementation in which p-type follower terminal 53 and n-type follower terminal 54 have each been implemented with a pair of cross-connected source followers.For example, the p-type follower terminal 53 includes a first PFET source follower 21 and a second PFET source follower 22 that are cross-coupled. Specifically, a source of the first PFET source follower 21 is connected to a gate of the second PFET source follower 22, and a source of the second PFET source follower 22 is connected to a gate of the first PFET source follower 21. In addition, the n-type follower terminal 54 includes a first NFET source follower 23 and a second NFET source follower 24 that are cross-coupled.By cross-coupling a pair of follower transistors, extended protection from overvoltage is provided. For example, cross-switching a pair of MOS transistor followers can limit gate-source voltages, thereby protecting the transistors from gate oxide breakdown or damage.In certain implementations, the first PFET source follower 21 and the second PFET source follower 22 are implemented using p-type DMOS transistors and / or the first NFET source follower 23 and the second NFET source follower 24 are implemented using n-type DMOS transistors.FIG. 3B is a schematic diagram of a node control circuit 70 according to another embodiment. The node control circuit 70 of FIG. 3B is similar to the node control circuit 60 of FIG. 3A, except that the node control circuit 70 further includes the setting circuit 31, the upper limit control circuit 35, and the lower limit control circuit 36 described above with respect to FIG. 2B.Various operating scenarios of the node control circuit 70 of FIG. 3B are illustrated in FIGS. 4A-4C. For clarity of the figures, the upper limit control circuit 35 and the lower limit control circuit 36 of FIG. 3B are not shown in FIGS. 4A-4C. Also, in this example, the set current source 40 of FIG. 3B operates with a current I SET, and the set resistor 44 of FIG. 3B operates with a resistance R SET.FIG. 4A is a schematic diagram illustrating a first example working scenario 110 of the node control circuit 70 of FIG. 3B. The first example working scenario 110 corresponds to an example in which the node voltage (V NODE) is above the lower limit of clamping set by V LOWER and also below the upper limit of clamping set by V UPPER. In this example, V corresponds to NODE I SET* R SET.As shown in FIG. 4A, the first PFET source follower 21 and the first NFET source follower 23 are turned off in this working scenario. In addition, the second PFET source follower 22 is turned on to limit the gate-source voltage of the first PFET source follower 21. Further, the second NFET source follower 24 is turned on to limit the gate-source voltage of the first NFET source follower 23.FIG. 4B is a schematic diagram illustrating a second example working scenario 120 of the node control circuit 70 of FIG. 3B. The second example working scenario 120 corresponds to an example in which V NODE reaches the upper limit of clamping set by V UPPER. In this example, V NODE corresponds to V UPPER+ | corresponds to V THP|, where V THP is the threshold voltage of the first PFET source follower 21.As shown in FIG. 4B, the first PFET source follower 21 and the second NFET source follower 24 are turned on, while the second PFET source follower 22 and the first NFET source follower 23 are turned off.FIG. 4C is a schematic diagram illustrating a third example working scenario 130 of the node control circuit 70 of FIG. 3B. The third example working scenario 130 corresponds to an example in which V NODE reaches the lower limit of clamping set by V LOWER. In this example, V NODE V LOWER- | corresponds to VTHN|, where VTHNis the threshold voltage of the first NFET source follower 23.As shown in FIG. 4C, the first PFET source follower 21 and the second NFET source follower 24 are turned off, while the second PFET source follower 22 and the first NFET source follower 23 are turned on.In certain embodiments herein, an error amplifier is included in a p-type follower terminal and / or an n-type follower terminal to increase precision of an upper and / or lower limit of the clamping. For example, in the context of a conversion using MOS transistors, including the error amplifiers compensates the lower voltage limit and the upper voltage limit for an offset corresponding to the threshold voltage of the MOS transistors. Also, in the context of a conversion using bipolar transistors, including the error amplifiers compensates for the lower voltage limit and the upper voltage limit for an offset resulting from the base-emitter voltage of the bipolar transistors.FIG. 5 is a schematic diagram of a node control circuit 160 according to another embodiment. The node control circuit 160 includes a setting circuit 1, a p-type follower terminal 163, and an n-type follower terminal 164. Although another embodiment of a node control circuit is shown in FIG. 5, the teachings herein are applicable to node control circuits implemented in a wide variety of ways.The p-type follower terminal 163 of FIG. 5 is similar to the p-type follower terminal 53 of FIG. 3A, except that the p-type follower terminal 163 further includes a clamping PFET transistor 151 and a first error amplifier 153. In addition, n-type follower terminal 164 of FIG. 5 is similar to n-type follower terminal 54 of FIG. 3A, except that n-type follower terminal 164 includes a clamping NFET transistor 152 and a second error amplifier 154. In certain implementations, the first error amplifier 153 and the second error amplifier 154 are implemented as transconductance amplifiers.The first error amplifier 153 controls a gate voltage of the first PFET source follower 21 such that a voltage difference between the noninverting input and the inverting input of the first error amplifier 153 is approximately equal to 0 V. In addition, the second error amplifier 154 controls a gate voltage of the first NFET source follower 23 such that a voltage difference between the noninverting input and inverting input of the second error amplifier 154 is approximately equal to 0 V.The feedback provided by the first error amplifier 153 and the second error amplifier 154 compensates for the threshold voltages of the PFET source follower 21 and the NFET source follower 23, respectively. In contrast, the node control circuit 70 of FIG. 3B provided an upper voltage limit of about V UPPER+ | V THP| and a lower voltage limit of about V LOWER- IVTHN|.By incorporating the error amplifiers, the upper and lower voltage limits are compensated for an offset corresponding to the threshold voltage. In certain applications, threshold voltage offset is undesirable because such offset may result in uncertainty in the available operating voltage range of the node. For example, the threshold voltage of a transistor may vary with temperature, process, and / or aging.The p-type follower terminal 163 of FIG. 5 also includes the terminal PFET 151 that operates to clamp the differential input to the first error amplifier 153 to a voltage difference of about |V THP|. In addition, the n-type follower terminal 164 of FIG. 5 also includes the terminal NFET 152 that operates to clamp the differential input to the second error amplifier 154 to a voltage difference of about |VTH|. Incorporating the clamp PFET 151 and the clamp NFET 152 provides a number of advantages including, but not limited to, protecting an input differential transistor pair of each error amplifier from overvoltage.Although FIGS. 2A-5 have been illustrated in the context of FETs, any of the follower terminals may be implemented herein using bipolar transistors or a combination of FETs and bipolar transistors. Moreover, while certain embodiments are illustrated herein as having both a p-type follower terminal and an n-type follower terminal, each of the embodiments disclosed herein may be modified to have the p-type follower terminal but not the n-type follower terminal or to have the n-type follower terminal but not the p-type follower terminal.FIG. 6 is a schematic diagram of a node control circuit 200 according to another embodiment. The node control circuit 200 includes a setting circuit 1, a p-type follower circuit 173, and an n-type follower circuit 174. The node control circuit 200 of FIG. 6 is similar to the node control circuit 160 of FIG. 5, except that the node control circuit 200 is implemented using bipolar transistors instead of FETs.For example, the p-type follower circuit 173 includes a first PNP emitter follower 181 and a second PNP emitter follower 182 that are cross-connected. In addition, the p-type follower circuit 173 includes a first error amplifier 153 and a terminal PNP transistor 191. The n-type follower circuit 174 further includes a first NPN emitter follower 183 and a second NPN emitter follower 184 which are cross-connected. In addition, n-type follower circuit 174 includes a second error amplifier 154 and a clamp NPN transistor 192.With continued reference to FIG. 6, the first error amplifier 153 operates to compensate for an upper limit provided by the p-type follower circuit 173 for the V BE of the first PNP emitter follower 181. In addition, the second error amplifier 154 operates to compensate for a lower limit provided by the n-type follower circuit 174 for the V BE of the first NPN emitter follower 183. Further details of the node control circuit 200 of FIG. 6 are similar to those described above.FIG. 7A is a schematic diagram of an embodiment of a feedback-connected node control system 210. Although an embodiment of feedback loops for a node control circuit is shown, the teachings herein are applicable to a wide range of node control circuits operating in a closed loop manner. In addition, the node control circuits herein may also be operated with a control circuit without feedback.The node control system 210 of FIG. 7A includes a setting circuit 1, a p-type follower terminal 3, an n-type follower terminal 4, a driving circuit 201, a detection circuit 202, a first feedback amplifier 203, and a second feedback amplifier 204. The node control system 210 operates to drive a device under test (DUT) 208, which in certain implementations is a sensor.The setting circuit 1, the p-type follower terminal 3 and the n-type follower terminal 4 operate to control a driving voltage (V DRIVE) of a node. As shown in FIG. 7A, the setting circuit 1 receives a set signal (SET), the p-type follower terminal 3 receives an upper clamping control signal (LIMIT UPPER) and the n-type follower terminal 4 receives a lower clamping control signal (LIMIT LOWER). The set circuit 1, p-type follower terminal 3, and n-type follower terminal 4 may be implemented according to one of the embodiments herein.With continued reference to FIG. 7A, the drive circuit 201 has an input receiving the drive voltage and an output electrically connected to the DUT 208 through the sensing circuit 202. The DUT 208 operates with a current I DUT through the DUT 208 and a voltage V DUT across the DUT 208 in this embodiment. The sensing circuit 202 converts the current I DUT to a corresponding voltage at the sensing circuit 202.In the illustrated embodiment, the first feedback amplifier 203 amplifies the voltage at the detection circuit 202 to generate a set feedback signal (FBK SET) which provides feedback to the set circuit 1, thereby adjusting the voltage level of the drive voltage. When the feedback loop of the setting circuit 1 is implemented in this manner, it controls the drive voltage such that the current I DUT through the DUT 208 is of a certain controlled current level.With continued reference to FIG. 7A, the second feedback amplifier 204 amplifies a voltage V DUT at the DUT 208 to generate an upper clamp feedback signal (FBK UPPER) for the p-type follower clamp 3 and a lower clamp feedback signal (FBK LOWER) for the n-type follower clamp 4.Providing feedback to the p-type follower terminal 3 and the n-type follower terminal 4 in this manner protects the DUT 208 from excessively large overvoltage or under-voltage condition damage.For example, certain types of DUTs (e.g., certain types of sensors) may have a limitation on a maximum working bias with which the DUT may operate without damage. Although in certain applications it may be desirable to provide feedback to the setting circuit 1 to achieve a particular current I DUT through the DUT 208 for measurement purposes (e.g., a sensor impedance measurement), forcing a current of a particular value through the DUT 208 may result in the DUT 208 being biased with a large voltage.The feedback to the p-type follower terminal 3 and the n-type follower terminal 4 provides dynamic adjustment at the upper and lower limits of the voltage range of the drive voltage, thereby protecting the DUT 208 from damage.In the illustrated embodiment, the bandwidths of the control loops of the setting circuit 1, the p-type follower terminal 3 and / or the n-type follower terminal 4 can be set separately. Independent control of the loop bandwidth may provide increased flexibility for providing measurement of DUTs with a wide range of impedance values.Although one embodiment is shown with both the p-type follower terminal 3 and the n-type follower terminal 4, in certain implementations, one of the p-type follower terminal 3 or the n-type follower terminal 4 is omitted.FIG. 7B is a schematic diagram of another embodiment of a feedback-connected node control system 220.The node control system 220 of FIG. 7B is similar to the node system 210 of FIG. 7A, except that the node control system 220 of FIG. 7B uses the first feedback amplifier 203 to generate the set feedback signal (FBK SET) based on amplifying the voltage V DUT at the DUT 208. In addition, the node control system 220 of FIG. 7B uses the second feedback amplifier 204 to generate the upper clamp feedback signal (FBK UPPER) and the lower clamp feedback signal (FBK LOWER) based on amplifying the voltage difference at the sensing circuit 202.By implementing the node control system 220 in this manner, the first feedback amplifier 203 provides feedback to the setting circuit 1 to achieve a certain voltage V DUT at the DUT 208.Although in certain applications it may be desirable to provide feedback to the setting circuit 1 to achieve a particular voltage V DUT across the DUT 208 for purposes of measurement (e.g., sensor impedance measurement), forcing a voltage having a particular value across the DUT 208 may cause the DUT 208 to sink or generate a large current.The feedback to the p-type follower terminal 3 and to the n-type follower terminal 4 from the second feedback amplifier 204 provides dynamic adjustment at the upper and lower limits of the voltage range of the drive voltage, thereby protecting the DUT 208 from damage to excessive current.FIG. 8A is a schematic diagram of another embodiment of a feedback connected node control system 230. The node control system 230 includes a setting circuit 221, a p-type follower terminal 53, an n-type follower terminal 54, a unit gain buffer 211, a sense resistor 212, a first feedback instrumentation amplifier 213, a second feedback instrumentation amplifier 214, a lower limit current source 215, a lower limit capacitor 217, an upper limit current source 216, and an upper limit capacitor 218. The node control system 210 operates to drive a DUT 208.In the illustrated embodiment, node control system 230 includes p-type follower terminal 53 and n-type follower terminal 54 of the embodiment of FIG. 3B. However, the node control system 230 may be modified to operate with any of the p-type follower terminals and / or n-type follower terminals described herein.As shown in FIG. 8A, the n-type follower terminal 54 receives a lower clamping control voltage (V LOWER), and the p-type follower terminal 53 receives an upper clamping control voltage (V UPPER). In certain implementations, at least one of the lower limit current source 215 or the lower limit capacitor 217 is controllable to adjust the lower clamping control voltage and / or at least one of the upper limit current source 216 or the upper limit capacitor 218 is controllable to adjust the upper clamping control voltage. For example, a control circuit (such as control circuit 305 of FIG. 9 ) may provide such adjustment or control to the illustrated components.With continued reference to FIG. 8A, the setting circuit 221 includes a setting current source 223 and a setting capacitor 224 operable to control the drive voltage (V DRIVE). In certain implementations, at least one of the set current source 223 or the set capacitor 224 is controllable to adjust the drive voltage. For example, a control circuit (such as control circuit 305 of FIG. 9 ) may provide such control to set circuit 221.In the illustrated embodiment, the unit gain buffer 211 has a non-inverting input that receives the drive voltage. The unity gain buffer 211 also has an output connected to an inverting input to provide negative feedback. In this example, the output of the unit gain buffer 211 is connected to the DUT 208 through the sense resistor 212 having a resistance value R SENSE. Although an example is shown with a DUT 208 driven by the unit gain buffer 211 through the sense resistor 212, other implementations are possible, including, but not limited to, implementations using a resistive transimpedance amplifier and / or a capacitive transimpedance amplifier.With continued reference to FIG. 8A, the first feedback instrumentation amplifier 213 amplifies a voltage across the sense resistor 212 to generate a set feedback current (I SETFB) that is provided to the set circuit 221. In addition, the second feedback instrumentation amplifier 214 amplifies a voltage V DUT at the DUT 208 to generate an upper clamp feedback current (I UPPERFB), to adjust the upper clamp control voltage (V UPPER) and a lower clamp feedback current (I LOWERFB) to adjust the lower clamp control voltage (V LOWER).In the illustrated embodiment, the first feedback instrumentation amplifier 213 provides feedback to the set circuit 221 to thereby control the current I DUT to a set point, while the second feedback instrumentation amplifier 214 provides feedback to the p-type follower terminal 53 and the n-type follower terminal 54 to limit the voltage range of the drive voltage, to thereby protect the DUT 208 from excessive voltage.Thus, the feedback used in the node control system 230 of FIG. 8A is similar to that of the node control system 210 of FIG. 7A. In another embodiment, the feedback provided by the first feedback instrumentation amplifier 213 and the second feedback instrumentation amplifier 214 is reversed such that the feedback is similar to that of the node control system 220 of FIG. 7B. For example, the first instrumentation amplifier 213 may be implemented to amplify the voltage V DUT across the DUT 208 instead of the voltage across the sense resistor 212, while the second instrumentation amplifier 214 may be implemented to amplify the voltage across the sense resistor 212 instead of the voltage V DUT across the DUT 208.FIG. 8B is a graphical representation of an example of simulation results for the node control system 230 of FIG. 8A.The graph has an upper portion with a curve 261 of scaled current of the set current source 223 versus time and a curve 262 of voltage V DUT across the DUT 208 versus time. As shown in the upper portion of the graph, the voltage V DUT on the DUT 208 is clamped to about + / - 9V in this example.With continued reference to FIG. 8B, the graph further includes a bottom portion having a scaled current curve 263 of the set current source 223 versus time and a current I DUT curve 264 of the DUT 208 versus time. As shown in the bottom portion of the graph, current I DUT through DUT 208 is clamped to about + / - 9 mA in this example.Although various examples of performance results have been shown, simulation or measurement results may vary based on a wide variety of factors, such as simulation models, simulation tools, simulation parameters, measurement conditions, fabrication technology, and / or implementation details. Accordingly, other results are possible.FIG. 9 is a schematic diagram of a module 310, according to an embodiment. The module 310 includes a semiconductor chip 304 attached to a module substrate 301. A chip is also referred to herein as a semiconductor die or an integrated circuit (IC). Although schematically depicted, module 310 may also include adhesive, solder, packaging, surface mount components, additional pins or pads, additional dies, and / or a wide variety of other structures, which have been omitted for clarity of the figure.Module 310 illustrates an example of an electronics module implemented in accordance with the teachings herein. In the illustrated embodiment, the semiconductor chip 304 includes a setting circuit 1, a p-type follower terminal 3, an n-type follower terminal 4, a driving circuit 201, a sensing circuit 202, a first feedback amplifier 203, a second feedback amplifier 204, and a control circuit 305 fabricated thereon. Although a particular circuitry is shown, other implementations are possible, such as implementations where one or more of the illustrated circuitry is omitted and / or where additional circuitry is included.The semiconductor die 304 may be implemented according to any of the embodiments herein. For example, the p-type follower circuit 3 and / or the n-type follower circuit 4 may be implemented according to one of the terminals of FIGS. 2A-6. Likewise, setting circuitry, feedback circuitry, drive circuitry, and / or other aspects of the semiconductor chip 304 according to any of the embodiments herein may be implemented.In the illustrated embodiment, module 310 includes an interface or bus (BUS) coupled to control circuit 305 by pins of semiconductor die 304. The bus can be used to program digital data onto the semiconductor die 304 to achieve a desired configuration of the module 310 for a given sensor 302. In the illustrated embodiment, the bus may be used to control one or more of the set signal (SET) supplied to the set circuit 1, the upper clamp control signal (LIMIT UPPER), supplied to the p-type follower terminal 3, or the lower clamp control signal (LIMIT LOWER), supplied to the n-type follower terminal 4.The control circuit 305 of FIG. 9 includes a memory circuit 306 that includes digital data indicative of a particular configuration of the semiconductor chip 304. Also, the memory circuit 306 receives digital data from the bus.In certain implementations, the memory circuit 306 includes volatile memory that is programmed with the desired configuration of the semiconductor die 304 using the post-power-on bus. For example, a user of module 310 may program memory circuit 306 with data indicating the desired configuration of semiconductor chip 304. However, other configurations are possible, such as implementations where the memory circuit 306 includes non-volatile memory (such as flash memory, read only memory (ROM), fuses, anti-fuses, and / or a magnetic storage device) programmed with the configuration data. In such implementations, after manufacture, the memory circuit 306 may be programmed with data associated with a particular target application or DUT.As shown in FIG. 9, the load pin (LOAD) of module 310 couples to a first terminal of sensor 302 and a load pin of semiconductor die 304. In this example, the feedback input pin (FB IN) of module 310 also couples to the first terminal of sensor 302 and to a feedback input pin of semiconductor die 304. However, other implementations are possible, such as implementations using other configurations of feedback. Including a load pin and a separate feedback input pin increases the flexibility of the module 310. In this example, module 310 also includes a ground pin (GND) coupled to a second terminal of sensor 302 and to a ground pin of semiconductor die 304. Thus, in this embodiment, a voltage at the sensor 302 is provided to the second feedback amplifier 204.In the illustrated embodiment, the semiconductor die 304 is implemented with feedback loops according to the node control system 210 of FIG. 7A. However, other implementations are possible. For example, in another embodiment, a semiconductor die with feedback loops is implemented in accordance with the node control system 220 of FIG. 7B.The module 310 of FIG. 9 is suitable for use in a wide range of applications. For example, module 310 may operate in combination with a wide variety of types of sensors, including sensors with varying impedances and / or desired bias conditions. Although an example of a module is shown, the teachings herein apply to a wide variety of types of electronics systems and modules. Accordingly, other implementations are possible.Conclusion: ConclusionThe above description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature and is not necessarily mechanically connected. Likewise, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature and is not necessarily mechanically coupled. Thus, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the illustrated circuits is not compromised).While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel devices, methods, and systems described herein may be embodied in a variety of other forms; further, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with other components and / or circuit topologies, and some elements may be deleted, moved, added, divided, combined, and / or modified. Each of these elements may be implemented in a variety of ways. Any suitable combination of the elements and acts of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.Although the claims presented herein are in a single dependency format for submission to the USPTO, it should be understood that each claim may depend on any preceding claim of the same type, except where clearly not technically feasible.

Claims

A node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) having a controllable voltage operating range and a set voltage, the node control circuit comprising: a set circuit (1) electrically connected to a node and configured to control a voltage of the node within a voltage range, the set circuit (1) configured to set the voltage of the node based on a set signal; and at least one clamp circuit (2) configured to control the voltage range, the at least one clamp circuit comprising a follower transistor clamp (53, 54, 163, 164, 173, 174) configured to receive a clamp control signal operable to adjust a voltage limit at which the follower transistor clamp activates to clamp the voltage of the node; wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises at least one of a pair of cross-connected source follower transistors (21, 22, 23, 24) or a pair of cross-connected emitter follower transistors (181, 182, 183, 184).The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of claim 1, further comprising a sensing circuit (202) and a driving circuit (201) configured to drive a device under test (DUT) (208) by the sensing circuit (202), wherein the driving circuit (201) is controlled by the voltage of the node.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of claim 2, further comprising a first feedback amplifier (203) configured to provide feedback to the set circuit (1) based on one of a voltage at the sense circuit (202) and a voltage at the DUT (208), and a second feedback amplifier (204) configured to provide feedback to the follower transistor terminal (53, 54, 163, 164, 173, 174) based on the other of the voltage at the sense circuit (202) and the voltage at the DUT (208).The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, wherein the node control circuit is further configured to change the voltage of the node substantially linearly with the set signal.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) is a p-type follower terminal configured to receive an upper clamping control signal operable to adjust an upper voltage limit at which the p-type follower terminal activates to clamp the voltage of the node, wherein the at least one clamping circuit (2) further comprises an n-type follower terminal configured to receive a lower clamping control signal operable to adjust a lower voltage limit at which the n-type follower terminal activates to clamp the voltage of the node.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, further comprising a control circuit (305) configured to receive digital data via an interface and control the set signal and the clamp control signal based on the digital data.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, wherein the setting circuit (1) comprises a current source (40) and a resistor (44) in series, wherein at least one of a current of the current source or a resistance value of the resistor can be controlled.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises at least one of a source follower transistor or an emitter follower transistor.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of claim 8, wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises a double diffused metal oxide semiconductor (DMOS) transistor source follower.The node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) of any preceding claim, wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises a follower transistor having an output coupled to the node, the node control circuit further comprising an error amplifier (153, 154) operable to control an input to the follower transistor to compensate for the voltage limit for a transistor offset of the follower transistor.An electronic module (310) comprising: a module substrate (301); and an amplifier die attached to the module substrate (301), the amplifier die comprising: a sensing circuit (202) coupled to a load pin; a driving circuit (201) configured to drive the load pin by the sensing circuit (202), wherein the driving circuit (201) is controlled by a voltage of a node; a node control circuit (50, 60, 70, 110, 120, 130, 160, 200, 230) comprising a setting circuit (1) configured to control the voltage of the node within a voltage range based on a setting signal, and at least one clamping circuit (2) configured to control the voltage range, wherein the at least one clamping circuit comprises a follower transistor clamp (53, 54, 163, 164, 173, 174) configured to receive a clamping control signal operable to adjust a voltage limit at which the follower transistor clamp activates to clamp the voltage of the node; wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises at least one of a pair of cross-connected source follower transistors (21, 22, 23, 24) or a pair of cross-connected emitter follower transistors (181, 182, 183, 184).The electronics module (310) of claim 11, wherein the amplifier die further comprises a first feedback amplifier (203) configured to provide feedback to the set circuit (1) based on one of a voltage at the sense circuit (202) or a voltage at a load coupled to the load pin, and a second feedback amplifier (204) configured to provide feedback to the follower transistor terminal (53, 54, 163, 164, 173, 174) based on the other of the voltage at the sense circuit (202) or the voltage at the load.The electronic module (310) of claim 11 or 12, wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) is a p-type follower terminal configured to receive an upper clamping control signal operable to adjust an upper voltage limit at which the p-type follower terminal activates to clamp the voltage of the node, wherein the at least one clamping circuit (2) further comprises an n-type follower terminal configured to receive a lower clamping control signal operable to adjust a lower voltage limit at which the n-type follower terminal activates to clamp the voltage of the node.The electronic module (310) of any of claims 11 to 13, wherein the amplifier die further comprises an interface and a control circuit (305) configured to receive digital data via the interface, wherein the control circuit is further configured to control the set signal and the clamp control signal based on the digital data.A method of controlling a voltage operating range and a set voltage of a node, the method comprising: receiving a set signal indicative of a target operating voltage of a node; setting a voltage of the node within a voltage range based on the set signal using a set circuit (1); and controlling the voltage range of the node using at least one clamping circuit (2) comprising adjusting a voltage limit provided by a follower transistor clamp (53, 54, 163, 164, 173, 174) based on a clamping control signal and activating the follower transistor clamp to clamp the voltage of the node in response to the voltage of the node reaching the voltage limit; wherein the follower transistor terminal (53, 54, 163, 164, 173, 174) comprises at least one of a pair of cross-connected source follower transistors (21, 22, 23, 24) or a pair of cross-connected emitter follower transistors (181, 182, 183, 184).The method of claim 15, further comprising driving a device under test (208) using a driving circuit (201) and controlling the driving circuit (201) using the voltage of the node.The method of claim 15 or 16, wherein activating the follower transistor clamp (53, 54, 163, 164, 173, 174) further comprises clamping the voltage of the node using at least one of a pair of cross-connected source follower transistors (21, 22, 23, 24) or a pair of cross-connected emitter follower transistors (181, 182, 183, 184).The method of any of claims 15 to 17, wherein adjusting the voltage limit provided by the follower transistor clamp (53, 54, 163, 164, 173, 174) comprises adjusting an upper voltage limit at which a p-type follower clamp activates to clamp the voltage of the node based on an upper clamp control signal, the method further comprising adjusting a lower voltage limit at which an n-type follower clamp activates to clamp the voltage of the node based on a lower clamp control signal.

Images