Method for patterning a silicon oxide-silicon nitride-silicon oxide stack and structures produced by this method

Abstract

Microfabrication process with the following steps: Providing a structure (800) comprising a layer stack (30, 40, 50) containing, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40), and a second silicon oxide layer (50), and a conductive material part (20) below the layer stack (30, 40, 50) and above a substrate (10); Producing a patterned etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Producing a via cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top side of the conductive material part (20) by isotropic etching of parts of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) with an isotropic etching process in which an etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30), wherein: the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical vapor deposition at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) comprises a second silicon oxide material produced by decomposition of tetraethyl orthosilicate.

Description

background

[0001] The present invention is directed to microfabrication processes and, more particularly, to processes for patterning a silicon oxide-silicon nitride-silicon oxide stack and structures fabricated by this process.

[0002] Microscopic components are used in various applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. In many cases, these microscopic components can include optical components. These microscopic components are typically fabricated by sequentially depositing different layers of material over a substrate and then patterning the material layers using lithographic patterning and etching processes. Microfabrication processes can be used to improve the integration density of various components by continually reducing the minimum feature size, allowing more components to be integrated into a given area.

[0003] A silicon oxide-silicon nitride-silicon oxide stack can be used as an optical filter that exploits the differences in the refractive indices of the different layers. Furthermore, such a silicon oxide-silicon nitride-silicon oxide stack can be used to provide passivation over a conductive structure by blocking the diffusion of moisture, ion dopants, and hydrogen atoms, and to improve the reliability and lifetime of the conductive structure.

[0004] Publication US 2018 / 0 082 999 A1 discloses a manufacturing method for a semiconductor device, wherein two gate electrode layers are separated by an ONO layer stack and wherein openings are etched in the layer stack to selectively connect the gate electrode layers.

[0005] The publication WILLIAMS, KR [et al.]: Etch rates for micromachining processing-Part II. In: Journal of Microelectromechanical Systems, Vol. 12, No. 6, 2003, pp. 761-778 discloses measurement results of different etching rates for different materials using different etchants.

[0006] Publication US 2007 / 0 164 322 A1 discloses manufacturing methods for semiconductor transistors using a protective layer and an oxide layer. It teaches that the protective layer can be formed on a silicon nitride basis and that the oxide layer can be selectively etched using buffered HF.

[0007] Publication DE 10 2004 050 358 A1 discloses methods for fabricating a semiconductor device. A dielectric layer stack comprises a lower silicon nitride layer as an etch stop layer and two overlying oxide layers, which are to be removed with an improved etching solution to minimize damage to a memory device.

[0008] The publication US 2004 / 0 233 374 A1 discloses a method for manufacturing an LCD device.

[0009] US 2004 / 0 256 619 A1 discloses a display device in which contact holes are formed, each having a side wall with an ideally tapered shape, and a corresponding manufacturing method.

[0010] US 5 962 916 A discloses a method in which contact holes corresponding to a source region and a drain region are formed in a layer insulating film.

[0011] JP 2013 - 207 174 A discloses a method for manufacturing semiconductor devices. Short description of the drawings

[0012] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 is a vertical cross-sectional view of an exemplary structure after fabricating a conductive material part and a layer stack including, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer over a substrate, according to an embodiment of the present invention. Fig. 2 is a vertical sectional view of the exemplary structure after forming a patterned etch mask layer according to an embodiment of the present invention. Fig. 3 is a vertical cross-sectional view of the exemplary structure after a first step of an isotropic etching process in which the second silicon oxide layer is etched through, according to an embodiment of the present invention. Fig. 4A is a vertical cross-sectional view of the exemplary structure after a second step of the isotropic etching process in which the silicon nitride layer is etched through, according to an embodiment of the present invention. Fig. Figure 4B is an enlarged view of an area B shown in Fig. 4A is shown. Fig. 5 is a graph comparing etch rates and refractive indices of a PECVD (plasma enhanced chemical vapor deposition) TEOS oxide, a PECVD silicon nitride, and a PVD silicon nitride, according to an embodiment of the present invention. Fig. 6 is a vertical sectional view of the exemplary structure after a third step of the isotropic etching process in which the first silicon oxide layer is etched through, according to an embodiment of the present invention. Fig. 7 is a vertical cross-sectional view of the exemplary structure after removing the patterned etch mask layer according to an embodiment of the present invention. Fig. 8 is a vertical cross-sectional view of the exemplary structure after forming a metallic contact structure in a via cavity according to an embodiment of the present invention. Fig. 9 is a vertical sectional view of the exemplary structure after mounting a semiconductor die according to an embodiment of the present invention. Fig. 10 is a flowchart illustrating an exemplary microfabrication method according to an embodiment of the present invention. Detailed description

[0013] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] In Fig. 1 illustrates an exemplary structure according to an embodiment of the present invention, which may include a substrate 10, a conductive material portion 20 disposed on a front side of the substrate 10, and a layer stack including, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50. The substrate 10 may be a dielectric material, a conductive material, and / or a semiconductor material. In one embodiment, the substrate 10 may comprise a transparent dielectric material, such as fused silica, quartz, and glass. In one embodiment, the substrate 10 may have a thermal conductivity of less than 10 x W / (m K). For example, fused silica, quartz, and glass have a thermal conductivity of about 1.3 x W / (m K). The substrate 10 may comprise a material with a thermal conductivity of less than 0.1 x W / (m K).The substrate 10 may have a sufficient thickness to provide mechanical support for the conductive material part 20 and the layer stack (30, 40, 50). In one embodiment, the substrate 10 may have a thickness of 10 µm to 3 mm, but smaller and larger thicknesses may also be used.

[0016] At least one conductive material portion 20 may be formed over the front side of the substrate 10. Each conductive material portion 20 includes at least one conductive material, which may be at least one metallic material or at least one transparent conductive material (such as a conductive metal oxide material). In one embodiment, each conductive material portion 20 may include an elemental metal, such as copper, tungsten, tantalum, titanium, ruthenium, or cobalt, an intermetallic alloy of at least two elemental metals, and / or a conductive metallic metal nitride material, such as tungsten nitride, tantalum nitride, or titanium nitride. Alternatively or additionally, each conductive material part 20 may comprise or consist essentially of a conductive metal oxide material such as doped zinc oxide, indium tin oxide, cadmium zinc oxide (Cd2SnO4), zinc stannate (Zn2SnO4), and doped titanium dioxide (TiO2).Exemplary doped zinc oxide materials are boron-doped zinc oxide, fluorine-doped zinc oxide, gallium-doped zinc oxide, and aluminum-doped zinc oxide. Other suitable materials are also within the intended scope of the invention. The conductive material of the at least one conductive material portion 20 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless plating, or a combination thereof. Each conductive material portion 20 can be manufactured as follows: patterning the conductive material, for example, by applying and lithographically patterning a photoresist layer over the conductive material, and transferring the pattern in the photoresist layer through the deposited conductive material portion with an etching process using the patterned photoresist layer as an etch mask.The etching process may be an anisotropic etching process, such as a reactive ion etching process, and / or an isotropic etching process, such as a wet etching process. The thickness of each conductive material portion 20 may be 50 nm to 3000 nm, e.g., 100 nm to 1000 nm, but smaller and larger thicknesses may also be used. The conductive material portion 20 may comprise transparent conductive layers (TCFs), such as transparent conductive oxide (TCO), transparent conductive polymers, ultra-thin metal layers, etc. Other suitable materials for use as the conductive material portion are also within the intended scope of the invention.

[0017] Subsequently, the layer stack of the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50 may be formed over the at least one conductive material portion 20. The first silicon oxide layer 30 may be formed by depositing a first silicon oxide material using a first CVD process. The first silicon oxide material may have an etch rate of the same order of magnitude as that for thermal silicon oxide in a wet etching process using a buffered oxide etching solution that is a mixture of 40 vol% NH4F in water and 49 vol% HF in water at room temperature with a volume ratio of 6:1 (hereinafter referred to as a "6:1 BOE solution"). Generally, the total deposited silicon oxide material has an etch rate in hydrofluoric acid-based etchants that is no lower than the etch rate of thermal oxide in the same etchant.Thermal silicon oxide refers to silicon oxide produced by thermal oxidation of silicon. All etch rates used herein are measured at room temperature (20°C) unless otherwise noted. In one embodiment, the first silicon oxide material may provide an etch rate in a 6:1 BOE solution that is less than 3.0 times the etch rate of thermal silicon oxide in a 6:1 BOE solution. In one embodiment, the etch rate of the first silicon oxide material in the 6:1 BOE solution may be less than 2.0 times or less than 1.25 times the etch rate of thermal silicon oxide in the 6:1 BOE solution. All etch rates are measured at room temperature, i.e., 20°C.

[0018] In one embodiment, in the first CVD process, a silicon oxide precursor gas is decomposed to deposit the first silicon oxide material of the first silicon oxide layer 30. The first CVD process may be a thermal CVD process in which the silicon oxide precursor gas is thermally decomposed, or it may be a plasma-enhanced CVD process in which the silicon oxide precursor gas is decomposed in a plasma environment. In one embodiment, the first silicon oxide layer comprises a first silicon oxide material produced by thermal decomposition or plasma decomposition of tetraethyl orthosilicate (TEOS). In one embodiment, the first silicon oxide material may be an undoped silicate glass material, i.e., a silicate glass material that does not contain p-type dopants (such as boron) or n-type dopants (such as phosphorus or arsenic).In one embodiment, the undoped silicate glass material of the first silicon oxide layer 30 may consist essentially of silicon atoms, oxygen atoms, or carbon atoms with an atomic concentration of 0.005% (i.e., 50 ppm) to 0.1% (i.e., 1000 ppm), and hydrogen atoms with an atomic concentration of 0.01% (100 ppm) to 1.0% (10,000 ppm), e.g., from 0.05% (500 ppm) to 0.5% (5000 ppm). In one embodiment, the undoped silicate glass material of the first silicon oxide layer 30 may be subsequently annealed before or after the deposition of the second silicon oxide layer 30 to drive off moisture and hydrogen gas, thereby reducing the etch rate in the 6:1 BOE solution.

[0019] Alternatively, the first silicon oxide material may be a doped silicate glass material, such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, arsenosilicate glass, or borophosphosilicate glass. The concentration of the dopants in the doped silicate glass material may be selected such that the etching rate of the first silicon oxide material in the 6:1 BOE solution is no greater than 3.0 times the etching rate of thermal silicon oxide in the 6:1 BOE solution. The thickness of the first silicon oxide layer 30 may be 100 nm to 1000 nm, e.g., 200 nm to 500 nm, but smaller and larger thicknesses may also be used. The thickness of the first silicon oxide layer 30 is hereinafter referred to as the first thickness t1.In one embodiment, the doped silicate glass material of the first silicon oxide layer 30 may consist essentially of silicon atoms, oxygen atoms, dopant atoms (such as boron atoms, phosphorus atoms, arsenic atoms, and / or fluorine atoms), and carbon atoms with an atomic concentration of 0.005% (i.e., 50 ppm) to 0.1% (i.e., 1000 ppm), and hydrogen atoms with an atomic concentration of 0.01% (100 ppm) to 1.0% (10,000 ppm), e.g., from 0.05% (500 ppm) to 0.5% (5000 ppm). When the first silicon oxide layer 30 comprises an undoped or doped silicate glass produced by a plasma-enhanced CVD process using TEOS as a precursor gas, the first silicon oxide layer 30 may have a refractive index of 1.40 to 1.55, e.g., B. from 1.43 to 1.50.

[0020] The silicon nitride layer 40 can be formed by depositing a silicon nitride material directly onto a top surface of the first silicon oxide layer 30 using a second CVD process. The silicon nitride material of the silicon nitride layer 40 can be a stoichiometric silicon nitride material in which an atomic ratio of silicon atoms to nitrogen atoms is exactly or nearly 3:4, i.e., a silicon nitride material with the chemical composition Si3N4. In other words, the silicon nitride material of the silicon nitride layer 40 is not silicon-rich; rather, a sufficient amount of nitrogen-containing gas (such as ammonia or nitrogen) is provided during the second CVD process to ensure the stoichiometric composition of the silicon nitride material of the silicon nitride layer 40.

[0021] Furthermore, the silicon nitride material of the silicon nitride layer 40 can be formed using a plasma-enhanced CVD process at a relatively low temperature, e.g., lower than 300°C. A silicon nitride material deposited using a plasma-enhanced CVD process can have a lower refractive index than silicon nitride materials deposited by thermal CVD at a temperature above 700°C or used as sputtering targets. For example, thermal silicon nitride materials or silicon nitride materials used as a sputtering target (PVD target) can have a refractive index of 1.99 to 2.22 at a wavelength of 632.8 nm (the laser wavelength in conventional thickness gauges). In contrast, a silicon nitride material deposited in a plasma-enhanced CVD process can have a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm.The reduction in the refractive index of the silicon nitride material deposited in a plasma-assisted CVD process may be due to the lower density of the silicon nitride material, which may be caused by the presence of a higher volume fraction occupied by voids and / or the use of process gases (such as nitrogen or argon) in the silicon nitride material deposited in the plasma-assisted CVD process.

[0022] In one embodiment, the etch rate of the silicon nitride material of the silicon nitride layer 40 in an n:1 BOE solution, where n is 3 to 12, may be 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide material of the first silicon oxide layer 30 in the n:1 BOE solution. In one embodiment, the etch rate of the silicon nitride material of the silicon nitride layer 40 in a 6:1 BOE solution may be 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide material of the first silicon oxide layer 30 in the 6:1 BOE solution.

[0023] Typically, the ratio of silicon to nitrogen in a silicon nitride material can have a significant impact on the etch rate of the silicon nitride material in dilute or buffered hydrofluoric acid. The etch rate of the silicon nitride material in dilute or buffered hydrofluoric acid increases as the ratio of silicon to nitrogen decreases. Thus, the etch rate of a stoichiometric silicon nitride material with a silicon to nitrogen ratio of 3:4, or 0.75, is higher than the etch rate of a silicon-rich silicon nitride material. The etch rate of the silicon nitride material in the silicon nitride layer 40 in a 6:1 BOE solution can be increased by adjusting process parameters. For example, by increasing the deposition rate of the silicon nitride material, the etch rate of the silicon nitride material in a hydrofluoric acid-based solution can be increased.

[0024] In the second CVD process, a silicon precursor gas and a nitrogen precursor gas are used together to produce a stoichiometric silicon nitride material. In one embodiment, the second CVD process may use silane or dichlorosilane as a silicon-containing precursor gas and ammonia or nitrogen as a nitrogen-containing precursor gas. In one embodiment, the second CVD process may comprise a plasma-enhanced CVD process using a silicon-containing precursor gas (such as silane or dichlorosilane) and a nitrogen-containing precursor gas (such as ammonia or nitrogen). In one embodiment, the second CVD process may comprise a thermal CVD process using a silicon-containing precursor gas (such as silane or dichlorosilane) and a nitrogen-containing precursor gas (such as ammonia).The thickness of the silicon nitride layer 40 can be 50 nm to 500 nm, but smaller and larger thicknesses can also be used. The thickness of the silicon nitride layer 40 is referred to below as thickness t2.

[0025] The second silicon oxide layer 50 may be formed by depositing a second silicon oxide material using a third CVD process. The second silicon oxide material may have an etch rate comparable to the etch rate of thermal silicon oxide in a wet etch process using 100:1 diluted hydrofluoric acid at room temperature. In one embodiment, the second silicon oxide material may provide an etch rate in the 6:1 BOE solution that is less than 3.0 times the etch rate of thermal silicon oxide in the 6:1 BOE solution.

[0026] In one embodiment, a silicon oxide precursor gas is decomposed in the second CVD process to deposit the second silicon oxide material of the second silicon oxide layer 50. The second CVD process may be a thermal CVD process in which the silicon oxide precursor gas is thermally decomposed, or it may be a plasma-enhanced CVD process in which the silicon oxide precursor gas is decomposed in a plasma environment.

[0027] In one embodiment, the second silicon oxide layer 50 comprises a second silicon oxide material produced by thermal decomposition or plasma decomposition of tetraethyl orthosilicate (TEOS). In one embodiment, the second silicon oxide material may be an undoped silicate glass material. In one embodiment, the undoped silicate glass material of the second silicon oxide layer 50 may consist essentially of silicon atoms, oxygen atoms, and carbon atoms with an atomic concentration of 0.005% (i.e., 50 ppm) to 0.1% (i.e., 1000 ppm), and hydrogen atoms with an atomic concentration of 0.01% (100 ppm) to 1.0% (10,000 ppm), e.g., from 0.05% (500 ppm) to 0.5% (5000 ppm). In one embodiment, the undoped silicate glass material of the second silicon oxide layer 50 may then be annealed to drive off moisture and hydrogen gas, thereby reducing the etch rate in the 6:1 BOE solution.Alternatively, the second silicon oxide material may be a doped silicate glass material, such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, arsenosilicate glass, or borophosphosilicate glass. The concentration of the dopants in the doped silicate glass material may be selected such that the etching rate of the second silicon oxide material in the 6:1 BOE solution is no greater than 3.0 times the etching rate of thermal silicon oxide in the 6:1 BOE solution. The thickness of the second silicon oxide layer 50 may be 100 nm to 500 nm, e.g., 100 nm to 250 nm, but smaller and larger thicknesses may also be used. The thickness of the second silicon oxide layer 50 will be referred to below as a third thickness t3.In one embodiment, the doped silicate glass material of the second silicon oxide layer 50 may consist essentially of silicon atoms, oxygen atoms, dopant atoms (such as boron atoms, phosphorus atoms, arsenic atoms, and / or fluorine atoms), and carbon atoms with an atomic concentration of 0.005% (i.e., 50 ppm) to 0.1% (i.e., 1000 ppm), and hydrogen atoms with an atomic concentration of 0.01% (100 ppm) to 1.0% (10,000 ppm), e.g., from 0.05% (500 ppm) to 0.5% (5000 ppm). When the second silicon oxide layer 50 comprises an undoped or doped silicate glass produced by a plasma-enhanced CVD process using TEOS as a precursor gas, the second silicon oxide layer 50 may have a refractive index of 1.40 to 1.55, e.g., B. from 1.43 to 1.50.

[0028] In one embodiment, the first silicon oxide material and the second silicon oxide material may be undoped silicate glass materials. In one embodiment, the second silicon oxide material has an etch rate that is 0.80 to 1.25 times the etch rate of the first silicon oxide layer 30 in the 6:1 BOE solution. In one embodiment, the second silicon oxide material may have the same etch rate in the 6:1 BOE solution as the first silicon oxide material. In one embodiment, the second silicon oxide material may be the same as the first silicon oxide material.

[0029] In Fig. 2, a patterned etch mask layer 57 may be formed over a top surface of the second silicon oxide layer 50. In one embodiment, the patterned etch mask layer 57 may comprise a patterned photoresist material layer. In one embodiment, the patterned photoresist material layer may comprise a MUV (mid ultraviolet) photoresist material or a DUV (deep ultraviolet) photoresist material, and may comprise a positive photoresist material or a negative photoresist material. A positive photoresist material is a photoresist material in which polymer molecules are de-crosslinked by exposure and can therefore be patterned by removing lithographically exposed portions and masking portions that are not exposed.A negative photoresist material is a photoresist material in which cross-linking between monomer molecules is induced by exposure to light and can therefore be patterned by removing parts that are not exposed lithographically.

[0030] In embodiments where the patterned etch mask layer 57 comprises a patterned photoresist material layer, the patterned etch mask layer 57 may be formed by applying a photoresist material, lithographically exposing the photoresist material, and developing the photoresist material. The photoresist material may be developed by removing lithographically exposed portions (in the case of a positive photoresist material) or lithographically unexposed portions (in the case of a negative photoresist material). At least one opening may be created in the photoresist material to form the patterned etch mask layer 57. An opening through the patterned etch mask layer 57 may have a horizontal cross-sectional shape of a rectangle, a circle, an ellipse or oval, a rounded rectangle, or another polygon, or another polygon with rounded corners.In one embodiment, the opening through the patterned etch mask layer 57 may have a parallel pair of straight sidewalls extending laterally along a horizontal direction (see, e.g., . Fig. 2). In another embodiment, the opening through the patterned etch mask layer 57 may have a circular or elliptical horizontal cross-sectional shape. Each opening through the patterned etch mask layer 57 may extend vertically to a top surface of an underlying conductive material portion 20. A top surface of the conductive material portion 20 may be physically exposed below an opening in the patterned etch mask layer 57.

[0031] In Fig. 3, an isotropic etch process may be performed to etch portions of the layer stack (30, 40, 50) located beneath each opening through the patterned etch mask layer 57. In one embodiment, a single isotropic etch process may be used to etch through the entire thickness of the layer stack (30, 40, 50), i.e., t1 + t2 + t3, and physically expose a respective underlying portion of the conductive material portion 20. In one embodiment, the chemicals of the single isotropic etch process may be selected such that the individual materials of the layer stack (30, 40, 50) are etched through at comparable etch rates that differ from each other by factors no greater than 6.0. In one embodiment, the isotropic etching process may be a wet etching process in which portions of the second silicon oxide layer 50, the silicon nitride layer 40, and the first silicon oxide layer 30 are sequentially etched.

[0032] In one embodiment, the isotropic etching process may be a single wet etching process using a buffered etching solution that is a mixture of 40 vol% NH4F in water and 49 vol% HF in water with a volume mixing ratio of n:1. The number n may be 3 to 12, e.g., 4 to 10 and / or 5 to 7.5. As an illustrative example, the number n may be 6. The wet etching process may be performed at room temperature, ie, at 20°C. Fig. 3 to 6, in the single wet etching process, a portion of the second silicon oxide layer 50 below the opening through the patterned etch mask layer 57, a portion of the silicon nitride layer 40 below the opening through the patterned etch mask layer 57, and a portion of the first silicon oxide layer 30 below the opening through the patterned etch mask layer 57 may be sequentially etched through to create a via cavity 59. Different time periods of the single isotropic etching process may be referred to as different steps of the single isotropic etching process, which are sequential segments of a contiguous time period during the single isotropic etching process.For example, the period in which a bottom surface of the via cavity 59 is a surface of the second silicon oxide layer 50 is referred to herein as a first step of the isotropic etching process; the period in which the bottom surface of the via cavity 59 is a surface of the silicon nitride layer 40 is referred to herein as a second step of the isotropic etching process; and the period in which the bottom surface of the via cavity 59 is a surface of the first silicon oxide layer 30 is referred to herein as a third step of the isotropic etching process.

[0033] The time at which the vertical cross-sectional profile of the exemplary structure in Fig. 3 corresponds to a point in time at which the first step of the single isotropic etching process (such as a wet etching process using an n:1 BOE solution) ends and the second step of the single isotropic etching process begins. During the first step of the isotropic etching process, the material of the second silicon oxide layer 50 (i.e., the second silicon oxide material) is isotropically etched with an undercut under the patterned etch mask layer 57, while a remaining portion of the second silicon oxide layer 50 covers the silicon nitride layer 40 under the patterned etch mask layer 57. Due to the isotropic nature of the etching process, such as a wet etching process using an n:1 BOE solution, i.e., a buffered oxide etch solution comprising a mixture of 40 vol. % NH4F in water and 49 vol.-% HF in water with a volume mixing ratio of n:1, the sidewalls of the second silicon oxide layer 50 may be concave surfaces. A radius of curvature Rc_o of the concave sidewalls of the second silicon oxide layer 50 at the end of the first step of the isotropic etching process may be equal to the third thickness t3, which is the thickness of the second silicon oxide layer 50.

[0034] In the Fig. 4A and Fig. 4B, the single isotropic etching process may continue with a second step in which the portion of the silicon nitride layer 40 located beneath the opening in the patterned etch mask layer 57 may be isotropically etched with the isotropic etchant, wherein portions of the second silicon oxide layer 50 located beneath proximal portions of the patterned etch mask layer 57 around each opening through that layer may be additionally etched.

[0035] In one embodiment, the etch rate of the silicon nitride material of the silicon nitride layer 40 in an n:1 BOE solution, where n is 3 to 12, may be 1 / 10 to 1 / 2 of the etch rate of the second silicon oxide material of the second silicon oxide layer 50 in the n:1 BOE solution. In one embodiment, the etch rate of the silicon nitride material of the silicon nitride layer 40 in a 6:1 BOE solution may be 1 / 10 to 1 / 2 of the etch rate of the second silicon oxide material of the second silicon oxide layer 50 in the 6:1 BOE solution.

[0036] Typically, the silicon nitride material of the silicon nitride layer 40 can be etched at a lower etch rate than the etch rate of the second silicon oxide layer 50. The ratio of the etch rate of the silicon nitride material of the silicon nitride layer 40 to the etch rate of the second silicon oxide material of the second silicon oxide layer 50 can be kept as high as possible by using a stoichiometric silicon oxide produced by chemical vapor deposition of the silicon nitride layer 40.

[0037] In Fig. Figure 5 shows a graph comparing etch rates and refractive indices of a PECVD-TEOS oxide, a PECVD silicon nitride, and a PVD silicon nitride determined under laboratory conditions. The PECVD-TEOS oxide was fabricated using a plasma-enhanced CVD process at 280 °C using tetraethyl orthosilicate (TEOS) as a silicon oxide precursor gas. The PECVD silicon nitride was fabricated using a plasma-enhanced CVD process at 275 °C using silane as a silicon-containing precursor gas and nitrogen gas as a nitrogen-containing precursor gas. The PVD silicon nitride was deposited by sputtering a silicon-nitrogen material from a sputtering target at 25 °C.The ratio of the etch rate of PECVD silicon nitride in the 6:1 BOE solution to the etch rate of PECVD silicon oxide in the 6:1 BOE solution was approximately 0.28, while the ratio of the etch rate of PVD silicon nitride in the 6:1 BOE solution to the etch rate of PECVD silicon oxide in the 6:1 BOE solution was approximately 0.03. Thus, the difference in etch rates between PECVD silicon nitride and PECVD silicon oxide is smaller than that between PVD silicon nitride and PECVD silicon oxide.

[0038] In one embodiment, during the single wet etching process, the etch rate of the silicon nitride layer 40 in an n:1 BOE solution (where n is 3 to 12) may be 1 / 10 to 1 / 2 of the etch rate of the second silicon oxide layer 50 in the n:1 BOE solution. Likewise, during the single wet etching process, the etch rate of the silicon nitride layer 40 in the n:1 BOE solution may be 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer 30 in the n:1 BOE solution.

[0039] In one embodiment, the silicon nitride material of silicon nitride layer 40 may be formed using a plasma-enhanced CVD process and may have a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm. In contrast, a thermal silicon nitride material deposited in a thermal CVD process at a temperature greater than 700°C or a sputtered silicon nitride material deposited from a sputtering target in a PVD process has a refractive index of 1.99 to 2.02. The microstructure of the silicon nitride material deposited in a plasma-enhanced CVD process causes a reduction in the refractive index relative to the refractive index of the thermal silicon nitride material or the sputtered silicon nitride material. In one embodiment, the silicon nitride material of the silicon nitride layer 40 has a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm.

[0040] Let us return to the Fig. 4A and Fig. 4B. The etch rate of the first silicon oxide layer 30 in the n:1 BOE solution may be at least 3 times the etch rate of the silicon nitride layer 40 in the isotropic etching process. Since all physically exposed surfaces of the silicon nitride layer 40 are physically exposed to the isotropic etchant (such as the n:1 BOE solution), the vertical etch pitch of the silicon nitride layer 40 at its sidewalls is determined by the lateral offset distance of each point on the sidewalls of the silicon nitride layer 40 from vertical planes containing the sidewalls of the patterned etch mask layer 57. Thus, the sidewalls of the silicon nitride layer 40 may be straight conical sidewalls extending from the bottom periphery of a respective concave sidewall of the second silicon oxide layer 50 to a top surface of the first silicon oxide layer 30 at the end of the second step of the single isotropic etching process.

[0041] The second silicon oxide material of the second silicon oxide layer 50 can be laterally recessed with concave etching surfaces that have an increasing radius of curvature throughout the etching step in which the silicon nitride layer 40 is etched through. The isotropic etchant can be continuously directed to the lower edges of the concave sidewalls of the silicon nitride coating 40 to provide a new concentric etch front for etching the material of the silicon nitride coating 40. The lower etch rate of the silicon nitride material of the silicon nitride layer 40 relative to the etch rate of the second silicon oxide material of the second silicon oxide layer 50 can result in the creation of a series of round etch fronts (ef_0, ef_1, ef_2) whose radius increases over time and which provide an overlapping surface in the shape of a conical two-dimensional plane with a cone angle α relative to the vertical direction.It is clear that in an isotropic etching process, an etched surface shrinks along a plane formed by the overlap of an infinite number of etch fronts. Furthermore, it is clear that the etching process occurs only on segments of the plane formed by the overlap of the etch fronts that overlap with the etched material.

[0042] Each circular etch front (ef_0, ef_1, ef_2) has a respective geometric center in a horizontal plane containing the interface between the silicon nitride layer 40 and the second silicon oxide layer 50. Points (P_0, P_1, P_2) correspond to the geometric centers of the circular etch fronts (ef_0, ef_1, ef_2). When the silicon nitride layer 40 is etched through and a top surface of the first silicon oxide layer 30 is physically exposed, a leading etch front ef_0 centered at an etch start point P_0 located at a lower edge of a concave surface of the second silicon oxide layer 50 becomes a starting point of the leading etch front ef_0. The isotropic etchant initiates the etching of the silicon nitride material of the silicon nitride layer 40, since the leading etch front ef_0 grows from a point to a circle with a finite radius.The etching distance d_0 of the foremost etch front ef_0 increases as the isotropic etching process progresses, and the etching distance d_0 reaches the value of the second thickness t2 when the silicon nitride layer 40 is etched through. Other etch fronts emerge as the lower edge of the concave surface of the second silicon oxide layer 50 recedes laterally, and the isotropic etchant begins to etch newly exposed top-side segments of the silicon nitride layer 40. While an unlimited number of etch fronts can be generated during the isotropic etching process, only two etch fronts (ef_1, ef_2) are shown. The first etch front ef_1 can grow isotropically after a first etch front center point P_1 has been physically exposed for the isotropic etchant, since the lower edge of the concave etch surface of the second silicon oxide layer 50 passes through the first etch front center point P_1.The first etch front ef_1 can grow isotropically in a round shape because the first etch distance d_1 between the first etch front ef_1 and the first etch front center point P_1 increases over time. Similarly, a second etch front ef_2 can grow isotropically when a second etch front center point P_2 is physically exposed to the isotropic etchant because the lower edge of the concave etching surface of the second silicon oxide layer 50 passes through the second etch front center point P_2. The second etch front ef_2 grows isotropically in a round shape because the second etch distance d_2 between the second etch front ef_2 and the second etch front center point P_2 increases over time.

[0043] The cone angle α of the straight conical sidewalls of the silicon nitride layer 40, measured relative to a vertical direction perpendicular to the top surface of the conductive material portion 20, may be the arctangent of the ratio of the etch rate of the second silicon oxide layer 50 in the isotropic etchant to the etch rate of the silicon nitride layer 40 in the isotropic etchant. The straight conical sidewalls of the silicon nitride layer 40 may lie in a respective two-dimensional (Euclidean) plane. Furthermore, the straight conical sidewalls of the silicon nitride layer 40 may remain in a respective two-dimensional (Euclidean) plane even after overetching, since the etch rate of the silicon nitride material is isotropic during overetching.In an illustrative example, in the case where the isotropic etchant is a 6:1 BOE solution, the second silicon oxide layer 50 has an etch rate of 8.2 nm / s in the 6:1 BOE solution, and the silicon nitride layer 40 has an etch rate of 2.3 nm / s in the 6:1 BOE solution, the cone angle α of the straight conical sidewalls of the silicon nitride layer 40 may be approximately an arctangent of [(8.2 nm / s) / (2.3 nm / s)] ≈ 1.30 rad ≈ 74.3°. The top surface of the first silicon oxide layer 30 is physically exposed at the end of the second step of the single isotropic etching process, which coincides with the beginning of the third step of the single isotropic etching process. At this point, a remaining portion of the silicon nitride layer 40 covers the first silicon oxide layer 30 under the patterned etching mask layer 57.

[0044] In Fig. 6, a third etching step of the isotropic etching process begins when the second etching step of the isotropic etching process ends. The materials of the first silicon oxide layer 30 and the second silicon oxide layer 50 can be etched, creating concave surfaces, and the material of the silicon nitride layer 40 can be etched, with the straight conical sidewalls of the silicon nitride layer 40 shifting laterally outward without creating concave surfaces. As stated above, the etching rates of the first silicon oxide layer 30 and the second silicon oxide layer 50 during the isotropic etching process are at least three times the etching rate of the silicon nitride layer 40. Therefore, the straight conical sidewalls of the silicon nitride layer 40 shift laterally outward during the third step of the isotropic etching process. At the time when the top surface of the conductive material portion 20 is physically exposed, as shown in Fig. 6, a radius of curvature Rc_f of the concave surfaces of the first silicon oxide layer 30 may be equal to the first thickness t1, ie, the thickness of the first silicon oxide layer 30. The third step of the isotropic etching process may include, after physically exposing the top surface of the conductive material part 20, an extended portion that is an overetch segment of the third step of the isotropic etching process. The radius of curvature of the concave surfaces of the first silicon oxide layer 30 may be increased during an overetch that exceeds the Fig. 6 detected time, become greater than the thickness of the first silicon oxide layer 30.

[0045] Below each opening in the patterned etch mask layer 57, a via cavity 59 is created, extending through the layer stack (30, 40, 50) downwards to a top side of the conductive material part 20. The via cavity 59 may include undercut regions UC in each layer of the layer stack (30, 40, 50). The undercut regions UC correspond to a volume located below the patterned etch mask layer 57, i.e., a volume with a planar overlap with the patterned etch mask layer 57 in a top-down view along a vertical downward direction. Each sidewall of the layer stack (30, 40, 50) may be located outside the vertical plane containing the sidewalls of the patterned etch mask layer 57, which define a respective opening through the patterned etch mask layer 57.A width w of the via cavity 59 increases strictly with a vertical distance vd from a horizontal top surface of the conductive material part 20.

[0046] In Fig. 7, the patterned etch mask layer 57 can be removed selectively for the materials of the conductive material portion 20 and the layer stack (30, 40, 50). For example, if the patterned etch mask layer 57 comprises a photoresist material, the patterned etch mask layer 57 can be removed by stripping or by dissolving it in an organic solvent.

[0047] The sidewalls of the first silicon oxide layer 30, the silicon nitride layer 40 and the second silicon oxide layer 50 may extend laterally (for example, along a direction perpendicular to the plane of the vertical sectional view of Fig. 7) with a uniform cross-sectional profile. Alternatively, the sidewalls of the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50 may be arranged around a substantially circular opening with a circular horizontal cross-sectional shape. In general, the exemplary structure of embodiments of the present invention may have a first concave sidewall of the first silicon oxide layer 30 with a first radius of curvature Rc_1 that is at least as large as the first thickness t1.Furthermore, the exemplary structure of embodiments of the present invention may include a second concave sidewall of the second silicon oxide layer 50 with a second radius of curvature Rc_2 that is at least the sum of the third thickness t3, the first thickness t1, and the product of the second thickness t2 and the ratio of the etch rate of the material of the second silicon oxide layer 50 during the isotropic etching process to the etch rate of the material of the silicon nitride layer 40 during the isotropic etching process. Furthermore, the exemplary structure of embodiments of the present invention may include straight conical sidewalls extending from a lower edge of the second concave sidewall of the second silicon oxide layer 50 to an upper edge of the first silicon oxide layer 30 with a cone angle α that may be 62° to 84°.

[0048] In Fig. 8, a metallic contact structure (60, 80) may be formed in the via cavity 59 directly on top of the conductive material portion 20. The metallic contact structure (60, 80) may comprise a combination of a bond pad 60 and a solder material portion 80. In one embodiment, a plurality of via cavities 59 may be created through the layer stack (30, 40, 50), and a plurality of metallic contact structures (60, 80) may be formed. As an illustrative example, the bond pad 60 may be formed by depositing and patterning metal layers such as an Al / Ni / Au stack, an Al / Ni / Cu stack, a Cu / Ni / Au stack, a Cu / Ni / Pd stack, a Ti / Ni / Au stack, a Ti / Cu / Ni / Au stack, a Ti-W / Cu stack, a Cr / Cu stack, or a Cr / Cu / Ni stack, or other UBM (Under Bump Metallization) stack known in the art.The solder material portion 80 comprises a solder material, such as a Sn-Ag alloy or another tin-based alloy. A transverse dimension (such as a diameter) of the solder material portion 80 may be 5 µm to 100 µm, but smaller and larger transverse dimensions may also be used. One of ordinary skill in the art will recognize that additional and / or alternative metallic contact structures (60, 80) may be formed in conjunction with the silicon oxide-silicon nitride-silicon oxide stack formed using the novel methods disclosed herein.

[0049] In Fig. 9 shows the exemplary structure after bonding an optical structure 800, comprising the substrate 10, the conductive material part 20, and the layer stack (30, 40, 50), to a semiconductor chip 900 having an optical semiconductor device 920. The optical semiconductor device 920 may be a semiconductor device that can capture or process incoming optical signals or optical images transmitted via the optical structure 800. The semiconductor chip 900 may be provided with front bond pads 890 to which the solder material parts 80 are bonded. Optionally, a light-transmissive fill material part 880 may be provided between the optical structure 800 and the semiconductor chip 900 to avoid condensation and / or contamination.

[0050] In one illustrative example, the optical semiconductor device 920 may comprise a complementary metal oxide semiconductor (CMOS) image sensor, a charge-coupled device (CCD), an optical sensor array for a light detection and ranging (LIDAR) application, or a suitable semiconductor-based optical signal detection device. In one embodiment, the optical structure 800 may comprise an optical filter that transmits or blocks light in a specific wavelength range. The thickness of each layer in the layer stack (30, 40, 50) may be selected to provide a suitable transmission wavelength range in which light is transmitted, while suppressing light transmission outside the transmission wavelength range.

[0051] In another example, the optical structure 800 may include a beam splitter that partially reflects and partially transmits an incident beam. In yet another example, the optical structure 800 may include an optical mirror for a broad wavelength range or for a specific wavelength range. Optionally, the semiconductor chip 900 may be connected to a printed circuit board 999 via bond structures (970, 980, 990), which may include, for example, chip-side bond pads 970, solder balls 980, and board-side bond pads 990.

[0052] In general, the optical structure 800 of the present invention may be attached to the semiconductor chip 900 or another optical device (such as a camera, an optical signal transmission device, or an optical sensor) using solder pieces, a conductive paste, and / or an adhesive material (such as epoxy). Embodiments are expressly contemplated herein in which the semiconductor chip 900 is Fig. 9 is replaced by another optical component which, when integrated with the optical structure 800, forms an optical module.

[0053] In Fig.10, a microfabrication method according to an embodiment of the present invention is illustrated in a flowchart 1000. In a step 1010, a layer stack comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 may be formed over a conductive material portion 20 on a substrate 10 using the methods described above. A structure may be provided comprising a layer stack including, from bottom to top, the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50, and the conductive material portion 20 beneath the layer stack (30, 40, 50) and above the substrate 10. In a step 1020, a patterned etch mask layer 57 (such as a patterned photoresist layer) having an opening may be formed over the layer stack (30, 40, 50).

[0054] In a step 1030, a via cavity 59 extending through the layer stack (30, 40, 50) and down to a top surface of the conductive material portion 20 may be created by isotropic etching portions of the second silicon oxide layer 50, the silicon nitride layer 40, and the first silicon oxide layer 30 during a single wet etching process. In one embodiment, a single wet etching process may be used using a buffered oxide etch solution that is a mixture of 40 vol% NH4F in water and 49 vol% HF in water with a volume mixing ratio of n:1, where n is 3 to 12. An etch rate of the silicon nitride layer 40 may be 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer 30.

[0055] The microfabrication method according to the invention (i.e., a method for producing structures having at least one dimension smaller than 1 µm) enables patterning of a layer stack comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 with a single etching process, which may be an isotropic etching process, such as a wet etching process, to create a via cavity 59. For example, an n:1 BOE solution may be used for the wet etching process. Such a wet etching process is a cost-effective process that uses inexpensive wet etching chemicals. Furthermore, such a wet etching process utilizes commonly used wet etching tools normally used for other microfabrication processes, and therefore, no new process tool needs to be purchased.Furthermore, only one patterned etch mask layer 57, such as a patterned photoresist layer, is used for the microfabrication process of the present invention. Thus, a combination of a single lithographic patterning process and a single isotropic etch process can be used to pattern the layer stack including the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50 to create the via cavity 59. Furthermore, by eliminating the dry etch process in favor of a wet etch process, the risk of photoresist mask burn can be eliminated. The various advantages of the disclosed embodiments enable significant cost savings and increased throughput during the microfabrication process.

[0056] To implement a single isotropic etching process for etching the layer stack comprising the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50, the etch rates of the first silicon oxide layer 30 and the second silicon oxide layer 50 in an isotropic etchant (such as an n:1 BOE solution) can be kept as low as possible, and the etch rate of the silicon nitride layer 40 can be increased as much as possible. For example, the deposition method and material composition for the first and second silicon oxide materials can be selected such that the etch rates of the first silicon oxide layer 30 and the second silicon oxide layer 50 are 1.0 to 1.25 times the etch rate of thermal silicon oxide. The etch rate of the silicon nitride material in the silicon nitride layer 40 can be increased by depositing a stoichiometric silicon nitride material using a plasma-enhanced CVD process.By maintaining the ratio of the etch rates of the silicon oxide materials of the first and second silicon oxide layers 30 and 50 in the isotropic etchant to the etch rate of the silicon nitride material of the silicon nitride layer 40 in the range of 2 to 10, a via cavity 59 can be created through the layer stack (30, 40, 50) with a sidewall profile described above. A metallic contact structure 60 can be formed in the via cavity 59 on the conductive material portion 20.

[0057] Embodiments of the present invention provide a cost-effective method for patterning a layer stack including a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 to create a via cavity 59. Furthermore, embodiments of the present invention provide a patterned structure in which a large cone angle α on the straight conical sidewalls of the silicon nitride layer 40 can define the contact area between the metallic contact structure 60 and the conductive material portion 20. The conductive material portion 20 may comprise a metallic material, such as a metal pad or metal line, or a transparent conductive oxide material. The methods of the present invention can be used for a substrate 10 with low thermal conductivity and high light transmittance, such as fused silica, quartz, or glass.Thus, various exemplary methods can be used for various optical components that utilize a substrate 10 with a low thermal conductivity.

[0058] The patterning method of various embodiments utilizes only one patterned etch mask layer 57 and only one isotropic etch process (which may be a wet etch process). In contrast, conventional methods for creating a via cavity through the oxide-nitride-oxide (ONO) layer stack typically utilize multiple etch processes. For example, a conventional method may utilize at least three etch processes (wet-dry-wet), which utilize at least two masks. One of ordinary skill in the art will recognize the numerous advantages that result from using a single isotropic etch process disclosed herein in the various embodiments over conventional methods that utilize multiple etch processes.For example, by using a single isotropic etch process instead of multiple etch processes in the various embodiments described herein, the overall processing cost and total processing time can be significantly reduced. These cost and time savings can be achieved because each additional etch process incurs additional cost and additional processing time. Furthermore, by reducing the processing steps to a single isotropic etch process using a single mask layer, the various embodiments described herein can further reduce the overall processing cost and total processing time, because each additional etch mask layer used in a conventional process requires the application and patterning of a photoresist layer in a lithographic tool.Furthermore, as explained above, conventional methods may utilize three etching processes, including a wet etching process, a dry etching process, and another etching process. In the patterning method of the various embodiments described herein, a single wet etching process may be used, thus avoiding potential damage to the second silicon oxide layer 50 that may occur during a dry etching process (such as a reactive ion etching process).

[0059] Embodiments of the present invention may thus provide a microscopic device comprising a substrate 10, a conductive material portion 20, and a layer stack (30, 40, 50) comprising, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50. In particular, in various embodiments, the microscopic device may be an optical device. In these embodiments, the substrate 10 may be a light-transmissive substrate, such as fused silica, quartz, or glass. The conductive material portion 20 may comprise a transparent conductive material (such as a transparent oxide material) or a metal that is opaque to light.In one embodiment, a first optical component fabricated on the substrate 10 may include a transparent conductive material as the respective conductive material portion 20, and a second optical component fabricated on the substrate 10 may include a metal (an opaque material) as the respective conductive material portion 20. The optical component fabricated by the microfabrication method of the present invention may include an optical filter, an optical mirror, a beam splitter, and / or other optical components that may be derived by adjusting the thicknesses of the individual layers in the layer stack including the first silicon oxide layer 30, the silicon nitride layer 40, and the second silicon oxide layer 50.In addition, an electrical contact can be made with each of the conductive material parts 20 in the optical components fabricated on the substrate 10.

[0060] In all the drawings and according to various embodiments of the present invention, a structure is provided comprising: a conductive material part 20 arranged on a substrate 10; a layer stack (30, 40, 50) comprising, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40 having a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm, and a second silicon oxide layer 50, and arranged above the conductive material part 20;and a via cavity 59 extending through the layer stack (30, 40, 50), wherein sidewalls of the via cavity 59 comprise first concave sidewalls of the first silicon oxide layer 30 adjacent to a top surface of the conductive material part 20, straight conical sidewalls of the silicon nitride layer 40 adjacent to a respective top end of the first concave sidewalls, and second concave sidewalls of the second silicon oxide layer 50 adjacent to a respective top end of the straight conical sidewalls, such that a width w of the via cavity 59 increases strictly with a vertical distance vd from a horizontal top surface of the conductive material part 20. A strict increase in a size with a parameter means that an increase in the value of the size corresponds to an increase in the value of the parameter.

[0061] As explained above, the cone angle α of the straight conical sidewalls of the silicon nitride layer 40 can be determined by the ratio of the etch rate of the second silicon oxide material of the second silicon oxide layer 50 in an n:1 BOE solution (where n is 3 to 12) to the etch rate of the silicon nitride layer 40 in the n:1 BOE solution. The ratio of the etch rates can be 2 to 10. In one embodiment, the straight conical sidewalls of the silicon nitride layer 40 can have a cone angle α of 62° (approximately the angle corresponding to the arctangent 2) to 84° (approximately the angle corresponding to the arctangent 10) with respect to a vertical direction perpendicular to a top surface of the conductive material part 20.

[0062] In one embodiment, the substrate 10 comprises, and / or consists essentially of, a transparent dielectric material selected from the group consisting of silica glass, quartz, and glass, and the conductive material part 20 comprises, and / or consists essentially of, a material selected from the group consisting of metallic material and transparent conductive oxide material.

[0063] In one embodiment, the substrate 10 has a thickness of 10 µm to 3 mm, the first silicon oxide layer 30 has a first thickness t1 of 100 nm to 1000 nm, the silicon nitride layer 40 has a second thickness t2 of 50 nm to 500 nm, and the second silicon oxide layer 50 has a third thickness t3 of 50 nm to 500 nm.

[0064] In one embodiment, the structure includes a metallic contact structure 60 disposed in the via cavity 59 on a top surface of the conductive material portion 20.

[0065] According to some embodiments of the present invention, a microfabrication method is provided, comprising the following steps: providing a structure comprising a layer stack (30, 40, 50) including, from bottom to top, a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50, and a conductive material portion 20 below the layer stack (30, 40, 50) and above a substrate 10; forming a patterned etch mask layer 57, having an opening through this layer, above the layer stack (30, 40, 50);and forming a via cavity 59 extending through the layer stack (30, 40, 50) and down to a top surface of the conductive material portion 20 by isotropic etching portions of the second silicon oxide layer 50, the silicon nitride layer 40, and the first silicon oxide layer 30 with an isotropic etching process in which an etch rate of the silicon nitride layer 40 is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer 30. In one embodiment, the microfabrication method of the present invention can be used to fabricate an optical structure, which may include an optical filter, an optical mirror, or a beam splitter.

[0066] According to one embodiment of the present invention, a method for patterning a structure is provided, comprising the following steps: forming a layer stack (30, 40, 50) comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 over a conductive material portion 20 on a substrate 10; forming a patterned etch mask layer 57 having an opening over the layer stack (30, 40, 50); and creating a via cavity 59 extending through the layer stack (30, 40, 50) and down to a top surface of the conductive material portion 20 by isotropically etching portions of the second silicon oxide layer 50, the silicon nitride layer 40, and the first silicon oxide layer 30 during a single wet etching process using a buffered oxide etch solution comprising a mixture of 40 vol.% NH4F in water and 49 vol.-% HF in water with a volume mixing ratio of n:1, where n is 3 to 12. In one embodiment, the patterning method of the present invention can be used to manufacture an optical structure, which may include an optical filter, an optical mirror, or a beam splitter.

[0067] According to one embodiment of the present invention, a structure is provided comprising: a conductive material portion 20 fabricated on a substrate 10; a layer stack (30, 40, 50) comprising a first silicon oxide layer 30, a silicon nitride layer 40, and a second silicon oxide layer 50 disposed over the conductive material portion 20; and a via cavity 59 extending through the layer stack (30, 40, 50) and downwards to a top side of the conductive material part 20, wherein sidewalls of the via cavity 59 comprise first concave sidewalls of the first silicon oxide layer 30 adjacent to a top side of the conductive material part 20, straight conical sidewalls of the silicon nitride layer 40 adjacent to a respective top end of the first concave sidewalls, and second concave sidewalls of the second silicon oxide layer 50,which adjoin a respective upper end of the straight conical sidewalls, such that a width w of the via cavity 59 increases strictly with a vertical distance vd from a horizontal top surface of the conductive material part 20. The silicon nitride layer 40 may have a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm. In one embodiment, the structure of the present invention may be an optical structure, which may include an optical filter, an optical mirror, or a beam splitter.

Claims

[1] Microfabrication process with the following steps: Providing a structure (800) comprising a layer stack (30, 40, 50) containing, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40) and a second silicon oxide layer (50), and a conductive material part (20) below the layer stack (30, 40, 50) and above a substrate (10); Producing a structured etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Producing a through-hole plating cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top surface of the conductive material part (20) by isotropic etching of portions of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) using an isotropic etching process in which the etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30), wherein: the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical evaporation at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) has a second silicon oxide material produced by decomposition of tetraethyl orthosilicate. [2] Microfabrication method according to claim 1, wherein the isotropic etching process comprises a wet etching process using a buffered oxide etching solution comprising a mixture of 40 vol% NH4F in water and 49 vol% HF in water with a volume mixing ratio of n : 1, wherein n is 3 to 12. [3] Microfabrication method according to one of the preceding claims, wherein the silicon nitride layer (40) has a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm. [4] Microfabrication process according to claims 1 to 3, wherein: The first silicon oxide material and the second silicon oxide material are undoped silicate glass materials, and the second silicon oxide material has an etch rate that is 0.80 to 1.25 times the etch rate of the first silicon oxide layer (30). [5] Microfabrication process according to any of the preceding claims, wherein the isotropic etching process comprises: a first step in which a material of the second silicon oxide layer (50) is isotropically etched with an undercut beneath the structured etch mask layer (57), while a remaining part of the second silicon oxide layer (50) covers the silicon nitride layer (40) beneath the structured etch mask layer (57); a second step in which a material of the silicon nitride layer (40) is etched at a lower etch rate than an etch rate of the second silicon oxide layer (50), while straight conical sidewalls are produced through the silicon nitride layer (40) and a remaining part of the silicon nitride layer (40) covers the first silicon oxide layer (30) under the structured etch mask layer (57); and a third step in which materials of the first silicon oxide layer (30) and the second silicon oxide layer (50) are etched, creating concave surfaces, and the material of the silicon nitride layer (40) is etched, displacing the straight conical sidewalls laterally outwards without creating concave surfaces. [6] Microfabrication method according to one of the preceding claims, further comprising producing a metallic contact structure (60, 80) in the via cavity (59) on a top side of the conductive material part (20). [7] Microfabrication method according to any of the preceding claims, wherein the substrate (10) comprises a transparent dielectric material selected from the group consisting of silica, quartz and glass, and has a thickness of 10 µm to 3 mm. [8] Microfabrication process according to any of the preceding claims, wherein the conductive material part (20) comprises a material selected from the group consisting of metallic material and transparent conductive oxide material, the first silicon oxide layer (30) has a first thickness of 100 nm to 1000 nm, the silicon nitride layer (40) has a second thickness of 50 nm to 500 nm, and the second silicon oxide layer (50) has a third thickness of 50 nm to 500 nm. [9] Procedure for structuring a structure (800) with the following steps: Forming a layer stack (30, 40, 50) comprising a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40) and a second silicon oxide layer (50) over a conductive material part (20) on a substrate (10); Producing a structured etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Creating a through-hole plating cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top surface of the conductive material part (20) by isotropic etching of portions of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) during a single wet etching process using a buffered oxide etching solution comprising a mixture of 40 vol% NH4F in water and 49 vol% HF in water with a volume mixing ratio of n : 1, where n is 3 to 12; wherein the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical evaporation at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) has a second silicon oxide material produced by decomposition of tetraethyl orthosilicate. [10] Method according to claim 9, wherein the layer stack (30, 40, 50) is produced as follows: Production of the first silicon oxide layer (30) by depositing a first silicon oxide material in a first CVD process (CVD: chemical evaporation); Production of the silicon nitride layer (40) by depositing a silicon nitride material in a second CVD process; and Producing the second silicon oxide layer (50) by depositing a second silicon oxide material in a third CVD process. [11] Method according to claim 9 or 10, wherein the etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30) during the single wet etching process. [12] Method according to any one of claims 9 to 11, wherein: the substrate (10) comprises a transparent dielectric material selected from the group consisting of silica, quartz and glass, and the conductive material part (20) comprises a material selected from the group consisting of metallic material and transparent conductive oxide material. [13] Method according to any one of claims 9 to 12, further comprising producing a metallic contact structure (60, 80) in the through-hole cavity (59) on a top side of the conductive material part (20) by depositing and structuring a conductive material. [14] Structure (800) with: a conductive material part (20) arranged on a substrate (10); a layer stack (30, 40, 50) comprising, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40) with a refractive index of 1.88 to 1.95 at a wavelength of 632.8 nm, and a second silicon oxide layer (50), arranged above the conductive material portion (20), wherein the etch rates of the first silicon oxide layer (30) and the second silicon oxide layer (50) are 1.0 to 1.25 times the etch rate of thermal silicon oxide; and a via-hole cavity extending through the layer stack (30, 40, 50), wherein side walls of the via-hole cavity (59) comprise first concave side walls of the first silicon oxide layer (30) adjoining a top surface of the conductive material part (20), straight conical side walls of the silicon nitride layer (40) adjoining a respective top end of the first concave side walls, and second concave side walls of the second silicon oxide layer (50) adjoining a respective top end of the straight conical side walls, such that a width of the via-hole cavity (59) strictly increases with a vertical distance from a horizontal top surface of the conductive material part (20); wherein the straight conical sidewalls of the silicon nitride layer (40) have a cone angle of 72° to 85° with respect to a vertical direction that is perpendicular to a top surface of the conductive material part (20). [15] Structure (800) according to claim 14, wherein the substrate (10) comprises a transparent dielectric material selected from the group consisting of silica, quartz and glass, and the conductive material part (20) comprises a material selected from the group consisting of metallic material and transparent conductive oxide material. [16] Structure (800) according to claim 14 or 15, wherein: the substrate (10) has a thickness of 10 µm to 3 mm, the first silicon oxide layer (30) has a thickness of 100 nm to 1000 nm, the silicon nitride layer (40) has a thickness of 50 nm to 500 nm, and the second silicon oxide layer (50) has a thickness of 50 nm to 500 nm. [17] Structure (800) according to one of claims 14 to 16, further comprising a metallic contact structure (60, 80) arranged in the via cavity (59) on a top surface of the conductive material part (20) and comprising a bond pad (60) and a solder material part (80). [18] Semiconductor device comprising the structure (80) according to claim 17, further comprising a semiconductor chip (900) comprising an optical semiconductor component (920), wherein the semiconductor chip (900) is provided with a front bond pad (890) to which the solder material part (80) is bonded.

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