Circuit and method for managing jump prediction information for different contexts

Abstract

An integrated circuit (201, 301) comprising: at least one processor (102) executing instructions in a pipeline (104), each instruction being associated with a particular translation context of a plurality of potential translation contexts used to distinguish otherwise identical virtual addresses from one another, and wherein the instructions include branch instructions; a first store (306) for branch prediction information characterizing results of branch instructions previously executed by the processor (102), wherein the first store (306) is dynamically partitioned into a plurality of partitions of one or more entries, and wherein the dynamic partitioning comprises updating a partition to include an additional entry during operation of the processor (102) by associating the additional entry with a particular subset of a plurality of translation contexts containing fewer than all of the plurality of potential translation contexts; a first circuit configured to provide a predicted branch result determined based on at least a portion of the branch prediction information; and a second circuit configured to provide an actual branch result based on an executed branch instruction and to update the branch prediction information based on the actual branch result; wherein providing a predicted branch result for a first branch instruction comprises retrieving a first entry from a first partition of the plurality of partitions based on an identified first subset of a plurality of translation contexts associated with the first branch instruction; and where a total number of entries in the first partition changes during the operation of the processor, wherein the first subset of multiple translation contexts comprises only translation contexts having an exception level value identical to an exception level value associated with the first branch instruction.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Application No. 62 / 619,384, filed January 19, 2018. background

[0002] The invention relates to managing branch prediction information for different contexts.

[0003] A processor pipeline has multiple stages through which instructions are advanced, one cycle at a time. An instruction is fetched (e.g., in an instruction fetch (IF) stage or stages). An instruction is decoded (e.g., in an instruction decode (ID) stage or stages) to determine an operation and one or more operands. Alternatively, in some pipelines, the instruction fetch and instruction decode stages might overlap. An instruction has its operands fetched (e.g., in an operand fetch (OF) stage or stages). An instruction issues or executes a flow, which typically starts the instruction's progression through one or more execution stages. Execution may involve applying the instruction operation to the operand(s) for an instruction of an arithmetic logic unit oran ALU (Arithmetic Logic Unit) instruction, storing to and loading from a memory address for a store instruction, or may include evaluating a condition of a conditional jump instruction to determine whether or not to take the jump. Finally, an instruction is executed or committed, which may include storing a result (e.g., in a write-back (WB) stage or stages).

[0004] Instructions are fetched based on a program counter (PC), which is a reference used to identify instructions within memory (e.g., within a portion of main memory or within a processor's instruction cache). The PC can progress through the addresses of a block of compiled instructions (referred to as a "basic block"), incrementing by a certain number of bytes (depending on the length of each instruction and how many instructions are being fetched at a time). At the end of this instruction block, there can be a jump instruction, which is either an unconditional jump instruction associated with a jump target address to which the PC will jump, or a conditional jump instruction that has a condition that must be evaluated to produce a Boolean jump direction result.For example, a jump direction result of "0" may indicate that the jump is not taken or NT (Not Taken) and the PC continues sequential movement to the next address in a current or subsequent block, and a jump direction result of "1" may indicate that a jump is taken or T (T = Taken) and the PC jumps (e.g., non-sequentially) to a jump target address at the start of a new instruction block.

[0005] There are several situations in which it may be useful to speculatively fetch an instruction that depends on the outcome of a branch instruction before the outcome has actually been determined. Processor architectures that support such speculation use branch prediction to determine a "predicted branch outcome" used in early stages of the pipeline (e.g., a predicted branch direction and / or a predicted branch target), which may or may not match the "actual branch outcome" ultimately determined in a later stage of the pipeline. If the predicted branch outcome does not match the actual branch outcome, the pipeline is flushed of all faulty instructions, and the correct instructions are fetched.

[0006] The following publications are known from the state of the art: US 2017 / 0 286 421 A1 relates to a device having processing circuitry for processing instructions from multiple threads. A memory structure is shared by the threads and has a number of entries. An indexing circuit generates a target index value identifying an entry of the memory structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to the information to be accessed from the memory structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads initiates the request. The key value for at least one of the threads is updated periodically. US 2009 / 0 089 564 A1 describes methods for protecting a branch instruction from side-channel vulnerabilities. A method includes receiving a request to modify the operation of a processor to protect it from side-channel attacks. The method further includes modifying branch prediction operation in response to the request. US 2008 / 0 052 499 A1 discloses hardware and / or software countermeasures to mitigate or eliminate vulnerabilities due to the observable and / or predictable states and state transitions of microprocessor components such as the instruction cache, data cache, branch prediction unit(s), branch target buffer, and other components. For branch prediction units, for example, various hardware and / or software countermeasures are provided to mitigate vulnerabilities in the branch prediction unit (BPU) and protect against security vulnerabilities due to the observable and / or predictable states and state transitions during BPU operations.

[0007] Mutlu, Onur: "Lecture 10: Branch Prediction, Computer Architecture.", ETH Zurich, October 25, 2017, slides 1-76; URL: https: / / safari.ethz.ch / architecture / fall2017 / doku.php introduces the fundamentals of branch prediction in computer architectures.

[0008] Wang, Zhenghong, et al.: “New cache designs for thwarting software cache-based side channel attacks.”, The 34th Annual International Symposium on Computer architecture : Conference proceedings, June 9-13, 2007, San Diego, California, USA, pp. 494-505, ISBN 978-1-59593-706-3 refers to mitigation approaches for software cache-based side channel attacks. A partition-based approach eliminates cache interference, while a randomization-based approach randomizes cache interference so that no information can be derived. New cache designs are presented: the partition-locked cache (PLcache) and the random permutation cache (RPcache). SUMMARY

[0009] The present invention is based on the object of securing branch predictions in a processor while simultaneously minimizing performance losses.

[0010] The object is achieved by an integrated circuit according to claim 1 or a method according to claim 12. Preferred embodiments are formulated in the dependent claims.

[0011] In one aspect, an integrated circuit comprises: at least one processor executing instructions in a pipeline, each instruction associated with a particular one of a plurality of potential contexts, and the instructions include branch instructions; a first memory for branch prediction information identifying results of branch instructions previously executed by the processor, the first memory being dynamically partitioned into a plurality of partitions having one or more entries, and wherein the dynamic partitioning comprises updating a partition to include an additional entry during operation of the processor by associating the additional entry with a particular subset of one or more contexts that includes fewer than all of the plurality of potential contexts;a first circuit configured to provide a predicted branch result determined based on at least a portion of the branch prediction information; and a second circuit configured to provide an actual branch result based on an executed branch instruction and to update the branch prediction information based on the actual branch result; wherein providing a predicted branch result for a first branch instruction comprises retrieving a first entry from a first partition of the plurality of partitions based at least in part on an identified first subset of one or more contexts associated with the first branch instruction; and wherein a total number of entries in the first partition changes during operation of the processor.

[0012] In another aspect, a method comprises: executing instructions in a pipeline of at least one processor, each instruction associated with a particular one of a plurality of potential contexts, the instructions comprising branch instructions; storing in a first memory branch prediction information indicating results of the branch instructions previously executed by the processor, wherein the first memory is dynamically partitioned into a plurality of partitions having one or more entries, and wherein the dynamic partitioning comprises updating a partition to include an additional entry during operation of the processor by associating the additional entry with a particular subset of one or more contexts that includes fewer than all of the plurality of potential contexts;Providing, by a first circuit, a predicted branch result determined based on at least a portion of the branch prediction information; and providing, by a second circuit, an actual branch result based on an executed branch instruction, and updating the branch prediction information based on the actual branch result; wherein providing a predicted branch result for a first branch instruction comprises retrieving a first entry from a first partition of the plurality of partitions based at least in part on an identified first subset of one or more contexts associated with the first branch instruction; and wherein a total number of entries in the first partition changes during operation of the processor.

[0013] The aspects may have one or more of the following characteristics.

[0014] Providing the predicted branch result for the first branch instruction comprises: calculating an index value based on a virtual address associated with the first branch instruction, determining a context-related identifier that identifies the first subset of the one or more contexts that have a context associated with the first branch instruction, and using the calculated index value and the determined context-related identifier to retrieve the first entry from the first partition.

[0015] Querying the first entry from the first partition comprises matching the determined contextual identifier with a stored contextual identifier stored in association with the first entry, and using the calculated index value to select the first entry from a range of multiple entries.

[0016] The first subset of one or more contexts includes only contexts that have an exception level value identical to an exception level value associated with the first branch instruction.

[0017] The first subset of one or more contexts of only the context associated with the first branch instruction and determining the context-related identifier that identifies the first subset comprises allocating sequence bits to identify the context associated with the first branch instruction from all contexts currently in use, wherein the allocated sequence of bits includes fewer bits than all bits associated with the context associated with the first branch instruction.

[0018] Providing the predicted branch result for the first branch instruction comprises: calculating an index value based on a virtual address associated with the first branch instruction and based on at least a portion of a context associated with the first branch instruction, and using the calculated index value to retrieve the first entry from the first partition.

[0019] Providing the predicted branch result for the first branch instruction comprises: determining a translated address translated from a virtual address associated with the first branch instruction within a virtual address space associated with a context within the first subset of one or more contexts, calculating an index value based on the translated address, and using the calculated index value to retrieve the first entry from the first partition.

[0020] Determining the translated address involves looking up a translation in a translation buffer or TLB (Translation Lookaside Buffer), and the translation lookup occurs in an earlier pipeline stage than a pipeline stage in which an instruction cache is accessed.

[0021] Providing the predicted branch result for the first branch instruction comprises: calculating a random value and storing the random value in association with the first subset of one or more contexts, calculating an index value based on the calculated random value and a virtual address associated with the first branch instruction, and using the calculated index value to retrieve the first entry from the first partition.

[0022] The branch instructions comprise conditional branch instructions, and the prediction information comprises one or both of the following: (1) branch direction predictions, which indicate whether a particular predicted branch result has a taken or T direction or a not taken or NT direction, and (2) branch target predictions, which indicate branch target addresses contained within particular predicted branch results that also have a taken or T direction.

[0023] The branch instructions comprise unconditional branch instructions and the prediction information comprises branch target predictions indicating branch target addresses intended as certain predicted branch results.

[0024] The aspects may have one or more of the following advantages.

[0025] In some cases, side effects of faulty instructions executed speculatively can persist long enough to make higher-privileged software running on the processor vulnerable to attacks by lower-privileged software. For example, some such vulnerabilities are described in "Spectre Attacks: Exploiting Speculative Execution" arXIV:1801.01203 [cs.CR] and "Meltdown" arXiv:18801.01207 [cs.CR].

[0026] A privilege level may be determined based on one or more of the following: an exception level and / or, for example, a security level, and is part of and / or determined by an instruction context. The privilege level generally determines the access rights associated with a particular context. The context associated with an instruction may include information about a privilege level, as well as information about other properties, such as that the virtual address of the instruction lies within a particular virtual address space, or that the instruction is associated with a particular virtual machine, or other attributes that define an environment in which an instruction having that context is executed. Instructions associated with different contexts are generally intended to be executed in isolation.Security concerns arise from the unintended ability to transfer information between contexts. One of the features of some processors that allows a program executing less privileged instructions to attack a program executing a higher privileged instruction is the state of a branch prediction element.

[0027] The techniques described herein are capable of mitigating certain potential vulnerabilities for certain microprocessor architectures (e.g., the ARMv8 microprocessor architecture). In particular, the techniques are capable of isolating a predictor state for different contexts, which is useful for enhanced security. For example, without such isolation, a less privileged program can "warm up" a branch predictor by executing carefully crafted code. If the more privileged program executes in the same branch prediction state, the less privileged program can predict which path will be taken by the more privileged program by timing the execution of the more privileged program, causing a security vulnerability.Isolating a predictor's state for different contexts is also beneficial for performance. Since different contexts may exhibit different branch prediction behavior, isolating the branch predictor states between contexts can also help increase branch prediction accuracy, thus improving performance.

[0028] While some existing techniques for increasing the accuracy of branch prediction could also be used to mitigate some of these vulnerabilities, they do not necessarily preserve security and performance simultaneously. For example, there are some techniques for saving and restoring a branch prediction table when a context switch occurs. However, perfectly saving and restoring an entire branch prediction table at each context switch can be so time-consuming as to become impractical. Partial or otherwise incomplete saving and restoring can allow some pollution between different contexts, increasing vulnerabilities.Also, such static partitioning of branch prediction information into separate tables does not achieve the same flexibility as dynamic partitioning of a single table (or other data structure), where different entries are assigned to different partitions during execution.

[0029] Other features and advantages of the invention will become apparent from the following description and from the claims. DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic diagram of a calculation system. Fig. Figure 2 is a schematic diagram of a processor. Fig. 3A-3F are schematic diagrams of a branch prediction circuit. Fig. Figure 4 is a state transition diagram for a 2-bit saturation counter element. DESCRIPTION

[0030] Fig. 1 shows an example of a computing system 100 in which the microprocessor architecture described herein could be used. The system 100 includes at least one processor 102, which could be a single central processing unit (CPU) or an array of multiple processor cores of a multi-core architecture. In this example, the processor 102 includes a pipeline 104, an instruction cache 106, and a data cache 108 (and other circuitry, not shown). The processor 102 is connected to a processor bus 110 that enables communication with an external memory system 112 and an input / output (I / O) bridge 114. The I / O bridge 114 enables communication over an I / O bus 116 with a variety of I / O devices 118A-118D (e.g., disk controller, network interface, display adapter, and / or user input devices such as a keyboard or mouse).

[0031] The external memory system 112 is part of a hierarchical memory system that includes multi-level caches, including the first-level (L1) instruction cache 106 and the data cache 108, and any number of higher-level caches (L2, L3, etc.) within the external memory system 112. Other circuitry (not shown) in the processor 102 that supports the caches 106 and 108 includes a translation buffer, as well as various other circuitry for handling a gap in the TLB or caches 106 and 108. For example, the TLB is used to translate an address of an instruction being fetched or data referenced from a virtual address to a physical address, and to determine if a copy of that address is in the instruction cache 106 or the data cache 108, respectively. If so, that instruction or data can be obtained from the L1 cache.If this is not the case, this gap is handled by the bridge circuit so that it can be executed by the external memory system 112. This is, of course, only an example. The exact distribution of which caches of which level are located within the processor 102 and which are located in the external memory system 112 may differ in other examples. For example, an L1 cache and an L2 cache could both be internal, and an L3 cache (or higher) could be external. The external memory system 112 also includes a main memory interface 120 connected to any number of memory modules (not shown) that serve as main memory (e.g., dynamic random access memory modules).

[0032] Branch prediction elements are an integral part of modern pipelined microprocessors. Typically, it takes multiple clock cycles to execute an instruction. For example, it requires one or more cycles for each different stage, including stages for fetching, decoding, executing, and retiring an instruction. Typically, the duration in modern microprocessors is between 10 and 25 cycles from start to finish. One potential difficulty is that when a program experiences a branch instruction, the instruction can alter the flow of control, so that the correct next instruction to be executed is not known with certainty until after the branch instruction reaches a certain stage, potentially deep in the pipeline. To avoid these difficulties, modern microprocessors employ a branch prediction element, which indicates the direction for conditional branch instructions as taken or not taken.T or not made, or NT (for example, an "IF" or "ELSE" path in a program), and / or predicts a branch instruction destination address for a non-conditional branch instruction or for a conditional branch instruction that has been made. If the prediction is correct, this allows the pipeline stages to continue receiving new instructions. But if the prediction is incorrect (i.e., a "misprediction"), there is an interrupt during which erroneous instructions are eliminated.

[0033] To predict the direction or target address of a branch instruction, the branch prediction elements include a memory for different branch prediction information and circuitry for setting and updating the branch prediction information, as will be described in more detail below. The branch prediction information may be stored in a variety of data structure types within a memory circuit, such as a memory circuit organized as a table representing a collection of entries accessed using an index value. The index is typically formed based on certain predetermined bits of the program counter element, or PC. For example, different bits of the PC are combined with a bitwise function, such as an XOR, to create an index in a branch prediction data structure.

[0034] The PC used to fetch the next instruction for execution is typically a virtual address of an instruction, where this virtual address is associated with a specific process (e.g., within a virtual address space associated with that process). This causes potential interference between different processes when they index into the branch prediction data structure, since the branch behavior of different processes typically differs. For example, system code executing at a higher privilege level (e.g., a higher exception level) would exhibit different branch behavior than user code executing at a lower privilege level (e.g., a lower exception level).The same virtual address for a branch instruction from two different processes may map to the same index, but these branch instructions may have different branch behaviors (e.g., one is T and the other is NT). As a result, the branch prediction state of one process may corrupt the branch prediction state of the other process.

[0035] Fig. 2 shows an example in which processor 102 is a superscalar processor configured to use branch prediction for speculative execution of instructions. Processor 102 includes circuitry for the various stages of pipeline 104. For one or more instruction fetch stages, instruction fetch circuitry 200 provides a PC to instruction cache 106 to fetch instructions fed into pipeline 104. For example, the PC may be a virtual address of the next instruction, in which case the PC may be incremented by the length of a virtual address in the case of sequential execution (i.e., without taking any branches of the branch instructions). Fetch circuitry 200 also provides the program count element to branch prediction circuitry 201; which will be used to provide a predicted result for branch instructions, as will be described in more detail below.In some implementations, part or all of branch prediction circuitry 201 is considered part of fetch circuitry 200. For one or more instruction decode stages, instruction decode stage 202 stores information in a buffer 204 for instructions in the instruction window awaiting issue.

[0036] Issue circuitry 206 determines in which cycle instructions in buffer 204 should be issued, making them available for progression through the circuitry of execution stages 208A, 208B, and 208C of pipeline 104. (This example has three execution stages, but other examples may have more or fewer execution stages.) There is at least one commit stage 210 that commits results of instructions that have progressed through execution stages 208A, 208B, and 208C. For example, commit stage circuitry 217 may write a result back to a register file (not shown).

[0037] The command window includes instructions that have not yet been issued (in buffer 204), as well as instructions that have been issued but are still executing, or "in transit," and have not yet committed. As instructions are issued, more instructions are added to the command window by being stored in buffer 204. Instructions leave the command window after they have been committed, but not necessarily in one-to-one correspondence with instructions that are added to the command window. Therefore, the size of the command window can vary. Instructions are added to the command window in order (i.e., according to a program order) and leave the command window in order. But in some implementations, instructions may be issued and / or executed out of order.

[0038] Between adjacent stages of the pipeline 104, the various paths through the pipeline circuitry indicate pipeline registers 211 (shown in Fig. 2 for the execution stages) that store the results of an upstream stage waiting to be passed down to the next stage. The pipeline registers 211 may be clocked by (i.e., receive a clocking signal derived from) a common clock (not shown). Thus, in each clock cycle, each pipeline register 211 (also referred to as a latch or set of flip-flops) passes a result from its input to its output and becomes ready to accept a new result into its input after the result has been generated by that stage's circuitry.

[0039] There can be multiple separate paths through the execution stages, each with different circuitry for executing different types of instructions. Fig. 2, two paths 208A and 208B are shown, but the execution stages may include any number of paths with associated circuitry separated by pipeline registers 211. The number of paths through the execution stages generally depends on the specific architecture, but may include sufficient paths that a number of instructions up to the issue width can advance through the same execution stages in the same cycle. The number of stages comprising functional circuitry for a given path may also vary. In this example, the first path 212A includes functional circuits 214A, 214B, and 214C located in the first execution stage 208A, the second execution stage 208B, and the third execution stage 208C, respectively. The second path 212B includes functional circuitry 216A and 216B located in the first execution stage 208A, and the third execution stage 208C, respectively.the second execution stage 208B, with the third execution stage 208C simply being a "silo stage" that passes a result without performing any further computation, thereby ensuring that each path progresses through the pipeline through the same number of stages. One path may include circuitry for executing memory instructions, another path may include a unit for various operations (e.g., ALU, multiplier, floating point unit), and yet another path may include circuitry for calculating branch conditions for branch instructions, providing an actual result of the branch instruction (e.g., 1: taken, 0: not taken) based on a branch condition for updating the branch prediction circuit 201.

[0040] One effect that branch prediction circuit 201 has on pipeline 104 is to cause certain stages of the pipeline to flush under certain circumstances. Specifically, there are two distinct circumstances in which flushing or partial flushing can occur.

[0041] In an example of a first circumstance, after a branch condition has been evaluated and an actual branch result is determined during the execution of a branch instruction, the actual branch result is compared to the predicted branch result previously provided by the branch prediction circuit 201. If the predicted branch result matches the actual branch result, then the prediction was correct. However, if the predicted branch result does not match the actual branch result, then a misprediction has occurred and all stages of the pipeline are flushed, and the entire pipeline is restarted at the branch target instruction (if the actual branch result is taken, or T) or the failure instruction (if the actual branch result is not taken, or NT).

[0042] In an example of a second circumstance, a partial flush occurs, which may only be required for the earlier stages in the pipeline. The fetch circuit 200 will typically send incrementing values ​​of the PC to the instruction cache 106. After the instructions return from the instruction cache and are decoded by the decode circuit 202, the branch prediction circuit 201 may output a predicted branch result indicating a taken branch. At this point, the two previous PC addresses sent to the instruction cache in the two previous cycles are in error because they applied to instructions sequentially after the branch instruction and not to the branch target. The values ​​of the pipeline stages associated with these two cycles of instructions coming from the instruction cache 106 are neglected.not taken into account, but not other values ​​deeper in the pipeline 104 (associated with earlier instructions that are not affected by the predicted jump result taken).

[0043] The branch prediction information used to determine predicted branch outcomes is a potential security vulnerability when shared between different contexts. An attacker program executing in a different context than a higher-privileged attacked or victim program is capable of "warming up" a shared branch prediction element so that when the victim program executes a particular branch instruction (e.g., associated with a particular IF statement executed as part of a system call), a particular predicted branch direction is provided. The attacker program can be configured (e.g., by reverse-engineering code of the victim program) to enforce a predetermined predicted branch direction, either deterministically or with high probability.For example, a particular entry within a branch prediction data structure associated with a particular virtual address of the particular branch instruction may be known, and the attacker program can train that particular entry to force the predetermined direction, which is provided as the resulting predicted branch direction. Alternatively, the attacker program can train multiple entries or all entries to provide the predetermined direction. If the forced direction was an incorrect prediction, the execution of the particular instruction will take longer than if the forced direction was a correct prediction. The attacker program is then able to learn which actual branch direction was taken by the victim program by measuring the number of clock cycles that elapse to complete the execution of the particular instruction.This is just one example of potential information at risk of being learned by the attacker's program—other potential vulnerabilities are also possible. For example, the attacker's program can force a predetermined, predicted jump destination address to be provided.

[0044] Some techniques for mitigating the vulnerabilities associated with sharing branch prediction state between different contexts rely on an initial translation of the virtual address of a particular branch instruction that the PC provides to the branch prediction circuitry. Modern processors support virtual memory, which allows program instructions executed by a CPU to reference data using virtual addresses within a virtual address space larger than a physical address space defined by the size of main memory. The instructions themselves, which are also stored in memory, can also be referenced using virtual addresses. Virtual memory involves address translation from one or more such virtual address spaces to a physical address space.The translation is performed using a page table that stores the mappings between virtual addresses and physical addresses at a granularity of memory pages. Some processors also support various types of virtualization that involve virtual machines, or VMs. For example, a hypervisor (also known as a virtual machine monitor, or VMM) can run on the physical system to manage all of the guest operating systems of a virtualized system. The hypervisor runs at a higher privileged access level than the guest operating systems. This means that only the hypervisor has access to the physical address space. Therefore, each guest operating system is provided with its own intermediate physical address space, into which one or more virtual address spaces are translated, and the hypervisor translates the intermediate physical addresses into physical addresses.

[0045] When establishing a translation from a particular virtual address to a particular physical address or intermediate physical address, various types of context information are used to distinguish otherwise identical virtual addresses from one another. This allows multiple independent virtual address spaces to exist for different processes, different virtual machines, or any variety of other distinguishing characteristics that support different virtual address spaces. Different pieces of context information can be used to distinguish between virtual addresses used within different virtual address (VA) to physical address (PA) translations (or VA to intermediate physical address (IPA) translations, or IPA to PA translations).For example, an operating system may use an address space identifier (ASID) (e.g., 16 bits) to identify a memory space (a virtual address space) associated with a running process. A hypervisor may use a virtual machine identifier (VMID) (e.g., 16 bits) to identify a memory space (intermediate physical address space) associated with a guest operating system of a virtual machine. Certain parameters may be associated with different classes of processes or software environments available in an architecture, such as a security state with values ​​of secure (S) or non-secure (NS), or an exception level (also called a priority level), for example, with values ​​of EL0 - EL3 (for a 2-bit exception level).All of this context information has in common a context (also called a "translation context" or a "software context") for a particular virtual address (e.g., the virtual address of an instruction such as a jump instruction).

[0046] Fig. 3A-3F show different examples of branch prediction circuitry configured to apply different techniques to mitigate vulnerabilities associated with sharing branch prediction state between different contexts.

[0047] Fig. 3A shows a branch prediction circuit 301A configured to perform branch prediction using a technique based on address translation. Two different processes, such as a process running an attacker program and a process running a victim program, will generally have different contexts. Typically, predetermined bits of a virtual address are used to generate an index value used to access an entry within the branch prediction data structure. Virtual addresses that have a different context but happen to share these predetermined bits (or happen to be identical, sharing all bits) would then result in the same index value, which could lead to some of the vulnerabilities described above.Thus, instead of indexing the branch prediction data structure using the virtual address, this address translation technique uses a physical address (or intermediate physical address) to generate the index value. An address translation module 302 performs this address translation on a virtual address of a received instruction (corresponding to the program counter value) to provide a physical address of the instruction to index logic 304A. Alternatively, the translated address provided to index logic 304A could be an intermediate physical address of the instruction. Determining a translated address translated from a virtual address may include looking up a translation in a translation buffer, or TLB.

[0048] Predetermined bits of this instruction's physical address are then used (e.g., using exclusive OR or XOR operations, respectively) to generate an index value to access an entry of the branch prediction data structure stored in the branch prediction information memory 306. Since virtual address spaces for different processes (with different contexts) are typically mapped into separate areas in the physical address space (perhaps partially shared), this increases the chances that the entries will differ between different processes. This also reduces certain types of vulnerabilities, since lower-privileged processes typically cannot predict which particular physical address can be mapped to a particular virtual address for a context different from their own (e.g., for a context of a higher-privileged process).For example, the address translation module 302 may include additional microtranslation buffers. While such a translation may add additional cycles to the pipeline front-end, the benefits in prediction accuracy may outweigh the cost of such a translation. In some implementations, even when a translation of an instruction's virtual address is performed for other reasons (e.g., for an instruction cache 106 that is physically indexed and / or physically tagged), the translation for branch prediction may occur earlier (e.g., the translation is initiated in an earlier pipeline stage) than it would for accessing the instruction cache. For example, the translation lookup may occur in an earlier pipeline stage than a pipeline stage at which the instruction cache is accessed.

[0049] Each entry of the branch prediction data structure (associated with a particular index) will store branch prediction information for one or more instruction addresses. The branch prediction information is used to determine a predicted branch outcome. For example, the branch prediction information may comprise a 2-bit value of a bimodal branch direction prediction element, such as the 2-bit saturation count element described below with reference to Fig. 4. States "10" or "11" indicate that the branch should be predicted as taken (T), and states "00" and "01" indicate that the branch should be predicted as not taken (NT). The information stored in and provided from the branch prediction information memory 306 varies for different types of branch instructions, including conditional branch instructions and unconditional branch instructions. For conditional branch instructions, the information stored within indexed entries includes branch direction predictions that indicate whether a particular predicted branch result has a taken (T) direction or a not taken (NT) direction. For conditional branch instructions, there may also be branch target predictions, either in the same data structure or in an associated data structure (e.g., a branch target buffer) indexed by the same index value.The branch target predictions indicate branch target addresses contained within specific predicted branch results, which also have a taken (T) direction. For unconditional branch instructions, since no direction is required (since the branch is always taken), the information stored within indexed entries includes the branch target predictions, which indicate branch target addresses intended as specific predicted branch results.

[0050] The predicted branch result is provided as output from branch prediction circuit 301A and is also fed back within the circuit to update logic 308. Update logic 308 also receives the actual branch result from a later stage of the pipeline to update the information within branch prediction information memory 306. The index value can also optionally be calculated using other information in addition to the virtual or physical address of a program counter element. In the illustrated examples, update logic 308 is used to update a global history memory 310, which stores branch history information in the form of a bit vector representing the past history of branch results for the last series of branch instructions.For example, the bit vector may be stored in a shift register that is updated based on actual branch results provided by the commit stage circuit 217. When a new bit value is shifted into the bit vector (where a 1 represents a taken branch or a 0 represents a not taken branch), the oldest bit value is shifted out of the end. Index logic 304A may combine bits from the global history with bits from the PC address to calculate the index value.

[0051] Fig. 3B shows branch prediction circuitry 301B configured to perform branch prediction using a context-related identifier (CID)-based technique, which can be used to dynamically partition memory 306 into partitions of varying sizes (e.g., a variable number of entries). Each entry in the branch prediction data structure can be marked with a calculated context-related identifier (CID), which is calculated by CID calculation circuitry 312 based on at least a portion of the received context information associated with the virtual address of the branch instruction represented by the received PC. Index logic 304B calculates an index value for a given branch instruction based on the untranslated virtual address represented by the PC.The CID for a given branch instruction is stored in a portion of memory 306 used for tagging entries, referred to as CID memory 314. CID calculation circuitry 312, CID memory 314, and other circuitry of branch prediction information memory 306 may be configured similarly to the circuitry within an associatively set cache, with the CID acting as the cache tag and the index value acting as the cache index. For example, a CID may be stored as part of a tag within a content-addressable memory (CAM), or as part of a tag distinguishing different areas of a random access memory (RAM).

[0052] The CID represents either full context information or partial context information. For example, in some architectures, full context information may comprise 35 bits: 2 bits for the exception level (EL), 1 bit for the non-secure / secure (NS / S) value, 16 bits for the VMID, and 16 bits for the ASID. Such full context information will more completely identify processes among themselves, helping to mitigate security vulnerabilities. However, there is a potentially significant overhead in terms of the integrated circuit area allocated to the CID memory 314. To reduce the overhead, the CID may include partial context information, such as only 16 bits for the VMID and 2 bits for the EL.Such partial context information would uniquely identify distinct subsets of contexts, where each subset contains fewer than all contexts, and each subset does not overlap with any other subset. This can prevent one VM from contaminating another VM's branch prediction element.

[0053] Alternatively, instead of simply concatenating subsets of bits from the full context information, techniques may be used that essentially compress the full context information into fewer bits. The CID calculation circuit 312 may calculate a CID configured to comprise fewer bits than the full context information, where these bits are assigned based on a stored mapping between CIDs and corresponding rows of the full context information. The mapping may be stored in the branch prediction circuit 301B. While the mapping itself occupies space on the integrated circuit, space may be saved in the CID memory 314. This effectively mitigates some of the vulnerabilities because only a relatively small number of contexts are currently in use at any one time (i.e., contexts that have been mapped by the stored mapping).Instead of a maximum of billions of simultaneous contexts (where 35 bits are 2. 35 or 32 billion different contexts) it may be sufficient for a modern microprocessor to be able to process thousands, or hundreds, or even dozens of simultaneous contexts (e.g. 6 bits result in 2 6or 64 different contexts). Consequently, if each currently-used context is mapped to a unique CID, there remains the same ability to mitigate certain security vulnerabilities as exists when using the full context information. In other words, the CID is assigned as a sequence of bits to uniquely identify the context associated with a particular branch instruction among all currently-used contexts, where the assigned sequence of bits contains fewer than all of the bits associated with the context associated with the particular branch instruction. Additional details on techniques for compressing context information can be found, for example, in U.S. Patent No. 9,779,028, entitled "MANAGING TRANSLATION INVALIDATION."

[0054] Fig. 3C shows a branch prediction circuit 301C configured to perform branch prediction using a technique also based on context information. However, instead of calculating a separate CID, the index logic 304C uses both the virtual address of the branch instruction represented by the PC and the context information (full or partial) to calculate an index value (e.g., using predetermined bits of each combined using XOR operations). This technique will probabilistically reduce collisions between different processes and consequently reduce the likelihood of one process contaminating another process's branch prediction information, further mitigating security vulnerabilities.

[0055] Fig. 3D shows a branch prediction circuit 301D configured to perform branch prediction using a technique based on randomization. The random value may be generated using any of a variety of techniques. For example, pseudorandom number generation may be performed by hardware using a device such as a linear-feedback shift register (LFSR) and / or a non-digital device on the integrated circuit implemented by the processor, such as a device comprising analog circuitry. Alternatively, a random value may be generated by software using a suitable algorithm, or by a combination of hardware and software. Circuit 301D includes circuit 316 for generating and storing random values.Circuitry 316 is capable of generating a random value for each context, or for each subset of contexts, and storing that random value in association with that context or subset of contexts (e.g., a subset of contexts mapped to a particular CID). Index logic 304D then uses both the virtual address of the branch instruction, represented by the PC, and the determined random value to calculate an index value. For example, the calculation may use a hash function that takes both the PC and the random value as input and generates an index value (e.g., using XOR operations). The stored random values ​​may be changed periodically to further mitigate potential security vulnerabilities, with some performance degradation when the implicit partitioning represented by the index value calculation changes.Storing random values ​​with access restricted to high privilege levels mitigates some potential security vulnerabilities because an attacker with a lower privilege level will not be able to access the random values.

[0056] Fig. 3E shows branch prediction circuitry 301E configured to perform branch prediction using a technique based on varying selection within multiple different prediction elements. Varying selection prevents an attacker program from reliably forcing an erroneous prediction by prediction circuitry 301E. One way this can be accomplished, for example, is by randomizing the prediction element to be used and, consequently, randomizing its corresponding prediction for at least one or more higher privilege levels. In this way, an attacker program at a lower privilege level is unable to reliably "warm up" the prediction used by a victim program at a higher privilege level.

[0057] In this example, index logic 304B, which calculates an index value for a given branch instruction based on the untranslated virtual address represented by the PC, may be used. Alternatively, any of the preceding techniques of Fig. 3A-3D to implement a first prediction element that provides a branch result predicted by a first prediction element. In addition, this example includes a prediction element selector 3018 that provides a predicted branch result for at least some branch instructions based on a selected prediction element of the plurality of prediction elements. The circuit 301E includes at least one additional prediction element that Fig. 3E as a second prediction element 320 providing a branch result predicted by a second prediction element to the prediction element selector 318. In other examples, there could be a third prediction element providing a branch result predicted by a third prediction element to the prediction element selector 318, or any number of additional prediction elements. The second prediction element 320 determines its predicted branch result independently of the branch prediction information within the memory 306. Because the second prediction element 320 provides the predicted branch results independently of the branch prediction information, the second prediction element 320 does not need to update the branch prediction information stored in the memory 306 based on an actual branch result provided later in the pipeline.This can be accomplished, for example, by disabling the update provided by update logic 308 or by ignoring its output when selecting second prediction element 320. Thus, by selecting a result from one of the prediction elements to provide the predicted branch result output by branch prediction circuit 301E, prediction element selector 318 reliably prevents an attacker program from forcing an erroneous prediction, even if it is able to "warm up" or otherwise manipulate the branch prediction information within memory 306.

[0058] For some branch instructions, such as branch instructions with a lower privilege level (e.g., corresponding to lower exception levels EL0 and EL1), as determined by context information fed to the prediction element selector 318, a first operating mode may be selected in which the branch result predicted by the first prediction element is used. However, there may be a certain class of branch instructions, such as branch instructions associated with a privilege level in a subset of higher privilege levels (e.g., corresponding to the higher exception levels EL2 and EL3), for which a second operating mode is used. For example, the second mode may be selected by setting a bit stored in the hardware.The second mode may be selected after checking the context information for each instruction, or the predictor selector 318 may make a decision to enter or exit the second mode at a coarser granularity rather than for each instruction, such as for groups of instructions that, for example, lie within a privileged region of the code. In the second mode of operation, the predictor selector 318 actively varies the selection of an active predictor for different branch instructions for which the predicted branch result of the selected predictor is intended.Varying the selection may be done in a manner that is not easily determined by an attacker program running at a lower privilege level, such as based on a hardware pseudorandom number generator within the predictor selector 318 or a random value generated by a victim program running at a higher privilege level (e.g., at one of the same privilege levels for which the second mode of operation is used).

[0059] In one example, there are two additional prediction elements in addition to the first prediction element that uses the branch prediction information in memory 306. The additional prediction element provides a first constant branch result value as the predicted branch result for all virtual addresses of the branch instructions, such as a constant "0" for a not-taken (NT) branch result. Another prediction element provides a second constant branch result as the predicted branch result for all virtual addresses of the branch instruction (different from the first constant branch result), such as a "1" for a taken (T) branch result. The prediction element selector 318 may randomly select from the three prediction elements, or may randomly select from two of the three prediction elements.While omitting the first prediction element may be detrimental to performance, it would still mitigate certain security vulnerabilities.

[0060] Alternatively, in another example, the prediction element selector 318 may select between the first and second modes of operation, but in the second mode of operation, the prediction may be configured to always provide a constant branch result (e.g., a constant "0" for a not-taken or NT branch result).

[0061] In some examples, processor 102 is configured to perform an operation as part of mitigating security vulnerabilities, and predictor selector 318 is configured based on at least a portion of that operation. For example, it may be useful to flush some or all of the memory structures on processor 102 in response to executing a privileged branch instruction or entering a privileged region of code. In particular, by flushing branch prediction information memory 306, any information created by an attacker program may be removed. In some processors, there is specialized circuitry that may be used to perform operations to flush memory structures.Flushing a memory structure removes the information stored in that structure, such as by setting all bits to a predetermined pattern, such as all zero bits, or a random pattern. When flushing branch prediction information memory 306 using a "flush" operation and access to memory 306 is prevented during the flush operation, it may be useful to allow other instructions to continue during the flush operation, as the flush operation may require multiple cycles (e.g., thousands of cycles) before it is completed. In such examples, predictor selector 318 may be configured to select second predictor 320 during the flush operation, and second predictor 320 may be configured to provide a constant branch result during the flush operation.

[0062] Processors and other integrated circuits can be complex and may include specialized circuitry that supports testing and otherwise managing various structures on a manufactured chip. For example, in addition to one or more processor cores, there may be various memory structures and devices that provide a variety of functionality used by—or in conjunction with—a processor. One type of circuitry that enables testing and management of such structures is based on built-in self-test (BIST) and built-in self-repair (BISR) techniques. A BIST module of an integrated circuit may support a variety of instructions that perform operations such as flushing memory structures that include branch prediction information memory 306.The operations that flush memory structures can be performed in different modes. For example, a "reset mode" can flush all memory structures on the processor (e.g., as part of booting a system using the processor), and a "non-reset mode" can flush only a specified set of one or more memory structures without flushing all memory structures on the processor. To reduce the number of cycles required to perform a flush operation, a BIST flush operation can be used in the non-reset mode, with memory 306 specified as the particular memory structure to be flushed.

[0063] Fig. 3F shows branch prediction circuitry 301F configured to perform branch prediction using an obfuscation technique that obfuscates branch target addresses stored in a portion of branch prediction information memory 306 that stores the branch target addresses, referred to as a branch target buffer 322. By obfuscating at least some branch target addresses (e.g., branch target addresses for branch instructions with context information indicating them as higher-privileged instructions), certain potential vulnerabilities can be mitigated. Updating the branch prediction information stored in memory 306 is still performed based on an actual branch result for a given execution of a particular branch instruction.But if a jump target address is included in the actual jump result (for an unconditional jump instruction or for a conditional jump instruction that resulted in a direction taken), then that jump target address is obfuscated by the obfuscation circuit 330.

[0064] In particular, obfuscation circuitry 330 calculates a random value (e.g., a pseudorandom number) and stores this random value in association with an identified subset of one or more contexts (e.g., using a CID, as described above, identifying a subset of contexts associated with the particular branch instruction). In this example, memory 340 stores the random values ​​in a data structure, such as a table indexed by the CIDs. Obfuscation circuitry 330 obfuscates the branch target address based at least in part on the random value. For example, obfuscation may include performing an exclusive-OR or XOR operation on the branch target address and the random value.The resulting obfuscated value output by the obfuscation circuit 330 is stored in a branch prediction information memory 306 using the same index value that would have been used without the obfuscation.

[0065] When branch prediction circuit 301F provides a predicted branch result for a subsequent execution of the particular branch instruction whose previous results were obfuscated, deobfuscation circuit 332 is used. Specifically, after retrieving the obfuscated value from branch prediction information memory 306 and retrieving the random value from memory 340, the deobfuscation circuit deobfuscates the obfuscated value using the random value to restore the actual branch result as the predicted branch result. For example, deobfuscation may involve performing an exclusive-OR operation on the obfuscated value and the random value. This works because performing an XOR operation twice using the same value does not result in any change to the bits of the value on which the operation is performed.Each bit is flipped only once and then flipped back to its original value. Alternatively, any of a variety of other pairs of operations with this property could be used by obfuscation circuit 330 and deobfuscation circuit 332 to obfuscate the bits of the jump target addresses stored in the BTB. However, one advantage of the XOR operation is its speed.

[0066] In other examples of the obfuscation technique, the branch prediction circuit does not have dedicated obfuscation and deobfuscation circuitry in the special-purpose hardware; instead, the transformations are performed by software executed by the general-purpose hardware of the processor 102.

[0067] Fig. Figure 4 shows an example of a state transition diagram 400 for a 2-bit saturation counter that can be used to provide a predicted jump direction. There are two values ​​of the 2-bit state variable (10 and 11) that predict a committed outcome, and two values ​​of the 2-bit state variable (01 and 00) that predict a non-committed outcome. Based on the state transitions in diagram 400, it can be seen that it takes two of the same actual jump outcomes in a row to switch from predicting one outcome to predicting the other outcome. The states are also known as "strong not committed" (00), "weak not committed" (01), "strong committed" (11), and weak committed (10).

[0068] In the example of Fig. 3B, storing different CIDs in the CID memory 314 in conjunction with different entries creates an explicit, dynamic partitioning of the memory 306 into different partitions. However, there is also a form of implicit, dynamic partitioning, which is used in the address translation example of Fig. 3A above and in the examples of Fig. 3C and Fig. 3D above, given that different context information maps a virtual address of a branch instruction to different, non-overlapping partitions of entries.

[0069] Techniques from different examples can also be combined in different ways. For example, in the example of the Fig. 3B, the index logic 304B determines an index value based on the untranslated virtual address represented by the PC, but in other examples, the translation of the example into Fig. 3A and the CID calculation of the example in Fig. 3B can be combined.

[0070] Other embodiments are within the scope of the following claims.

Claims

[1] An integrated circuit (201, 301) comprising: at least one processor (102) executing instructions in a pipeline (104), each instruction being associated with a particular translation context of a plurality of potential translation contexts used to distinguish otherwise identical virtual addresses from one another, and wherein the instructions include branch instructions; a first store (306) for branch prediction information characterizing results of branch instructions previously executed by the processor (102), wherein the first store (306) is dynamically partitioned into a plurality of partitions of one or more entries, and wherein the dynamic partitioning comprises updating a partition to include an additional entry during operation of the processor (102) by associating the additional entry with a particular subset of a plurality of translation contexts containing fewer than all of the plurality of potential translation contexts; a first circuit configured to provide a predicted branch result determined based on at least a portion of the branch prediction information; and a second circuit configured to provide an actual branch result based on an executed branch instruction and to update the branch prediction information based on the actual branch result; wherein providing a predicted branch result for a first branch instruction comprises retrieving a first entry from a first partition of the plurality of partitions based on an identified first subset of a plurality of translation contexts associated with the first branch instruction; and where a total number of entries in the first partition changes during the operation of the processor, wherein the first subset of multiple translation contexts comprises only translation contexts having an exception level value identical to an exception level value associated with the first branch instruction. [2] The integrated circuit (201, 301) of claim 1, wherein providing the predicted jump result for the first jump instruction comprises: Calculating an index value based on a virtual address associated with the first branch instruction, Determining a contextual identifier that identifies the first subset of a plurality of translation contexts that has a translation context associated with the first branch instruction, and using the calculated index value and the determined contextual identifier to retrieve the first entry from the first partition. [3] The integrated circuit (201, 301) of claim 2, wherein retrieving the first entry from the first partition comprises matching the determined contextual identifier with a stored contextual identifier stored in association with the first entry, and using the calculated index value to select the first entry from a set of multiple entries. [4] The integrated circuit (201, 301) of claim 1, wherein providing the predicted jump result for the first jump instruction comprises: Calculating an index value based on a virtual address associated with the first branch instruction and based on at least a portion of a translation context associated with the first branch instruction, and Use the calculated index value to retrieve the first entry from the first partition. [5] The integrated circuit (201, 301) of claim 1, wherein providing the predicted jump result for the first jump instruction comprises: Determining a translated address translated from a virtual address associated with the first branch instruction within a virtual address space associated with a translation context within the first subset of multiple translation contexts, Calculate an index value based on the translated address, and use the calculated index value to retrieve the first entry from the first partition. [6] The integrated circuit (201, 301) of claim 5, wherein determining the translated address comprises looking up a translation in a translation lookaside buffer, and wherein looking up the translation occurs in a pipeline stage earlier than a pipeline stage at which an instruction cache is accessed. [7] The integrated circuit (201, 301) of claim 1, wherein providing the predicted jump result for the first jump instruction comprises: Calculating a random value and storing the random value in conjunction with the first sub-sentence from multiple translation contexts, Calculating an index value based on the calculated random value and a virtual address associated with the first branch instruction, and Use the calculated index value to retrieve the first entry from the first partition. [8] The integrated circuit (201, 301) of claim 1, wherein the branch instructions comprise conditional branch instructions, and the prediction information comprises one or more of the following: (1) branch direction predictions indicating whether a particular predicted branch result has a taken direction (T direction) or a not taken direction (NT direction), and (2) branch target predictions indicating branch target addresses contained within the particular predicted branch results that also have a T direction. [9] The integrated circuit (201, 301) of claim 1, wherein the branch instructions comprise unconditional branch instructions, and wherein the prediction information comprises branch target predictions indicating branch target addresses that are provided as certain predicted branch results. [10] The integrated circuit (201, 301) of claim 1, wherein the first subset of multiple translation contexts comprises a particular translation context used to translate a virtual address of the first branch instruction. [11] The integrated circuit (201, 301) of claim 1, wherein each particular subset of a plurality of translation contexts specifies a unique value for each of two or more of a plurality of values ​​that together comprise a particular translation context, and wherein the plurality of values ​​comprises an exception level and at least one of the following: an address space identifier, a virtual machine identifier, a security state. [12] A method comprising: Executing instructions in a pipeline (104) of at least one processor (102), each instruction being associated with a particular translation context of a plurality of potential translation contexts used to distinguish otherwise identical virtual addresses from one another, and wherein the instructions include branch instructions; Storing, in a first memory (306), branch prediction information characterizing results of branch instructions previously executed by the processor (102), wherein the first memory (306) is dynamically partitioned into a plurality of partitions of one or more entries, and wherein the dynamic partitioning comprises updating a partition to include an additional entry during operation of the processor (102) by associating the additional entry with a particular subset of a plurality of translation contexts containing fewer than all of the plurality of potential translation contexts; Providing, from a first circuit, a predicted branch result determined based on at least a portion of the branch prediction information; and Providing, from a second circuit, an actual branch result based on an executed branch instruction, and updating the branch prediction information based on the actual branch result; wherein providing a predicted branch result for a first branch instruction comprises retrieving a first entry from a first partition of the plurality of partitions based on an identified first subset of a plurality of translation contexts associated with the first branch instruction; and wherein the total number of entries in the first partition changes during operation of the processor (102), wherein the first subset of multiple translation contexts comprises only translation contexts having an exception level value identical to an exception level value associated with the first branch instruction. [13] The method of claim 12, wherein providing the predicted branch result for the first branch instruction comprises: calculating an index value based on a virtual address associated with the first branch instruction; determining a contextual identifier identifying the first subset of a plurality of translation contexts having a translation context associated with the first branch instruction; and using the calculated index value and the determined contextual identifier to retrieve the first entry from the first partition. [14] The method of claim 13, wherein retrieving the first entry from the first partition comprises matching the determined contextual identifier with a stored contextual identifier stored in association with the first entry, and using the calculated index value to select the first entry from a set of multiple entries. [15] The method of claim 12, wherein providing the predicted branch result for the first branch instruction comprises: Calculating an index value based on a virtual address associated with the first branch instruction and based on at least a portion of a translation context associated with the first branch instruction, and Use the calculated index value to retrieve the first entry from the first partition. [16] The method of claim 12, wherein providing the predicted branch result for the first branch instruction comprises: Determining a translated address translated from a virtual address associated with the first branch instruction within a virtual address space associated with a translation context within the first subset of multiple translation contexts, Calculating an index value based on the translated address, and Use the calculated index value to retrieve the first entry from the first partition. [17] The method of claim 16, wherein determining the translated address comprises looking up a translation in a translation lookaside buffer, and wherein looking up the translation occurs in an earlier pipeline stage in which an instruction cache is accessed. [18] The method of claim 12, wherein providing the predicted branch result for the first branch instruction comprises: Calculating a random value and storing the random value in conjunction with the first sub-sentence from multiple translation contexts, Calculating an index value based on the calculated random value and a virtual address associated with the first branch instruction, and Use the calculated index value to retrieve the first entry from the first partition. [19] The method of claim 10, wherein the branch instructions comprise conditional branch instructions, and wherein the prediction information comprises one or more of the following: (1) branch direction predictions indicating whether a particular predicted branch result has a taken direction (T) or a not taken direction (NT), and (2) branch target predictions indicating branch target addresses contained within the particular predicted branch results that also have a T direction. [20] The method of claim 10, wherein the branch instructions comprise unconditional branch instructions, and wherein the prediction information comprises branch target predictions indicating branch target addresses that are provided as certain predicted branch results. [21] The method of claim 12, wherein the first subset of multiple translation contexts comprises a particular translation context used to translate a virtual address of the first branch instruction. [22] The method of claim 12, wherein each particular subset of a plurality of translation contexts specifies a unique value for each of two or more of a plurality of values ​​that together comprise a particular translation context, and wherein the plurality of values ​​comprises an exception level and at least one of the following: an address space identifier, a virtual machine identifier, a security state.

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