Integrated multiplying analog-to-digital converter with successive approximation

Abstract

Analog / digital converter ADC designed to convert an analog input signal into a digital output signal with N bits o n , n ∈ (0, ..., N-1}, wherein the ADC comprises a controller (100), a digital / analog converter DAC (11) and a comparator (12), wherein - the comparator (12) is designed to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC (11); - the controller (100) is designed to receive the binary signal generated by the comparator (12) and, based on the binary signal, to generate a digital control signal comprising N bits c n , n ∈ (0, ..., N-1}, contains; - the DAC (11) is adapted to generate the analog output signal based on the digital control signal generated by the controller (100); wherein the controller (100) comprises: a register adapted to store a previous sum value, and an adder adapted to determine a test sum value by, when the ADC sets the bit o n of the digital output signal, the previous sum value and a test value that is 2 n times a gain factor is added.

Description

[0001] This document relates to analog-to-digital converters (ADCs). In particular, this document relates to successive approximation ADCs (SAR ADCs), which convert a continuous analog waveform into a discrete digital representation using a binary search. background

[0002] Fig. Figure 1 shows an exemplary analog-to-digital converter (ADC) based on the principle of successive approximation (SAR). Typically, such an ADC includes an analog voltage comparator 12 for comparing an analog input voltage with the output of an internal digital-to-analog converter (DAC) 11 and for outputting the comparison result to a SAR logic unit 10. Although Fig.1 shows a circuit alternative in which the analog input voltage is applied via a multiplexer 13, switching elements 14, and a capacitor 16 to the same input terminal of the comparator 12 to which the output of the DAC 11 is connected (also via switching elements 14 and a capacitor 16). It can be assumed that—in a simplified ADC design—the analog input voltage and the output signal of the DAC 11 are applied to two different terminals of the comparator 12. For example, the analog input voltage can be applied to the inverting input of the comparator 12, and the output voltage of the DAC 11 can be applied to the non-inverting input of the comparator 12, or vice versa.

[0003] The following is an overview of the SAR algorithm with reference to the Fig.1 is given. The SAR logic unit 10 is initialized so that the most significant bit (MSB) is equal to a digital 1. In Fig.For example, bit D7 may be set to 1 while the remaining bits D6 through D0 are set to 0. This digital code D7-D0 is fed to the DAC 11, which then provides the analog equivalent of this digital code to the comparator 12 for comparison with the analog input voltage. If the output voltage of the DAC 11 exceeds the analog input voltage, the comparator 12 causes the SAR logic unit 10 to reset this bit; otherwise, the bit remains set to 1. Then, the next bit is set to 1 and the same test is performed, continuing this binary search until each bit D7-D0 has been tested. The resulting code D7-D0 is the digital approximation of the analog input voltage and is finally output as an 8-bit result at the end of the conversion by the ADC.

[0004] Typically, the digital output signal provided by the ADC converter must be calibrated to compensate for design variations and / or to map the digital output signal to a desired range. For example, the analog input signal may represent a temperature measurement, and the raw data of the digital output signal must be mapped to degrees Celsius. For this purpose, a slope correction factor and an offset can be determined to calibrate the digital output signal accordingly. Generally, both the slope correction factor and the offset can be determined in a pre-operational phase of the ADC by analyzing at least two uncalibrated ADC conversion results. During ADC operation, the digital output signal of the DAC 11 is multiplied by the determined slope correction factor in a multiplier 18, and the determined offset is added to this signal in an adder 19.

[0005] However, current ADC calibration and mapping techniques require a separate block to perform the desired operations, i.e., multiplication in the multiplier 18 and addition in the adder 19. Furthermore, these operations are performed after the result has been provided by the actual ADC converter, i.e., after the result from the DAC 11 has been converted into Fig. 1. These additional operations, especially multiplication, are costly due to the space required for multiplier 18 and cause additional time delay. Furthermore, the space required for the additional multiplier 18 increases significantly as the number of bits of the digital output signal increases.

[0006] This document addresses the above-mentioned technical problems. In particular, this document addresses the technical problem of creating an analog-to-digital converter (ADC) based on the principle of successive approximation with improved calibration of the digital output signal in terms of processing time and chip area.

[0007] US7 038 609 B1 describes a SAR converter with improved performance by effectively precharging the most significant bits of the SAR with a value that makes the associated DAC output almost equal to the signal to be converted. Summary

[0008] According to one aspect, an analog-to-digital converter (ADC) is presented that is designed to convert an analog input signal into a digital output signal with N bits o n, n ∈ {0, ..., N-1}. The analog input signal can be, for example, an input voltage or an input current measured across a shunt resistor. The ADC can comprise a controller, a digital-to-analog converter DAC, and a comparator. The comparator can be configured to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC. The controller can be configured to receive the binary signal generated by the comparator and, based on the binary signal, generate a digital control signal comprising N bits c n, n ∈ {0, ..., N-1}. The DAC may be configured to generate the analog output signal based on the digital control signal generated by the controller. The controller may comprise: a register configured to store a previous sum value, and an adder configured to determine a test sum value by, when the ADC sets the bit o n of the digital output signal, the previous sum value and a test value that is 2 n times a gain factor. The bits of the digital output signal are returned by the ADC after conversion is complete.

[0009] The presented ADC relies on an implicit shift adder in the conventional SAR algorithm and adds an additional adder (which can be part of an arithmetic logic unit AU or a floating-point unit FPU, for example) to determine a test sum value for the n-th bit, instead of simply setting the n-th bit to 1 in the conventional SAR algorithm. In general, the test value can be represented by a binary representation of the gain factor shifted by n bits, i.e., to the position of the bit o nof the digital output signal being tested. For the special case of a gain factor equal to 1, the claimed ADC behaves similarly to a conventional SAR ADC, i.e., the n-th bit is set to 1 and a test value is added in which the n-th bit is 1 and all other bits are 0. In other words, if the gain factor 1 is chosen, the additional adder is actually not required. To put the present invention into practice, the gain factor is therefore preferably chosen to be different from the identity, i.e., different from 1.

[0010] If the gain factor is selected to be different from 1, an additional multiplication operation is integrated into the DAC control. This extension of the shift operation in a SAR DAC acts as a multiplier, which is not included in the conventional design. Therefore, the need for an additional expensive digital multiplication block to multiply the output of a conventional SAR ADC is eliminated at the expense of a slight increase in the control overhead of the stressed ADC, e.g., through an additional adder and additional registers. This can save both space and time.

[0011] To achieve a desired slope correction factor, the gain factor must be set to the multiplicative inverse of the slope correction factor, i.e., the gain factor must be set to 1 divided by the slope correction factor. Consequently, the values ​​of the digital output signal of the claimed ADC are an approximation of the digital output signal of a conventional SAR ADC multiplied by the slope correction factor.

[0012] On the one hand, the proposed controller can be designed to generate the digital control signal based on the test sum value and, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value in the register as the new sum value. In other words, the register can be updated with the test sum value, so that the previous sum value previously stored in the register is no longer valid. For example, the previous sum value can be overwritten by the test sum value. On the other hand, the controller can be designed to leave the previous sum value unchanged and not increment the previous sum value with the test value if the binary signal indicates that the analog input signal is less than or equal to the analog output signal corresponding to the test sum value.

[0013] Furthermore, the ADC can be designed to convert the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. The ADC can be designed to set the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is less than or equal to the analog output signal corresponding to the test sum value.

[0014] The proposed controller can be designed to perform the analog / digital conversion with the most significant bit MSB o N-1of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value. When the MSB is set to a predetermined offset value, the values ​​of the digital output signal of the claimed ADC are an approximation of the digital output signal of a conventional SAR ADC plus an additional offset corresponding to the predetermined offset value. In other words, any post-processing adder that may be required to calibrate the output of a conventional SAR ADC is replaced by pre-setting the controller's register with the predetermined offset value. If addition of a negative number is desired, the binary complement of the corresponding binary number can be used.

[0015] The ADC can be designed to start the analog-to-digital conversion by first setting the most significant bit MSB o N-1of the digital output signal and continues bit by bit until the least significant bit (LSB) o O of the digital output signal. At the end of the conversion process, the digital control signal can be equal to the digital output signal.

[0016] According to another aspect, a controller for controlling the operation of an analog-to-digital converter (ADC) is presented. The ADC may be configured to convert an analog input signal into a digital output signal having N bits or n, n ∈ {0, ..., N-1}, wherein the ADC may comprise a digital-to-analog converter DAC and a comparator. The comparator may be configured to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC, and the DAC may be configured to generate the analog output signal based on a digital control signal. The controller may be configured to receive the binary signal generated by the comparator and, based on the binary signal, generate the digital control signal comprising N bits c n , n ∈ {0, ..., N-1}, for controlling the DAC. Furthermore, the controller may comprise: a register configured to store a previous sum value, and an adder configured to determine a test sum value by adding the bit o n of the digital output signal, the previous sum value and a test value that is 2 ntimes a gain factor. The test value may be represented by a binary representation of the gain factor shifted by n bits. The controller may be configured to generate the digital control signal based on the test sum value and then, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value as the new sum value in the register.

[0017] On the one hand, the controller can be designed to set the bit of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. On the other hand, the controller can be designed to set the bit of the digital output signal to 0 if the binary signal indicates that the analog input signal is less than or equal to the analog output signal corresponding to the test sum value.

[0018] The controller can be designed to perform the analog / digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value. To be more precise, the controller can be designed to start the analog-to-digital conversion by first setting the most significant bit MSB o N-1of the digital output signal and continues bit by bit until the least significant bit LSB o O of the digital output signal.

[0019] According to a further aspect, a method for converting an analog input signal into a digital output signal is presented, wherein the digital output signal comprises N bits o n , n ∈ {0, ..., N-1}. The method uses or provides a digital-to-analog converter DAC and a comparator. A step of the method may comprise generating a binary signal by the comparator by comparing the analog input signal with an analog output signal of the DAC. A further step of the method may comprise generating the analog output signal by the DAC based on a digital control signal comprising N bits c n, n ∈ (0, ..., N-1}. The digital control signal for controlling the DAC can be generated based on the binary signal. A previous sum value can be stored in a register and a test sum value can be generated when the ADC sends the bit o n of the digital output signal by adding the previous sum value and a test value that is 2 n times a gain factor. The test value can be obtained by shifting a binary representation of the gain factor by n bits.

[0020] The method may further comprise generating the digital control signal based on the test sum value and, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, storing the test sum value as a new sum value.

[0021] On the one hand, the method may further comprise setting the bit on of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. On the other hand, the method may further comprise setting the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is less than the analog output signal corresponding to the test sum value.

[0022] The method can perform analog / digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or a predetermined offset value. In particular, the method can start the analog-to-digital conversion by first setting the most significant bit MSB o N-1 of the digital output signal and proceeds bit by bit until the least significant bit LSB o Oof the digital output signal.

[0023] The method may further comprise determining a further test sum value by adding the previous sum value and a further test value which is 2 n times the gain factor, where n is an integer that is either less than 0 or greater than N-1; and changing the digital output signal that contains bits o n , n ∈ {0, ..., N-1}, based on the determined further test sum value.

[0024] For example, the method may further comprise: determining further o n -values ​​by adding the previous sum value and another test value, which is 2 n times the gain factor, where n is an integer that is either less than 0 or greater than N-1. The method may further comprise: changing the digital control signal c m, where the new corresponding test sum is mapped to the {0, ..., M-1} range of the digital control signal, or setting this range to a maximum if it is used when finally returning an extended output signal containing bits o n , n ∈ (0, ..., N-1}, based on the determined further test sum value is exceeded. In other words, the number of digital control bits may differ from the number of digital output bits. In particular, the number of digital control bits may be greater than the number of digital output bits.

[0025] It should be noted that the methods and systems, including their preferred embodiments, as presented in this document can be used independently or in combination with the other methods and systems disclosed in this document. Furthermore, the features presented in the context of a system are also applicable to a corresponding method. Furthermore, all aspects of the methods and systems described in this document can be combined in any way. In particular, the features of the claims can be combined in any way.

[0026] In this document, the term “coupling”, “connecting”, “coupled” or “connected” refers to elements that are in electrical communication with each other, whether directly, for example via wires, or in some other way Brief description of the drawings

[0027] The invention is explained below by way of example with reference to the accompanying drawings; Fig. 1 a circuit diagram of an example SAR ADC; Fig. 2 a flowchart of an exemplary algorithm for successive approximation; Fig. 3 a circuit diagram of another exemplary SAR ADC; and Fig. 4 a flowchart of another exemplary algorithm for successive approximation. Detailed description

[0028] Fig. Figure 1 shows a circuit diagram of an exemplary SAR ADC known from the prior art. The ADC includes an analog voltage comparator 12, which compares an analog input voltage with the output of an internal digital-to-analog converter (DAC) 11 and outputs the result of the comparison to a SAR logic unit 10 (also referred to as the controller in the following description). Fig.Figure 1 shows a circuit in which the analog input voltage is applied via a multiplexer 13, switching elements 14, and a capacitor 16 to the same input terminal of the comparator 12 as the output of the DAC 11. In fact, the output of the DAC 11 is also connected to the same input terminal via the switching elements 14 and the capacitor 16. Furthermore, a reference offset voltage is applied via the switching elements 15 and the capacitor 17 to the second input terminal of the comparator 12. It should be noted, however, that in an alternative design of the ADC in Fig.1, the multiplexer 13, the switching elements 14, 15, and the capacitors 16, 17 can be omitted, and the analog input voltage and the output signal of the DAC 11 can be applied directly to two different terminals of the comparator 12. For example, the analog input voltage can be applied to the inverting input of the comparator 12 and the output voltage of the DAC 11 can be applied to the non-inverting input of the comparator 12, or vice versa.

[0029] The output of DAC 11 is connected to a 16-bit multiplier 18, whose output is in turn connected to the input of an 8-bit adder 19. Generally, the system may include an n-bit multiplier and an m-bit adder. As described in the Background section, multiplier 18 and adder 19 are required to map the output signal of the conventional SAR-DAC to a desired range.

[0030] The Fig.The overall system shown in Figure 1 comprises a first explicit serial multiplier 18, which is used during the calibration of the results provided by the DAC 11. In addition, the Fig. 1 includes a second implicit multiplier hidden within the mathematics of the SAR algorithm. The present invention seeks to utilize and modify this second implicit multiplier to integrate the first explicit multiplier into the SAR algorithm, thus eliminating the need for the first explicit serial multiplier 18.

[0031] In fact, the steps performed by the SAR algorithm are comparable to a serial shift and add multiplier with an added decision step. However, the SAR logic is implemented differently because this implicit multiplier is a special case with no carry-through. Instead, the SAR algorithm performs this implicit multiplication by setting the bit under test (BUT) to binary 1, i.e., b'1, and then making a decision about the modified DAC output relative to the analog input voltage. This decision is then carried over to the next step of the algorithm. This starts at the MSB and is shifted right to the LSB for each iteration of the SAR algorithm.

[0032] The inventors of the present invention have recognized that the Fig.The conventional SAR algorithm shown in Figure 2 essentially performs similar steps to those performed in serial multiplication. This corresponds to a left shift of b'1 to the bit under test and then adding this value to a current sum value. If this result is less than the analog input voltage, the sum value is updated to be the previous sum value plus this shifted b'1 value.

[0033] To show the similarity between the conventional SAR algorithm and a shift-and-add multiplication, Fig. 2 uses a special notation of the conventional SAR algorithm, which includes not only an ADC variable representing the digital control signal supplied by the controller 10 to the DAC 11, but also a sum value SUM. However, it is important to note that the flowchart in Fig.2 explicitly separates the ADC variable and the sum value SUM used in the SAR algorithm for clarity only. For a typical SAR algorithm, these two values ​​are equal and implicit.

[0034] In step 20 of the SAR algorithm in Fig.2, the system is initialized by setting both a SUM variable and an ADC variable to 0. In step 21, a binary 1 (b'1) is shifted to the bit under test, BUT, i.e., to the position of the MSB in the first step of the algorithm. In step 22, a check is made to see if the sum of the SUM variable and the shifted binary 1 is less than the analog input signal. If yes, the algorithm branches to step 23, where the SUM variable is incremented by the value of the binary 1 shifted to the BUT, and the bit in the ADC variable at the BUT position is set to 1. If no, the algorithm branches to step 24, where the SUM variable remains unchanged and the bit in the ADC variable at the BUT position is set to 0. In step 25, the BUT is shifted one bit to the right and the algorithm jumps back to step 21 until the LSB is reached.As mentioned above, multiplication and addition are performed for calibration purposes in the subsequent steps 26 and 27, respectively. The algorithm ends in step 28.

[0035] A step-by-step operation of the typical SAR algorithm is shown in Table 1 below. For this system, the DAC's LSB is 1.0 V for an analog input signal (ADC input) of 5.0 V. For recalibration, the multiplier has a gain (slope correction factor) of 2 and an offset of 1. The multiplier does not need to be an explicit power of 2, but is set this way to simplify the example. In the table, at each step of the SAR algorithm, the updated values ​​for each step are printed in bold. The system result has a final 1-bit LSB error, which is further multiplied by the serial multiplier. Table 1: Typical SAR operation LSB 1V ADC input 5V Reinforcement 2 Offset 1 Cycle:Step SUM ADC BUT 'b1moved SUM +shift ADC decision 10 0000 0000 0000 11 0000 0000 1000 1000 12 0000 0000 1000 1000 1000 N 1:3b 0000 0000 1000 1:4 0000 0000 0100 2:1 0000 0000 0100 0100 2:2 0000 0000 0100 0100 0100 J 2:3a 0100 0100 0100 2:4 0100 0100 0010 3:1 0100 0100 0010 0010 3:2 0100 0100 0010 0010 0110 N 3:3b 0100 0100 0010 3:4 0100 0100 0001 4:1 0100 0100 0001 0001 4:2 0100 0100 0001 0001 0101 N 4:3b 0100 0100 0001 4:4 0100 0100 0000,1 SAR issue 0100 4 Serial multiplier 1000 8 Offset addition 1000 9 Final result 1000 9

[0036] Fig. Figure 3 shows a circuit diagram of an exemplary SAR-ADC based on the principles of the present invention. In the SAR-ADC of Fig. 3, the post-processing multiplication and addition are integrated into the control of the DAC 11. For this purpose, a transpose SAR logic unit (T-SAR logic unit) 100 is used. The remaining circuit components are identical to those in Fig. 1 identical.

[0037] Fig.Figure 4 shows a flowchart of an exemplary successive approximation algorithm based on the principles of the present invention. The transpose SAR integrates the post-processing multiplier and adder into the implicit serial SAR multiplier discussed above. To this end, the system no longer shifts a binary 1 b'1 into the bit under test, BUT. Instead, the system shifts an N-bit gain into the BUT (step 41). The resulting test value is then added to the SUM variable and compared to the analog input voltage, i.e., the ADC input (step 42). If it is less than the ADC input, the shifted gain is added to SUM (step 43). If not, the current value of SUM is retained (step 44). The BUT is now shifted right once (step 45), and the algorithm repeats.

[0038] It is important to note that in Figure 4, the post-processing adder 19 is replaced by pre-filling the SUM register with the desired offset. If the desired offset is negative, the 2's complement is used. Together, these two changes eliminate the required post-processing.

[0039] The transpose SAR breaks the equality between the sum and the ADC result. For each bit, the ADC result of that bit is set to 1 if the sum plus the shifted gain is less than the ADC input. This creates a difference in the sum because the ADC result is only shifted by a single bit, while the shifted gain is added to the sum.

[0040] The system can multiply the DAC input to the comparator by the gain factor rather than the ADC output. This is the reverse operation compared to the typical post-processing steps in a conventional SAR. Therefore, the gain factor used must be the inverse of the required gain (slope correction factor).

[0041] A step-by-step operation of the transpose SAR algorithm is shown in Table 2. The system is designed to mirror that in Table 1. The SUM variable is preset to the two's complement of 1 to act as an offset of +1. The gain factor is also set to 0.5 to achieve a final gain of 2. As shown, the final result of the transpose SAR ADC doubles the input value plus one. Table 2 Transpose SAR operation LSB 1V ADC input 5V Reinforcement 2=>'b0.1 Offset +1 Cycle:Step SUM ADC BUT Shifted reinforcement SUM +shift ADC decision 1:0 1111 0000 1000 1:1 1111 0000 1000 0100 1:2 1111 0000 1000 0100 0011 J 1:3a 0011 1000 1000 1:4 0011 1000 0100 2:1 0011 1000 0100 0010 2:2 0011 1000 0100 0010 0101 N 2:3b 0011 1000 0100 2:4 0011 1000 0010 3:1 0011 1000 0010 0001 3:2 0011 1000 0010 0001 0100 J 3:3a 0100 1010 0010 3:4 0100 1010 0001 4:1 0100 1010 0001 0000,1 4:2 0100 1010 0001 0000,1 0100,1 J 4:3a 0100,1 1011 0001 4::4 0100,1 1011 0000,1 Final result 1011 'd11

[0042] Two further examples of the transpose SAR algorithm with a gain factor of 10 binary and 0.1 binary are shown in Tables 3 and 4. In Tables 3 and 4, the summed result corresponds to the values ​​(SUM + shift) in Tables 1 and 2. Table 3: Divide by 2 (gain factor = 2) 4-bit ADC LSB=1V Input=7V Multiplication='b10 DAC Result >=Input Summated result ADC result 1 bit Summated result 00000 + bit to be tested * M 1[0]000 =DAC setting 10000 16V Yes 00000 0000 2 bits Summated result 00000 + bit to be tested * M 01[0]00 =DAC setting 01000 8V Yes 00000 0000 3 bits Summated result 00000 + bit to be tested * M 001[0]0 =DAC setting 00100 4V No 00100 0010 4 bits Summated result 00100 + bit to be tested * M 0001[0] =DAC setting 00110 6V No 00110 0011 Table 4: Multiply by 2 (gain factor = 0.5) 4-bit ADC LSB=1V Input=7V Multiplication='b0,1 DAC Result >=Input Summated result ADC result 1 bit Summated result 0000 + bit to be tested * M [0]100 =DAC setting 0100 4V No 0100 1000 2 bits Summated result 0100 + bit to be tested * M 0[0]10 =DAC setting 0110 6V No 0110 1100 3 bits Summated result 0110 + bit to be tested * M 00[0]1 =DAC setting 0111 7V Yes 0110 1100 4 bits Summated result 0110 + bit to be tested * M 000[0],1 =DAC setting 0110,1 6,5V No 0110,1 1101

[0043] It is important to note two differences in this algorithm. The inverse of the target gain must be programmed into the system as the gain factor. For this reason, for a gain of 2, 0.5 is used as the gain in the examples in Tables 2 and 4. It is also important to note that for the offset in Table 2, to achieve an offset of plus 1, minus 1 is used in 2's complement form.

[0044] The final result returns an error of 1 LSB for both examples. The maximum value of this error is determined by the value of the residual. It is important to note that conventional SAR calibration returns an error within + / - 1 LSB. An example with a larger error is given below in Table 5. Table 5: Residual errors 4-bit ADC LSB=1V Input=7V Multiplication='b100 DAC Result >=Input Summated result ADC result 100000 32V Yes 000000 000000 010000 16V Yes 000000 000000 001000 8V Yes 000000 000000 000100 4V No 000100 000001

[0045] There are three major improvements to the system and its implementation.

[0046] 1. As can be seen from the examples above, the basic algorithm requires additional DAC bits. This is determined by the desired multiplication or division range. This is problematic because extending the DAC in either direction is expensive and difficult. This problem must be solved for values ​​both larger and smaller than the DAC range. For the high side, the system should detect that the current value to be programmed into the DAC is larger than the DAC range. This can be achieved with an overflow bit in the summing node. The DAC should then be set to the maximum possible value. A modified example is shown below. 4-bit ADC LSB=1V Input=7V Multiplication='b10 Target DAC Actual DAC Result >=Input Summated result ADC result 10000 1111 15V Yes 0000 0000 01000 1000 8V Yes 0000 0000 00100 0100 4V No 0100 0010 00110 0110 6V No 0110 0011

[0047] For values ​​smaller than the DAC range, the summed result only needs to track these values, but only map them to the DAC when the resulting value drifts back into the LSB range. This results in an error of less than 1 LSB. An example is given in the following table: 4-bit ADC LSB=1V Input=7V Multiplication='b0,1 Target DAC Actual DAC Result >=Input Summated result ADC result 0100 0100 4V No 0100 1000 0110 0110 6V No 0110 1100 0111 0111 7V Yes 0110 1100 0110,1 0110 6V No 0110,1 1101

[0048] A more complex example is shown in the following table: 4-bit ADC LSB=1V Input=7V Multiplication='b0.11 Target DAC Actual DAC Result >=Input Summated result ADC result 0110 0110 6V No 0110 1000 1001 1001 9V Yes 0110 1000 0111,1 0111 7V Yes 0110 1000 0110,11 0110 6V No 0110,11 1001

[0049] 2. As previously explained, the degree of error in the system is determined by the size of the remainder after division. The system can further calculate the remainder by continuing the SAR for a few more steps. This can be done with or without the improvement from point 1. As long as the summed result takes the remaining bits into account and transfers them to the DAC LSB bit, the potential error in the final result remains within + / - 1 LSB. The following table continues the example from above. 4-bit ADC LSB=1V Input=7V Multiplication='b0.11 Target DAC Actual DAC Result >=Input Summated result ADC result 0110 0110 6V No 0110 1000 1001 1001 9V Yes 0110 1000 0111,1 0111 7V Yes 0110 1000 0110,11 0110 6V No 0110,11 1001 0111,001 0111 7V Yes 0110,11 10010 0110,1111 0110 6V No 0110,1111 1001,01

[0050] The previous example returned an ADC result of 9 V, as shown in step 4. 9 V multiplied by 0.75 results in 6.75 V, with an error of 0.25 V. If the sequence continues, the final result is 9.25 V, yielding a final value of 6.9375 V, which is much closer to the actual result. Combining 1 and 2 results in the following table: 4-bit ADC LSB=1V Input=7V Multiplication='b100 Target DAC Actual DAC Result >=Input Summated result ADC result 100000 1111 15V Yes 0000 0000 010000 1111 15V Yes 0000 0000 001000 1000 8V Yes 0000 0000 000100 0100 4V No 0100 0001 000110 0110 6V No 0110 0001,1 000111 0111 7V Yes 0110 0001,10

[0051] For the described ADC mapping and calibration, both a gain and an offset are calculated. Previously, the system only adjusted the gain by changing the algorithm. The offset can also be easily added to the system. This can be achieved by either pre-assigning the summed result with the offset value or by adding the offset value to the final ADC result.

[0052] The described modification of the SAR algorithm enables area savings, as a post-processing multiplier and / or a post-processing adder are no longer required. In the example simulation shown in the table below, a saving of approximately 5-6% was achieved. The area estimate was determined for the described transposition SAR ADC. The simulation is based on a 6-channel, 12-bit SAR ADC. The area comparison is shown in the following table: Tra nsposition SAR block Area (µm 2 ) Area in gates New SAR ADC 10596,5439 564 Registers required for calibration 18972,4 1063 ADC control without multiplier (68351,0078 - 8000) 3164 In total 90984,4 4792 SAR block Area (µm 2 ) Area in gates Conventional SAR ADC 7956,0319 423 Calibration machine 68351,0078 3645 Registers required for calibration 18972,4 1063 In total 95459,4397 5131

[0053] For this comparison, the conventional SAR ADC controller was replaced with the transpose SAR ADC controller. The transpose SAR ADC controller requires an additional 140 gates, but saves 500 gates by eliminating the post-processing multiplier. This results in an area reduction of approximately 5-6% in the ADC.

[0054] The primary area used for this ADC is the calibration engine. This may include round-robin selection, warm-up selection, ADC clock, test logic, averaging, offset addition, multiple conversion options, and the multiplier. A simpler ADC results in a larger percentage savings. The area savings should also be proportional to the number of bits in the ADC.

[0055] As a further advantage, it becomes possible to calculate the ADC residual from a measurement. This can allow the ADC to return more bits than the DAC range when calculating fractional bits (see, for example, Improvement 2 described above).

[0056] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments described in this document are expressly intended to be for explanatory purposes only to facilitate the reader's understanding of the principles of the proposed methods and systems. Furthermore, all statements contained herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include their equivalents.

Claims

[1] Analogue / digital converter (ADC) designed to convert an analogue input signal into a digital output signal with N bits o n , n ∈ (0, ..., N-1}, wherein the ADC comprises a controller (100), a digital / analog converter DAC (11) and a comparator (12), wherein - the comparator (12) is designed to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC (11); - the controller (100) is designed to receive the binary signal generated by the comparator (12) and, based on the binary signal, to generate a digital control signal comprising N bits c n , n ∈ (0, ..., N-1}, contains; - the DAC (11) is adapted to generate the analog output signal based on the digital control signal generated by the controller (100); wherein the controller (100) comprises: a register adapted to store a previous sum value, and an adder adapted to determine a test sum value by, when the ADC sets the bit o n of the digital output signal, the previous sum value and a test value that is 2 n times a gain factor is added. [2] The ADC of claim 1, wherein the test value is represented by a binary representation of the gain shifted by n bits. [3] The ADC of claim 1 or 2, wherein the controller (100) is configured to generate the digital control signal based on the test sum value, and when the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value in the register as a new sum value. [4] ADC according to one of claims 1 to 3, wherein the ADC is adapted to convert the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. [5] ADC according to one of claims 1 to 4, wherein the ADC is adapted to convert the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value. [6] ADC according to one of claims 1 to 5, wherein the controller (100) is designed to perform the analog / digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value. [7] ADC according to one of claims 1 to 6, wherein the ADC is arranged to start the analog-to-digital conversion by first detecting the most significant bit MSB o N-1 of the digital output signal and continues bit by bit until the least significant bit (LSB) o O of the digital output signal. [8] Controller for controlling the operation of an analogue / digital converter ADC designed to convert an analogue input signal into a digital output signal with N bits o n, n ∈ {0, ..., N-1}, wherein the ADC comprises a digital / analog converter DAC (11) and a comparator (12), wherein the comparator (12) is designed to generate a binary signal by comparing the analog input signal with an analog output signal of the DAC (11), and the DAC (11) is designed to generate the analog output signal based on a digital control signal, wherein - the controller (100) is designed to receive the binary signal generated by the comparator (12) and, based on the binary signal, to generate the digital control signal comprising N bits c n , n ∈ {0, ..., N-1}, to control the DAC (11). - the controller (100) comprises: a register configured to store a previous sum value, and an adder configured to determine a test sum value by, when the ADC sets the bit o nof the digital output signal, the previous sum value and a test value that is 2 n times a gain factor is added. [9] The controller of claim 8, wherein the test value is represented by a binary representation of the gain factor shifted by n bits. [10] The controller of any one of claims 8 and 9, wherein the controller (100) is configured to generate the digital control signal based on the test sum value and, when the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, to store the test sum value in the register as a new sum value. [11] Controller according to one of claims 8 to 10, wherein the controller (100) is adapted to set the bit o nof the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. [12] Controller according to one of claims 8 to 11, wherein the controller (100) is adapted to set the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value. [13] Controller according to one of claims 8 to 12, wherein the controller (100) is designed to perform the analog / digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or to a predetermined offset value. [14] Controller according to one of claims 8 to 13, wherein the controller (100) is adapted to start the analog / digital conversion by first setting the most significant bit MSB o N-1 of the digital output signal and continues bit by bit until the least significant bit (LSB) o O of the digital output signal. [15] Method for converting an analog input signal into a digital output signal comprising N bits o n , n ∈ {0, ..., N-1}, using a digital / analog converter DAC (11) and a comparator (12), the method comprising: - generating a binary signal by the comparator (12) by comparing the analog input signal with an analog output signal of the DAC (11); - generating the analog output signal by the DAC (11) based on a digital control signal having N bits c n , n ∈ (0, ..., N-1}; - generating the digital control signal for controlling the DAC (11) based on the binary signal; - Saving a previous total value; - Determine a test sum value when the ADC sends the bit o n of the digital output signal by adding the previous sum value and a test value that is 2 n times an amplification factor. [16] The method of claim 15, wherein the test value is obtained by shifting a binary representation of the gain factor by n bits. [17] A method according to any one of claims 15 or 16, further comprising: - Generating the digital control signal based on the test sum value; - and then, if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value, storing the test sum value as the new sum value. [18] A method according to any one of claims 15 to 17, further comprising: - Setting the bit o n of the digital output signal to 1 if the binary signal indicates that the analog input signal is greater than the analog output signal corresponding to the test sum value. [19] A method according to any one of claims 15 to 18, further comprising: - Setting the bit o n of the digital output signal to 0 if the binary signal indicates that the analog input signal is smaller than the analog output signal corresponding to the test sum value [20] A method according to any one of claims 15 to 19, further comprising: - Start the analog / digital conversion with the most significant bit MSB o N-1 of the digital output signal by initializing the previous sum value to 0 or a predetermined offset value. [21] A method according to any one of claims 15 to 20, further comprising: Start the analog / digital conversion by first setting the most significant bit MSB o N-1 of the digital output signal is determined and continues bit by bit until the least significant bit LSB o O of the digital output signal. [22] A method according to any one of claims 15 to 21, further comprising: - Determine further o n -values ​​by adding the previous sum value and another test value, which is 2 n times the gain factor, where n is an integer that is either less than 0 or greater than N-1; and - Changing the digital control signal c m , where the new corresponding test sum is mapped to the {0, ..., M-1} range of the digital control signal, or setting this range to a maximum if it is used when finally returning an extended output signal containing bits o n, n ∈ {0, ..., N-1}, based on the determined further test sum value is exceeded.

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