Silicon carbide semiconductor device and method for producing a silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device (10) comprising: a semiconductor substrate (30) containing silicon carbide and having a front surface and a rear surface opposite the front surface, the semiconductor substrate (30) containing: a first semiconductor layer (34) of a first conductivity type having an upper surface and a lower surface, and a second semiconductor layer (35) disposed on the upper surface of the first semiconductor layer (34) and having an upper surface forming the front surface of the semiconductor substrate (30) and a lower surface facing the upper surface of the first semiconductor layer (34); a first semiconductor region (4) of the first conductivity type selectively disposed at the upper surface of the second semiconductor layer (35); a second semiconductor region (5) of a second conductivity type selectively disposed at the upper surface of the second semiconductor layer (35) and having a lower surface with a smaller depth than a lower surface of the first semiconductor region (4); a third semiconductor region (2) of the second conductivity type having a lower impurity concentration than the second semiconductor region (5), wherein the third semiconductor region (2) is a portion of the second semiconductor layer (35) excluding the first semiconductor region (4) and the second semiconductor region (5), wherein the third semiconductor region (2) contains: a high impurity concentration region (2b) of the second conductivity type facing the second semiconductor region (5) in the depth direction and touching the second semiconductor region (5), and a low impurity concentration region (2a) of the second conductivity type facing the high impurity concentration region (2b) in a direction parallel to the front surface of the semiconductor substrate (30), the low impurity concentration region (2a) having an upper surface facing the first semiconductor region (4) and a lower surface facing the upper surface of the first semiconductor layer (34) in the depth direction, the low impurity concentration region (2a) being a portion of the third semiconductor region (2) excluding the high impurity concentration region (2b); a trench (6) penetrating the first semiconductor region (4) and the low impurity concentration region (2a) from the front surface of the semiconductor substrate (30) and reaching the first semiconductor layer (34); a gate insulating film (7) disposed on an inner surface of the trench (6); a gate electrode (8) disposed over the gate insulating film (7) in the trench (6); a first electrode (11) electrically connected to the first semiconductor region (4) and to the second semiconductor region (5); and a second electrode (16) arranged at the rear surface of the semiconductor substrate (30), wherein the impurity concentration in the high impurity concentration region (2b) decreases towards the low impurity concentration region (2a) in a direction parallel to the front surface of the semiconductor substrate (30).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention

[0001] Embodiments of the invention relate to a silicon carbide semiconductor device and to a method for manufacturing a silicon carbide semiconductor device. 2. Description of the state of the art

[0002] Silicon carbide (SiC) has a larger energy gap than silicon (Si) and, as a result, has a higher critical field strength than silicon, so it is expected to be a semiconductor material that can sufficiently reduce the on-resistance. Furthermore, in a semiconductor device (hereinafter, a silicon carbide semiconductor device) using silicon carbide as a semiconductor material, a reduced on-resistance is required, and vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) utilize a trench-gate structure that structurally easily achieves a low on-resistance characteristic.

[0003] A trench-gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on a front surface of a semiconductor substrate. In a trench-gate structure, a channel (an n-type inversion layer) is formed in a portion of a p-type base region along a trench sidewall in a vertical direction (depth direction). Although reducing the thickness of the p-type base region shortens the channel length and thereby enables reduced ON resistance by channel shortening, short-channel effects increase, causing new problems to arise. Thus, a structure for improving the problems caused by increases in short-channel effects has been proposed (see, for example, Japanese Patent Application Laid-Open No. JP 2017-168665 A).

[0004] In Japanese Patent Application No. JP 2017-168665 A, a structure is disclosed in which directly under an n ++-source region, separated from the trench sidewall by a predetermined distance and adjacent to a portion of the p-base region forming the channel, a p + -region with a higher impurity concentration than the p-base region. The p + -region is a so-called HALO region and suppresses depletion layers that form in the p-base region, each from a pn junction between the p-base region and the n ++ source region and a pn junction between the p-base region and the n-current spreading region. The HALO region is formed by ion implantation (hereinafter oblique ion implantation) of p-type impurities from a direction oblique with respect to a sidewall of a trench.

[0005] In Fig. 13 shows a conventional silicon carbide semiconductor device that does not include a HALO region. Fig. 13 is a cross-sectional view of a structure of the conventional silicon carbide semiconductor device. Fig. The conventional silicon carbide semiconductor device 110 shown in Figure 13 is a vertical MOSFET that does not include a HALO region. A semiconductor substrate 130 is a silicon carbide epitaxial substrate in which an n + On a starting substrate (not shown) containing silicon carbide, silicon carbide epitaxial layers 131, 132 forming an n-type drift layer 101 and a p-type base region 102 are successively deposited. A thickness t101 of the p-type silicon carbide epitaxial layer 132 is reduced, thereby shortening a channel length L, enabling channel shortening.

[0006] In the semiconductor substrate 130, at positions deeper from a front surface of the semiconductor substrate 130 toward a drain, which is a bottom of a trench 106, first and second p +-Area 121, 122. The first p + -Area 121 faces the bottom of trench 106. The second p + -Area 122 is selectively provided between (mesa area) adjacent trenches 106 and separated from the trenches 106. The first and second p + Regions 121, 122 are provided, thereby suppressing the electric field applied to a gate insulating film in an OFF state and increasing the breakdown voltage. Reference numerals 111, 112, and 113 are metal films that configure a source electrode.

[0007] A process for the production of the Fig. 13 will be described. Fig. 14 is a flowchart showing an overview of a method for manufacturing the conventional silicon carbide semiconductor device. On an n +An n-type silicon carbide epitaxial layer 131 is deposited on a starting substrate containing silicon carbide. Under different conditions, ion implantation is repeatedly carried out, which selectively forms an n-type current spreading region 103 and the first and second p-type + -region 121, 122. A portion of the n-type silicon carbide epitaxial layer 131 with the exception of the n-type current spreading region 103 and the first and second p + -Area 121, 122 becomes the n - -Drift Area 101.

[0008] Subsequently, the p-type silicon carbide epitaxial layer 132 is deposited on the n-type silicon carbide epitaxial layer 131 (step S101). Subsequently, ion implantation (hereinafter, channel ion implantation) of n-type impurities or p-type impurities for gate threshold voltage control is performed in the p-type silicon carbide epitaxial layer 132 (step S102). Subsequently, an outer peripheral region of the p-type silicon carbide epitaxial layer 132 is removed, leaving the p-type silicon carbide epitaxial layer 132 in a plateau shape (mesa shape) in an active region (step S103). Subsequently, ion implantation is performed in the p-type silicon carbide epitaxial layer 132 to form the n-type silicon carbide epitaxial layer 132. ++ -Source area 104 is executed (step S104).

[0009] Subsequently, an ion implantation is carried out in the p-silicon carbide epitaxial layer 132 to form a p ++-contact area 105 is carried out (step S105). In a process of step S105, the p ++ -Contact area 105 is formed with a box profile. The conditions of this 3-step ion implantation are monovalent aluminum (Al + ) as a dopant and respective acceleration energies of 160 keV, 90 keV and 40 keV. A portion of the p-type silicon carbide epitaxial layer 132 except for the n ++ -Source area 104 and the p ++ -contact area 105 becomes the p-base area 102.

[0010] Subsequently, a predetermined edge termination structure is formed in an edge termination region surrounding a periphery of the active region (step S106). Subsequently, a heat treatment is performed to activate all impurity ions implanted into the semiconductor substrate 130 (step S107). Subsequently, the trench 106 is formed to a predetermined depth from the front surface of the semiconductor substrate 130 (step S108). Subsequently, a gate electrode 108 is formed in the trench 106 via a gate insulating film 107 (step S109). Thereafter, a source electrode and a drain electrode (not shown) are formed on both surfaces of the semiconductor substrate 130, respectively, as surface electrodes (S110), thereby forming the Fig. 13 shown MOSFET is completed.

[0011] A method for manufacturing a conventional silicon carbide semiconductor device including a HALO region will be described below. Fig. 15 is a flowchart showing an overview of another example of a method for manufacturing the conventional silicon carbide semiconductor device. The method for manufacturing a conventional silicon carbide semiconductor device in Fig. 15 differs from the method for manufacturing the conventional silicon carbide semiconductor device 110 in Fig. 14, by forming a HALO region (step S118) by oblique ion implantation onto the trench sidewall after forming the trench (step S117) and before forming the gate electrode (step S120). The heat treatment for impurity activation (step S119) is performed after forming the HALO region.

[0012] The acceleration energy of the oblique ion implantation in step S118 is controlled, whereby the HALO region is formed in a portion separated by a predetermined distance from the trench sidewall, and a p-type impurity concentration of a portion of the p-type base region along the trench sidewall can be made relatively low. The portion of the p-type base region along the trench sidewall is a portion where a channel is formed. Steps S111 to S117, S119 to S121 of the method for manufacturing the conventional silicon carbide semiconductor device in Fig. 15 are respectively similar to steps S101 to S106, S108, S107, S109, S110 of the method for manufacturing the conventional silicon carbide semiconductor device 110 in Fig. 14.

[0013] As a method for relatively reducing an impurity concentration of the portion where the channel is formed in the p-base region, the following method has been proposed. In an n - -drift region, p-type impurities are ion-implanted, resulting in a p + -region, which becomes a p-base region. The p-impurities diffuse here from the interior of the p + -area, whereby a + region is inverted to a p-type, thereby forming a p-type region (see, for example, Japanese Patent Application Laid-Open No. JP 2007-281265 A). In Japanese Patent Application Laid-Open No. JP 2007-281265 A, the portion that is inverted to a p-type and becomes a p-type region is formed in a portion along the trench sidewall of the p-base region, thereby relatively reducing an impurity concentration of a portion of the p-base region where a channel is formed.

[0014] Other generic silicon carbide semiconductor devices are described, for example, in US 2017 / 365709 A1, US 2013 / 146969 A1, US 2012 / 007173 A1 and DE 10 2017 209 017 A1. SUMMARY OF THE INVENTION

[0015] A first aspect of the invention relates to a silicon carbide semiconductor device according to claim 1.

[0016] In the embodiment, a width of the high impurity concentration region in the direction parallel to the front surface of the semiconductor substrate is larger than a width of the second semiconductor region.

[0017] In the embodiment, the high impurity concentration region has a part facing the first semiconductor region and another part facing the second semiconductor region in the depth direction, the impurity concentration in the high impurity concentration region decreases toward the front surface of the semiconductor substrate in the depth direction and toward the back surface of the semiconductor substrate in the depth direction, and the first semiconductor region has an upper surface constituting the front surface of the semiconductor substrate and a lower surface facing the high impurity concentration region, and a point of the high impurity concentration region having a highest impurity concentration is located at a position separate from the lower surface of the first semiconductor region in the depth direction.

[0018] In the embodiment, a distance between the high impurity concentration region and an outer surface of the trench in the direction parallel to the front surface of the semiconductor substrate is in a range of 0.04 µm to 0.2 µm.

[0019] In the embodiment, the distance between the high impurity concentration region and the outer surface of the trench is in a range of 0.06 µm to 0.1 µm.

[0020] A second aspect of the invention relates to a method for producing a silicon carbide semiconductor device according to claim 6. Further aspects of the invention are the subject of the subclaims, the drawings and the description of embodiments.

[0021] In the embodiment, the fifth process and the sixth process are executed sequentially.

[0022] In the embodiment, a region of the second ion implantation in the sixth process is set deeper in a depth direction than a top surface of the first semiconductor region. Further, the method may include widening a size of the opening of the ion implantation mask in the direction parallel to the top surface of the second semiconductor layer after the fifth process and before the sixth process.

[0023] In the embodiment, a distance between the high impurity concentration region and an outer surface of the trench in the direction parallel to the front surface of the semiconductor substrate in the sixth process is in a range of 0.04 µm to 0.2 µm.

[0024] In the embodiment, the distance between the high impurity concentration region and the outer surface of the trench is in a range of 0.06 µm to 0.1 µm.

[0025] In the embodiment, in the sixth process, the second conductivity type impurities implanted by the second ion implantation diffuse into the second semiconductor layer, and the impurity concentration in the high impurity concentration region decreases toward the low impurity concentration region in the direction parallel to the upper surface of the second semiconductor layer.

[0026] In the embodiment, the second conductivity type impurities implanted by the second ion implantation diffuse in the sixth process, and a width of the high impurity concentration region becomes larger than a width of the opening of the ion implantation mask in the direction parallel to the upper surface of the second semiconductor layer.

[0027] Objects, features and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to a first embodiment. Fig. 2 is a characteristic diagram of the impurity concentration distribution in the section line AA' in Fig. 1 Fig. 3 is a characteristic diagram of the impurity concentration distribution in the section line BB' in Fig. 1. Fig. 4 is a flowchart showing an overview of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig. 5 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture. Fig. 6 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture. Fig. 7 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture. Fig. 8 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture. Fig. 9 is a cross-sectional view of the silicon carbide semiconductor device according to a second embodiment during manufacture. Fig. 10 is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment during manufacture. Fig. Figure 11 is a characteristic diagram schematically showing the distribution of impurities ion-implanted in a silicon carbide epitaxial layer. Fig. 12 is a characteristic diagram showing a relationship between the peak concentration of a first portion of a p-type high concentration region and a separation distance in a second example. Fig. 13 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device. Fig. 14 is a flowchart of an overview of a method for manufacturing the conventional silicon carbide semiconductor device. Fig. 15 is a flowchart of an overview of another example of a method for manufacturing a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0028] First, problems associated with conventional techniques will be described. As described above, a HALO region is provided in a MOSFET, whereby, even if the channel length is shortened to reduce the ON resistance, increases in short-channel effects (effects that occur due to depletion layers expanding from a source side and a drain side in the p-type base region, respectively) when the MOSFET is ON can be suppressed and decreases in the gate threshold voltage can be suppressed. Thus, both a low ON resistance and a high gate threshold voltage can be achieved.

[0029] However, when the HALO region is formed by oblique ion implantation onto the trench sidewall, fluctuations in the formation positions of the HALO region can easily occur, and the properties of the unit cells formed on a semiconductor wafer surface can vary. The main causes of fluctuations in the formation positions of the HALO region include trench dimensions, the angle of the trench sidewall, the position of the ion implantation source from the trench sidewall, and the positions of unit cells (functional units of the device) on the semiconductor wafer surface.

[0030] Furthermore, a process sequence is described from the method for manufacturing the conventional silicon carbide semiconductor device 110 which does not include the HALO region (see Fig. 14), when the HALO region is formed by oblique ion implantation onto the trench sidewall (see Fig. 15), so that production control becomes complicated due to design changes of the production line. Furthermore, the oblique ion implantation (step S118 in Fig. 15) in both side walls of the trench, so that the process lead time for forming the HALO area becomes longer.

[0031] Embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and the accompanying drawings, layers and regions preceded by n or p indicate that the majority charge carriers are electrons or holes. In addition, a + or - following n or p indicates that the impurity concentration is higher or lower, respectively, than in layers and regions without + or -. In the following description of the embodiments and in the accompanying drawings, main portions that are the same bear the same reference numerals and will not be described repeatedly.

[0032] A structure of a silicon carbide semiconductor device according to a first embodiment will be described. Fig. 1 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to the first embodiment. Fig. 1 shows two adjacent unit cells (functional elements of an element) of a vertical MOSFET in which silicon carbide is used as a semiconductor material. Fig. 1 only a portion of the unit cells arranged in an active region is shown and an edge termination region surrounding a periphery of the active region is not shown (similar in Fig. 5 to 10). The active region is a region in which current flows when the semiconductor device is in an ON state.

[0033] The edge termination region is a region between the active region and a chip side surface (an edge of a semiconductor substrate 30) and is a region of an n -Drift region 1, which mitigates the electric field on a front side of the semiconductor substrate 30 and maintains the breakdown voltage (withstand voltage). In the edge termination region, for example, an edge termination structure such as a RESURF, a field plate, a p-type region configuring a junction termination extension (JTE) structure, a guard ring, etc. are disposed. The breakdown voltage is a voltage threshold at which no erroneous operation or destruction of the semiconductor device occurs.

[0034] Fig. 2 and Fig. 3 are characteristic diagrams of the impurity concentration distribution in the section line AA' and in the section line BB' in Fig. 1. Fig. 2 shows the impurity concentration distribution of a p-type high concentration region 2b of the p-type base region 2 in a depth direction (in a vertical direction) from a front surface of the semiconductor substrate 30. Fig. 3 shows an effective impurity concentration distribution of the p-type high concentration region 2b of the p-type base region 2 in a direction parallel (in a horizontal direction) to the front surface of the semiconductor substrate 30. The impurity concentration distributions in Fig. 2 and Fig. 3 are obtained by vertical diffusion and horizontal diffusion of p-type impurities, which occur due to a session of ion implantation 43 described below to form the p-type high concentration region 2b (see Fig. 7).

[0035] A silicon carbide semiconductor device 10 according to the Fig. The first embodiment shown in Figures 1 to 3 is a vertical MOSFET that includes a trench gate structure in the active region of the semiconductor substrate 30 and that includes the p-type base region (third semiconductor region) 2 configured by portions 2a, 2b with different impurity concentrations. The semiconductor substrate 30 is a silicon carbide epitaxial substrate (semiconductor chip) in which a silicon carbide layer is formed by epitaxy on a front surface of an n-type semiconductor layer. + -output substrate (a third semiconductor layer) 31, which is an n + -Drain region 15, successive silicon carbide epitaxial layers 32, 33, 34, 35 are formed, which form the n-buffer layers 14, 13, the n - -drift region 1 and the p-base region 2.

[0036] On one side of a front surface (a main surface of a side of the p --silicon carbide epitaxial layer (second semiconductor layer) 35) of the semiconductor substrate 30, a MOS gate with a trench gate structure is provided. The MOS gate is surrounded by a p-base region 2, an n ++ -Source region (first semiconductor region) 4, by a p ++ -contact region (second semiconductor region) 5, by a trench 6, by a gate insulating film 7 and by a gate electrode 8. The trench 6 penetrates the p - -Silicon carbide epitaxial layer 35 from the front surface of the semiconductor substrate 30 in the depth direction and reaches the n - -Silicon carbide epitaxial layer (first semiconductor layer) 34. The depth direction is a direction from the front surface of the semiconductor substrate 30 to a back surface.

[0037] The trench 6 is arranged in a stripe shape, for example, in a direction parallel to the front surface of the semiconductor substrate 30. The gate insulating film 7 is provided in the trench 6 along an inner wall of the trench 6. The gate electrode 8 is provided on the gate insulating film 7 in such a way that it is embedded in the trench 6. As described below, between (mesa region) adjacent trenches 6, the p-base region 2, the n ++ -Source area 4 and the p ++ -Contact area 5 is provided. A unit cell is configured through sections between centers of adjacent mesa areas.

[0038] In a surface layer on a side of the n-type silicon carbide epitaxial layer 34 facing a source (toward a source electrode 12), an n-type current spreading region 3 is provided in contact with the p-type silicon carbide epitaxial layer 35 (the p-type base region 2). The n-type current spreading region 3 is an n-type region having the same conductivity type as the n-type. - -drift region 1 and with a higher impurity concentration than the n - -drift region 1 and is a so-called current spreading layer (CSL). A bottom of trench 6 ends in the n-type current spreading region 3.

[0039] The n-type current spreading region 3 reaches a sidewall of the trench 6 in a direction parallel to the front surface of the semiconductor substrate 30. Furthermore, the n-type current spreading region 3 reaches a position deeper than the bottom of the trench 6 in the direction of a drain (toward a drain electrode 16) from an interface with the p-type base region 2. A portion of the n-type silicon carbide epitaxial layer 34 except for the n-type current spreading region 3 and the n-type region 23 described below is the n-type current spreading region 3. - -drift region 1. The n-current spreading region 3 is between the n - -drift region 1 and the p-base region 2 and is in contact with the n-drift region 1 and the p-base region 2.

[0040] In the n-current spreading region 3, a first and a second p + -Area 21, 22. The first p +-region 21 at a deeper position towards the drain as an interface between the p-base region 2 and the n-current spreading region 3 is arranged separately from the p-base region 2. Furthermore, the first p + -Area 21 is provided closer to the drain than the trench 6 and faces the bottom of the trench 6 in the depth direction. A depth of the first p + -Area 21 can be changed in various ways and the first p + -Area 21 can be reached with the n - -Drift area 1 are in contact.

[0041] The second p + -Area 22 is between (Mesa area) the adjacent trenches 6, separated from the first p + -region 21 and in contact with the p-base region 2. It is sufficient if the second p + -area 22 is positioned closer to the drain than the bottom of the trench 6 and with the n --drift region 1. At deeper positions towards the drain than the bottom of the trench 6, pn junctions are formed between the first and the second p + -Area 21, 22 and the n-stream widening area 3 (or the n - -drift region 1) is formed, whereby the concentration of the electric field at the gate insulating film 7 at the bottom of the trench 6 can be alleviated.

[0042] For example, the second p + -Area 22 is located in a central section of the mesa area. Directly below the second p + -Area 22 can be in contact with the second p + -region 22, the n-region 23 may be selectively provided. The n-region 23 has a function of reducing the breakdown voltage in the vicinity of the second p + -region 22 so that it is lower than the breakdown voltage near the first p +-region 21. The n-region 23 is provided, whereby the breakdown voltage near a center of the mesa region is lower than the breakdown voltage near the bottom of the trench 6, which allows an avalanche breakdown to occur more easily near the center of the mesa region than near the bottom of the trench 6. The second p + -area 22 and the n-area 23 can be omitted.

[0043] The n ++ -Source area 4 and the p ++ -Contact area 5 are selective in the p - -silicon carbide epitaxial layer 35 and are in contact with each other. The n ++ -Source area 4 and the p ++ -Contact region 5 are exposed to the front surface of the semiconductor substrate 30. The n ++-Source region 4 is arranged in contact with a sidewall of the trench 6 and faces the gate electrode 8 via the gate insulating film 7 on the sidewall of the trench 6. The n ++ -Source region 4 reaches a depth d1 of, for example, about 0.45 µm from the front surface of the semiconductor substrate 30. The p ++ -Contact area 5 is closer to the center of the mesa area than the n ++ -source region 4. A width w1 of the p ++ -Contact area 5 can be, for example, 1.0 µm.

[0044] The p ++ -Contact region 5 ends at a depth d2, e.g., of approximately 0.4 µm, which is less than the depth d1 of the n ++ -Source area 4. The p ++ -Contact region 5 can reach a depth d2 from the front surface of the semiconductor substrate 30 greater than the depth d1 of the n ++-source region 4. In the p- silicon carbide epitaxial layer 35, with the exception of the n ++ -Source area 4 and the p ++ -Contact area 5 a section closer to the drain than the n ++ -Source area 4 and the p ++ -Contact region 5 the p-base region 2. A depth d3 from the front surface of the semiconductor substrate 30 to the interface between the p-base region 2 and the n-current spreading region 3 is, for example, about 1.1 µm.

[0045] In the p-type base region 2, an impurity concentration in a portion separated from the sidewall of the trench 6 by a predetermined distance in a direction parallel to the front surface of the semiconductor substrate 30 is higher than an impurity concentration of a portion (hereinafter, p-type channel region) 2a along the sidewall of the trench 6. The p-type channel region (low impurity concentration region) 2a is a portion where a channel (an n-type inversion layer) is formed when the MOSFET is ON, and is located along the sidewall of the trench 6 directly below (toward the drain) the n ++ -Source Area 4. The p - -Canal area 2a is connected to the n ++ -source region 4 and with the n-current spreading region 3 and is in contact with the gate insulating film 7 at the side wall of the trench 6.

[0046] The p-high concentration region (region with high impurity concentration) 2b is directly below the p ++ -Contact area 5 is provided and runs directly under the n ++ -source region 4. The p-type high concentration region 2b is adjacent to the p-type channel region 2a in a direction parallel to the front surface of the semiconductor substrate 30. The p-type high concentration region 2b suppresses depletion layers in the p-type base region 2 from a pn junction between the p-type base region 2 and the n-type ++The p-type high-concentration region 2b is provided, which suppresses increases in short-channel effects when the MOSFET is ON and suppresses decreases in the gate threshold voltage, even if the thickness (= the channel length L) of the p-type channel region 2a is reduced to reduce the ON resistance. When the p-type high-concentration region 2b has a higher impurity concentration than the p-type channel region 2a, it functions as a HALO region.

[0047] The p-type high concentration region 2 is configured by first, second and third sections 2c, 2d, 2e, which are formed by diffusion of p-type impurities in the depth direction formed during the ion implantation 43 (see Fig. 7) for forming the p-type high concentration region 2b described below. The first to third sections 2c to 2e of the p-type high concentration region 2b are positioned at different depths from the front surface of the semiconductor substrate 30. Furthermore, by diffusion (hereinafter, by the diffusion in the horizontal direction) of the p-type impurities in a direction parallel to the front surface of the semiconductor substrate 30, which takes place during the ion implantation 43 for forming the p-type high concentration region 2b, the first to third sections 2c to 2e of the p-type high concentration region 2b extend from the p ++ -Contact area 5 away from a center of the mesa area towards the two trenches 6 and are in contact with the p--channel area 2a.

[0048] The first section 2c (the hatched section) of the p-type high concentration region 2b shows a peak value (maximum value: hereinafter, peak concentration) of the impurity concentration of the p-type high concentration region 2b. The second and third sections 2d, 2e (sections with lighter hatching than the first section 2c) of the p-type high concentration region 2b have impurity concentrations that are lower than those of the first section 2c. The second and third sections 2d, 2e of the p-type high concentration region 2b are adjacent to sides of the first section 2c facing the source and the drain, respectively. The second section 2d of the p-type high concentration region 2b is in contact with the p ++ -contact region 5. The third section 2e of the p-high concentration region 2b is in contact with the n-current spreading region 3. In Fig. 1, the impurity concentration distribution of the p-type high concentration region 2b, which results from the diffusion in the vertical direction and from the diffusion in the horizontal direction of the p-type impurities, is indicated by a different hatching (similar to Fig. 8).

[0049] The lengths x2a, x2b, over which the first section 2c of the p-high concentration region 2b is separated from the p ++ -Contact area 5 from both ends of the p ++-contact region 5 in the direction of the respective trenches 6, are, for example, approximately 0.2 µm, regardless of the conditions of the ion implantation 43 for forming the p-type high concentration region 2b. The second and third sections 2d, 2e of the p-type high concentration region 2b also extend essentially by the same length as the second section 2c of the p-type high concentration region 2b in the direction of the respective trenches 6. In other words, the width w2 of the p-type high concentration region 2b is approximately 0.4 µm (= 0.2 µm × 2) greater than the width w1 of the p-type ++ -Contact area 5.

[0050] It is sufficient that the first portion 2c of the p-type high concentration region 2b is separated from the sidewall of the trench 6 by a distance (hereinafter, separation distance) Tch, for example, in a range of approximately 0.04 μm to 0.2 μm. If the separation distance Tch of the first portion 2c of the p-type high concentration region 2b from the sidewall of the trench 6 is smaller than the above lower limit, the width of the p-type channel region 2a is too narrow, and thus the function as a MOSFET is not achieved. If the separation distance Tch exceeds the above upper limit, the effect of the p-type high concentration region 2b as a HALO region is not obtained.

[0051] The wider the separation distance Tch is set, the more process margin can be ensured for forming the p-type high-concentration region 2b. Thus, the disappearance of the p-type channel region 2a due to the diffusion of the p-type impurities in the horizontal direction, which occurs during the ion implantation 43 for forming the p-type high-concentration region 2b, can be suppressed. For example, the separation distance Tch can be set in a range of about 0.06 μm to 0.1 μm, thereby further improving the trade-off between reducing the ON resistance and suppressing the decrease in the gate threshold voltage.

[0052] The first section 2c of the p-high concentration area 2b is separated from the n ++ -source region 4. The first section 2c of the p-high concentration region 2b can be separated from the n ++ -Source region 4 at a position at a depth where the impurity concentration of the n ++-source region 4 is not reduced by the diffusion in the vertical direction of the p-type impurities that occurs during the ion implantation 43 for forming the p-type high concentration region 2b. The first section 2c of the p-type high concentration region 2b can be connected to the p ++ -Contact area 5 in contact.

[0053] It is sufficient that a depth position of the peak concentration of the first portion 2c of the p-type high concentration region 2b is positioned in the p-type high concentration region 2b and is positioned at a depth d4, for example, in a range of approximately 0.4 µm to 1.5 µm from the front surface of the semiconductor substrate 30. The peak concentration of the first portion 2c of the p-type high concentration region 2b may, for example, be in a range of approximately 1 × 10 17 cm -3 up to 1 · 10 18 cm -3The magnitude of the effect of the HALO region through the p-high concentration region 2b is determined by the peak concentration of the first section 2c of the p-high concentration region 2b.

[0054] The impurity concentration of the p-type high concentration region 2b in the depth direction is indicated by the peak concentration in the first section 2c and decreases with increasing proximity to the source and drain from the depth position of the peak concentration (see Fig. 2). The impurity concentration of the p-type high concentration region 2b in a direction parallel to the front surface of the semiconductor substrate 30 is determined by the peak concentration in a portion directly below the p ++ -Contact 5 and takes in a direction from the p ++ -Contact area 5 away with increasing proximity to the trenches 6 (see Fig. 3).

[0055] The first portion 2c in the p-type high concentration region 2b may have a final shape positioned closer to the trench 6 than the second and third portions 2d, 2e in a direction parallel to the front surface of the semiconductor substrate 30. Specifically, for example, an interface between the p-type high concentration region 2b and the p-type channel region 2a may be curved substantially in an arc shape in which the p-type high concentration region 2b protrudes toward the trench 6 in a direction parallel to the front surface of the semiconductor substrate 30, and in the first portion 2c of the p-type high concentration region 2b, a distance to the sidewall of the trench 6 is shorter than that for the second and third portions 2d, 2e (not shown).

[0056] On the front surface of the semiconductor substrate 30, an interlayer insulating film 9 is provided, covering the gate electrode 8. The interlayer insulating film 9 may be, for example, a borophosphosilicate glass (BPSG) film or an undoped silicate glass (NSG) film. In each mesa region, a contact hole 9a is provided, which penetrates the interlayer insulating film 9 in the depth direction and reaches the semiconductor substrate 30. A width of the contact hole 9a may be, for example, 1.5 µm. The n ++ -Source area 4 and the p ++ -Contact area 5 free.

[0057] In the contact hole 9a, on the front surface of the semiconductor substrate 30, a silicide layer (first electrode) 11 is provided, which forms an ohmic contact with the semiconductor substrate 30. The silicide layer 11 can be, for example, a nickel silicide layer (NiSi or NiSi2 layer). The source electrode 12 is provided on a surface of the silicide layer 11 and on a surface of the interlayer insulating film 9 in such a way that it is embedded in the contact holes 9a. The source electrode 12 is connected to the n ++ -Source area 4 and with the p ++ -Contact area 5 electrically connected.

[0058] The source electrode 12 is, for example, an aluminum alloy layer containing aluminum (Al), such as aluminum silicon (AISi). The source electrode 12 may be a stacked film in which a barrier metal and the aluminum alloy layer are sequentially stacked. The barrier metal has a function of preventing interaction and / or atom diffusion between regions facing each other via the barrier metal. The barrier metal may be, for example, a titanium film (Ti film) and a titanium nitride film (TiN film).

[0059] On the side of a rear surface (a rear surface of the n + -starting substrate 31, which contains the n + -drain region 15) of the semiconductor substrate 30 are the n-buffer regions 13, 14 and the n + -Drain region 15 is provided. The n-buffer region 13 is provided at a position which is deeper from the rear surface of the semiconductor substrate 30 than the n-buffer region 14 and the n +-Drain area 15. The n-buffer area 14 is between the n-buffer area 13 and the n + -drain area 15 is provided. The n-buffer areas 13, 14 can be omitted. The n + -Drain region 15 is exposed on the rear surface of the semiconductor substrate 30.

[0060] The n-buffer region 13, for example, is a recombination promotion layer containing an element that forms recombination centers (hole trapping centers). The hole density during bipolar operation can be reduced by recombination of the n-buffer region 13, whereby the basal plane dislocations (BPDs) of the n + -starting substrate 31 become stacking defects, which makes it possible to prevent the extension into the n--drift region 1. The n-buffer region 14 is a dislocation transformation layer that suppresses the basal plane dislocations of the n + -starting substrate 31 as starting points generated stacking defects in the n --Drift area 1 can be spread out.

[0061] The drain electrode (second electrode) 16 is provided on the rear surface of the semiconductor substrate 30 as a whole. The drain electrode 16 is connected to the n + -Drain region 15. The silicide layer of the rear surface of the semiconductor substrate 30 may, for example, be a stacked film formed by a stacked molybdenum film (Mo film) and a nickel film (Ni film) that forms an ohmic contact with the semiconductor substrate 30. The thickness of the molybdenum film and the nickel film may be 0.7 µm and 0.1 µm, respectively.

[0062] The drain electrode 16 also serves as a drain pad. The drain electrode 16 may, for example, be a stacked film in which a titanium film (Ti film), a nickel film (Ni film), and a gold film (Au film) are sequentially stacked. The thicknesses of the titanium film, the nickel film, and the gold film may be 0.25 µm, 1.45 µm, and 0.1 µm, respectively.

[0063] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment will be described. Fig. 4 is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are cross-sectional views of the silicon carbide semiconductor device according to the first embodiment during manufacture. In Fig. 5 to 8 are the n-buffer areas 14, 13 (see Fig. 1) (similar Fig. 9 and Fig. 10) is not shown. Here, as an example, a case is described in which (similar Fig. 7) the depth d1 of the n ++ -source region 4 from the front surface of the semiconductor substrate 30 is smaller than the depth d2 of the p ++ -contact region 5 from the front surface of the semiconductor substrate 30.

[0064] As in Fig. 5, first the n + -starting substrate (the semiconductor wafer) 31 is prepared, which leads to the n + -Drain area 15. Subsequently, on the front surface of the n + -starting substrate 31, the silicon carbide epitaxial layers 32, 33 are successively formed by epitaxy, which lead to the n-buffer regions 14, 13 (see Fig. 1). In addition, on a surface of the n-type silicon carbide epitaxial layer 33, the n-type silicon carbide epitaxial layer 34, which belongs to the n --Drift region 1 is formed with a thickness t1 which is smaller than that of the n--silicon carbide epitaxial layer 34 after product completion.

[0065] Subsequently, in a surface layer of the n--silicon carbide epitaxial layer 34, the first p + -Area 21 and a p + -Area 22a. The p + -Area 22a is a section of the second p + -Area 22. Below, directly under the p + -region 22a, the n-region 23 is selectively formed by photolithography and ion implantation of n-impurities.

[0066] Subsequently, the n-type current spreading region 3 is formed by photolithography and ion implantation of n-type impurities in the surface layer of the n-type silicon carbide epitaxial layer 34, for example, spanning the entire active region. A formation sequence of the n-type current spreading region 3, the first p+ -Area 21 and the p + -area 22a and the n-area 23 can be interchanged. A section of the n - -silicon carbide epitaxial layer 34 closer to the drain than the n-current spreading region 3 and the n-region 23 becomes the n-drift region 1.

[0067] Subsequently, the thickness of the n- silicon carbide epitaxial layer 34 is increased by epitaxy by a predetermined thickness t2. Subsequently, at a depth that corresponds to the p + -region 22a, by photolithography and ion implantation of p-type impurities in a section where the thickness of the n- silicon carbide epitaxial layer 34 is increased, selectively a p + -area 22b. A width of the p + -area 22b may be smaller than a width of the p + -area 22a. The p + -Regions 22a, 22b are connected in the depth direction, whereby the second p + -Area 22 is being trained.

[0068] Subsequently, in the portion where the thickness of the n-type silicon carbide epitaxial layer 34 is increased, an n-type region is formed by photolithography and ion implantation of n-type impurities, e.g., spanning the entire active region, which becomes the n-type current spreading region 3, thereby increasing the thickness of the n-type current spreading region 3. As a result, the n-type current spreading region 3 is formed between the first and second p + -Area 21, 22 is designed in such a way that it is connected to the first and the second p + -Area 21, 22 is in contact. A training sequence of the p + -region 22b and the n-region, which becomes the n-current spreading region 3, can be exchanged.

[0069] Subsequently, the p-type silicon carbide epitaxial layer 35 is formed on the n-type silicon carbide epitaxial layer 34 by epitaxy, which becomes the p-type base region 2 (step S1: second process). Through the processes up to this point, the semiconductor substrate (semiconductor wafer) 30 is manufactured in which the silicon carbide epitaxial layers 32 to 35 are formed on the n-type silicon carbide epitaxial layer 34. + -starting substrate 31 are deposited successively. The p - The silicon carbide epitaxial layer 35 can be formed by ion implanting p-type impurities into an n-type epitaxial film. Subsequently, ion implantation (channel ion implantation) of n-type impurities or p-type impurities for gate threshold voltage control is performed in the p-type silicon carbide epitaxial layer 35 (step S2).

[0070] Subsequently, an outer peripheral portion of the p-type silicon carbide epitaxial layer 35 is removed, leaving the p-type silicon carbide epitaxial layer 35 in a plateau shape (mesa shape) in the active region (step S3). As a result, the n-type silicon carbide epitaxial layer 34 is exposed on the front surface of the semiconductor substrate 30 in the edge termination region. Subsequently, in a surface layer of the p-type silicon carbide epitaxial layer 35, the n-type impurity is formed by photolithography and ion implantation of n-type impurities, e.g., spanning the entire active region. ++ -Source region 4 is formed (step S4: third process).

[0071] As in Fig. 6 is shown below on a surface of the p - -Silicon carbide epitaxial layer 35 in sections corresponding to the training areas of the p ++-contact region 5, an ion implantation mask 41 with openings 41a is formed. Subsequently, from a direction substantially orthogonal to the front surface of the semiconductor substrate 30 using the ion implantation mask 41 as a mask, p-type impurities are ion implanted (first ion implantation) 42, wherein in the surface layer of the p- silicon carbide epitaxial layer 35 at the depth d2, the p ++ -Contact area 5 is formed, which is the n ++ -source region 4 in the depth direction (part 1 of step S5: fifth process). The ion implantation 42 may be performed in multiple steps (multiple times).

[0072] For example, ion implantation 42 with several steps (in Fig. 4 second to fourth step) with different acceleration energies the p ++-Contact area 5 is formed with a box profile. The conditions of the 3-step ion implantation 42 can be, for example, monovalent aluminum (Al + ) as a dopant, and the acceleration energies therefor may be, for example, 160 keV, 90 keV, and 40 keV in this order. A portion of the p-type silicon carbide epitaxial layer 35 except for the n ++ -Source area 4 and the p ++ -Contact area 5 becomes the p-base area 2.

[0073] Furthermore, in continuation with the described ion implantation 42, as in Fig. 7, using the same ion implantation mask 41 from a direction substantially orthogonal to the front surface of the semiconductor substrate 30, an ion implantation (second ion implantation) 43 of ion implanting p-type impurities is performed, which selectively forms the p-type high concentration region 2b in the p-type silicon carbide epitaxial layer 35 (part 2 of step S5: sixth process). The ion implantation 43 is performed with a higher acceleration energy than the ion implantation 42 for forming the p-type impurity. ++ -Contact area 5 (in Fig. 4, first step). In the process in step S5, the order of the ion implantations 42, 43 can be reversed.

[0074] The ion implantation mask 41 with the openings 41a is divided into sections, the training areas of the p ++ contact area 5, whereby the ion implantation 43 of p-type impurities directly under the p ++-Contact Area 5 is enabled. As in Fig. As shown in Figure 8, the p-type high concentration region 2b, which has the first to third sections 2c to 2e with different impurity concentrations, is formed by the diffusion of the p-type impurities in the vertical direction by the ion implantation 43 directly under the p ++ -Contact region 5 is formed. The first portion 2c of the p-type high concentration region 2b is formed near a depth of an ion implantation region 43, and the second and third portions 2d, 2e are formed relatively closer to the source and drain, respectively, from the depth of the ion implantation region 43.

[0075] Furthermore, the p-type impurities implanted by the ion implantation 43 diffuse by the lengths x2a, x2b (see Fig. 1), which are about 0.2 µm from the ends of the openings 41a of the ion implantation mask 41, in the horizontal direction from the p ++-contact area 5. Thus, the p-high concentration area 2b runs from directly under the p ++ -Contact area 5 to directly below the n ++ -source region 4. The width w2 of the p-type high concentration region 2b is larger than a width w11 of the openings 41a of the ion implantation mask 41 by about 0.4 µm (= 0.2 µm 2). The peak impurity concentrations of the p-type high concentration region 2b in the vertical direction and in the horizontal direction are determined by a dose amount of the ion implantation 43.

[0076] The conditions of ion implantation 43 can be, for example, divalent aluminum (Al 2+) as a dopant and, for example, 700 keV as an acceleration energy therefor. The ion implantation 43 may be performed in multiple steps (multiple times). A portion of the p-type base region 2 excluding the p-type high concentration region 2b becomes the p-type channel region 2a of the p-type base region 2. In other words, the p-type channel region 2a of the p-type base region 2 without introduction of impurities by the ion implantations 42, 43 is a region having an impurity concentration equal to that during the epitaxy of the p-type silicon carbide epitaxial layer 35. The process of step S4 and the process of step S5 may be interchanged.

[0077] After the ion implantation mask 41 has been removed, a predetermined edge termination structure is subsequently formed in the edge termination region (step S6). For ion implantation masks used in all ion implantations performed in these manufacturing processes, resist films may be used as the masks or oxide films may be used as the masks. Subsequently, a heat treatment is carried out to activate all impurity ions implanted into the semiconductor substrate 30 (step S7). Subsequently, the trench 6 is formed, which forms the n ++ -source region 4 and the p-channel region 2a of the p-base region 2 and the first p + -region 21 in the n-current spreading region 3 is reached (step S8: seventh process).

[0078] Subsequently, by a general method, polysilicon (poly-Si), for example, is embedded into the trench 6 via the gate insulating film 7, thereby forming the gate electrode 8 (step S9: eighth process). After that, the silicide layer 11 and the source electrode 12 as the surface electrode are formed on the front surface of the semiconductor substrate 30. A silicide layer (not shown) and the drain electrode 16 as a surface electrode are formed on the back surface of the semiconductor substrate 30 (step S10: ninth and tenth processes). After that, the semiconductor substrate 30 is divided (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 including the p-type base region having the p-type high concentration region 2b.

[0079] As described above, the p-type base region according to the first embodiment has a p-type high concentration region in contact with the p-type channel region in a portion separated from the trench sidewall. The impurity concentration of the p-type high concentration region points directly under the p ++ The p-type high concentration region forms a peak concentration at the contact region and decreases in a direction parallel to the front surface of the semiconductor substrate toward the p-type channel region side. The p-type high concentration region acts as a HALO region, suppressing increases in short-channel effects and suppressing decreases in the gate threshold voltage, thereby enabling both a high gate threshold voltage and a low ON resistance to be achieved and suppressing leakage current during the OFF state.

[0080] Furthermore, according to the first embodiment, using the ion implantation for forming the p ++ By using an ion implantation mask used to form the contact region, p-type impurities are ion-implanted from a direction substantially vertical to the front surface of the semiconductor substrate, thereby forming the p-type high-concentration region having the above-described impurity concentration distribution. When forming the p-type high-concentration region that becomes a HALO region, oblique ion implantation onto the trench sidewall is not performed as conventionally, so the p-type high-concentration region can be formed with dimensional accuracy. Thus, the fluctuation of properties of unit cells formed on a surface of a semiconductor wafer can be suppressed.

[0081] Furthermore, the p-type high concentration region according to the first embodiment can be formed by increasing the number of steps (number) of ion implantation in the ion implantation processes for forming the p ++ -contact region; and thus, it is substantially equivalent to no changes in the number of processes and the order of the processes in the method for manufacturing the conventional silicon carbide semiconductor device (see Fig. 14), which does not contain a HALO region. Production line design changes, etc., are unnecessary, and compared to a case where the p-type high-concentration region is formed by oblique ion implantation onto the trench sidewall, the process lead time can be shortened. Thus, the p-type high-concentration region of the p-type base region can be formed efficiently.

[0082] Based on Fig. 4 to 6 and 8 to 10, a method for manufacturing the silicon carbide semiconductor device according to a second embodiment will be described. Fig. 9 and Fig. 10 are cross-sectional views of the silicon carbide semiconductor device according to the second embodiment during manufacturing. The method for manufacturing the silicon carbide semiconductor device according to the second embodiment applies the method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment and is a method for manufacturing a silicon carbide semiconductor device in which the separation distance Tch (see Fig. 1) of the first section 2c of the p-type high concentration region 2b is shortened from the side wall of the trench 6.

[0083] In the method for manufacturing the silicon carbide semiconductor device according to the second embodiment, first, similarly to the first embodiment, the processes in steps S1 to S4 are sequentially carried out (see Fig. 4 and Fig. 5). The following, similar to the first embodiment, is divided into sections corresponding to the training areas of the p ++ -contact region 5, the ion implantation mask 41 with the openings 41a is formed and, using the ion implantation mask 41 as a mask, the ion implantation 42 of p-type impurities is carried out, whereby the p ++ -Contact area 5 is selectively trained (see Fig. 6).

[0084] As in Fig. 9, a width w12 of the openings 41a' of the ion implantation mask 41 is subsequently increased by photolithography and etching. As shown in Fig. 10, are subsequently formed using the ion implantation mask 41 having the openings 41a' with a larger width w12 than at the time of formation of the p ++ -Contact region 5 as a mask from a direction substantially orthogonal to the front surface of the semiconductor substrate 30 p-type impurities are ion-implanted (second ion implantation) 44 and is in the p - -silicon carbide epitaxial layer 35, the p-type high concentration region 2b is selectively formed (step S5).

[0085] The conditions of the ion implantation 44 are, for example, the same conditions as those of the ion implantation 43 in the first embodiment. By the ion implantation 44, similar to the first embodiment, directly under the p ++-Contact region 5, the p-type high concentration region 2p of the p-type base region 2 is formed. Furthermore, the p-type impurities ion-implanted by the ion implantation 44 diffuse by about 0.2 µm from the ends of the openings 41a', which are in the ion implantation mask 41 and have the increased width w12, in the horizontal direction.

[0086] As described above, in the second embodiment, during the ion implantation 44 for forming the p-type high concentration region 2b, the ion implantation mask 41 is used in which the width w12 of the openings 41a' is larger than that during the ion implantation 42 for forming the p-type high concentration region 2b. ++-contact region 5. As a result, the width w2 of the p-type high concentration region 2b becomes larger than when the p-type high concentration region 2b is formed in the first embodiment, so that the separation distance Tch of the first portion 2c of the p-type high concentration region 2b from the sidewall of the trench 6 can be shortened.

[0087] Instead of the ion implantation mask 41, an ion implantation mask having openings with the width w12 may be newly formed, and the ion implantation 44 may be performed using the newly formed ion implantation mask as a mask. Thus, the processes in steps S6 to S10 are sequentially performed similarly to the first embodiment (see Fig. 4), thereby completing a silicon carbide semiconductor device in which the separation distance Tch of the first portion 2c of the p-type high concentration region 2b from the sidewall of the trench 6 is further shortened.

[0088] As described above, according to the second embodiment, similar effects to those of the first embodiment can be obtained. Furthermore, according to the second embodiment, the opening widths of the ion implantation mask used in the ion implantation for forming the p-type high concentration region are widened, thereby enabling the separation distance of the first portion of the p-type high concentration region to be further shortened.

[0089] In a first example, the diffusion in the horizontal direction of p-type impurities ion-implanted into the silicon carbide epitaxial layer was verified. Fig. Figure 11 is a characteristic diagram schematically showing the distribution of impurities ion-implanted into a silicon carbide epitaxial layer. Fig. Figure 11 shows results of a simulation of the diffusion of p-type impurities ion-implanted from a given point (1 point) 52 of a surface (ion implantation surface) of the silicon carbide epitaxial layer 51. In Fig. In Fig. 11, a region 53 where many p-type impurities exist is indicated by hatching, and the p-type impurity diffusion to positions outside the region 53 is not shown. The diffusion of the p-type impurities can be estimated by scanning capacitance microscopy, nonlinear dielectric scanning microscopy, scanning microwave microscopy, or the like.

[0090] In Fig. 11, a horizontal axis is a depth [Å] from the ion implantation surface of the silicon carbide epitaxial layer 51. In Fig. 11, a vertical axis is a length of diffusion of p-type impurities in the horizontal direction from the predetermined point 52 (= 0 [Å]) of the ion implantation surface of the silicon carbide epitaxial layer 51 in a direction (the horizontal direction) parallel to the ion implantation surface. The intersection line CC' passes through the predetermined point 52 of the ion implantation surface of the silicon carbide epitaxial layer 51 and is a intersection line orthogonal to the ion implantation surface. The conditions of ion implantation of p-type impurities into the silicon carbide epitaxial layer 51 were divalent aluminum (Al 2+ ) as the dopant and that the acceleration energy for it was set to 700 keV, for example.

[0091] From the Fig. From the results shown in Figure 11, it was confirmed that the p-type impurities ion-implanted from the predetermined point 52 of the ion implantation surface of the silicon carbide epitaxial layer 51 expand, diffuse from the ion implantation surface of the silicon carbide epitaxial layer 51 in the vertical direction, and diffuse in the horizontal direction substantially symmetrically centered around the predetermined point 52. Further, it was confirmed that a length x2' of diffusion in the horizontal direction at a depth position of about 0.4 μm from the ion implantation surface of the silicon carbide epitaxial layer 51 is about 0.2 μm.

[0092] Subsequently, a relationship between the peak concentration of the first portion 2c of the p-type high concentration region 2b and the separation distance Tch of the first portion 2c of the p-type high concentration region 2b from the sidewall of the trench 6 was verified. Fig. 12 is a characteristic diagram showing a relationship between the peak concentration of a first portion of a p-type high concentration region and the separation distance in a second example. Fig. In FIG. 12, a horizontal axis represents the peak concentration of the first portion of the p-type high concentration region, and a vertical axis represents a gate threshold voltage Vth of the silicon carbide semiconductor device 10 according to the first embodiment described above. The voltage applied between the drain and source in the silicon carbide semiconductor device 10 was set to 20 V.

[0093] From the Fig.From the results shown in Figure 12, it was confirmed that the gate threshold voltage Vth does not vary easily regardless of the peak concentration of the first portion 2c of the p-type high concentration region 2b when the separation distance Tch is wider than 0.1 μm. Further, it was confirmed that the narrower the separation distance Tch is set, the higher the gate threshold voltage Vth can be set. Thus, the present invention is useful when the separation distance Tch is 0.1 μm or smaller. Further, it was confirmed that the higher the peak concentration of the first portion of the p-type high concentration region is set, the higher the gate threshold voltage Vth can be set.

[0094] In the foregoing, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention. For example, the above-described ion implantation conditions for forming the p ++ -contact area and the p-high concentration area are an example and they can be adjusted differently according to specifications.

[0095] According to the described embodiments of the present invention, the p-type high concentration region functions as a HALO region, suppressing increases in short-channel effects and suppressing gate threshold voltage reductions, thereby enabling both a high gate threshold voltage and a low ON resistance, as well as suppressing leakage current during the OFF state. Furthermore, according to the described embodiments of the invention, in forming the p-type high concentration region that becomes the HALO region, oblique ion implantation onto the trench sidewall, such as that conventionally used, is not used, so the p-type high concentration region can be formed efficiently and with dimensional accuracy.

[0096] The silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention achieve an effect that a base region having a high concentration region can be formed efficiently and with dimensional accuracy in a portion separated from the trench sidewall.

[0097] As described, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device are useful for power semiconductor devices used in power conversion equipment and power supply devices such as industrial machines.

[0098] While the invention has been described with reference to a specific embodiment for the purpose of full and clear disclosure, it is intended that the appended claims not be limited thereto, but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which properly fall within the basic teachings presented herein.

Claims

[1] A silicon carbide semiconductor device (10) comprising: a semiconductor substrate (30) containing silicon carbide and having a front surface and a rear surface opposite the front surface, the semiconductor substrate (30) containing: a first semiconductor layer (34) of a first conductivity type having an upper surface and a lower surface, and a second semiconductor layer (35) disposed on the upper surface of the first semiconductor layer (34) and having an upper surface forming the front surface of the semiconductor substrate (30) and a lower surface facing the upper surface of the first semiconductor layer (34); a first semiconductor region (4) of the first conductivity type selectively disposed at the upper surface of the second semiconductor layer (35); a second semiconductor region (5) of a second conductivity type selectively disposed at the upper surface of the second semiconductor layer (35) and having a lower surface with a smaller depth than a lower surface of the first semiconductor region (4); a third semiconductor region (2) of the second conductivity type having a lower impurity concentration than the second semiconductor region (5), wherein the third semiconductor region (2) is a portion of the second semiconductor layer (35) excluding the first semiconductor region (4) and the second semiconductor region (5), wherein the third semiconductor region (2) contains: a high impurity concentration region (2b) of the second conductivity type facing the second semiconductor region (5) in the depth direction and touching the second semiconductor region (5), and a low impurity concentration region (2a) of the second conductivity type facing the high impurity concentration region (2b) in a direction parallel to the front surface of the semiconductor substrate (30), the low impurity concentration region (2a) having an upper surface facing the first semiconductor region (4) and a lower surface facing the upper surface of the first semiconductor layer (34) in the depth direction, the low impurity concentration region (2a) being a portion of the third semiconductor region (2) excluding the high impurity concentration region (2b); a trench (6) penetrating the first semiconductor region (4) and the low impurity concentration region (2a) from the front surface of the semiconductor substrate (30) and reaching the first semiconductor layer (34); a gate insulating film (7) disposed on an inner surface of the trench (6); a gate electrode (8) disposed over the gate insulating film (7) in the trench (6); a first electrode (11) electrically connected to the first semiconductor region (4) and to the second semiconductor region (5); and a second electrode (16) arranged at the rear surface of the semiconductor substrate (30), wherein the impurity concentration in the high impurity concentration region (2b) decreases towards the low impurity concentration region (2a) in a direction parallel to the front surface of the semiconductor substrate (30). [2] The silicon carbide semiconductor device (10) according to claim 1, wherein a width of the high impurity concentration region (2b) in a direction parallel to the front surface of the semiconductor substrate (30) is larger than a width of the second semiconductor region (5). [3] Silicon carbide semiconductor device (10) according to claim 1 or 2, wherein the high impurity concentration region (2b) has, in the depth direction, a part facing the first semiconductor region (4) and another part facing the second semiconductor region (5), the impurity concentration in the high impurity concentration region (2b) decreases in the depth direction toward the front surface of the semiconductor substrate (30) and decreases in the depth direction toward the rear surface of the semiconductor substrate (30), and the first semiconductor region (4) has an upper surface forming the front surface of the semiconductor substrate (30) and the lower surface facing the high impurity concentration region (2b), and wherein a point of the high impurity concentration region (2b) having a highest impurity concentration is located at a position separated from the lower surface of the first semiconductor region (4) in the depth direction. [4] The silicon carbide semiconductor device (10) according to claim 1 to 3, wherein a distance between the high impurity concentration region (2b) and an outer surface of the trench (6) in a direction parallel to the front surface of the semiconductor substrate (30) is in a range of 0.04 µm to 0.2 µm. [5] The silicon carbide semiconductor device (10) according to claim 4, wherein the distance between the high impurity concentration region (2b) and the outer surface of the trench (6) is in a range of 0.06 µm to 0.1 µm. [6] A method of manufacturing a silicon carbide semiconductor device (10), the method comprising: in a first process, depositing a first semiconductor layer (34) of a first conductivity type containing silicon carbide on an upper surface of a starting substrate (31) of the first conductivity type containing silicon carbide, the first semiconductor layer (34) having a lower impurity concentration than the starting substrate (31); in a second process, depositing a second semiconductor layer (35) of a second conductivity type containing silicon carbide on a surface of the first semiconductor layer (34), the second semiconductor layer (35) having a top surface; in a third process, selectively forming a first semiconductor region (4) of the first conductivity type at the upper surface of the second semiconductor layer (35); in a fourth process, forming an ion implantation mask (41) having an opening at a predetermined position on the upper surface of the second semiconductor layer (35); in a fifth process, performing a first ion implantation of impurities of a second conductivity type using the ion implantation mask (41) to form, at the upper surface of the second semiconductor layer (35), a second semiconductor region (5) of the second conductivity type having a higher impurity concentration than the second semiconductor layer (35) and having a lower surface with a smaller depth than a lower surface of the first semiconductor region (4); in a sixth process, forming a third semiconductor region (2) of the second conductivity type and having a lower impurity concentration than the second semiconductor region (5), wherein the third semiconductor region (2) is a portion of the second semiconductor layer (35) except for the first semiconductor region (4) and the second semiconductor region (5), the sixth process comprising: Carrying out a second ion implantation of impurities of the second conductivity type using the ion implantation mask (41) with a higher acceleration energy than an acceleration energy of the first ion implantation to form a high impurity concentration region (2b) of the second conductivity type in the second semiconductor layer (35) closer to a rear surface of the starting substrate (31) than the second semiconductor region (5), which high impurity concentration region (2b) has a higher impurity concentration than the second semiconductor layer (35) and a lower impurity concentration than the second semiconductor region (5), and Leaving a portion of the third semiconductor region (2) other than the high impurity concentration region (2b) as a low impurity concentration region (2a) of the second conductivity type, which faces the high impurity concentration region (2b) in a direction parallel to the upper surface of the second semiconductor layer (35) and contacts the second semiconductor region (5); in a seventh process, forming a trench (6) penetrating the first semiconductor region (4) and the low impurity concentration region (2a) from the upper surface of the second semiconductor layer (35) and reaching the first semiconductor layer (34); in an eighth process, forming a gate insulating film (7) on an inner surface of the trench (6) and a gate electrode (8) in the trench (6) via the gate insulating film (7); in a ninth process, forming a first electrode (11) electrically connected to the first semiconductor region (4) and to the second semiconductor region (5); and in a tenth process, forming a second electrode (16) at the rear surface of the starting substrate (31). [7] The method according to claim 6, wherein the fifth process and the sixth process are executed sequentially. [8] The method according to claim 6 or 7, wherein a region of the second ion implantation in the sixth process is set deeper in the depth direction than the lower surface of the first semiconductor region (4). [9] The method according to claim 6 to 8, further comprising widening a size of the opening of the ion implantation mask (41) in a direction parallel to the upper surface of the second semiconductor layer (35) after the fifth process and before the sixth process. [10] The method according to claim 6 to 9, wherein a distance between the high impurity concentration region (2b) and an outer surface of the trench (6) in a direction parallel to the front surface of the semiconductor substrate (30) in the sixth process is in a range of 0.04 µm to 0.2 µm. [11] The method according to claim 10, wherein the distance between the high impurity concentration region (2b) and the outer surface of the trench (6) is in a range of 0.06 µm to 0.1 µm. [12] The method according to claim 6 to 11, wherein the second conductivity type impurities implanted by the second ion implantation diffuse into the second semiconductor layer (35) in the sixth process, and the impurity concentration in the high impurity concentration region (2b) decreases toward the low impurity concentration region (2a) in the direction parallel to the upper surface of the second semiconductor layer (35). [13] The method according to claim 6 to 12, wherein the second conductivity type impurities implanted by the second ion implantation diffuse into the second semiconductor layer (35) in the sixth process, and a width of the high impurity concentration region (2b) becomes larger than a width of the opening of the ion implantation mask (41) in a direction parallel to the upper surface of the second semiconductor layer (35).

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