CURRENT-TO-DIGITAL PRECISION CONVERTER

Abstract

A delta-sigma modulator (110) for detecting a current input signal from a current source (120), the delta-sigma modulator (110) comprising: a first node (138) configured to connect to the current source (120) and receive the current input signal, wherein the first node (138) is an input of the delta-sigma modulator (110); a capacitive summing circuit (132) having an input connected to the first node (138) and an output connected to a second node (142), the capacitive summing circuit (132) being configured to amplify a signal at the first node (138) and deliver an amplified signal to the second node (142), the capacitive summing circuit (132) comprising (i) a first amplifier (134) having an input connected to the first node (138) and an output connected to the second node (132) and (ii) a first capacitance (136) connected between the output of the first amplifier (134) and the input of the first amplifier (134); a loop filter circuit (140) having an input connected to the second node (142) and an output connected to a third node (152), the loop filter (140) being configured to filter the amplified signal at the second node (142) and supply a filtered signal to the third node (152); a quantizer circuit (150) having an input connected to the third node (152) and an output connected to a fourth node (154), the fourth node (154) being an output of the delta-sigma modulator (110), the quantizer circuit (150) being configured to quantize the filtered signal at the third node (152) and supply a quantized signal to the fourth node (154); a first feedback path (160) connected between the fourth node (154) and the first node (138), wherein at least one second capacitor (670) is arranged in the first feedback path (160) and is configured to capacitively couple the quantized signal to the first node (138); a first switch (404) connected between the current source (120) and the first node (138); and at least one processor configured to operate the first switch (404) to (i) open a first predetermined time period before any change in the value of the quantized signal at the fourth node (154) and (ii) close a second predetermined time period after any change in the value of the quantized signal at the fourth node (154).

Description

FIELD OF INVENTION

[0001] The device and method disclosed in this document relate to current sensing and, in particular, to a current-to-digital converter. GENERAL STATE OF THE ART

[0002] Unless otherwise indicated herein, the materials described in this section do not constitute prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.

[0003] Current sensing circuits are widely used in many sensor applications to process an analog current signal and convert it to the digital domain. For current sensing applications requiring high resolution and narrow bandwidth, a delta-sigma modulator (DSM) is often used to perform digitization due to its superior power efficiency compared to other analog-to-digital converter (ADC) architectures. However, in many applications, such as sensing the current of a high-impedance sensor, the current sensing circuit must have a high input impedance to avoid consuming current and degrading the sensor's performance.Accordingly, when measuring a current from a high-impedance sensor, conventional DSM-based current sensing circuits must utilize some type of front-end signal processing circuitry, such as a preamplifier stage, to convert the high-impedance sensor current signal into a low-impedance output signal so that it can be digitized.

[0004] Fig. 1 shows a conventional DSM-based current acquisition system 10 for measuring and digitizing a current signal I IN from a signal source 20 with high output impedance. The current signal I IN is supplied to a front-end signal processing stage 30 before being digitized by a delta-sigma modulator 40 to produce a digital output signal D OUTHowever, as the required resolution increases, the high dynamic range enforced at the input nodes of both the front-end signal processing stage 30 and the delta-sigma modulator 40 results in a relatively high-performance implementation. Accordingly, what is needed is a current sensing circuit that provides high input impedance, low power consumption, and high dynamic range.

[0005] US 2008 / 0062022 A1 describes a delta-sigma modulator with a feedback topology in which various feedback paths are provided between the quantizer output and the integrator stages of the loop filter. Part of the feedback is provided via AC-coupled paths to reduce the signal levels within the loop filter. The goal is to reduce the linearity and component size requirements within the filter.

[0006] US 9,602,126 B2 describes a sigma-delta analog-to-digital converter in which the filtering for noise shaping is partially shifted to the feedback path. The converter includes a digital filter unit in the feedback path, which allows for the distribution of poles between the feedforward and feedback paths. This arrangement is particularly suitable for low-latency applications, such as digital audio amplifiers.

[0007] US 2006 / 0250853 A1 describes a method for current measurement using a delta-sigma modulator, which can be used in particular for reading flash memory cells. The system comprises an integration stage, a clocked comparator, and a feedback circuit that stabilizes the integrator output. The average cell current is provided as a digital output signal, with noise components suppressed by averaging. BRIEF PRESENTATION

[0008] The present invention provides a delta-sigma modulator and a current detection system having the features of the independent claims. Further advantageous embodiments are the subject of the dependent claims.

[0009] A delta-sigma modulator for detecting a current input signal from a current source is disclosed. The delta-sigma modulator comprises: a first node configured to connect to the current source and receive the current input signal, the first node being an input of the delta-sigma modulator; a capacitive summing circuit having an input connected to the first node and an output connected to a second node, the capacitive summing circuit configured to amplify a signal at the first node and provide an amplified signal to the second node, the capacitive summing circuit comprising (i) a first amplifier having an input connected to the first node and an output connected to the second node, and (ii) a first capacitance connected between the output of the first amplifier and the input of the first amplifier;a loop filter circuit having an input connected to the second node and an output connected to a third node, the loop filter being configured to filter the amplified signal at the second node and deliver a filtered signal to the third node; a quantizer circuit having an input connected to the third node and an output connected to a fourth node, the fourth node being an output of the delta-sigma modulator, the quantizer circuit being configured to quantize the filtered signal at the third node and deliver a quantized signal to the fourth node; and a first feedback path connected between the fourth node and the first node, at least one second capacitance being arranged in the first feedback path and configured to capacitively couple the quantized signal to the first node.

[0010] A current sensing system is disclosed. The current sensing system comprises: a current source configured to provide a current input signal; and a delta-sigma modulator comprising: a first node configured to connect to the current source and receive the current input signal, the first node being an input of the delta-sigma modulator;a capacitive summing circuit having an input connected to the first node and an output connected to a second node, the capacitive summing circuit being configured to amplify a signal at the first node and deliver an amplified signal to the second node, the capacitive summing circuit comprising (i) a first amplifier having an input connected to the first node and an output connected to the second node, and (ii) a first capacitance connected between the output of the first amplifier and the input of the first amplifier; a loop filter circuit having an input connected to the second node and an output connected to a third node, the loop filter being configured to filter the amplified signal at the second node and deliver a filtered signal to the third node;a quantizer circuit having an input connected to the third node and an output connected to a fourth node, wherein the fourth node is an output of the delta-sigma modulator, the quantizer circuit configured to quantize the filtered signal at the third node and deliver a quantized signal to the fourth node; and a first feedback path connected between the fourth node and the first node, wherein at least one second capacitance is arranged in the first feedback path and configured to capacitively couple the quantized signal to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above aspects and other features of the delta-sigma modulator and current sensing system are discussed in the following description in conjunction with the accompanying drawings. Fig. Figure 1 shows a conventional DSM-based current acquisition system for measuring and digitizing a current signal from a high-impedance signal source. Fig. Figure 2 shows a current sensing system that uses a power-efficient architecture for current-to-digital conversion. Fig. 3 shows an exemplary implementation of the current detection system of Fig. 2. Fig. Figure 4 shows an exemplary alternative current sensing system with a capacitive front-end conditioning stage for comparison. Fig. 5 shows another current detection system with a switch configured to selectively connect the signal source to the delta-sigma modulator. Fig. Figure 6 shows another current sensing system with a dynamic element matching circuit arranged in at least the primary feedback path in addition to the FIR DAC. Fig. Figure 7 shows another current sensing system with a dynamic element matching circuit arranged in at least the primary feedback, without a FIR DAC. DETAILED DESCRIPTION

[0012] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiments illustrated in the drawings and described in the following written specification. It is to be understood that no limitation as to the scope of the disclosure is intended. It is further understood that the present disclosure includes all alterations and modifications to the illustrated embodiments and further includes applications of the principles of the disclosure that would normally occur to one of ordinary skill in the art to which the present disclosure relates.

[0013] Fig. Figure 2 shows a current sensing system 100 that utilizes a power-efficient architecture for current-to-digital conversion. The current sensing system 100 achieves over 15-bit resolution and sub-MHz bandwidth with greatly reduced power consumption by advantageously reducing the number of nodes in the system that require high dynamic range. Reducing the number of nodes in the system that require high dynamic range is accomplished by incorporating a capacitive conditioning stage into the primary feedback loop of a delta-sigma modulator (DSM) 110, so that high dynamic range only needs to be enforced at a single node of the delta-sigma modulator 110. Furthermore, the capacitive conditioning stage helps establish a very high input impedance at the input 112 of the delta-sigma modulator 110.In this way, the input 112 of the delta-sigma modulator 110 can be connected directly to a high-impedance signal source 120 without the need for a front-end preamplifier stage or the like.

[0014] The current detection system 100 includes the delta-sigma modulator 110, which is configured to directly receive an analog current input signal I IN from a high-impedance signal source 120 at the input 112 and providing a digital output signal D OUTat an output 114. The delta-sigma modulator 110 includes, in a forward path, a summing block 130, a loop filter 140, and a quantizer 150. The delta-sigma modulator 110 includes a negative feedback loop (also referred to herein as the "DSM loop") formed by a primary feedback path 160 with a FIR-DAC (finite impulse response digital-to-analog converter) 170. Furthermore, in at least some embodiments, the delta-sigma modulator 110 includes an offset correction circuit formed by a secondary feedback path 180 with an offset correction circuit 190.

[0015] The high-impedance signal source 120 is a time-varying current signal source with very high impedance, such as a time-varying capacitance, a capacitively coupled time-varying voltage source, or the like. In many embodiments, the high-impedance signal source 120 is a high-impedance sensor configured to measure a particular physical quantity or parameter. In some embodiments, the high-impedance sensor may comprise a capacitive sensor, such as a microphone, biased by a high-impedance source, such as a reverse-biased diode. In one embodiment, the high-impedance signal source 120 has an impedance on the order of, for example, at least one gigaohm or higher. In this way, the high-impedance signal source 120 can be considered similar to an ideal current source (which has a theoretically infinite impedance).It should be understood that when a high-impedance sensor is provided as a signal source, the current sensing system 100 must have a high input impedance to avoid drawing current (beyond a negligible amount) and thus degrading the performance of the high-impedance sensor. The current sensing system 100 described herein advantageously achieves a very high input impedance without any front-end signal conditioning circuitry between the signal source 120 and the delta-sigma modulator 110. Although the current sensing system 100 is most advantageously utilized in conjunction with a high-impedance current source, the high-impedance signal source 120 may alternatively comprise a low-impedance signal source without affecting the functionality of the current sensing system 100 and while still achieving improved power efficiency.

[0016] The summing block 130 is operatively connected to the input 112 to provide the current input signal I IN to receive, and with the primary feedback path 160, in particular with an output of the FIR-DAW 170, to provide a negative feedback current signal I FB to receive. The summing block 130 includes a capacitive summing circuit 132 configured to receive the current input signal I IN and the negative feedback current signal I FB at a summing node 138. The capacitive summing circuit 132 also serves as a signal conditioning function and is configured to amplify a sum or difference from the current input signal I IN and the negative feedback current signal I FB and outputting a difference signal V DIFFat a first intermediate node 142. The capacitive summing circuit 132, in combination with the input capacitance of the signal source 120 and / or the capacitance of the FIR-DAC 170, is designed as a pure amplification stage and has a flat or all-pass frequency response / transfer function H CSand is not configured to filter or otherwise shape the frequency content of the output signal. In many embodiments, the capacitive summing circuit 132 is configured to have a gain G greater than 1 (e.g., G = 3), but in some embodiments, the capacitive summing circuit 132 may merely act as a buffer with a unity gain. In at least one embodiment, the capacitive summing circuit 132 includes at least one amplifier 134 having a capacitor 136 connected between its output terminal and its negative input terminal. The negative input terminal of the amplifier 134 is connected to the input 112 and is configured to receive the current input signal I IN The difference signal V DIFF is supplied to the output terminal of amplifier 134.

[0017] The loop filter 140 is operatively connected to the output of the summing block 130 and / or the first intermediate node 142 and is configured to filter the difference signal V DIFF and supplying the filtered signal V FILT at a second intermediate node 152. The loop filter 140 includes one or more filter stages, which may include continuous-time filter stages, discrete-time filter stages, and / or hybrid filter stages. In at least one embodiment, the one or more filter stages of the loop filter 140 are noise-shaping filters with a frequency response / transfer function H LF , which has a higher frequency content of the difference signal V DIFFsuppressed. It is understood that suppressing higher-frequency content helps reduce quantization noise in current sensing system 100. In at least some embodiments, one or more of the filter stages comprise integrator circuits, each including an amplifier, a capacitor connected between the output terminal and the inverting input terminal of the amplifier, and a resistor connected to the inverting input terminal.

[0018] The quantizer 150 is operatively connected to the output of the loop filter 140 and / or the second intermediate node 152 and is configured to quantize and / or digitize the filtered signal V FILT and delivering a quantized digital output signal D OUTat an output node 154 connected to the output 114. It is understood that a quantized signal is a signal with only a predetermined number of possible values / magnitudes. In at least one embodiment, the quantizer 150 includes one or more comparators configured to generate a single-bit or multi-bit output signal. In particular, in the case of a single-bit output, the quantizer 150 includes a single comparator configured to output a first voltage / current value (e.g., a logic "high" voltage) in response to the filtered signal V FILT is above a threshold, and outputting a second voltage / current value (e.g., a logic “low” voltage) in response to the filtered signal V FILTis below the threshold. In the case of a multi-bit output, the quantizer 150 comprises a plurality of comparators configured to output a different voltage / current level based on comparisons of the filtered signal V FILT with several different thresholds.

[0019] The primary feedback path 160 is provided between the output of the quantizer 150 and / or the output node 154 and an input of the summing block 130 and / or the summing node 138. The FIR DAC 170 is provided in the primary feedback path 160 and has an input connected to the output of the quantizer 150 and an output connected to the input of the summing block 130. The FIR DAC 170 is configured to convert the quantized digital output signal D OUT into the analog negative feedback current signal I FB. In at least one embodiment, the FIR-DAC 170 has a frequency response / transfer function H FIR . In at least one embodiment, the FIR DAC 170 includes digital logic 172 configured to operate one or more switches and / or taps connected to an array of capacitors 176 to generate the negative feedback current signal I FB It is understood that the FIR-DAW 170 improves the gain of the 200 system.

[0020] The secondary feedback path 180 is also provided between the output of the quantizer 150 and an input of the summing block 130. The offset correction circuit 190 is provided in the secondary feedback path 180 and has an input connected to the output of the quantizer 150 and an output connected to the input of the summing block 130. The offset correction circuit 190 is configured to set the DC bias and / or the DC operating point at the input of the summing block 130 and to cancel any offset in the system 100. In particular, the offset correction circuit 190 is configured to adjust or correct the DC offset present at the inverting input of the amplifier 134 so that it is equal to a desired DC bias point (e.g., zero). In some embodiments, the offset correction circuit 190 includes a proportional integrator circuit and / or a low-pass filter circuit.The offset correction circuit 190 can be implemented using analog, digital, or mixed components.

[0021] It is understood that the negative feedback current signal I FB a similar but negative form to the current input signal I IN Accordingly, the difference signal V DIFF compared to the current input signal I IN with the negative feedback current signal I FB of quite small size. Accordingly, the capacitive summing circuit 132 can achieve a relatively large gain G with a relatively small capacitor 136. Since the difference signal V DIFF is quite small, high dynamic range requirements do not have to be enforced at the input of the loop filter 140. Thus, the loop filter 140 can be implemented in a more power-efficient manner.

[0022] Fig. 3 shows a current sensing system 200, which is an exemplary implementation of current sensing system 100. In current sensing system 200, high-impedance signal source 120 is depicted as an ideal current source 122 coupled directly to input 112. However, high-impedance signal source 120 may alternatively be depicted as a voltage source coupled to input 112 via a capacitor (not shown) with a capacitance C1.

[0023] The summing block 130 is implemented with a capacitive summing circuit 232, formed by an amplifier 234 with a capacitor 236, connected between its output and its inverting input. The capacitor 236 has a capacitance C1 / G, where G is the gain of the capacitive summing circuit 232. The noise of the capacitive summing circuit 232 is connected as a voltage source 238 with a voltage V n1which is connected to a non-inverting input amplifier 234. The capacitive summing circuit 232 is configured to amplify a sum or difference of the current input signal I IN and the negative feedback current signal I FB and outputting a difference signal V DIFF , as discussed above similarly with respect to the current sensing system 100.

[0024] The loop filter 140 includes at least one integrator circuit 242 formed by an amplifier 244 with a capacitor 246 connected between its output and its inverting input, and a resistor 248 coupled between the input of the amplifier 244 and the output of the amplifier 234 of the capacitive summing circuit 232. The resistor 248 may take the form of a resistor, a switched capacitor, or the like. The capacitor 246 has a capacitance C2, and the resistor 248 has a resistance R. In some embodiments, the later stages 250 of the loop filter 140 may include further integrators configured similarly. The integrator 232 and / or the later stages 250 are configured to filter the difference signal V DIFF and delivering a filtered signal V FILT , as discussed above analogously with respect to the current detection system 100.

[0025] The FIR-DAC 170 includes logic 272 configured to operate a plurality of switches and / or taps 274 connected to an array of capacitors 276 to generate the negative feedback current signal I FB to generate. The capacitors 276 have a total capacitance C1. In at least one embodiment, the total capacitance of the capacitors 276 is greater than or equal to the time-varying capacitance of the high-impedance signal source 120. The digital logic 272 is configured to operate the switches and / or taps 274 to generate the analog negative feedback current signal I FB based on the quantized digital output signal D OUTto generate, as similarly discussed above with respect to current sensing system 100. In particular, each capacitor 276 has a first terminal connected to summing node 138 and a second terminal connected to at least one of switches and / or taps 274. Digital logic 272 is configured to operate switches and / or taps 274 to selectively connect the second terminal of each capacitor 176 to either a first voltage (e.g., VDD) or a second voltage (e.g., GND). Digital logic 272 may include any suitable logic, such as delay elements, a processor, a controller, a programmable logic device, one or more logic gates, or the like.

[0026] The current sensing system 200 has significantly reduced input-referred noise compared to a similar system in which the capacitive summing circuit 232 is not included within the DSM loop, but rather a front-end conditioning stage is included between the high-impedance signal source 120 and the input 112 of the delta-sigma modulator 110. In particular, Fig. 4 shows, for comparison purposes, an exemplary implementation of a current sensing system 300 similar to current sensing system 200, except that the capacitive summing circuit 232 is removed from the DSM loop and instead a similar capacitive conditioning circuit 332 is used to couple the high-impedance signal source 120 to the input 112 of a delta-sigma modulator 310. Furthermore, in current sensing system 300, the array of capacitors 176 is substituted by an array of resistors 376 having a total resistance R. Finally, it should be understood that the DC bias point of system 300 is set by resistors 248 and 376, rather than an offset correction circuit as in system 200. Other elements of current sensing system 300 that are equivalent to the elements of current sensing system 200 are designated by the same reference numerals and will not be described in detail again.

[0027] In the exemplary current sensing system 300, the capacitive conditioning circuit 332 and the first integrator 242 of the loop filter 140 dominate the system input-referred noise. Specifically, the input-referred noise of the current sensing system 300 is approximately equal to: Vn12‖sC1‖2+8kTR‖sC1‖2, where s = jω, k is the Boltzman constant and T is the working temperature.

[0028] Consequently, the amplifiers in the capacitive conditioning circuit 332 and the first integrator 242 must consume current to suppress noise and provide sufficient drive strength for a small resistance R.

[0029] Again with reference to Fig. 3, to address this problem, the current sensing system 200 advantageously includes the capacitive summing circuit 232 within the DSM loop of the delta-sigma modulator 110, which serves the signal conditioning function. By moving the capacitive summing circuit 232 into the DSM feedback loop, the capacitive summing circuit 232 amplifies only the difference between the input current signal I IN and the negative feedback current signal I FB , which allows the use of a reduced feedback capacitor C1G to amplify the signal and attenuate noise from later stages. Furthermore, by using capacitors 276 in the FIR DAC 170 instead of resistors 376, a source of noise in the feedback path 160 is eliminated. As a result, the input-referred noise of the current sensing system 200 is approximately equal to: Vn12(C1G+C1C1G)2‖sC1G‖2+4kTR‖sC1G‖2=Vn12‖sC1‖2(1+1G)2+4kTR‖sC1G‖2.

[0030] For G > 1, the noise penalty of the capacitive signal conditioning stage is limited, while the noise reduction of subsequent loop filter stages is significant. Thus, current sensing system 200 has greatly improved performance compared to current sensing system 300 for most situations. In particular, current sensing system 200 has reduced input-referred noise, enabling a more power-efficient implementation for given gain, resolution, and bandwidth requirements.

[0031] Fig. 5 shows another current sensing system 400 that is substantially similar to current sensing system 200, except that it further includes a switch 404 configured to selectively connect and disconnect high-impedance signal source 120 to and from input 112 of delta-sigma modulator 110 based on a control signal. In at least one embodiment, a processor, controller, or the like (not shown) is configured to actuate switch 404 with a control signal such that switch 404 is briefly opened while the value of the quantized output signal D OUT at the output node 154. In this way, changes in the value of the quantized output signal D OUT no interference with the input current signal I INIn at least one embodiment, switch 404 is opened a small predetermined time period before the end of each clock cycle of the comparators of quantizer 150 and closed a small predetermined time period after the beginning of each clock cycle of the comparators of quantizer 150. In embodiments where high-impedance current source 120 is a sensor, this improves system performance by not causing such disturbances.

[0032] Fig. 6 shows another current sensing system 500 that is substantially similar to current sensing system 200, except that it further includes a dynamic element matching (DEM) circuit 504 disposed in at least the primary feedback path 160. In some embodiments, the DEM circuit 504 is disposed in a shared portion of both the primary and secondary feedback paths 160 and 180. In particular, the DEM circuit 504 is included in embodiments with a multi-bit quantizer 150. The DEM circuit 504 is configured to mitigate nonlinearity in the FIR DAC 170 when used with a multi-bit quantizer.

[0033] In at least some embodiments, the FIR DAC 170 may be omitted when a multibit quantizer 150 and a DEM circuit 504 are used. In particular, Fig. 7 shows another current detection system 600 that is substantially similar to current detection system 500, except that FIR DAC 170 is eliminated. Instead, the FIR DAC is replaced by a capacitor 670 configured to capacitively couple the output of DEM circuit 504 and / or the quantized output signal D OUT to summing node 138. Capacitance 670 may be one or more capacitors connected in parallel and / or in series. In at least one embodiment, capacitive summing circuit 132, in combination with the input capacitance of signal source 120 and capacitance 670, is configured as a pure gain stage and has a flat or all-pass frequency response / transfer function H CS and is not designed to filter or otherwise shape the frequency content of the output signal, to which the same above with respect Fig. 2 described manner.

Claims

[1] A delta-sigma modulator (110) for detecting a current input signal from a current source (120), the delta-sigma modulator (110) comprising: a first node (138) configured to connect to the current source (120) and receive the current input signal, wherein the first node (138) is an input of the delta-sigma modulator (110); a capacitive summing circuit (132) having an input connected to the first node (138) and an output connected to a second node (142), the capacitive summing circuit (132) being configured to amplify a signal at the first node (138) and deliver an amplified signal to the second node (142), the capacitive summing circuit (132) comprising (i) a first amplifier (134) having an input connected to the first node (138) and an output connected to the second node (132) and (ii) a first capacitance (136) connected between the output of the first amplifier (134) and the input of the first amplifier (134); a loop filter circuit (140) having an input connected to the second node (142) and an output connected to a third node (152), the loop filter (140) being configured to filter the amplified signal at the second node (142) and supply a filtered signal to the third node (152); a quantizer circuit (150) having an input connected to the third node (152) and an output connected to a fourth node (154), the fourth node (154) being an output of the delta-sigma modulator (110), the quantizer circuit (150) being configured to quantize the filtered signal at the third node (152) and supply a quantized signal to the fourth node (154); a first feedback path (160) connected between the fourth node (154) and the first node (138), wherein at least one second capacitor (670) is arranged in the first feedback path (160) and is configured to capacitively couple the quantized signal to the first node (138); a first switch (404) connected between the current source (120) and the first node (138); and at least one processor configured to operate the first switch (404) to (i) open a first predetermined time period before any change in the value of the quantized signal at the fourth node (154) and (ii) close a second predetermined time period after any change in the value of the quantized signal at the fourth node (154). [2] The delta-sigma modulator (110) of claim 1, wherein the first feedback path (160) comprises: a first FIR, Finite Impulse Response, digital-to-analog converter (170) arranged in the first negative feedback path, wherein the FIR digital-to-analog converter (170) is configured to convert the quantized signal at the fourth node (154) into an analog feedback signal and supply the analog feedback signal to the first node (138). [3] Delta-sigma modulator (110) according to claim 2, wherein the FIR digital-to-analog converter (170) comprises: a plurality of second capacitors (176,276), each second capacitor (176) having a first terminal and a second terminal, the first terminal of each second capacitor being connected to the first node (138); a plurality of second switches (240) configured to selectively connect the second terminal of each second capacitor (274) to a first voltage and a second voltage; and a processor (272) configured to operate the plurality of second switches (176,276) to provide the analog feedback signal at the first node (138). [4] The delta-sigma modulator (110) of claim 1, further comprising: a second feedback path (180) connected between the fourth node (154) and the first node (138), the second feedback path (180) comprising: an offset correction circuit (190) arranged in the second feedback path (180), wherein the offset correction circuit (190) is configured to correct a DC offset in the delta-sigma modulator (110) by adjusting a DC offset at the first node (138) to a predetermined DC offset value. [5] The delta-sigma modulator (110) of claim 1, wherein the capacitive summing circuit (132) in combination with the at least one second capacitance (176) provides a flat frequency response. [6] The delta-sigma modulator (110) of claim 1, wherein the loop filter (140) comprises: at least one noise-shaping filter. [7] Delta-sigma modulator (110) according to claim 6, wherein the loop filter (140) comprises: at least one integrator circuit. [8] The delta-sigma modulator (110) of claim 7, wherein the at least one integrator circuit comprises: a second amplifier; a third capacitor connected between an output of the second amplifier and an input of the second amplifier; and a resistor connected between the second node and the input of the second amplifier. [9] Delta-sigma modulator (110) according to claim 1, wherein: the quantizer (150) is a multibit quantizer; and the first feedback path (160) comprises a dynamic element matching circuit. [10] The delta-sigma modulator (110) of claim 1, wherein the first node (138) is directly connected to the current source (120). [11] The delta-sigma modulator (110) of claim 1, wherein the current source (120) is a time-varying capacitance. [12] The delta-sigma modulator (110) of claim 1, wherein the current source (120) is a capacitive sensor. [13] The delta-sigma modulator (110) of claim 1, wherein the current source (120) is a time-varying voltage coupled to the input via a fourth capacitance. [14] Current detection system (100) comprising: a current source (120) configured to provide a current input signal; and a delta-sigma modulator (110) according to one of claims 1 to 13.

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