Hexagonal connection patterns for high-density component packaging

Abstract

Component that features the following: a variety of power supply components; a multitude of mass elements; one or more pairs of transmitting elements; and one or more pairs of receiving elements, each pair of receiving elements being separated from other pairs of receiving elements and from all of the one or more pairs of transmitting elements by one or more of the ground elements, the power supply elements or both; where the elements (400) are arranged in a hexagonal pattern.

Description

[0001] The present disclosure relates to semiconductor packaging: The present disclosure also relates to interconnection patterns and ball grid and / or pin patterns for semiconductor packages (semiconductor housings).

[0002] Rapid advances in electronics, networking, and communication technologies, driven by immense customer demand, have led to the widespread adoption of electronic components and devices of all kinds. The fabrication processes that create the component circuitry on semiconductor (integrated circuit) chips have progressed through many different manufacturing nodes over the past four decades, from 6-µm processes in the mid-1970s to 7-nm processes at the time of writing. The ever-increasing density, functionality, and complexity of the circuitry have presented significant challenges for the semiconductor packaging that supports the integrated circuit chips, including challenges in the mechanical and electrical integration of the semiconductor packaging with an external system circuit.

[0003] US 2013 / 0087918A1 describes a system and method for assigning power supply and ground pins, as well as single-ended or differential signal pairs, to a ball grid array semiconductor package using a hexagonal pattern.

[0004] US 2017 / 0033054A1 describes interconnection patterns for the packaging of electronic components. These interconnection patterns are designs for solder ball arrangements or other types of interconnection mechanisms within a semiconductor package.

[0005] US 2014 / 0293566A1 describes a circuit board that includes a substrate, multiple ground electrodes, and multiple signal electrodes.

[0006] In accordance with one aspect of the invention, a component having the features of the independent claim is provided.

[0007] Beneficial further training opportunities are listed in the sub-requirements.

[0008] Advantageously, each of the one or more pairs of transmitting elements is separated from other pairs of transmitting elements and from all of the one or more pairs of receiving elements by one or more of the ground elements, the current elements, or both.

[0009] Advantageously, each of the multitude of power supply elements of one size is separated from each of the other power supply elements of other sizes by at least one of a ground element, a pair of transmitting elements and a pair of receiving elements.

[0010] Advantageously, each of the one or more pairs of receive elements is assigned to a receive track of a serializer / deserializer (SerDes) circuit, and each of the one or more pairs of transmit elements is assigned to a transmit track of the SerDes circuit.

[0011] Advantageously, the multitude of connecting elements includes a boundary row configured to run adjacent to an edge of the semiconductor package, with none of the multitude of power supply elements located in the boundary row.

[0012] Advantageously, there are eight pairs of receive elements, with each pair of receive elements being assigned to one of eight receive tracks of a serializer / deserializer (SerDes) circuit, and there are eight pairs of transmit elements, with each pair of transmit elements being assigned to one of eight transmit tracks of the SerDes circuit.

[0013] Advantageously, the SerDes circuit is communicatively connected to a packet switch.

[0014] Advantageously, the SerDes circuit is communicatively connected to a packet router.

[0015] In accordance with one aspect, a connection pattern for a semiconductor package is provided, which has the following features: featuring a multitude of connecting elements arranged in a hexagonal pattern: a variety of power supply components; a multitude of mass elements; one or more pairs of transmitting elements; and one or more pairs of receiving elements; the multitude of connecting elements includes the following: a border row configured to run adjacent to a semiconductor package border; and none of the numerous power supply elements are located in the outer row. Advantageously:

[0016] The multitude of power supply elements exhibits individual connecting power supply elements and: Each connecting power supply element of the multitude of power supply elements of one size is located in a neighbor-free configuration with respect to each of the other connecting power supply elements of other sizes from the multitude of power supply elements.

[0017] In accordance with one aspect, a component is provided which has the following features: a group of coupling circuit layers; an integrated circuit chip bonded to a first surface of the group of coupling circuit layers; an arrangement of hexagonally arranged, electrically conductive connecting elements on a second surface of the group of coupling circuit layers, wherein the electrically conductive connecting elements are organized into a plurality of groups, where one or more of the groups each exhibit the following: a variety of power supply components; a multitude of mass elements; one or more pairs of transmitting elements; and one or more pairs of receiving elements, each of which is separated from other pairs of receiving elements and of all of which is separated from the one or more pairs of transmitting elements by one or more grounding elements, power supply elements or both.

[0018] Advantageously, each of the one or more pairs of transmitting elements is separated from other pairs of transmitting elements and from all of the one or more pairs of receiving elements by one or more of ground elements, current elements or both.

[0019] Advantageously, each of the multitude of power supply elements of one size is separated from each of the other power supply elements of other sizes by at least one of a ground element, a pair of transmitting elements and a pair of receiving elements.

[0020] Advantageously, each of the one or more pairs of receiving elements and pairs of transmitting elements, which are located in an adjacent group of electrically conductive connecting elements, is separated by one or more grounding elements, power supply elements, or both.

[0021] Advantageously, the electrically conductive connecting elements include a boundary row configured to be adjacent to a boundary of the second surface of the group of coupling circuit layers, with none of the plurality of power supply elements located in the boundary row.

[0022] Advantageously, each of the one or more pairs of receive elements is assigned to a receive track of a serializer / deserializer (SerDes) circuit, and each of the one or more pairs of transmit elements is assigned to a transmit track of the SerDes circuit.

[0023] Advantageously, there are eight pairs of receive elements, with each pair of receive elements being assigned to one of eight receive tracks of a serializer / deserializer (SerDes) circuit, and there are eight pairs of transmit elements, with each pair of transmit elements being assigned to one of eight transmit tracks of the SerDes circuit.

[0024] Advantageously, the SerDes circuit is communicatively connected to a packet switch.

[0025] Advantageously, the SerDes circuit is communicatively connected to a packet router.

[0026] Advantageously, at least one of the multitude of power supply elements of one size is separated from the other power supply elements of other sizes by at least one of a ground element, a pair of transmitting elements and a pair of receiving elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A more complete understanding of the invention and its many associated advantages will readily be obtained by referring to the following detailed description, when considered in conjunction with the accompanying drawings, wherein the drawings: Fig. 1 illustrates a simplified example of a semiconductor package; Fig. 2. A connection pattern from the prior art is illustrated; Fig. 3 a simplified functional block diagram of an integrated circuit architecture in accordance with an embodiment of the present disclosure is illustrated; Fig. 4 Connection patterns illustrated in accordance with some embodiments of the present disclosure; and Fig.Figure 5 illustrates a bottom view of a component package in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028]

[0007] The detailed description set forth below is intended as a description of various configurations of the technology relating to the invention and is not intended to represent the only configurations in which the technology relating to the invention can be practiced. The attached drawings are included herein and form part of the detailed description. The detailed description includes specific details for the purpose of providing a comprehensive understanding of the technology relating to the invention. However, the technology relating to the invention is not limited to the specific details set forth herein and can be practiced using one or more implementations. In one or more cases, structures and components, respectively, are required.Components are shown in a simplified form to avoid obscuring the concepts of the technology relating to the invention.

[0029]

[0008] Reference is now made to the drawings, in which the same reference numerals denote identical or corresponding parts through the multiple views, with exemplary aspects of the disclosure including interconnection patterns and ball / pin patterns for component packaging. The interconnection patterns and ball / pin patterns for component packaging discussed below allow high-density integrated circuit chips to be assembled into packages (encapsulations, housings) of a manufacturable size. The interconnection patterns can be patterns for solder ball arrangements or other types of electrical interconnection mechanisms in a semiconductor package.Despite the increased density of the interconnection patterns, the interconnection patterns still meet the demanding crosstalk specifications and other signal integrity specifications for high-speed transmit and receive signaling, which is carried out by the interconnection patterns to and from the high-density circuitry on the chip within the packaging.

[0030]

[0009] Fig. Figure 1 illustrates a simplified example of a semiconductor package. Fig.Figure 1 shows a package cross-section 100, which has circuit layers defined on substrates that can be bonded together and which can, for example, use vias to couple or connect the circuit layers. The package cross-section 100 shows an integrated circuit chip 104 bonded to a first surface of a group of coupling circuit layers 106. The coupling circuit layers 106 are connected to an array of electrically conductive connecting elements 107, which are arranged in groups of connection patterns, for example, on a second surface of the coupling circuit layers 106.In some embodiments, the connecting elements 108 may be in the form of a ball grid array (BGA) of solder balls, through which the package is soldered to solder pad patterns on a printed circuit board (PCB) 110. The principles discussed below are also applicable to other types of interconnection patterns composed of other types of electrically conductive connecting elements, including pin grid arrays (PGAs) of pins, land grid arrays (LGAs) of planar metal contacts, and other types of interconnection mechanisms. Furthermore, the principles discussed below are also applicable to any circuit subject to signal performance specifications, in addition to the specific types of networking and communication circuits described below.

[0031]

[0010] Assigning signal connections, power connections, and ground connections to the connection points (whether solder balls, pins, or solder pads) within a connection pattern is a considerable technical challenge for high-speed circuits. For example, high-speed serializer / deserializer (SerDes) cores (-SerDes cores) used in networking and communication devices must meet stringent signal performance specifications to ensure reliable operation, in particular FEXT (far-end crosstalk) and NEXT (near-end crosstalk) specifications.Other signal performance specifications that may be applicable include transmit (Tx) and receive (Rx) return loss (RL), Tx and Rx common mode (CM) RL, insertion loss (IL), and Tx and Rx FEXT measured at the PCB.

[0032]

[0011] A significant challenge in signal allocation is that the overall package size must be kept within a manufacturable range, but increasing the density of the interconnect pattern to reduce the package size can negatively impact signal performance. As circuit speed increases, signal specifications become more stringent, and as the number of circuit cores on a chip within a package increases, the challenge of finding a feasible interconnect pattern that is manufacturable and meets the required signal integrity specifications becomes extremely difficult. It should also be noted that achieving a smaller package size also considerably reduces manufacturing costs. Reducing the package size from 75 mm to, for example, 70 mm can result in savings per package on the order of US$20.

[0033]

[0012] Another factor that influences the signal specifications is the effective receive distance with respect to signals sent from a communication partner to the package, for example, via circuit traces on a PCB. The effective distances are sometimes categorized as long range or short range. An insertion loss of 30 dB or better between the package and a communication partner can represent a short range, while an insertion loss greater than 30 dB can represent a long range. For short-range implementations, the receive signal specifications typically allow more crosstalk because the received signals are stronger, whereas long-range implementations must meet a more conservative receive crosstalk specification because the received signals are weaker and more easily affected by noise and interference.Overlaps are disrupted.

[0034]

[0013] Fig. Figure 2 illustrates a prior art connection pattern 200 for four adjacent SerDes core instances. The example, which is shown in Fig. Figure 2 illustrates that each SerDes core instance comprises four differential Tx pairs and four differential Rx pairs (four lanes), one or more power supplies, and ground signals. Prior art connection patterns, such as those shown in Fig. As illustrated in Figure 2, large numbers of, for example, 128 four-lane SerDes cores in body sizes of less than about 75 mm cannot be accommodated.

[0035]

[0014] In some embodiments described below, eight-lane SerDes core instances each comprise eight differential Tx pairs, eight differential Rx pairs, power supplies, and ground signals, although SerDes cores of other speeds and / or with a different number of lanes can also use the concepts disclosed herein. These SerDes cores can be part of an integrated circuit chip (such as the integrated circuit chip 104 described in Fig. 1 shown), which may also include a high-speed switch and / or router circuit core within the integrated circuit. Fig. Figure 3 illustrates a simplified functional block diagram of such an architecture. Fig.3. One or more SerDes cores 305 can be connected to, for example, a switch and / or router circuit core 310 to provide an interface to this circuit core. The function of the switch and / or router circuit core 310 can be, for example, to mediate or route network data (packets and the like) from a connection provided by one of the SerDes cores 305 to a connection provided by another of the SerDes cores 305. Although only a single Tx and Rx signal line is shown associated with each of the SerDes cores 305, it should be recognized that each of the SerDes cores 305 can have multiple Tx and Rx signal lines. In some embodiments, for example, each of the SerDes cores 305 can have eight differential Tx pairs and eight differential Rx pairs. Furthermore, in Fig.Three power supply and ground connections that may be required for the operation of the circuit in each of the SerDes 305 cores are not shown.

[0036]

[0015] Fig. Figure 4 illustrates connection patterns in accordance with embodiments of the present disclosure. In the Fig. In the embodiments shown in Figure 4, the connecting elements 400 (solder balls, pins, etc.) can be arranged in a staggered or hexagonal pattern. The use of a hexagonal pattern can increase the connection density by approximately 13% compared to a conventional rectangular (square) pattern. Furthermore, in a hexagonal pattern, each connection point is equidistant from each of its six nearest neighbors. Fig.Figure 4 illustrates two hexagonal connection patterns - pattern 1 403 can be used along the left and right edges of a component package, while pattern 2 405 can be used on the top and bottom edges of a component package.

[0037]

[0016] Fig. Figure 5 illustrates a bottom view of a component package 500 in accordance with some embodiments of the present disclosure. Fig. 5 is pattern1 510, one of a variety of patterns1 along the left and right edges of component package 500, while pattern2 515 is one of a variety of patterns2 along the top and bottom edges of component package 500.

[0038]

[0017] Referring again to Fig.4. The signal connections in each of the connection patterns can be arranged to ensure high signal integrity. For example, connection patterns 403 and 405 can be used to interface-couple eight-lane 400Gbps SerDes cores. These connection patterns can follow one or more specific design rules to help ensure that the connection patterns meet required signal integrity specifications. Not all connection patterns need to follow the same rule or rules, and whether a given rule applies may depend on a speed threshold or other decision factors. For example, each Rx pair of AGND (Analog Ground) connections (or terminals) (shown, for example, as dashed areas 410 and 412) and / or AVDD (Analog Supply Voltage) connections (or terminals) can be configured as follows:Each Tx pair can be surrounded (isolated) by a combination of AGND (Analog Ground) and AVDD (Analog Supply Voltage) connections (for example, shown as dashed areas 415 and 417). To reduce EMI and common-mode return loss, AVDD connections can be avoided in the outermost rows of connections (adjacent to the package edge). Either the Tx or the Rx connections can be placed adjacent to the package edge.

[0018] Example design rules are described in the following table: Connection pattern design rules Rule Explanation Rx pair placement Rx pairs that tend to transmit weak received signals are in a non-adjacent configuration and have isolation with respect to Tx pairs and other Rx pairs and may also have surrounding (nearest-neighbor) isolation 410 & 412 in which the Rx pairs are surrounded by ground, current or a combination of ground and current. Tx pair placement Tx pairs that tend to transmit strong signals may have a surrounding (nearest neighbor) insulation 415 & 417 in which the Tx pairs are surrounded by ground, current or a combination of ground and current. Package edge There are no AVDD connections (terminals) in edge row 420 of the connection pattern running along package edge 425 to help achieve improved EMI and CM-RL performance. AVDD placement For certain designs above a velocity threshold, this rule can restrict or limit the connection pattern so that some or all AVDD connections (terminals) are neighbor-free. That is, no AVDD connection of one size can be adjacent to an AVDD connection of another size. This rule can reduce or minimize AVDD plane resonance.

[0039]

[0019] The connection pattern design rules shown above can apply within each individual group of connection patterns 403 and 405, but in some embodiments they can also apply to the overall connection patterns of adjacent groups, such as those shown in Fig. 5 are shown. For example, an Rx pair 435 in Fig. 4 is isolated at the left edge of a group of other Rx pairs when another group is positioned to the left of connection pattern 403, as illustrated.

[0040]

[0020] The above description has been provided to enable a person skilled in the art to carry out and use the claimed inventions. The principles described above can be modified, and the principles and their variations can be applied to achieve other connection patterns and to achieve other design objectives. For example, given the design rules expressed above, many other permutations of connection points forming connection patterns can be implemented that also satisfy any given set of signal specifications. That is to say, the description and the drawings provide examples of the inventions, and the inventions are not limited to only the specific examples provided.

[0041]

[0021] To the extent that the above descriptions are considered to be descriptive of separate embodiments, the organization of the description into embodiments serves only to facilitate understanding of the concepts of the invention described herein. Thus, the features of each embodiment can be combined with features of the other embodiments without restriction. It is obvious that numerous modifications and variations of the present invention are possible in light of the above teachings.

Claims

[1] Component comprising the following: a variety of power supply components; a multitude of mass elements; one or more pairs of transmitting elements; and one or more pairs of receiving elements, each pair of receiving elements being separated from other pairs of receiving elements and from all of the one or more pairs of transmitting elements by one or more of the ground elements, the power supply elements or both; where the elements (400) are arranged in a hexagonal pattern. [2] Component according to claim 1, wherein each pair of transmitting elements is separated from other pairs of transmitting elements and from all of the one or more pairs of receiving elements by one or more of the grounding elements, the power supply elements or both. [3] Component according to one of the preceding claims, wherein each of the plurality of power supply elements of one size is separated from each of other power supply elements of other sizes by at least one of a ground element, a pair of transmitting elements and a pair of receiving elements. [4] Component according to one of the preceding claims, wherein each of the one or more pairs of receiving elements is assigned to a receiving track of a serializer / deserializer, SerDes, circuit and each of the one or more pairs of transmitting elements is assigned to a transmitting track of the SerDes circuit. [5] Component according to claim 4, wherein the SerDes circuit is communicatively connected to a packet switch.

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