METHOD FOR PRODUCING A SEMICONDUCER-ON-ISOLATOR (SOI) SUBSTRATE AND SEMICONDUCER STRUCTURE

Abstract

Method (2000) for fabricating a semiconductor structure (100) comprising the following steps: Generating (2004) a plurality of bulk microdefects (604) in a handle substrate (102); Enlarging (2006) the size of the plurality of bulk microdefects (604) to generate a plurality of bulk macrodefects, BMDs (104), in the handle substrate (102); Removing (2008) some of the majority of BMDs (104) from a first defect-free area (108a) and a second defect-free area (108b) arranged along opposite faces of the handle substrate (102); Fabrication (2010) of an insulating layer (110, 110a, 110b) on the handle substrate (102); and Fabrication (2012) of a device layer (112, 904) as an active layer with a semiconductor material on the insulating layer (110); wherein the first (108a) and the second (108b) defect-free region vertically enclose a central region (106) of the handle substrate (102) which has a higher concentration of the majority of BMDs (104) than the first (108a) and the second (108b) defect-free region; and i) wherein the insulating layer (110, 110a, 110b) extends continuously around the outer edges of the handle substrate (102); and / or ii) wherein the insulating layer (110, 110a, 110b) completely encloses the handle substrate (102).

Description

background

[0001] Integrated circuits have traditionally been fabricated on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate comprises a handle substrate, an insulating layer over the handle substrate, and a fixture layer over the insulating layer. Among other advantages, an SOI substrate results in reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed).

[0002] US 2010 / 0038755A1 describes a process for manufacturing a silicon wafer. The process involves the generation and stabilization of embryos, which are transformed into oxygen precipitates by subsequent thermal annealing during the fabrication of a semiconductor device. In the silicon wafer, embryos are largely removed from an exposed zone and distributed in relatively high concentrations in a bulk area. By controlling the embryo behavior, a silicon wafer with a specific oxygen precipitate concentration profile is produced with high reliability and reproducibility by subsequent thermal annealing.

[0003] US 2006 / 0138601A1 describes a heteroepitaxial semiconductor wafer with a heteroepitaxial layer on the front face of the wafer containing a secondary material with a different crystal structure than the primary material. The heteroepitaxial layer is largely defect-free. A surface layer contains the primary material and is free of secondary material. It is adjacent to the heteroepitaxial layer. A bulk layer contains the primary material and is free of secondary material. It is adjacent to the surface layer and extends through the midplane. Summary

[0004] The present invention relates to a method according to claim 1 and a semiconductor structure according to claim 3. Claim 2 describes a particularly advantageous embodiment of the method according to claim 1. Claims 4 to 13 describe particularly advantageous realizations of the semiconductor structure according to claim 3. Brief description of the drawings

[0005] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows a sectional view of some embodiments of a semiconductor structure with an SOI substrate having a central bulk macrodefect (BMD) region vertically surrounded by low-defect regions. Fig. Figure 2 shows a diagram of some embodiments of a BMD concentration as a function of the position in a handle substrate of an SOI substrate. The Fig. 3A and Fig. Figure 3B shows some further embodiments of a semiconductor structure with an SOI substrate having a central region with BMDs that is vertically enclosed by low-defect regions. Fig. Figure 4 shows a sectional view of some further embodiments of a semiconductor structure with an SOI substrate having a central region with BMDs that is vertically enclosed by low-defect regions. Fig. Figure 5 shows a sectional view of some other embodiments of an integrated chip die with an SOI substrate having a central region with BMDs that is vertically enclosed by low-defect regions. The Fig. Figures 6A to 19 show sectional views of some embodiments of a method for producing an SOI substrate with a handle substrate having a central region with a plurality of BMDs arranged between low-defect regions. Fig. Figure 20 shows a flowchart of some embodiments of a method for producing an SOI substrate with a handle substrate having a central region with a plurality of BMDs arranged between low-defect regions. Detailed description

[0006] Specific examples of components and arrangements according to the present invention are described below. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] SOI substrates are used in numerous integrated chip applications. For example, in recent years, SOI substrates have found widespread use in logic devices, bipolar CMOS / DMOS devices (CMOS: complementary metal-oxide semiconductor; DMOS: double-diffusion metal-oxide semiconductor), high-voltage devices (e.g., devices operating at 100 V or more), embedded flash memory devices, and the like. SOI substrates typically feature a thick layer of semiconductor material (e.g., a handle substrate) separated by an insulating layer from an overlying device layer (i.e., an active layer). Transistor devices are most often fabricated in the device layer.Transistors fabricated in the device layer are able to switch signals faster and operate at lower voltages, and they are much less susceptible to signal noise from cosmic background radiation particles than devices fabricated in a bulk substrate.

[0008] A handle substrate, used to fabricate a SOI substrate, can be produced using the Czochralski method. In the Czochralski method, silicon is melted in a quartz crucible at high temperatures. A seed crystal is then immersed in the molten silicon and slowly withdrawn outwards to extract a large, single-crystal cylindrical blank. This blank is then cut to produce the handle substrate. During the handle substrate fabrication process, oxygen from the quartz crucible can migrate into the silicon. This oxygen can enter the silicon crystal as precipitates, creating bulk microdefects such as slip lines, crystal-originating particles (COPs), or similar features.

[0009] In bulk substrates, bulk microdefects can lead to creepage paths between adjacent transistor devices, since the transistor devices are formed in a substrate that exhibits the bulk microdefects. A handle substrate of an SOI substrate can, however, contain bulk microdefects (e.g., with a concentration of less than 1 × 10⁻⁶). 8 Bulk microdefects / cm² 3The negative electrical effect of bulk microdefects on the transistor devices is mitigated because the transistor devices are fabricated in a fixture layer separated from the handle substrate by an insulating layer. However, it has been found that unwanted wafer deformation (bending) in a handle substrate can strain a fixture layer and lead to slip lines (i.e., defects resulting from the introduction of thermoelastic stresses caused by high-temperature treatment) in the fixture layer during high-temperature thermal annealing processes (e.g., thermal processes above approximately 1000 °C). Furthermore, unwanted wafer deformation can also lead to coverage defects in photolithographic processes performed during subsequent processing.

[0010] In some embodiments, the present invention relates to a method for producing an SOI substrate that includes a handle substrate with high structural integrity, minimizing unwanted wafer deformation (bending). In some embodiments, the SOI substrate includes a handle substrate bonded to a fixture layer by means of an insulating layer. The handle substrate comprises a semiconductor material and low-defect regions arranged along opposing outermost faces and around a central region. The central region has a relatively high concentration of bulk macrodefects (BMDs) (e.g., higher than about 1 × 10⁻⁶). 8 BMDs / cm 3), while the defect-free regions have a lower concentration of BMDs than the central region. The relatively high concentration and large size (e.g., greater than approximately 2 nm) of the BMDs in the central region result in reduced handle wafer deflection, as the BMDs introduce materials (e.g., oxide) into the handle substrate that have a higher stiffness than the semiconductor material. Furthermore, the lower concentration of BMDs in the defect-free regions prevents defects from the handle wafer from affecting an overlying layer. The relatively low wafer deformation of the handle substrate minimizes the formation of overlap defects and slip lines in the device layer.

[0011] Fig. Figure 1 shows a sectional view of some embodiments of a semiconductor structure 100 with an SOI substrate having a central bulk macrodefect (BMD) region vertically surrounded by low-defect regions.

[0012] The semiconductor structure 100 comprises an SOI substrate 101 with an insulating layer 110 arranged between a handle substrate 102 and a device layer 112 (i.e., an active layer). In some embodiments, the insulating layer 110 may extend continuously around the outermost surfaces of the handle substrate 102. In some embodiments, the handle substrate 102 may comprise a first semiconductor material, such as silicon, germanium, or the like. In some embodiments, the insulating layer 110 may comprise an oxide (e.g., silicon dioxide, germanium oxide, or the like), a nitride (e.g., silicon nitride), or the like. In some embodiments, the device layer 112 may comprise a second semiconductor material, such as silicon, germanium, or the like. In some embodiments, the first semiconductor material may be the same material as the second semiconductor material.

[0013] The handle substrate 102 has a central region 106 that is arranged vertically between a first low-defect region 108a and a second low-defect region 108b. The first low-defect region 108a is arranged along a top surface 102t of the handle substrate 102, and the second low-defect region 108b is arranged along a bottom surface 102b of the handle substrate 102. In some embodiments, the first low-defect region 108a can extend to a depth d1 into the handle substrate 102, and the second low-defect region 108b can extend to a depth d2 into the handle substrate 102. For example, the first defect-free area 108a can extend from the top 102t to the first depth d1, and the second defect-free area 108b can extend from the bottom 102b to the second depth d2.

[0014] The first depth d1 can be large enough to prevent defects along an upper part of the handle substrate 102 that could weaken the bond between the handle substrate 102 and the insulating layer 110. Alternatively, the first depth d1 can be small enough to impart stiffness to the handle substrate 102, preventing deflection (e.g., the first depth d1 can give the central region 106 a thickness sufficient to prevent deflection of the handle substrate 102). In some embodiments, the first depth d1 and the second depth d2 can each be approximately 0.05 µm to approximately 50 µm, for example. In other embodiments, the first depth d1 and the second depth d2 can each be approximately 0.05 µm to approximately 100 µm.In further embodiments, the first depth d1 and the second depth d2 can each be approximately 0.05 µm to approximately 10 µm, approximately 0.5 µm to approximately 10 µm, approximately 5 µm to approximately 20 µm, or approximately 1 µm to approximately 20 µm. It should be understood that other values ​​for the first depth d1 and the second depth d2 are also possible.

[0015] A plurality of bulk macrodefects (BMDs) 104 are arranged in the handle substrate 102. The central region 106 has a first concentration of the plurality of BMDs 104, while the first defect-free region 108a and the second defect-free region 108b have one or more second concentrations of the plurality of BMDs 104. The first concentration is higher than the one or more second concentrations. In some embodiments, the first concentration can be higher than approximately 1 × 10⁻⁶ 8 BMDs / cm 3 In other embodiments, the first concentration can be higher than approximately 5 × 10⁻⁶. 8 BMDs / cm3 In some embodiments, one or more of the second concentrations can be approximately zero, so that the top surface 102t and the bottom surface 102b of the handle substrate 102 are largely free of BMDs. Because the top surface 102t and the bottom surface 102b of the handle substrate 102 are largely free of BMDs, it is avoided that the majority of BMDs 104 impair adhesion to the insulating layer 110.

[0016] In various embodiments, the majority of BMDs 104 can comprise slip lines, crystal-derived particles (COPs), or the like. Slip lines are defects that arise in a substrate from the introduction of thermoelastic stresses caused by high-temperature treatment, while COPs are voids in the substrate. In some embodiments, the majority of BMDs 104 can have sizes 105 (e.g., lengths or widths) greater than about 2 nm. In other embodiments, the majority of BMDs 104 can have sizes 105 greater than about 5 nm. In still other embodiments, the majority of BMDs 104 can have sizes 105 ranging from about 3 nm to 100 nm, about 50 nm to about 100 nm, or about 75 nm to about 100 nm. It should be understood that other sizes are also possible.

[0017] The relatively large size and high concentration of most BMDs 104 impart good structural integrity to the handle substrate 102, which reduces its deflection. This is because most BMDs 104 incorporate materials into the substrate 102 that have greater structural integrity (e.g., stiffness) than the primary semiconductor material, thereby increasing the structural stiffness of the handle substrate 102. For example, most BMDs 104 may contain an oxide that has greater stiffness than pure silicon, thus reducing the deflection of the handle substrate 102.

[0018] The relatively small deflection of the handle substrate 102 can mitigate the formation of slip lines in the device layer 112. Furthermore, the relatively small deflection of the handle substrate 102 can also and / or alternatively reduce coverage defects in lithographic processes performed on the device layer 112. In some embodiments, lithographic coverage defects can be reduced by up to approximately 85%. For example, a handle substrate 102 that does not have a high concentration of BMDs in the central region 106 can have a maximum coverage defect of approximately 136 nm, whereas a handle substrate 102 with a concentration of approximately 4.5 × 10 9 BMDs / cm 3 in the middle area 106, has a maximum coverage error of about 22 nm.

[0019] Fig. Figure 2 is a diagram 200 showing some embodiments of a BMD concentration as a function of position in a handle substrate of an SOI substrate.

[0020] As shown in diagram 200, the concentration of bulk macrodefects (BMDs) in a first defect-free region 108a has a first value υ1, the concentration of BMDs in a second defect-free region 108b has a second value υ2, and the concentration of BMDs in a middle region 106 has a third value υ3, which is greater than the first value υ1 and the second value υ2. In some embodiments, the first value υ1 and the second value υ2 are approximately zero. In some embodiments, the third value υ3 may be approximately 1 × 10 8 BMDs / cm 3 up to about 1 × 10 10 BMDs / cm 3 In other embodiments, the third value υ3 can be approximately 8 × 10 8 BMDs / cm 3 up to about 9 × 10 9 BMDs / cm 3The third value υ3 can be larger or smaller in other embodiments. If the third value υ3 is approximately 1 × 10 8 BMDs / cm 3 up to about 1 × 10 10 BMDs / cm 3 If the BMDs are in a central area of ​​a handle substrate (e.g., of handle substrate 102), they can reduce deflection of the handle substrate.

[0021] The Fig. 3A and Fig. Figure 3B shows some further embodiments of a semiconductor structure with an SOI substrate having a central region with BMDs that is vertically enclosed by low-defect regions.

[0022] Fig. Figure 3A shows a sectional view 300 of some further embodiments of a semiconductor structure. As shown in the sectional view 300, the semiconductor structure comprises an SOI substrate 101 with a handle substrate 102, an insulating layer 110, and a fixture layer 112. The handle substrate 102 can be or comprise a semiconductor material such as silicon, germanium, or the like. In some embodiments, the handle substrate 102 is doped with p- or n-type dopants. In some embodiments, the handle substrate 102 has a thickness T. hsfrom about 700 µm to about 800 µm, from about 750 µm to about 800 µm, or with other suitable values. In some embodiments, the handle substrate 102 can have a resistivity of about 8 Ωcm to about 12 Ωcm, from about 10 Ωcm to about 12 Ωcm, or with other suitable values. In some embodiments, the handle substrate 102 can have an oxygen concentration of about 9 parts per million atoms (ppm) to about 30 ppmm. In other embodiments, the handle substrate 102 can have an oxygen concentration of about 9 ppmm to about 15 ppmm. In still other embodiments, the handle substrate 102 can have an oxygen concentration of more than 30 ppmm or less than 9 ppmm. The low oxygen concentration and high specific resistance reduce substrate and / or radio frequency (RF) losses.

[0023] The insulating layer 110 is arranged over the handle substrate 102 and may comprise an oxide, e.g., silicon dioxide, silicon-rich oxide (SRO), or the like; a nitride, e.g., silicon nitride; or the like. In some embodiments, the insulating layer 110 completely covers the top surface 102t of the handle substrate 102. In at least some embodiments where the handle substrate 102 has a high resistivity, completely covering the top surface 102t of the handle substrate 102 prevents arcing during plasma treatment (e.g., plasma etching) used to fabricate components (not shown) in the device layer 112. In some embodiments, the insulating layer 110 completely encloses the handle substrate 102.

[0024] The insulating layer 110 has a first insulating thickness T fi between the handle substrate 102 and the device layer 112. The first insulating thickness Tfi is so large that a high degree of electrical isolation is provided between the handle substrate 102 and the device layer 112. In some embodiments, the first insulating thickness T is fi approximately 0.2 µm to approximately 2.5 µm, approximately 1 µm to approximately 2 µm, or it has other suitable values. In some embodiments, the insulating layer 110 has a second insulating thickness T. si along a bottom surface 102b of the handle substrate 102 and / or along side walls of the handle substrate 102. In some embodiments, the second insulating thickness T si smaller than the first insulation thickness T fi In some embodiments, the second insulating thickness T is si approximately 2 nm to 600 nm, approximately 2 nm to 301 nm, approximately 301 nm to 600 nm, or it has other suitable values.

[0025] In some embodiments, the insulating layer 110 has stepped profiles on SOI edge parts 102e of the SOI substrate 101, each located on opposite sides of the SOI substrate 101. In some embodiments, the insulating layer 110 has top surfaces located on the SOI edge parts 102e, which are below a top surface of the insulating layer 110 with a vertical recess amount V. Ri are recessed. The vertical recess amount V Ri For example, the wavelength can be approximately 2 nm to 600 nm, approximately 2 nm to 301 nm, or approximately 301 nm to 600 nm, or it can have other suitable values. In some embodiments, the insulating layer has 110 inner sidewalls with a lateral insulating recess amount LR. i The outermost side walls of the insulation layer 110 are laterally recessed. The lateral insulation recess amount LR iFor example, it may be approximately 0.8 mm to 1.2 mm, approximately 0.8 mm to 1.0 mm or approximately 1.0 mm to 1.2 mm, or it may have other suitable values.

[0026] The device layer 112 is arranged above the insulating layer 110 and can comprise a semiconductor material such as silicon, germanium, or the like. The device layer 112 has a thickness T d In various embodiments, the thickness T can vary. d The dimension may be approximately 0.2 mm to approximately 10.0 mm or approximately 1 mm to approximately 5 mm, or it may have other suitable values. In some embodiments, the device layer 112 has outermost side walls with a lateral component recess amount LR. d Each is recessed laterally from the outermost side walls of the handle substrate 102. The lateral component recess amount LR dFor example, the thickness can be approximately 1.4 mm to 2.5 mm, approximately 1.4 mm to approximately 1.9 mm, or approximately 1.9 mm to approximately 2.5 mm, or it can have other suitable values. Since the outermost sidewalls of the device layer 112 are each laterally recessed from the outermost sidewalls of the handle substrate 102, the central region 106 extends laterally beyond opposite outermost sidewalls of the device layer 112 with non-zero distances.

[0027] Fig. Figure 3B shows a top view 302 of some embodiments of the sectional view 300. As shown in the top view 302, the SOI substrate 101 can have a substantially round shape. In some embodiments, the SOI substrate 101 has a plurality of IC dies 304 arranged in a grid transverse to the device layer 112. In some embodiments, an inner side wall 110isw of the insulating layer 110 has a lateral insulating recess LR. iThe insulating layer 110 is laterally recessed from an outer side wall 110osw. In some embodiments, a side wall 112sw of the device layer 112 has a lateral component recess amount LR. d laterally recessed from a side wall 102sw (shown in the phantom) of the handle substrate 102.

[0028] Fig. Figure 4 shows a sectional view of some further embodiments of a semiconductor structure 400 with an SOI substrate having a central region with BMDs that is vertically enclosed by defect-free regions.

[0029] The semiconductor structure 400 comprises a plurality of transistor devices 402 arranged in a device layer 112 of an SOI substrate 101. In various embodiments, the transistor devices 402 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar transistors (BJTs), or the like. In some embodiments, the transistor devices 402 can have a gate structure arranged between a source region 404a and a drain region 404b. The gate structure can include a gate electrode 408 separated from the device layer 112 by a dielectric gate layer 406. The source region 404a and the drain region 404b have a first doping type and are directly adjacent to parts of the device layer 112 that have a second doping type opposite to the first.In various embodiments, the dielectric gate layer 406 can be or comprise silicon oxide, silicon nitride, silicon oxide nitride, or the like. In various embodiments, the gate electrode 408 can be or comprise doped polysilicon, a metal, or the like. In some embodiments, the multiple transistor devices 402 can be electrically separated from one another by insulating structures 403 arranged in a top surface of the device layer 112. In some embodiments, the insulating structures 403 can comprise one or more dielectric materials arranged in a trench in the top surface of the device layer 112.

[0030] A dielectric structure 410 is arranged above the SOI substrate 101. The dielectric structure 410 comprises a plurality of interlayer dielectric (ILD) layers stacked on top of each other. In various embodiments, the dielectric structure 410 can comprise boron phosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), and / or silicon oxide or the like. The dielectric structure 410 encloses a plurality of conductive interconnect layers. In various embodiments, the plurality of conductive interconnect layers can comprise conductive contacts 412, connecting wires 414, and interconnect vias 416. The conductive contacts 412, the connecting wires 414, and the interconnect vias 416 can be, for example, copper, aluminum-copper, aluminum, tungsten, or the like.

[0031] Fig. Figure 5 shows a sectional view of some embodiments of a semiconductor die 500 with an SOI substrate having a central region with BMDs vertically enclosed by low-defect regions. The semiconductor die 500 is a singulated die, which, for example, is a detached region of the semiconductor structure 400. Fig. It can be 4.

[0032] The semiconductor die 500 has a handle substrate 102 connected to a fixture layer 112 by means of an upper insulating layer 110U. In some embodiments, a lower insulating layer 110L, not connected to the upper insulating layer 110U, may be arranged along a bottom surface of the fixture layer 112 facing away from the upper insulating layer 110U. In some embodiments, the handle substrate 102, the fixture layer 112, the upper insulating layer 110U, and the lower insulating layer 110L have sidewalls aligned along a line extending along one side of the semiconductor die 500. In these embodiments, the handle substrate 102 extends to the outermost sidewalls of the upper insulating layer 110U and the lower insulating layer 110L.

[0033] The handle substrate 102 has a central region 106, which is vertically enclosed by a first low-defect region 108a and a second low-defect region 108b. The central region 106 has a plurality of BMDs 104. The plurality of BMDs 104 extends between a first outermost sidewall of the semiconductor die 500 and a second outermost sidewall of the semiconductor die 500.

[0034] The Fig. Figures 6A to 19 show sectional views 600 to 1900 of some embodiments of a method for producing an SOI substrate with a handle substrate having a central region with a plurality of BMDs arranged between low-defect regions. Fig. Figures 6A to 19 are described for a procedure, but it should be understood that the structures shown in these figures are not limited to the procedure, but can be used as structures independently and separately from the procedure.

[0035] The Fig. Figures 6A to 6D are sectional views 600 to 614 showing some embodiments of a method for producing a handle substrate having a central region with a plurality of BMDs arranged between low-defect regions.

[0036] As shown in section view 600 of Fig. As shown in Figure 6A, a handle substrate 102 is provided. In some embodiments, the handle substrate 102 may comprise a semiconductor material, such as silicon, germanium, or the like. In some embodiments, the handle substrate 102 has a resistivity of about 8 Ωcm to about 12 Ωcm. In some embodiments, the handle substrate 102 has an oxygen concentration of about 9 ppma to about 30 ppma.

[0037] As shown in section view 602 of Fig. As shown in Figure 6B, a plurality of bulk microdefects 604 are generated in the handle substrate 102. In some embodiments, the plurality of bulk microdefects 604 can have sizes 606. In some embodiments, the sizes 606 range from about 0.2 nm to about 5 nm. In some embodiments, the plurality of bulk microdefects 604 can be generated by a first thermal process 608 performed on the handle substrate 102. In some embodiments, the handle substrate 102 can be treated in the first thermal process 608 at a temperature of about 500 °C to about 800 °C for a duration of about 2 hours to about 8 hours. In other embodiments, the handle substrate 102 can be treated in the first thermal process 608 at a temperature of less than 500 °C or more than 800 °C for a duration of less than 2 hours or more than 8 hours.In some embodiments, the multiple bulk micro-defects 604 are generated such that they are essentially homogeneous between a top surface 102t and a bottom surface 102b of the handle substrate 102.

[0038] As shown in section view 610 of Fig. As shown in Figure 6C, the sizes of the majority of bulk microdefects (604 of Fig. 6B) enlarged to generate a plurality of bulk macrodefects (BMDs) 104 in the handle substrate 102. The plurality of BMDs 104 have sizes 105 that are larger than the sizes of a plurality of microdefects (606 of Fig. 6B). In some embodiments, the sizes 105 can be approximately 1000% to approximately 20000% larger than the sizes of the majority of microdefects (606 of Fig. 6B). In some embodiments, the sizes 105 are approximately 3 nm to approximately 100 nm. In some embodiments, the majority of BMDs can be produced by a second thermal process 612, which is carried out on the handle substrate 102. In some embodiments, the second thermal process 612 can be carried out at a higher temperature than the first thermal process 608. In some embodiments, the handle substrate 102 can be treated in the second thermal process 612 at a temperature of approximately 1050 °C to approximately 1150 °C for a duration of approximately 2 hours to approximately 4 hours. In other embodiments, the handle substrate 102 can be treated in the second thermal process 612 at a temperature of less than 1050 °C or more than 1150 °C for a duration of less than 2 hours or more than 4 hours.

[0039] As shown in section view 614 of Fig. As shown in Figure 6D, some of the majority of BMDs 104 are removed from the defect-free regions 108a and 108b, which are arranged along the top and bottom surfaces of the handle substrate 102. This removal of some of the majority of BMDs 104 from the defect-free regions 108a and 108b results from the creation of a central region 106 of the handle substrate 102, which has a higher concentration of BMDs 104 than the defect-free regions 108a and 108b. In some embodiments, the central region 106 has a concentration of BMDs 104 approximately 1 x 10 8 BMDs / cm 3 up to about 1 × 10 10 BMDs / cm 3 In other embodiments, the central region 106 has a concentration of BMDs 104 of approximately 8 × 10 8 BMDs / cm 3 up to about 9 × 10 9 BMDs / cm 3In some embodiments, the defect-free areas 108a and 108b can extend to a depth d1 and d2, respectively, into the handle substrate 102, which is approximately 50 nm and 50 µm, respectively.

[0040] In some embodiments, a majority of the BMDs 104 from the defect-free regions 108a and 108b are removed by a third thermal process 616. In some embodiments, the third thermal process 616 can be carried out by treating the handle substrate 102 in a high-temperature environment with argon and / or hydrogen gas. In some embodiments, the handle substrate 102 can be treated with argon and / or hydrogen gas at a temperature of about 1100 °C to about 1200 °C for a duration of about 1 hour to about 16 hours. In other embodiments, the handle substrate 102 can be treated with argon and / or hydrogen gas at a temperature of less than 1100 °C or more than 1200 °C for a duration of less than 1 hour or more than 16 hours.

[0041] The Fig. Figures 7A to 7C show sectional views 700 to 712 of some alternative embodiments of the manufacture of a handle substrate with a central area having a plurality of BMDs arranged between defect-free areas.

[0042] As shown in section view 700 of Fig. As shown in Figure 7A, a handle substrate 102 is provided which has a plurality of bulk microdefects 702. In some embodiments, the handle substrate 102 may have nitrogen-doped silicon (e.g., a p-type nitrogen-doped silicon substrate). In some embodiments, the handle substrate 102 has an oxygen concentration of about 9 ppma to about 15 ppma. In other embodiments, the handle substrate 102 has an oxygen concentration of less than 9 ppma (e.g., about 0 ppma) or more than about 15 ppma, or with other suitable values. In some embodiments, the plurality of bulk microdefects 702 may have sizes 704 of about 0.2 nm to about 3 nm.

[0043] As shown in section view 706 of Fig. As shown in Figure 7B, the number and / or density of the plurality of bulk microdefects 702 in the handle substrate 102 are increased from a first non-zero number to a second non-zero number. In some embodiments, the number and / or density of the plurality of bulk microdefects 702 in the handle substrate 102 is increased by performing a first thermal process 710 on the handle substrate 102. In some embodiments, during the first thermal process 710, the handle substrate 102 can be exposed to a temperature of about 500 °C to about 800 °C for a duration of about 2 hours to about 8 hours. In other embodiments, during the first thermal process 710, the handle substrate 102 can be exposed to a temperature of less than 500 °C or more than 800 °C for a duration of less than 2 hours or more than 8 hours.In some embodiments, the first thermal process 710 can increase the size of the majority of bulk microdefects 702. For example, in some embodiments, the majority of bulk microdefects 702 can have sizes 708 ranging from about 0.2 nm to about 5 nm.

[0044] As shown in section view 712 of Fig. As shown in Figure 7C, a second thermal process 714 is performed on the handle substrate 102 to remove some of the majority of BMDs 104 from the defect-free regions 108a and 108b, which are arranged along the top and bottom surfaces of the handle substrate 102. Removing some of the majority of BMDs 104 from the defect-free regions 108a and 108b creates a central region 106 of the handle substrate 102, which has a higher concentration of BMDs 104 than the defect-free regions 108a and 108b. In some embodiments, the defect-free regions 108a and 108b can extend to a depth d1 and d2, respectively, into the handle substrate 102, which is approximately 50 nm and 50 µm, respectively.

[0045] The second thermal process 714 also determines the sizes of the second majority of bulk microdefects (702 of Fig. 7B) is enlarged to generate a plurality of bulk macrodefects (BMDs) 104 with sizes 105. In some embodiments, the sizes 105 are approximately 2 nm to approximately 100 nm. In some embodiments, during the second thermal process 714, the handle substrate 102 is treated with argon and / or hydrogen gas at a temperature of approximately 1100 °C to approximately 1200 °C for a duration of approximately 1 hour to approximately 16 hours. In other embodiments, during the second thermal process 714, the handle substrate 102 can be treated at a temperature of less than 1100 °C or more than 1200 °C for a duration of less than 1 hour or more than 16 hours.

[0046] As shown in section view 800 of Fig. As shown in Figure 8, a first insulating layer 110a is produced along one or more surfaces of the handle substrate 102. In some embodiments, the first insulating layer 110a is produced such that it completely covers a top surface 102t of the handle substrate 102. In some further embodiments, the first insulating layer 110a is produced such that it completely encloses the handle substrate 102. In these embodiments, the first insulating layer 110a is produced such that it extends continuously around an outer edge of the handle substrate 102. In some embodiments, the first insulating layer 110a comprises silicon oxide, silicon nitride, or the like. In some embodiments, the first insulating layer 110a is produced with a thickness T. fi' manufactured from approximately 0.2 µm to 2.0 µm, from approximately 0.2 µm to 1.1 µm, from approximately 1.1 µm to 2.0 µm or with other suitable values.

[0047] In some embodiments, the first insulating layer 110a can be produced by a thermal oxidation process. For example, the first insulating layer 110a can be produced by a dry oxidation process using oxygen gas (e.g., O2) or another gas as an oxidizing agent. As another example, the first insulating layer 110a can be produced by a wet oxidation process using steam as an oxidizing agent. In some embodiments, the first insulating layer 110a is produced at temperatures of about 800 °C to about 1100 °C, from about 800 °C to about 950 °C, from about 950 °C to about 1100 °C, or at other suitable values. In other embodiments, the first insulating layer 110a can be produced by chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0048] In some embodiments, a first wet cleaning process can be carried out on the handle substrate 102 before the production of the first insulating layer 110a. In some embodiments, the first wet cleaning process can be carried out by treating the handle substrate 102 for about 30 s to about 120 s with a first wet cleaning solution containing 1% hydrofluoric acid, then for about 15 s to about 120 s with a second wet cleaning solution containing ozone and demineralized water, and finally for about 15 s to about 120 s with a third wet cleaning solution containing demineralized water, ammonia solution and aqueous hydrogen peroxide.

[0049] As shown in section view 900 of Fig. As shown in Figure 9, a sacrificial substrate 902 is provided. In some embodiments, the sacrificial substrate 902 comprises a semiconductor material, such as silicon, germanium, or the like. In some embodiments, the sacrificial substrate 902 is doped with p- or n-type dopants. In some embodiments, the sacrificial substrate 902 may have a resistivity of less than about 0.02 Ωcm. In some embodiments, the resistivity may be from about 0.01 Ωcm to about 0.02 Ωcm. In other embodiments, the resistivity may be less than about 0.01 Ωcm. In some embodiments, the sacrificial substrate 902 has a lower resistivity than the handle substrate 102. In some embodiments, a thickness T is ss of the sacrificial substrate 902 approximately 700 µm to approximately 800 µm or approximately 750 µm to approximately 800 µm, or it has other suitable values.

[0050] A fixture layer 904 is produced on the sacrificial substrate 902. The fixture layer 904 has a thickness T. d In some embodiments, the thickness T can be d The thickness T can range from approximately 2 µm to approximately 9 µm. In some embodiments, the thickness T can be different. dThe device layer 904 is smaller than or equal to approximately 5 µm. In some embodiments, the device layer 904 comprises a semiconductor material such as silicon, germanium, or the like. In some embodiments, the device layer 904 comprises the same semiconductor material as the sacrificial substrate 902, has the same doping type as the sacrificial substrate 902, and / or has a lower doping concentration than the sacrificial substrate 902. For example, the sacrificial substrate 902 may be or comprise P+ monocrystalline silicon, while the device layer 904 may be or comprise P monocrystalline silicon. In some embodiments, the device layer 904 has a low resistivity. The low resistivity may, for example, be greater than that of the sacrificial substrate 902.Furthermore, the low resistivity can be, for example, less than 8 Ωcm, 10 Ωcm, or 12 Ωcm, and / or can be, for example, approximately 8 Ωcm to approximately 12 Ωcm, approximately 8 Ωcm to approximately 10 Ωcm, or approximately 10 Ωcm to approximately 12 Ωcm, or can have other suitable values. In some embodiments, molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), another suitable epitaxy process, or a combination thereof can be used as a method for producing the device layer 904.

[0051] In some embodiments, after the fabrication of the device layer 904 on the sacrificial substrate 902, the device layer 904 and the sacrificial substrate 902 are cleaned by a second wet cleaning process. In some embodiments, the second wet cleaning process can be carried out by treating the device layer 904 and the sacrificial substrate 902 for about 30 s to about 120 s with a first wet cleaning solution containing 1% hydrofluoric acid, then for about 15 s to about 120 s with a second wet cleaning solution containing ozone and demineralized water, and finally for about 15 s to about 120 s with a third wet cleaning solution containing demineralized water, ammonia solution, and aqueous hydrogen peroxide.

[0052] As shown in section view 1000 of Fig. As shown in Figure 10, the fixture layer 904 and the sacrificial substrate 902 are structured to remove portions of the fixture layer 904 and the sacrificial substrate 902 in edge regions 1002. Removing portions of the fixture layer 904 and the sacrificial substrate 902 in the edge regions 1002 prevents defects (e.g., cracks, chips, etc.) from forming in the fixture layer 904 and the sacrificial substrate 902 during a subsequent grinding and / or wet-chemical etching process. The structuring creates a step 1004 at an edge of the sacrificial substrate 902. The step 1004 is defined by the sacrificial substrate 902. In some embodiments (not shown), the step 1004 extends in a closed loop around an outer circumference of the sacrificial substrate 902. In some embodiments, the step 1004 has a width W of about 0.8 mm to about 1.4 mm, of about 0.8 mm to about 1.0 mm, of about 1.0 mm to about 1.2 mm, or with other suitable values.In some embodiments, the step 1004 is recessed beneath a top surface of the device layer 904 with a distance D of approximately 30 µm to approximately 120 µm, of approximately 30 µm to approximately 75 µm, of approximately 70 µm to approximately 120 µm or with other suitable values.

[0053] In some embodiments, the structuring is carried out by etching the device layer 904 and the sacrificial substrate 902 according to a mask 1006 that is fabricated over the device layer 904. In some embodiments, the mask 1006 comprises silicon nitride, silicon oxide, a photoresist, and / or the like. In some embodiments, the mask 1006 comprises silicon oxide that is deposited by a deposition process, e.g., PVD, plasma-enhanced chemical vapor deposition (PECVD), metal-organic CVD (MOCVD), or the like. In these embodiments, the silicon oxide can be deposited by a PECVD process at a temperature of about 200 °C to about 400 °C. In other embodiments, the silicon oxide can be deposited by a PECVD process at a temperature of about 350 °C to about 400 °C, from about 250 °C to about 350 °C, or at other suitable values.In some embodiments, the silicon oxide can be deposited with a thickness of approximately 50 nm to approximately 300 nm. In some further embodiments, the silicon oxide can be deposited with a thickness of approximately 50 nm to approximately 1000 nm, from approximately 100 nm to approximately 200 nm, or with other suitable values.

[0054] After completion of the structuring process, the mask 1006 is removed, and the device layer 904 and the sacrificial substrate 902 are cleaned to remove etch residues and / or other unwanted byproducts generated during the structuring process. In some embodiments, the mask 1006 can be removed by treatment with 1% hydrofluoric acid for a duration of approximately 180 s to approximately 600 s.In some embodiments, the sacrificial substrate 902 can be cleaned by a third wet cleaning process, which is carried out by treating the device layer 904 and the sacrificial substrate 902 for about 30 s to about 120 s with a first wet cleaning solution containing 1% hydrofluoric acid, then for about 15 s to about 120 s with a second wet cleaning solution containing demineralized water, ammonia water and aqueous hydrogen peroxide, and finally for about 15 s to about 120 s with a third wet cleaning solution containing demineralized water, hydrochloric acid and aqueous hydrogen peroxide.

[0055] As shown in section view 1100 of Fig. As shown in Figure 11, a second insulating layer 110b is produced along a top surface 904t of the device layer 904. In some embodiments, the second insulating layer 110b is produced such that it completely covers the top surface 904t of the device layer 904. In some embodiments, the second insulating layer 110b comprises silicon oxide and / or another suitable dielectric. In some embodiments, the second insulating layer 110b is produced from the same dielectric material as the first insulating layer 110a. In some embodiments, the thickness T is si'The second insulating layer 110b has a diameter of approximately 600 nm. In some embodiments, the second insulating layer 110b can be produced by a deposition process (e.g., CVD, PVD, or the like). In other embodiments, the second insulating layer 110b can be produced by a microwave plasma oxidation process. For example, the second insulating layer 110b can be produced by a microwave plasma process. In some embodiments, the plasma process can be carried out at a temperature of approximately 300 °C to approximately 400 °C. In some embodiments, hydrogen, helium, oxygen, or the like can be used as a gas source for the plasma process.

[0056] In some embodiments (not shown), the second insulating layer 110b can be produced such that it completely encloses the sacrificial substrate 902 and the device layer 904. In these embodiments, the second insulating layer 110b can be produced by a thermal oxidation process. For example, the second insulating layer 110b can be produced by a dry oxidation process using oxygen gas (e.g., O2), hydrogen gas, helium gas, or the like. As another example, the second insulating layer 110b can be produced by a wet oxidation process using steam as an oxidizing agent. In some embodiments, the second insulating layer 110b is produced at temperatures of about 750 °C to about 1100 °C, about 750 °C to about 925 °C, about 925 °C to about 1100 °C, or at other suitable values.

[0057] As shown in section view 1200 of Fig. As shown in Figure 12, the sacrificial substrate 902 is bonded to the handle substrate 102, so that the device layer 904 is located between the handle substrate 102 and the sacrificial substrate 902. The bonding process brings the first insulating layer 110a into contact with the second insulating layer 110b. Then, in a processing chamber maintained at a low pressure (e.g., a pressure of about 0.0001 mbar to about 150 mbar), the first insulating layer 110a is brought into contact with the second insulating layer 110b. In some embodiments, the bonding process can be carried out by treating the first insulating layer 110a and the second insulating layer 110b with a nitrogen-based plasma. In some embodiments, the nitrogen-based plasma can be generated from nitrogen gas at a power of about 50 W to about 200 W.In some embodiments, the first insulating layer 110a and the second insulating layer 110b can be treated with the nitrogen-based plasma for approximately 10 s to approximately 120 s. In some embodiments, a fourth wet cleaning process is carried out after the nitrogen-based plasma treatment. The fourth wet cleaning process can be carried out for approximately 15 s to approximately 120 s with a wet cleaning solution containing demineralized water, ammonia solution, and aqueous hydrogen peroxide.

[0058] In some embodiments, a high-temperature nitrogen tempering process can be carried out after the fourth wet cleaning process. The high-temperature nitrogen tempering process increases the strength of the bonds between the first insulating layer 110a and the second insulating layer 110b. The high-temperature nitrogen tempering process can be carried out by introducing nitrogen gas into a processing chamber in which the sacrificial substrate 902 and the handle substrate 102 are clamped. In some embodiments, the high-temperature nitrogen tempering process can be carried out at a temperature of about 250 °C to about 450 °C, from about 200 °C to about 500 °C, or at other suitable values. In some embodiments, the high-temperature nitrogen tempering process can be carried out for about 30 min to about 240 min, about 50 min to about 200 min, or for another duration at atmospheric pressure.

[0059] As shown in section view 1300 of Fig. As shown in Figure 13, a first thinning process is carried out. In the first thinning process, an upper part of the second insulating layer 110b and then an upper part of the sacrificial substrate 902 are removed. In some embodiments, the first thinning process is carried out into the second insulating layer 110b and the sacrificial substrate 902 until the device layer 904 and the sacrificial substrate 902 together have a predetermined thickness T. pd have. The specified thickness T pd For example, it can be approximately 14 µm to approximately 50 µm, approximately 20 µm to approximately 32.5 µm or approximately 32.5 µm to approximately 45 µm, or it can have other suitable values.

[0060] In some embodiments, the first thinning process is carried out partially or completely by mechanical grinding. In some embodiments, the first thinning process is carried out partially or completely by chemical-mechanical polishing (CMP). In some embodiments, the first thinning process is carried out by mechanical grinding followed by CMP. As explained above, by removing the edge region (1102 of Fig. 11) prevents the formation of edge defects in the edge area during grinding.

[0061] As shown in section view 1400 of Fig. As shown in 14, an etching process is carried out to remove the sacrificial substrate (902 of Fig. 14) to remove. In some embodiments, the etching also removes part of the second insulating layer 110b on the side walls of the device layer 904. Furthermore, in some embodiments, the etching process laterally etches the side walls 904s of the device layer 904. This lateral etching can, for example, cause the side walls 904s of the device layer 904 to be curved and / or concave. After completion of the etching, the thickness T d The thickness of the device layer 904, for example, may be approximately 0.6 µm to approximately 9.5 µm, approximately 1.8 µm to approximately 7.8 µm, approximately 5.05 µm to approximately 9.5 µm, or may have other suitable values.

[0062] In some embodiments, the etching is carried out using hydrofluoric acid, nitric acid, and acetic acid (HNA), another wet etchant, a dry etchant, or another etchant. In HNA etching, for example, the sacrificial substrate 902 can be etched with a chemical solution containing hydrofluoric acid, nitric acid, and acetic acid. In some embodiments, due to the different doping concentrations of the sacrificial substrate 902 and the device layer 904, the etching can be carried out at a higher rate for the sacrificial substrate 902 than for the device layer 904. The different etching rates allow the thickness T to be adjusted. d The device layer 904 should be very uniform across its entire surface (so that, for example, a total thickness variation of less than approximately 50 nm or 150 nm is achieved). In some embodiments, the total thickness variation (TTV) increases with the thickness T.d the device layer 904. For example, the TTV can be less than approximately 50 nm if the thickness T d The thickness of the device layer 904 is less than approximately 300 nm, and the TTV can be greater than approximately 50 nm but less than approximately 150 nm, depending on the thickness T. d the device layer 904 is larger than approximately 300 nm.

[0063] As shown in section view 1500 of Fig. As shown in Figure 15, the device layer 904 is structured to remove edge portions 904e of the device layer 904. In some embodiments, removing the edge portions 904e of the device layer 904 results in the lateral removal of approximately 1.4 µm to approximately 2.3 µm of the device layer 904. Removing the edge portions 904e also reduces edge defects of the device layer 904. In some embodiments, the structuring also results in a further lateral recess of the side walls 904s of the device layer 904. In some embodiments, after the removal of the edge portions 904e, the side walls 904s of the device layer 904 have a lateral component recess amount LR. d Each side of the handle substrate 102 is recessed.

[0064] In some embodiments, the structuring is carried out by etching the device layer 904 according to a mask 1502 that is produced over the device layer 904. The mask 1502 can, for example, comprise silicon nitride, silicon oxide, another hard mask material, a photoresist, another mask material, or a combination thereof. In some embodiments, the mask 1502 can comprise an oxide layer and an overlying photoresist layer. In these embodiments, the oxide layer can be deposited by a deposition process (e.g., PVD, CVD, PECVD, or the like) with a thickness of about 10 nm to about 30 nm. Subsequently, the photoresist can be deposited by spin coating with a thickness of about 1 µm to about 8 µm.The device layer 904 can be etched by dry etching or another etching process, which may, for example, terminate on the first insulating layer 110a and the second insulating layer 110b. After completion of the structuring process, the mask 1502 can be removed. In some embodiments, a photoresist material in the mask 1502 can be removed by plasma removal, hydrofluoric acid, or the like. In some embodiments, the mask 1502 can be treated with an O₂ plasma (e.g., if the mask 1502 is or contains a photoresist). In some embodiments, the mask 1502 can be treated with hydrofluoric acid for 120 s to 240 s (e.g., if the mask 1502 is or contains an oxide).

[0065] As shown in section view 1600 of Fig. As shown in Figure 16, a second thinning process is carried out in the device layer 904 to increase the thickness T. dto reduce the thickness of the device layer 904. In various embodiments, after the second thinning process, the device layer 904 can have a thickness T. d The thickness may be from approximately 0.3 µm to approximately 8.0 µm, from approximately 0.3 µm to approximately 4.15 µm, or from approximately 4.15 µm to approximately 8.0 µm, and / or may be greater than approximately 0.3 µm, 1.0 µm, 2.0 µm, 5.0 µm, or 8.0 µm, or may have other suitable values. The device layer 904, the first insulating layer 110a, the second insulating layer 110b, and the handle substrate 102 together define an SOI substrate 101. In some embodiments, the second thinning process is carried out by mechanical grinding, CMP, or the like.

[0066] In some embodiments, a fifth wet cleaning process is carried out after the second thinning process to remove etch residues and / or other undesirable byproducts that formed during the structuring. In some embodiments, the fifth wet cleaning process removes oxide that formed on the device layer 904 during the structuring. In some embodiments, the fifth wet cleaning process is carried out by treating the device layer 904 for about 30 s to about 120 s with a first wet cleaning solution containing 1% hydrofluoric acid, then for about 15 s to about 120 s with a second wet cleaning solution containing demineralized water, ammonia solution, and aqueous hydrogen peroxide, and finally for about 15 s to about 120 s with a third wet cleaning solution containing demineralized water, hydrochloric acid, and aqueous hydrogen peroxide.

[0067] As shown in section view 1700 of Fig. As shown in Figure 17, an epitaxial process 1704 is performed to produce a device layer 112 with increased thickness. The epitaxial process 1704 produces an epitaxial layer 1702 on the device layer 904, resulting in a device layer 112. The epitaxial layer 1702 can be produced with a thickness of approximately 0.2 µm to approximately 6 µm. The resulting device layer 112 can have a thickness of approximately 5 µm to approximately 10 µm. In some embodiments, the epitaxial process 1704 can be performed at a temperature of approximately 1100 °C to approximately 1200 °C. Due to the high structural integrity of the handle substrate 102 (which is based on the relatively high density of the BMDs 104 in the middle region 106 of the handle substrate 102), the formation of slip lines by the high temperature of the epitaxy process is prevented.

[0068] As shown in the sectional view 1800 from Fig. As shown in Figure 18, a plurality of transistor devices 402 are fabricated in the device layer 112. In some embodiments, a method for fabricating the transistor devices 402 comprises depositing a dielectric layer over the device layer 112 and depositing a conductive layer such that it covers the dielectric layer. The conductive layer and the dielectric layer are patterned (e.g., by a photolithographic or etching process) to fabricate a gate electrode 408 and a dielectric gate layer 406. Once the gate electrode 408 is in the correct position, dopants can be implanted into the device layer 112 to define lightly doped portions of the source / drain regions 404a and 404b.

[0069] In some embodiments, the multiple transistor devices 402 can be separated from one another by insulating structures 403. In some embodiments, the insulating structures 403 can be shallow trench insulating structures (STIs). In these embodiments, the insulating structures 403 can be produced by etching the device layer 112 to define trenches in the device layer 112. The trenches can then be filled with one or more dielectric materials. In some embodiments, a high-temperature annealing process can be carried out after etching the device layer 112 to repair damage that occurred during the etching process. In some embodiments, the high-temperature annealing process can be carried out at a temperature of more than 1000 °C. In some embodiments, the high-temperature annealing process can be carried out for a duration of more than 1 hour.Because of the high structural integrity of the handle substrate 102 (due to the relatively high density of the BMDs 104 in the middle area 106 of the handle substrate 102), the formation of slip lines is prevented by the high temperature of the tempering process.

[0070] As shown in the 1900 section view from Fig. As shown in Figure 19, a dielectric structure 410 is fabricated over the device layer 112. A plurality of interconnection layers 412 to 416 are fabricated in the dielectric structure 410. In some embodiments, the dielectric structure 410 may comprise a plurality of stacked interlayer dielectric (ILD) layers 410a to 410e fabricated over the device layer 112. In some embodiments (not shown), the multiple stacked ILD layers are separated by etch stop layers (not shown). In some embodiments, the plurality of interconnection layers 412 to 416 may comprise conductive contacts 412, connecting wires 414, and interconnect vias 416. The plurality of interconnection layers 412 to 416 may be fabricated as follows: fabricating one or more of the ILD layers (e.g.,of an oxide, a low-k dielectric or an ultra-low-k dielectric) over the device layer 112; selective etching of the ILD layer to define a via opening and / or a trench in the ILD layer; deposition of a conductive material (e.g. copper, aluminum, etc.) in the via opening and / or the trench; and performing a planarization process (e.g. chemical-mechanical planarization).

[0071] Fig. Figure 20 shows a flowchart of some embodiments of a Method 2000 for producing an SOI substrate with a handle substrate having a central region with a plurality of BMDs arranged between defect-free regions.

[0072] Although Method 2000 is presented and described here as a series of steps or events, it should be understood that the presented sequence of these steps or events should not be interpreted in a restrictive sense. For example, some steps may be performed in different sequences and / or concurrently with other steps or events than those presented and / or described here. Furthermore, it may not be necessary to implement one or more aspects or embodiments of the description presented here. Additionally, one or more of the steps described here may be performed in a single step or in several separate steps and / or phases.

[0073] In step 2002, a plurality of bulk macrodefects are generated in a central region of a handle substrate. The central region of the handle substrate is vertically enclosed by defect-poor regions that have a concentration of bulk microdefects lower than that of the central region (e.g., approximately zero). In some embodiments, the plurality of bulk macrodefects can be generated according to steps 2004 to 2008.

[0074] In step 2004, a plurality of bulk microdefects are generated in a handle substrate. Fig. 6A and Fig. Figure 6B shows sectional views 600 and 602 of some embodiments corresponding to step 2004. Fig. 7A and Fig. Figure 7B shows sectional views 700 and 706 of some alternative embodiments corresponding to step 2004.

[0075] In step 2006, the sizes of the majority of bulk microdefects are increased to generate a majority of bulk macrodefects in the handle substrate. In some embodiments, the sizes of the majority of bulk microdefects can be increased by treating the bulk microdefects with a thermal process (which, for example, has a temperature greater than approximately 1000 °C, greater than approximately 1100 °C, or other suitable values). Fig. Figure 6C shows a sectional view 610 of some embodiments corresponding to step 2006. Fig. Figure 7C shows a sectional view 712 of some alternative embodiments corresponding to step 2006.

[0076] In step 2008, some of the bulk macro defects are removed from the low-defect areas located along the outer surfaces of the handle substrate. Fig. Figure 6D shows a sectional view 614 of some embodiments, corresponding to step 2008. Fig. Figure 7C shows a sectional view 712 of some alternative embodiments corresponding to step 2008.

[0077] In a step in 2010, a first insulating layer is produced on the handle substrate. Fig. Figure 8 shows a sectional view of some embodiments corresponding to step 2010.

[0078] In a step in 2012, a device layer is produced on a sacrificial substrate. Fig. Figure 9 shows a sectional view of 900 of some embodiments, corresponding to step 2012.

[0079] In a step in 2014, a second insulating layer is produced on the sacrificial substrate and the device layer. Fig. Figure 11 shows a sectional view 1100 of some embodiments corresponding to step 2014.

[0080] In a step in 2016, the handle substrate is bonded to the fixture layer and the sacrificial substrate. Fig. Figure 12 shows a sectional view 1200 of some embodiments corresponding to step 2016.

[0081] In a step in 2018, the sacrificial substrate will be removed to expose the device layer. Fig. Figure 13 shows a sectional view 1300 of some embodiments corresponding to step 2013.

[0082] In step 2020, an epitaxial layer is produced on the fixture layer. The production of the epitaxial layer on the fixture layer results in a fixture layer with increased thickness. Fig. Figure 17 shows a sectional view 1700 of some embodiments corresponding to step 2020.

[0083] In step 2022, a transistor component is fabricated in the fixture layer. In some embodiments, the transistor components are fabricated according to steps 2024 to 2028.

[0084] In step 2024, insulation structures are produced in the fixture layer. In some embodiments, the insulation structures are produced in a trench that is etched into the fixture layer. Fig. Figure 18 shows a sectional view 1800 of some embodiments corresponding to step 2024.

[0085] In step 2026, a tempering process is performed on the fixture layer. This tempering process repairs damage caused by etching of the fixture layer. Fig. Figure 18 shows a sectional view 1800 of some embodiments corresponding to step 2026.

[0086] In step 2028, a gate structure is manufactured above the device layer. Fig. Figure 18 shows a sectional view 1800 of some embodiments corresponding to step 2028.

[0087] In a step in 2030, source and drain areas will be manufactured in the device layer. Fig. Figure 18 shows a sectional view 1800 of some embodiments, corresponding to step 2030.

[0088] In step 2032, compound layers are produced in a dielectric structure above the device layer. Fig. Figure 19 shows a sectional view 1900 of some embodiments corresponding to step 2032.

[0089] Thus, in some embodiments, the present invention relates to a method for producing an SOI substrate that has a handle substrate with high structural integrity, minimizing undesirable wafer deformation (bending). The SOI substrate has a handle substrate with a central region containing a relatively high concentration of bulk macrodefects (BMDs). The relatively high concentration (e.g., higher than about 1 × 10⁻⁶) 8 BMDs / cm 3) and large sizes (e.g., larger than about 2 nm) of the BMDs result in less deflection (e.g., higher stiffness) of the handle wafer due to oxide and / or air in the BMDs.

[0090] In some embodiments, the present invention relates to a method for fabricating a semiconductor structure. The method comprises the following steps: generating a plurality of bulk microdefects in a handle substrate; enlarging the size of the plurality of bulk microdefects to generate a plurality of bulk macrodefects (BMDs) in the handle substrate; removing some of the plurality of BMDs from a first defect-free region and a second defect-free region arranged along opposite faces of the handle substrate; fabricating an insulating layer on the handle substrate; and fabricating a device layer with a semiconductor material on the insulating layer, wherein the first and second defect-free regions vertically enclose a central region of the handle substrate that has a higher concentration of the plurality of BMDs than the first and second defect-free regions.In some embodiments, the majority of BMDs have first sizes that are approximately 1000% to approximately 20000% larger than the second sizes of the majority of bulk microdefects. In some embodiments, the multiple BMDs each have a size that is approximately 3 nm to approximately 100 nm. In some embodiments, the method further comprises: performing a first thermal process on the handle substrate to generate the majority of bulk microdefects; and performing a second thermal process on the handle substrate to increase the sizes of the majority of bulk microdefects in the handle substrate to generate the majority of BMDs. In some embodiments, the first thermal process is performed at a first maximum temperature, and the second thermal process is performed at a second maximum temperature that is higher than the first maximum temperature.In some embodiments, the method further includes treating the handle substrate in an environment with argon or hydrogen gas to remove some of the majority of BMDs from the handle substrate and to create the first and second defect-free regions. In some embodiments, the middle region has a BMD concentration of approximately 8 × 10⁻⁶. 8 BMDs / cm 3 up to about 9 × 10 9 BMDs / cm 3In some embodiments, the method further comprises: performing a first thermal process on the handle substrate to increase the number of bulk microdefects in the handle substrate from a first non-zero number to a second non-zero number; and performing a second thermal process on the handle substrate to increase the size of the majority of bulk microdefects in the handle substrate to generate the majority of BMDs. In some embodiments, the method further comprises: fabricating the device layer on a sacrificial substrate; performing a bonding process to bond the device layer and the sacrificial substrate to the handle substrate; and removing the sacrificial substrate from the device layer after performing the bonding process.In some embodiments, the insulating layer is manufactured in such a way that it extends continuously around the outer edges of the handle substrate.

[0091] In some embodiments, the present invention relates to a method for fabricating a semiconductor-on-insulator (SOI) substrate. The method comprises the following steps: performing a first thermal process to generate a plurality of bulk microdefects in a handle substrate; performing a second thermal process to generate a plurality of bulk macrodefects (BMDs) in the handle substrate by increasing the size of the plurality of bulk microdefects; performing a third thermal process to remove some of the plurality of BMDs from a first defect-free region and a second defect-free region arranged along opposite faces of the handle substrate; fabricating an insulating layer on the handle substrate; and fabricating a device layer with a semiconductor material on the insulating layer.In some embodiments, the first and second defect-free regions vertically enclose a central region that has a higher concentration of BMDs than the first and second defect-free regions. In some embodiments, the first thermal process is carried out at a first temperature in a first region of approximately 500 °C to approximately 800 °C, the second thermal process is carried out at a second temperature in a second region of approximately 1050 °C to approximately 1150 °C, and the third thermal process is carried out at a third temperature in a third region of approximately 1100 °C to approximately 1200 °C. In some embodiments, the first defect-free region and the second defect-free region each extend into the handle substrate to depths of approximately 50 nm to approximately 100 µm. In some embodiments, the second thermal process and the third thermal process are one and the same thermal process.

[0092] In further embodiments, the present invention relates to a semiconductor structure. The semiconductor structure comprises: a handle substrate with a plurality of bulk macrodefects (BMDs); an insulating layer arranged on a top side of the handle substrate; and a device layer with a semiconductor material arranged on the insulating layer, wherein the handle substrate has a first defect-free region and a second defect-free region, which vertically enclose a central region of the handle substrate having a higher concentration of the plurality of BMDs than the first and second defect-free regions. In some embodiments, the plurality of BMDs each have a size greater than about 5 nm. In some embodiments, the central region extends laterally between a first outermost side wall of the handle substrate and a second outermost side wall of the handle substrate.In some embodiments, the central region has a concentration of BMDs of approximately 8 × 10. 8 BMDs / cm 3 up to about 9 × 10 9 BMDs / cm 3 In some embodiments, the central area extends laterally beyond opposite outermost side walls of the device layer by non-zero distances.

Claims

[1] Method (2000) for fabricating a semiconductor structure (100) comprising the following steps: Generating (2004) a plurality of bulk microdefects (604) in a handle substrate (102); Enlarging (2006) the size of the plurality of bulk microdefects (604) to generate a plurality of bulk macrodefects, BMDs (104), in the handle substrate (102); Removing (2008) some of the majority of BMDs (104) from a first defect-free area (108a) and a second defect-free area (108b) arranged along opposite faces of the handle substrate (102); Fabrication (2010) of an insulating layer (110, 110a, 110b) on the handle substrate (102); and Fabrication (2012) of a device layer (112, 904) as an active layer with a semiconductor material on the insulating layer (110); wherein the first (108a) and the second (108b) defect-free region vertically enclose a central region (106) of the handle substrate (102) which has a higher concentration of the majority of BMDs (104) than the first (108a) and the second (108b) defect-free region; and i) wherein the insulating layer (110, 110a, 110b) extends continuously around the outer edges of the handle substrate (102); and / or ii) wherein the insulating layer (110, 110a, 110b) completely encloses the handle substrate (102). [2] Method according to the preceding claim, comprising removing edge parts of the device layer (112, 904) such that the device layer (112) has outermost side walls (904s) which are recessed laterally from the outermost side walls of the handle substrate (102) with a lateral component recess amount. [3] Semiconductor structure (100) with: a handle substrate (102) with a plurality of BMDs (104); an insulating layer (110, 110a, 110b) arranged on a top side of the handle substrate (102); and a device layer (112, 904) as an active layer with a semiconductor material, which is arranged on the insulating layer (110, 110a, 110b); wherein the handle substrate (102) has a first defect-free region (108a) and a second defect-free region (108b) which vertically enclose a central region (106) of the handle substrate (102) which has a higher concentration of the majority of BMDs (104) than the first (108a) and the second (108b) defect-free regions; and i) wherein the insulating layer (110, 110a, 110b) extends continuously around the outer edges of the handle substrate (102); and / or ii) wherein the insulating layer (110, 110a, 110b) completely encloses the handle substrate (102). [4] Semiconductor structure (100) according to claim 3, wherein the multiple BMDs (104) each have a size greater than about 5 nm. [5] Semiconductor structure (100) according to one of claims 3 or 4, wherein the central region (106) extends laterally between a first outermost side wall of the handle substrate (102) and a second outermost side wall of the handle substrate (102). [6] Semiconductor structure (100) according to one of claims 3 to 5, wherein the central region (106) has a concentration of BMDs (104) of approximately 8 × 10 8 BMDs / cm 3 up to about 9 × 10 9 BMDs / cm 3 amounts. [7] Semiconductor structure (100) according to one of claims 3 to 6, wherein the central region (106) extends laterally beyond opposite outermost side walls of the device layer (112, 904) by non-zero distances. [8] Semiconductor structure (100) according to any one of claims 3 to 7, wherein the insulating layer (110, 110a, 110b) has a first insulating thickness between the handle substrate (102) and the device layer (112, 904) and a second insulating thickness along a bottom side of the handle substrate (102) and / or along side walls of the handle substrate (102), wherein the second insulating thickness is smaller than the first insulating thickness. [9] Semiconductor structure (100) according to any one of claims 3 to 8, wherein the insulating layer (110, 110a, 110b) has a first insulating thickness between the handle substrate (102) and the device layer (112, 904) which is between 0.2 micrometers and 2.5 micrometers. [10] Semiconductor structure (100) according to any one of claims 3 to 9, wherein the insulating layer (110, 110a, 110b) has a second insulating thickness along a bottom side of the handle substrate (102) and / or along side walls of the handle substrate (102) which is between 2 nanometers and 0.6 micrometers. [11] Semiconductor structure (100) according to any one of claims 3 to 10, wherein the thickness of the device layer (112, 904) is between 0.2 mm and 10 mm. [12] Semiconductor structure (100) according to one of claims 3 to 11, wherein the device layer (112, 904) has outermost side walls (904s) which are recessed laterally from the outermost side walls of the handle substrate (102) with a lateral component recess amount. [13] Semiconductor structure (100) according to any one of claims 3 to 12, wherein the handle substrate (102) has a thickness between 700 micrometers and 800 micrometers.

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