DETERMINATION OF A RESULTING DATA WORD WHEN ACCESSING A STORAGE

Abstract

Methods for determining a resulting data word when accessing memory cells of a memory, including: (a) Reading a set of memory cells in a single read operation, (b) wherein a first data word and a second data word are determined from the set of memory cells read, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) where the first data word and the second data word represent the respective memory cell - assumes a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values ​​are larger and - assumes a second value if the first comparison with the first reference value and the second comparison with the second reference value show that both reference values ​​are smaller, (d) wherein the first data word and the second data word for the respective memory cell take on at least a third value if the conditions according to feature (c) are not met, (e) Determining the resulting data word based on the first data word or based on the second data word.

Description

[0001] Random Access Memory (RAM) is increasingly being deployed, e.g., as - static RAM (SRAM), - dynamic RAM (DRAM), - synchronous dynamic RAM (SDRAM, DDR-SDRAM, etc.), - ferroelectric RAM (FRAM, FeRAM), - magnetic RAM (MRAM), phase-change RAM (PRAM, PCRAM) or - resistive RAM (RRAM, ReRAM).

[0002] Details can be found, for example, at https: / / de.wikipedia.org / wiki / Random-Access_Memory.

[0003] For example, a memory cell can represent the states 0 and 1. When reading a memory cell, an analog cell current I is generated by a read amplifier. cellThe cell current is determined. States 0 and 1 are subject to different cell current distributions (frequency distributions for the cell current). When reading the memory cell, it should be determined to which distribution the currently measured cell current belongs and whether the memory cell therefore represents the value 0 or the value 1.

[0004] The states 0 and 1 can be distinguished from each other if the distributions do not overlap. A reading window refers to a distance or gap between the distributions. The larger the reading window, the better the separation of states 0 and 1.

[0005] For many types of memory, especially RRAM and MRAM, the read window is significantly smaller and can change over time and / or depending on external influences (e.g., shrink or shift).

[0006] The task is therefore to improve existing approaches and, in particular, to provide a robust memory read concept that can also cope with small read windows.

[0007] This problem is solved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

[0008] To solve the problem, a method is proposed for determining a resulting data word when accessing memory cells of a memory, comprising: (a) Reading a set of memory cells in a single read operation, (b) wherein a first data word and a second data word are determined from the set of memory cells read, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) where the first data word and the second data word represent the respective memory cell - assumes a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values ​​are larger and - assumes a second value if the first comparison with the first reference value and the second comparison with the second reference value show that both reference values ​​are smaller, (d) wherein the first data word and the second data word for the respective memory cell take on at least a third value if the conditions according to feature (c) are not met, (e) Determining the resulting data word based on the first data word or based on the second data word.

[0009] Preferably, the memory cell is a binary memory cell. Before reading, a binary value was written to the memory cell. The read value of the memory cell represents a state of the memory cell.

[0010] For example, a single read operation is performed to determine the physical values ​​for the set of memory cells. These physical values ​​result from their underlying frequency distributions. The physical values ​​determined in this single read operation are used to derive at least two data words, for example, one data word per reference value.

[0011] Accordingly, further reference values ​​can be provided, leading to additional data words. By comparing the individual (identical) components of the data words (each component corresponds to a memory cell), the reliability of the affected memory cell can be determined.

[0012] The first, second, and third values ​​can each be a pair of values ​​or an n-tuple (where n is the number of data words) with multiple (binary) values. For example, each of these values ​​can take one of the values ​​[0,0], [1, 1], [0,1], or [1,0].

[0013] In particular, the first reference value can be the smallest reference value and the second reference value the largest reference value. This is especially advantageous when there are more than two reference values.

[0014] The approach proposed here thus enables fault-tolerant handling even with small read windows. For example, analog values ​​provided by a sense amplifier (SA) can be compared with multiple reference values. Such a comparison can be performed in the voltage domain, the current domain, and / or the time domain.

[0015] It is a further development that at least one third value comprises a pair of values ​​with binary values ​​that are different from each other.

[0016] It is a further education course that - the resulting data word is determined by the first data word, - if the first data word is a codeword of an error code or - if the first data word can be corrected using the error code, or - the resulting data word is determined by the second data word, - if the second data word is a code word of the error code or - if the second data word can be corrected using the error code.

[0017] Error code C is preferably an error-correcting and / or error-detecting code.

[0018] It is a further development step that a predefined action is executed if the error of the first data word or the second data word cannot be corrected using the error code.

[0019] It is a further training course that continues to include the procedure: - Performing a comparison with a third reference value that is different from the first and second reference values, - wherein the components of the first data word and the second data word are determined depending on comparisons with the first reference value, with the second reference value and with the third reference value.

[0020] It is a further development that if the conditions according to feature (c) are not met, the first data word and the second data word for the respective memory cell, depending on a comparison with a further reference value, assume at least the third value.

[0021] The third value is different from the first value and the second value.

[0022] The additional reference value can be a third reference value positioned between the first and second reference values. For example, the first reference value can be the smallest and the second the largest. In this case, the additional reference value, as the third reference value, is larger than the first reference value and smaller than the second.

[0023] If the value read from the memory cell lies between the first and second reference values, a comparison with the third reference value can determine whether the value read from the memory cell is closer to the first or the second reference value. The third value can be determined based on how close the read value is to the first or the second reference value. For example, the third value could be a two-component value.

[0024] For example, if the first value is [0,0] and the second value is [1,1], then the third value can be determined as [0, 1] or as [1,0] depending on whether the value read from the memory cell is smaller or larger than the third reference value.

[0025] Alternatively, if the first value is [1,0] and the second value is [0,1], then the third value can be determined as [0,0] or as [1, 1] depending on whether the value read from the memory cell is smaller or larger than the third reference value.

[0026] It is a further education course that - another data word is determined, with each memory cell being assigned a component of the further data word, - the next data word is a third data word, - the first data word, the second data word and / or the third data word for the respective memory cell according to feature (c) take on the first value or the second value according to the conditions of feature (c), - the first data word, the second data word and / or the third data word take on at least one third value if the conditions according to feature (c) are not met, - the resulting data word is determined based on the first data word, the second data word, and the third data word.

[0027] The first, second, and third values ​​are each, for example, three-component binary values. If, for instance, the first value is [0, 0, 0] and the second value is [1, 1, 1], then the third value can be defined as a three-component binary value that is different from the first and second values, e.g., [0, 1, 1] or [1, 1, 0].

[0028] It is an option that the third value can be determined differently or the same for different memory cells.

[0029] It is a further development that a fourth data word is determined as a component-wise XOR operation of the first, second and third data words.

[0030] For example, a fourth component can be introduced, determined by an XOR operation of the three preceding components. If the bits of a three-component value of a data word are [b1, b2, b3], then a fourth bit for this data word is obtained as follows: b4=b1⊕b2⊕b3 and the data word becomes [b1,b2,b3,b4].

[0031] For example, if the first value for the first, second, and third data word is determined to be [0,0,0] and the second value for the first, second, and third data word is determined to be [1,1,1], then the first value for the first, second, third, and fourth data word will be [0,0,0,0] and the second value for the first, second, third, and fourth data word will be [1, 1, 1, 1], since, as explained above, the fourth component is defined by the three previous components.

[0032] For example, if the third value for the first, second and third data word of a first memory cell is [1,1,0] and for the third value of a second memory cell is [0,1,0], then the third value of the first memory cell for the first, second, third and fourth data word is determined to be [1,1,0,0] and the third value of the second memory cell for the first, second, third and fourth data word is determined to be [0, 1,0, 1].

[0033] This results in pairs of the first, second, third, and fourth components of the third values ​​of the first and second memory cells: [1,0], [1,1], [0,0], and [0, 1]. These are pairs of components corresponding to the first and second memory cells for the first data word, the second data word, the third data word, and the fourth data word.

[0034] It is a further development that, when reading memory cells further, at least one of the reference values ​​is not used, depending on the previously determined errors.

[0035] It is a further development that different read memory cells or groups of memory cells are at least partially compared with different reference values.

[0036] It is a further development that the reading of the set of memory cells takes place after an initialization or a switch-on.

[0037] It is a further development that the value read out per memory cell has a time dependency and is compared in a time domain with at least one reference value.

[0038] It is a further training that, based on steps (c) and (d), a classification of the memory cells with regard to their reliability is carried out.

[0039] For example, if condition (c) is not met, it can be concluded that the memory cell has a lower reliability than if condition (c) is met.

[0040] Furthermore, a device is proposed for determining a resulting data word when accessing memory cells of a memory, wherein the device is configured to perform the following steps: (a) Reading a set of memory cells in a single read operation, (b) wherein a first data word and a second data word are determined from the set of memory cells read, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) where the first data word and the second data word represent the respective memory cell - assumes a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values ​​are larger and - assumes a second value if the first comparison with the first reference value and the second comparison with the second reference value show that both reference values ​​are smaller, (d) wherein the first data word and the second data word for the respective memory cell take on at least a third value if the conditions according to feature (c) are not met, (e) Determining the resulting data word based on the first data word or based on the second data word.

[0041] The device can be part of the memory or implemented separately from it. In particular, the device can include a processing unit that performs the steps mentioned herein. The processing unit can include at least one of the following components: a processor, a microcontroller, an integrated circuit, an ASIC, an FPGA, or a logic unit. The processing unit can be implemented as at least one physical unit. In particular, the processing unit can be distributed across multiple physical units.

[0042] The foregoing explanations concerning the procedures apply accordingly to the device. The steps of the procedure described here can be carried out using the device.

[0043] The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, are described below in conjunction with a schematic description of exemplary embodiments, which are explained in more detail in connection with the drawings. For clarity, identical or equivalent elements may be designated with the same reference numerals.

[0044] They show: Fig. 1 a schematic diagram showing distributions of physical values ​​for memory cells of a memory as well as two reference values; Fig. 2 a schematic diagram showing distributions of physical values ​​for memory cells of a memory as well as three reference values; Fig. 3 a schematic circuit arrangement with latches for determining digital values ​​in the time domain.

[0045] It is proposed to read digital values ​​from memory cells of a memory device with the highest possible reliability using at least two reference values. The digital values ​​can be binary values ​​(also referred to as bits) or multi-valued digital values.

[0046] The reliability of memory cells can vary; in particular, memory cells can exhibit different states (also referred to as reliability states) with regard to their reliability. For example, a memory cell in a first reliability state has a low probability of outputting an erroneous value. Conversely, in a second reliability state, the memory cell has a high probability of providing an erroneous value when read. Thus, in the second reliability state, the memory cell can output the value 0 or 1 with a 50% probability, while in the first reliability state, the memory cell has a significantly lower probability of outputting an erroneous value.

[0047] When reading n memory cells S p1 ,...,S pn can a first data word W1=x11,…,xn1 with n components x11,…,xn1 (also referred to as bits) and a second data word W2=x12,…,xn2 with n components x12,…,xn2 be determined.

[0048] In another example, more than two data words can be determined when reading the memory cells.

[0049] The memory cells Sp1,...,Sp n can be used with the bits x1,...,x n have been described.

[0050] It is an option for a codeword of an error code C to use the bits x1,...,x n includes. For example, the bits x1,... 'x n together with address bits and / or bits derived from address bits, form a codeword.

[0051] In particular, the bits x1,...,x n Form a codeword for error code C. Error code C can be an error-correcting code and / or an error-detecting code.

[0052] The following example assumes that the bits x1,...,x n Form a code word for error code C.

[0053] From the first data word W 1 and the second data word W 2 This results in a data word W. r as follows: Wr=x1r,…,xnr.

[0054] For i = 1,...,n, when reading a memory cell Sp i two reference values R−i and R+i with R−i<R+iundR+i−R−i=Δi> 0 used.

[0055] The memory cell Sp i has a physical value V i which is, for example, an electrical resistance. A read current determined by the resistance of the memory cell can, for example, be used with the first reference value. R−i as well as with the second reference value R+i can be compared.

[0056] A first digital value αi can be determined by whether the reading stream is smaller or larger than the first reference value R−i is. The second digital value β i can be determined by whether the reading stream is smaller or larger than the second reference value R+i is.

[0057] For example, one is used when reading the memory cell Sp i specific reading stream with both the first reference value R_i to determine the first digital value α i as well as with the second reference value R+i to determine the second digital value β i compared. In this example, α is i and β i about binary values.

[0058] It is an option to have more than two reference values, for example three reference values. R−i,Ri,R+i can be used, with which a reading of the memory cell Spi A specific physical value is compared. This physical value could be, for example, a reading current, a charge, or a voltage (e.g., related to the reading current).

[0059] Optionally, a value derived from the state of the memory cell can be compared with at least two reference values ​​in order to determine at least two digital values.

[0060] Several approaches are known for determining a binary value when reading a memory cell using reference values. Document US 9,805,771 discloses that a binary value can be determined when reading memory cells in a time domain.

[0061] For example, the read current of a memory cell can be integrated over a capacitor. Similarly, a current corresponding to a reference value can be integrated over a capacitor, and it can be determined whether the integral of the read current reaches a threshold before or after the integral of the reference value's current. If the integral of the read memory cell's current reaches the threshold before the integral of the reference value's current, a first digital value for the memory cell can be determined upon reading. If the integral of the read memory cell's current reaches the threshold after the integral of the reference value's current, a second digital value for the memory cell can be determined upon reading.

[0062] Accordingly, a comparison of a state stored in a memory cell with several reference values ​​can be performed.

[0063] When reading a memory cell Sp i The read physical value or a value derived from the physical value can be compared with both the first reference value and the second reference value without having to read this physical value again.

[0064] The extracted value can also be an indirectly extracted value, e.g., a value that was determined from the extracted value.

[0065] It is possible to determine the location or position of the read value relative to the first reference value and the second reference value.

[0066] This determines whether the read value is greater or less than the first and / or second reference value. If the comparison is in the time domain, it can be determined whether, and if so, which reference value will be reached earlier or later.

[0067] A read value from memory cell Sp i The result is compared to the first and second reference values. Values ​​can be... xi1 and xi2 an i-th component of the first data word W 1 and the second data word W 2 as follows: - If the read value is greater than the first reference value and greater than the second reference value, the components are xi1 and xi2 the two data words W 1 and W 2 equal and have a first value. - If the read value is smaller than the first reference value and smaller than the second reference value, the components are xi1 and xi2 the two data words W 1 and W 2 are the same and have a second value that differs from the first value. - If the read value is greater than the first reference value and less than the second reference value, or if the read value is less than the first reference value and greater than the second reference value, the components are xi1 and xi2 They are unequal, or inverse, of each other. For example, one of the values ​​can be 0 and the other 1.

[0068] Is the memory cell Sp i For example, if it has been described with a 1 and the value read from the memory cell is positioned between the first and second reference values, then one of the values xi1 or xi2 equals 1. Regardless of whether the memory cell Sp is read i Whether a correct or an incorrect physical value was read is indicated in one of the two data words W. 1 and W 2 The i-th component is correct.

[0069] For further explanation, see Fig. 1 referred.

[0070] Into the memory cells Sp1,... ,Sp n The bits to be stored will be x1,...,x n written, the bits of a codeword of an error code C are.

[0071] It is an option that the bits x1,...,x n Together with other bits, they form a codeword for the error code C. These other bits can be address bits or bits derived from address bits. The address is preferably the address under which the bits x1,...,x are located. n stored in the memory.

[0072] For example, the address can be provided by an address generator as a write address when writing and as a read address when reading.

[0073] It is also an option for the additional bits to include a password that is checked, for example, when writing and / or reading.

[0074] Error code C can be an Hsiao code. For example, error code C could be a 1-bit error-correcting and 2-bit error-detecting code, or a 2-bit error-correcting and 3-bit error-detecting BCH code.

[0075] As mentioned above, when reading memory cells Sp1,..., Sp n the first data word W 1 and the second data word W 2 determined. The first data word W 1 The first data word is either a codeword for error code C or not a codeword for error code C. The second data word is W. 2either a codeword for error code C or no codeword for error code C.

[0076] Is the first data word W 1 A codeword of the error code C can be in the resulting data word W. r can be used.

[0077] Is the first data word W 1 If there is no codeword of error code C and it differs from a codeword of error code C in faulty bits, such that a correctable error of code C exists, then the data word W 1 into a corrected first data word W 1,cor corrected. The corrected first data word W 1,cor can be in the resulting data word W r can be used.

[0078] Does the first data word W differ? 1 For example, if exactly one bit of a codeword containing error code C is affected, then a 1-bit error occurs. If the error code is an Hsiao code, this 1-bit error can occur in the first data word W. 1into the corrected first data word W 1,cor to be corrected.

[0079] Is the first data word W 1 If there is no codeword of error code C and it differs from any codeword of error code C in bits that constitute a non-correctable error of error code C, the first data word W is used. 1 marked as uncorrectable.

[0080] Is the second data word W 2 If there is no codeword of error code C and it differs from a codeword of error code C in faulty bits, such that a correctable error of code C exists, then the data word W 2 into a corrected second data word W 2,cor corrected. The corrected second data word W 2,cor can be in the resulting data word W r can be used.

[0081] Is the second data word W 2If there is no codeword of error code C and it differs from any codeword of error code C in bits that constitute a non-correctable error of error code C, the second data word W is used. 2 marked as uncorrectable.

[0082] An error in the bits of the first data word can occur, for example, if an i-th bit xi1, for which the two digital values ​​α i and β i are the same and that's considered xi1=αi=βi is determined to be faulty. If such an error occurs with a low probability, the memory cell Sp is i in a reliable condition.

[0083] An error in the bits of the first data word can occur, for example, if a j-th bit xj1, for which the two digital values ​​αj and β j are unequal and that is considered xj1=0 is determined, is faulty. The binary value 0 of the first data word, for example, is determined for all memory cells for which the corresponding first digital value is not equal to the second digital value. The component xj2 of the second data word W 2 is then equal to 1.

[0084] The memory cell Sp j is in an unreliable state. The memory cell Sp j In its unreliable state, it outputs, for example, the binary value 0 or the binary value 1 with a probability of 50%. One of the output values ​​is correct, the other is erroneous.

[0085] Since the component xj1 of the first data word equal to 0 and the component xj2 of the second data word W 2 If the result is equal to 1, then either the corresponding component of the first data word or the corresponding component of the second data word is error-free.

[0086] If, in an example, only a few memory cells are in an unreliable state, the probability pu that a memory cell is in an unreliable state is low. In this case, the memory cell in the unreliable state outputs an erroneous value with a probability of 1 / 2 pu.

[0087] Fig. Figure 1 shows distributions of physical values ​​V for memory cells of a memory. Distribution 11 is assigned to a binary value 1 and distribution 12 is assigned to a binary value 0. Distributions 11 and 12 overlap in an overlap region 13.

[0088] Furthermore, a reference value R + 17 and a reference value R_ 18 are shown, where R + -R_ > 0 applies.

[0089] For a memory cell Sp i With i = 1,...,n, a first digital value α is obtained. i to αi={1 for Vi≤R−0 for Vi>R−, and a second digital value β i to βi={1 for Vi≤R+0 for Vi>R+.

[0090] It is assumed below that the reference values ​​for three memory cells under consideration are Sp j 14, Sp k 15 and Sp l 16 (j ≠ k ≠ l) are equal. Three physical values ​​V are given as examples. j , V k and V l each compared with reference values ​​17 and 18.

[0091] The physical value V j the memory cell Sp j 14 is smaller than either of the reference values ​​17 and 18. Therefore, the digital values ​​are given by α. j =β j = 1. From this it follows xj1=xj2=1 for the j-th bit xj1 of the first data word W 1 and for the j-th bit xj2 of the second data word W 2 .

[0092] The physical value V jIt is not within the overlap area 13. The digital values ​​α j and β j the memory cell Sp j 14 are both equal to 1. The memory cell Sp j 14 can be considered reliable when reading the memory cell Sp j In case 14, there is only a low probability of a reading error.

[0093] The physical value V k the memory cell Sp k 15 is greater than either of the reference values ​​17 and 18. Therefore, the digital values ​​are given by α. k = β k = 0. Therefore, xk1=xk2=0 for the k-th bit xk1 of the first data word W 1 and for the k-th bit xk2 of the second data word W 2 .

[0094] The physical value V k It is not within the overlap area 13. The digital values ​​α k and β k the memory cell Sp k15 are both equal to 0. The memory cell Sp k 15 can be considered reliable when reading the memory cell Sp k In case 15, there is only a low probability of a reading error.

[0095] The physical value V l the memory cell Sp l 16 is greater than the reference value 18 and less than the reference value 17. Therefore, the digital values ​​are given by α. l = 0 ≠ β l = 1. From this it follows xl1=0 for the l-th bit xl1 of the first data word W 1 and xl2=1 for the l-th bit xl2 of the second data word W 2 .

[0096] The physical value V l It lies within the overlap area 13. It is more likely a read error when reading memory cell Sp. l 16 is to be expected when reading the memory cells Sp j14 and Sp k 15. The memory cell Sp l can be considered unreliable.

[0097] There is no error in the n - 1 components x11,…,xl−11,xl+11,…,xn1 of the first data word W 1 and in the n - 1 components x12,…,xl−12,xl+12,…,xn2 of the second data word W 2 before, then either the first data word is W 1 or the second data word W 2 a code word for error code C.

[0098] The first data word W 1 and the second data word W 2 differ in the bits xl1 by W 1 and xl2 by W 2 Since α l ≠β l applies, were xl1=0 and xl2=1 set. Either x l = 0 or x l = 1 into memory cell Sp l written.

[0099] Was xl = 0 in memory cell Sp l 16 written, then W 1 error-free and a code word for error code C. Was x l = 1 into memory cell Sp l 16 written, then W 2 error-free and a code word for error code C.

[0100] Is W 1 If the data word is error-free and contains a codeword of the error code C, then the resulting data word is W. r to W 1 definitely. Is W 2 If the data word is error-free and contains a codeword of the error code C, then the resulting data word is W. r to W 2 certainly.

[0101] For example, it is assumed that x l = 0 in memory cell Sp l 16 was written and that thus W 1 is error-free and is a code word of the error code.

[0102] If there is now an additional bit, for example the first bit with 1 ≠ l, both in W 1 as well as in W 2 faulty, although x11=x12 and α1 =β1 holds, then the first data word W 1 A 1-bit error occurred in the first bit. The second data word W 2 exhibits a 2-bit error, where the first bit and the l-th bit are faulty.

[0103] If, for example, the error code C is a known 1-bit error-correcting and 2-bit error-detecting Hsiao code, then the first data word is W. 1 Correctable using code C.

[0104] Accordingly, the erroneous first data word W 1 using the Hsiao code into the first corrected data word W 1,cor to be corrected.

[0105] The second data word W 2 is not correctable using the example error code C. Due to the error code in W 2In the case of an existing 2-bit error, the faulty second data word is recognized as uncorrectable by the error code C, which is an example of a 1-bit error correcting and 2-bit error detecting Hsiao code.

[0106] The resulting data word W r is then equal to W 1,cor .

[0107] For example, if the error code C is a 2-bit error-correcting and 3-bit error-detecting BCH code, the first data word W 1 , which has a 1-bit error in the first bit, into the corrected first data word W 1,cor corrected. Also the second data word W 2 , which has a 2-bit error in the first bit and in the l-th bit, is converted into the second corrected data word W by the error code C 2,cor corrected. The resulting data word W r In this case, it is to W r = W 1,cor = W 2,cor certainly.

[0108] However, if, for example, a 2-bit error also occurs in the first and second bits of both the first data word W 1 as well as in the second data word W 2 If l ≠ 1,2, this 2-bit error can occur in the first data word W. 1 into the corrected first data word W 1,cor can be corrected. The second data word, however, has 3-bit errors in the first, second, and l-th bits, which cannot be corrected by the error code C. The faulty second data word W 2 is recognized as uncorrectable. The resulting data word W r results in W r = W 1,cor .

[0109] In another example, it is assumed that the fifth and seventh bit positions of the corresponding digital values ​​are unequal, i.e., α5 ≠ β5 and α7 ≠ β7. For the first data word W 1 Then x5 = x7 = 0 is determined, and for the second data word W 2x5 = x7 = 1.

[0110] Bits x3 and x7 were written to memory cells Sp5 and Sp7. There are four possible assignments for bits x3 and x7, which can be distinguished as follows: - x3 = x7 = 0: The first data word W 1 is in the bits x51 and x71 flawless. - x3 = x7 = 1: The second data word W 2 is in the bits x52 and x72 flawless. - x3 = 0 and x7 = 1: Both the first data word W 1 indicates in the bits x51 and x71 as well as the second data word W 2 indicates in the bits x52 and x72 a 1-bit error occurred. - x5 = 1 and x7 = 0: Both the first data word W 1 indicates in bits x3 and x71 as well as the second data word W 2indicates in the bits x52 and x72 a 1-bit error occurred.

[0111] Depending on which values ​​have been written to memory cells Sp5 and Sp7, and regardless of whether the bits read from these memory cells are faulty or correct, the following applies: Either one of the data words W 1 or W 2 is in the corresponding bits x51 and x71 or in the bits x52 and x72 The data words are error-free, or both contain a 1-bit error in these bits. Either no error occurs in one of the data words, or at most a 1-bit error occurs, such that the number of errors in at least one of the data words can be reduced by at least one error.

[0112] Fig. Figure 2 shows a distribution of physical values ​​V for memory cells of a memory. Distribution 21 is assigned to a binary value 1 and distribution 22 is assigned to a binary value 0. Distributions 21 and 22 overlap in an overlap region 23.

[0113] Furthermore, a reference value R + 27, a reference value R_ 28 and a reference value R 29 are shown, where R + > R > R_ > 0 applies.

[0114] The reference value R_ 28 can be used as the left reference value, the reference value R 29 can be used as the middle reference value, and the reference value R + 27 can be described as the right reference value.

[0115] Three memory cells are used. j 24, Sp k 25 and Sp l 26 with their corresponding physical values ​​V j , V k and V lThis can involve physical states of the memory cells or states derived from the physical states of the memory cells.

[0116] For the sake of simplicity, it is assumed below that the reference values ​​27 to 29 are the same for all three memory cells 24 to 26. However, examples are also possible that provide at least partially different reference values.

[0117] By comparing each physical value with three reference values, three binary digital values ​​can be determined for each of the memory cells as follows: For the memory cell Sp j 24 with the physical value V j are the digital values ​​α j , β j and γ j through αj={1 for Vj≤R−0 for Vj>R−, βj={1 for Vj≤R+0 for Vj>R+, γj={1 for Vj≤R+0 for Vj>R+. certainly.

[0118] For the memory cell Sp k 25 with the physical value V k are the digital values ​​α k , β k and γ k through αk={1 for Vk≤R−0 for Vk>R−, βk={1 for Vk≤R+0 for Vk>R+, γk={1 for Vk≤R+0 for Vk>R+. certainly.

[0119] For the memory cell Sp l 26 with the physical value V l are the digital values ​​α l , β l and γ l through αl={1 for Vl≤R−0 for Vl>R−, βl={1 for Vl≤R+0 for Vl>R+, γl={1 for Vl≤R+0 for Vl>R+. certainly.

[0120] Out of Fig. 2 results in: αj=βj=γj=1, αk=βk=γk=0, αl=0,βl=γl=1. Are a first data word W1=x11,…,xn1 and a second data word W2=x12,…,xn2 If provided, then it is an option for i = 1, ... , n the bits xi1 of the first data word and the bits xi2 to determine the second data word such that:

[0121] It is xi1=xi2=αi for αi=βi, and it is xi1=γi and xi2=γ¯i for αi≠βi.

[0122] For the memory cell Sp j 24 is α j = β j = 1, and the memory cell is in a reliable state. The j-th component xj1 of the first data word W 1 , and the j-th component xj2 of the second data word W 2 are equal and equal α j = β j .

[0123] For the memory cell Sp k 25 is α k = β k = 0, and the memory cell is in a reliable state. The k-th component xk1 of the first data word W 1 and the k-th component xk2 of the second data word W 2 are equal and equal α k = β k .

[0124] For the memory cell Sp l 26 is α l ≠ β l and the memory cell is in an unreliable state. Its corresponding physical value V j lies in the overlap region 23 of distributions 21 and 22. The l-th component xl1 of the first data word W 1 is equal to γ1 and the l-th component xl2 of the second data word W 2 is equal to γ̅1. The l-th component of the first data word and the second data word are unequal and inverse to each other.

[0125] It is an option to use a first data word. W1=x11,…,xn1, a second data word W2=x12,…,xn2, a third data word W3=x13,…,xn3 and a fourth data word W4=x14,…,xn4 to use and the bits for the data words W 1 , W 2 , W 3 , W 4 and for i=1,...,n the bits xi1,xi2,xi3,xi4 for example, to be determined in the following way: xi1=xi2=xi3=xi4=αi for αi=βi and xi1=0,xi2=1,xi3=γi,xi4=γ¯i=γi⊕1 for αi≠βi.

[0126] This then applies to i = 1,...,n xi4=xi1⊕xi2⊕xi3, so that the components of the fourth data word W 4 equal to an exclusive-OR sum (also called an XOR sum) of the corresponding components of the data words W 1 , W 2 and W 3 are.

[0127] For example, is a memory cell Sp K with 1 ≤ K ≤n a first memory cell that is in an unreliable state, such that α K ≠ β K applies and is a memory cell Sp Lwith 1 ≤ K < L ≤ n a second memory cell that is in an unreliable state, such that α L ≠ β L If this is the case, then it is advantageous if tuples [xK1,xL1],[xK2,xL2],[xK3,xL3],[xK4,xL4] the bits of the data words W 1 ,W 2 ,W 3 ,W 4 are determined in such a way that these tuples form all four possible binary tuples.

[0128] For the first memory cell Sp K in an unreliable state, for example xK1, xK2, xK3, xK4 to xK1=0,xK2=1,xK3=0,xK4=1 certainly.

[0129] For the second memory cell Sp L in an unreliable state, for example xL1,xL2,xL3,xL4 to xL1=0,xL2=1,xL3=1,xL4=0 certainly.

[0130] Then it applies [xK1,xL1]=[0,0], [xK2,xL2]=[1,1], [xK3,xL3]=[0,1], [xK4,xL4]=[1,0] and each of the four possible tuples [0,0], [1,1], [0, 1], [1,0] occurs in one of the four data words.

[0131] Is one of the data words W 1 ,W 2 ,W 3 ,W 4 If a codeword of the used error code C is used, then this codeword can be used as the resulting data word W. r can be determined. Is one of the data words W 1 ,W 2 ,W 3 ,W 4 , for example W 2 , a faulty data word that is converted into a codeword W using the error code C 2,cor If the code C is correctable, then the codeword W can be 2,cor as the resulting data word W r = W 2,cor be used.

[0132] The case of memory cells Sp is considered as an example. K and Sp L the only two memory cells of the memory cells S p1 ,...,Sp n are unreliable. The digital values ​​γ Kand γ L form the tuple [γ K , γ L ].

[0133] In one of the four data words W 1 ,W 2 ,W 3 ,W 4 is one of the tuples [xK1,xL1]=[0,0], [xK2,xL2]=[1,1], [xK3,xL3]=[0,1], [xK4,xL4]=[1,0] equal to the tuple [x K ,x L ] of the bits x K ,x L , which are stored in the memory cells Sp K and Sp L have been written, regardless of which binary values ​​were stored in the memory cells Sp K and Sp L output was incorrect or correct in an unreliable state.

[0134] For example, for x K = 1, x L = 1 the second data word W 2 A codeword of the error code C if there is no error in the n - 2 bits x12…,xK−12,xK+12,…,xL−12,xL+12,…,xn2 An error occurred in one of these n - 2 bits of the second data word W. 2 It is then correctable as a 1-bit error, regardless of whether two memory cells are in an unreliable state and regardless of whether these two memory cells output erroneous or correct binary values. Example: Reading memory cells, evaluation in the time domain

[0135] The following describes, as an example, the reading of memory cells in the time domain using multiple reference values. Three memory cells Sp1, Sp2, and Sp3 and two different reference values ​​R_ and R_ are used as examples. + considered.

[0136] Depending on the state of memory cell Sp1, a derived value v1(t) is determined. This derived value v(t)1 is a binary, time-dependent value. Up to a certain time τ1, it takes the value 0, and from that time τ1 onwards, it takes the value 1.

[0137] For example, the state of memory cell Sp1 can be determined by an electrical resistance value R1. Depending on the resistance value R1, a read current I1 is determined when reading memory cell Sp1. The read current I1 can be integrated over time using a capacitance Ca to obtain a voltage V1(t), which is then compared to a threshold voltage V using a comparator. The binary, time-dependent value v1(t) is provided at the comparator's output. As long as the voltage V1(t) ≤ V, v1(t) = 0. If the voltage V1(t) > V, v1(t) = 1.

[0138] Accordingly, when reading memory cell Sp2, a binary derived value v2(t) is determined, which takes the value 0 up to a time τ2 and the binary value 1 from time τ2 onwards.

[0139] Furthermore, when reading the memory cell Sp3, a binary derived value v3(t) is determined, which takes the value 0 up to a time τ3 and the binary value 1 from a time τ3 onwards.

[0140] Furthermore, a binary derived value r_(t) is determined for the reference value R_, which takes the value 0 up to a time τ_ and the binary value 1 from the time τ_ onwards.

[0141] Additionally, the reference value R is used + a binary derived value r + (t) determines the time up to τ + the value 0 and from time τ + takes the binary value 1.

[0142] Fig. Figure 3 shows a circuit arrangement with 6 latches 311, 312, 321, 322, 331 and 332. Each of the latches includes a data input, an input for a hold signal, and a data output. Furthermore, in Fig.Figure 3 shows five inputs 31 to 35, with input 31 receiving a binary signal v1(t), input 32 receiving a binary signal v2(t), input 33 receiving a binary signal v3(f), input 34 receiving a binary signal r_(t) and input 35 receiving a binary signal r + (t) is located.

[0143] Input 31 is connected to the data inputs of latches 311 and 312, input 32 is connected to the data inputs of latches 321 and 322, and input 33 is connected to the data inputs of latches 331 and 332.

[0144] Input 34 is connected to the hold signal inputs of latches 312, 322 and 332, and input 35 is connected to the hold signal inputs of latches 311, 321 and 331.

[0145] The value α1 is provided at the output of latch 311, the value β1 is provided at the output of latch 312, the value α2 is provided at the output of latch 321, the value β2 is provided at the output of latch 322, the value α3 is provided at the output of latch 331 and the value β3 is provided at the output of latch 332.

[0146] When the hold signal of a latch assumes the value 1, the value present at the data input of the respective latch is stored in the latch.

[0147] For example, if τ_ < τ1, then the value 0 is stored in latch 311. The hold signal r_(t) is equal to 1 before the signal v1(t) at the data input assumes the value 1. If τ + If < τ1, then the value 0 is also stored in Latch 312 and α1 = β1.

[0148] If τ_ < τ1, then the value 0 is stored in latch 311. If τ + > τ1, then the value 1 is stored in latch 312 and α1 ≠ β1.

[0149] The other values ​​stored in the latches are determined analogously. This is based on the temporal order in which the binary signals v1(t), v2(t), v3(t), r_(t) and r are received. + If (t) takes the value 1, the contents of the latches are determined. The contents of the latches further determine the values ​​α1, β1, α2, β2, α3 and β3.

[0150] If n memory cells are read, then 2n latches can be used with two reference values. If N > 2 reference values ​​are used, then Nn latches can be used. Determining a reference value from a set of reference values

[0151] The following is an example of how at least one reference value can be determined from a set of reference values.

[0152] Five reference values ​​serve as examples R−−,R−,R,R+,R++ with R−−>R−>R>R+>R++ a set of reference values.

[0153] It is an option to use a physical value determined during the readout or a value derived from the physical value with the reference values ​​R when reading memory cells. - and R + to compare, determine digital values ​​and a first data word W 1 (R - ,R + ) and a second data word W 2 (R - ,R + ) to form.

[0154] Is the first data word W 1 (R - ,R + ) If the result is error-free or correctable using the error code under consideration, then the first data word, or, if applicable, the corrected first data word, can be used as the resulting data word W. r (R - ,R + ) can be used.

[0155] Is the second data word W 2 (R - ,R +) If the second data word is error-free or correctable using the error code under consideration, then the second data word, or, if applicable, the corrected second data word, can be used as the resulting data word W. r (R - ,R + ) can be used.

[0156] The memory cells can be part of an addressable memory. For example, memory cells of a first memory area, which is determined by a first address range, can be accessed using the reference values ​​R. - and R + The data can be read out. It is possible to determine how many errors occur when reading the memory cells using the reference values ​​R. - and R + have occurred. For example, it can be determined how many read operations under a read address of the selected memory area result in an error that cannot be corrected using the error code.

[0157] One option is to access memory cells of a second memory area, which may be determined by a second address range, using the two reference values ​​R -- and to read R, a first data word W 1 (R -- ,R), a second data word W 2 (R -- ,R) and a resulting data word W r (R -- ,R) to form, as above for the reference values ​​R - and R + described.

[0158] This allows us to determine how many errors occur when reading the memory cells of the second memory area using the reference values ​​R. -- and R have occurred. This allows, for example, the determination of how many read operations under the read address of the selected memory area resulted in an error that cannot be corrected using the error code.

[0159] For additional memory areas, further reference values ​​or combinations of reference values ​​can be used during readout, and it can be determined how many errors cannot be corrected by the error code.

[0160] Another option is to use, when reading memory cells at a later time, those reference values ​​or combinations of reference values ​​that have resulted in, for example, a minimal number of uncorrectable errors.

[0161] It is also an option to determine the number of unreliable cells encountered when reading data from the various memory areas.

[0162] If an addressable memory is used, for example, in a motor vehicle, different memory areas can be read and suitable reference values ​​or combinations of reference values ​​determined during power-up. The determined reference value or combination of reference values ​​can then be used during subsequent operation. Such an approach to determining reference values ​​can be advantageous if the distribution of the physical values ​​corresponding to the stored values ​​1 and 0 changes due to temperature fluctuations or charge loss over time. The reference values ​​used can also be dynamically adapted to the changing physical state of the memory cells.

[0163] Although the invention has been illustrated and described in detail by the at least one embodiment shown, the invention is not limited to this embodiment and other variations can be derived from it by a person skilled in the art without leaving the scope of protection of the invention.

Claims

[1] Method for determining a resulting data word when accessing memory cells of a memory comprising: (a) Reading a set of memory cells in a single read operation, (b) wherein a first data word and a second data word are determined from the set of memory cells read, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) where the first data word and the second data word represent the respective memory cell - assumes a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values ​​are larger and - assumes a second value if the first comparison with the first reference value and the second comparison with the second reference value show that both reference values ​​are smaller, (d) wherein the first data word and the second data word for the respective memory cell take on at least a third value if the conditions according to feature (c) are not met, (e) Determining the resulting data word based on the first data word or based on the second data word. [2] Method according to claim 1, wherein the at least one third value comprises a pair of binary values ​​that are different from each other. [3] Method according to any one of the preceding claims, - where the resulting data word is determined by the first data word, - if the first data word is a codeword of an error code or - if the first data word can be corrected using the error code, or - where the resulting data word is determined by the second data word, - if the second data word is a code word of the error code or - if the second data word can be corrected using the error code. [4] Method according to claim 3, wherein a predetermined action is performed if the error of the first data word or the second data word cannot be corrected by means of the error code. [5] A method according to any of the preceding claims, comprising - Performing a comparison with a third reference value that is different from the first and second reference values, - wherein the components of the first data word and the second data word are determined depending on comparisons with the first reference value, with the second reference value and with the third reference value. [6] A method according to any of the preceding claims, wherein, if the conditions according to feature (c) are not met, the first data word and the second data word for the respective memory cell assume at least the third value depending on a comparison with a further reference value. [7] Method according to any one of the preceding claims, - wherein a further data word is determined, wherein each memory cell is assigned a component of the further data word, - where the additional data word is a third data word, - where the first data word, the second data word and / or the third data word for the respective memory cell according to feature (c) take on the first value or the second value according to the conditions of feature (c), - where the first data word, the second data word and / or the third data word take on at least one third value if the conditions according to feature (c) are not met, - where the resulting data word is determined based on the first data word, the second data word, and the third data word. [8] Method according to claim 7, wherein a fourth data word is determined as a component-wise XOR operation of the first, second and third data word. [9] A method according to any of the preceding claims, wherein, during further reading of memory cells, at least one of the reference values ​​is not used depending on the previously determined errors. [10] Method according to any of the preceding claims, wherein different read-out memory cells or groups of memory cells are at least partially compared with different reference values. [11] Method according to any of the preceding claims, wherein the reading of the set of memory cells takes place after initialization or power-up. [12] Method according to any of the preceding claims, wherein the value read out per memory cell has a time dependency and is compared in a time domain with the at least one reference value. [13] Method according to any of the preceding claims, wherein the memory cells are classified with regard to their reliability by means of steps (c) and (d). [14] Device for determining a resulting data word when accessing memory cells of a memory, wherein the device is configured to perform the steps: (a) Reading a set of memory cells in a single read operation, (b) wherein a first data word and a second data word are determined from the set of memory cells read, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) where the first data word and the second data word represent the respective memory cell - assumes a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values ​​are larger and - assumes a second value if the first comparison with the first reference value and the second comparison with the second reference value show that both reference values ​​are smaller, (d) wherein the first data word and the second data word for the respective memory cell take on at least a third value if the conditions according to feature (c) are not met, (e) Determining the resulting data word based on the first data word or based on the second data word.

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