Multi-swipe decision forward eliminator with precursor and postcursor swipes and method for its operation

Abstract

Decision forward equalizer, exhibiting: multiple precursor taps configured to sample a received signal with different time delay measures; multiple postcursor taps configured to sample the received signal with different time delay measures; a cursor tap configured to sample the received signal; several preliminary decision separators configured to quantize outputs from the multiple precursor taps and multiple postcursor taps; and a summing element that is configured to combine scaled outputs provided by the multiple preliminary decision separator stages and the sampled signal received from the cursor tap.

Description

GENERAL STATE OF THE ART

[0001] Feed-forward equalizers (FFE) and decision-feedback equalizers (DFE) are among the most common equalizers used in state-of-the-art SerDes receivers to compensate for inter-symbol interference (ISI). Both equalizers have their respective advantages and disadvantages. FFE has the ability to correct both precursor and postcursor ISI, but also tends to amplify noise and crosstalk. DFE corrects postcursor ISI and does not amplify noise in the process, but it lacks the ability to correct precursor ISI. DFE is a powerful equalizer for postcursor ISI correction, but suffers from error propagation, whereas this is not the case with FFE.For DSP-based SerDes, a parallel data path for both of these equalizers is required, and FFE is well-suited for such implementations, whereas this is not the case for DFE, as its complexity increases exponentially with the number of taps. Although DFE is preferred over FFE due to its inherent ability not to amplify noise, it is not practical to implement it for post-eursor ISI correction beyond the first few taps. As such, most DSP SerDes receivers use multiple FFE taps to correct both precursor and post-eursor ISI, followed by only one or two DFE taps for post-eursor correction.

[0002] US 2015 / 0312056A1 relates to a receiver comprising a slicer with an input for receiving a sequence of symbols exhibiting intersymbol interference. The slicer determines a state associated with each symbol based on a threshold. A feedback equalization unit is coupled to the slicer to apply equalization to the symbol fed to the slicer input, based on previously acquired symbol states. A least-mean-squares unit works with the slicer and the feedback equalization unit to estimate a channel impulse response based on the equalized symbols. The least-mean-squares unit feeds the estimated channel impulse response into a maximum-likelihood sequence estimation unit to generate an estimated bit sequence based on the estimated channel impulse response.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a block diagram of a communication system according to examples in the present disclosure. Fig. Figure 2 shows a block diagram of a SerDes receiver architecture according to examples in the present disclosure. Fig. Figure 3 shows an example of a signal illustrating locked, early and late clock conditions according to examples in the present disclosure. Fig. Figures 4A-4C show an example of waveforms that identify precursor, cursor and postcursor positions, according to examples in the present disclosure. Fig. 5. shows a block diagram of a SerDes receiver architecture according to examples in the present disclosure. Fig. Figure 6 shows a block diagram of a forward equalizer (FFE) with m precursor and n postcursor taps according to examples in the present disclosure. Fig. Figures 7A-7B show block diagrams of a decision-feedback equalizer (DFE) according to examples in the present disclosure. Fig. Figure 8 shows a block diagram of a single-stage, multiple-tap decision feed forward equalizer (DFFE) according to examples in the present disclosure. Fig. Figure 9 shows a conceptual block diagram of a DFFE according to examples in the present disclosure. Fig. Figure 10 shows a conceptual block diagram of a two-stage DFFE according to examples in the present disclosure. Fig. Figure 11 shows a linear model of an ideal feedback equalizer according to examples in the present disclosure. Fig. Figure 12 shows a linear model of a DFFE according to examples in the present disclosure. Fig. Figure 13 shows a linear model of a two-stage DFFE according to examples in the present disclosure. Fig. Figure 14 shows a signal-stage DFFE for cascaded DFFEs according to examples in the present disclosure. Fig. Figure 15 shows a three-stage DFFE with DFE outputs as initial provisional decisions according to examples in the present disclosure. Fig. Figure 16 shows a three-stage DFFE according to examples in the present disclosure. Fig. Figure 17 shows a single-stage DFFE for a cascaded DFFE according to examples in the present disclosure. Fig. Figure 18 is a flowchart illustrating an example of a procedure according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described subsequently for the sake of simplicity. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not itself establish any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used here for simple description to convey the relationship of one element or feature to one or more other elements or features depicted in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used here can be interpreted accordingly.

[0007] The examples described here involve a digital signal processing serializer / deserializer receiver architecture (DSP-SerDes receiver architecture) that incorporates a decision forward equalizer (DFFE), and equalization and clock data acquisition modules (equalization and CDR modules) that are integrated with common auto-matching in such a way that the signal is optimally shaped for improved CDR and SerDes performance. SerDes is a device commonly used in high-speed communications to compensate for limited inputs and outputs. A SerDes device converts data between parallel interfaces and serial interfaces using one or more differential lines to transmit data from point A to point B.

[0008] Fig. Figure 1 shows a block diagram of a SerDes communication system 100 according to examples in the present disclosure. More precisely, the SerDes system 100 has a transmitter 104 which is communicatively coupled to a receiver 112 via a communication channel 108. The transmitter 104 is configured to send one or more signals to the receiver 112 through the communication channel 108. The transmitter 104 may have one or more limited pulse response filters for conditioning data before transmission to the communication channel 108. The communication channel 108 may be a physical transmission medium, such as a backplane, a drive head in a magnetic recording system, copper cables, optical fibers, one or more coaxial cables and / or wires, or the communication channel 108 may have one or more radio frequency channels (RF channels).Although a use in a SerDes communication system 100 is described here, examples of the present disclosure are not limited to this and some examples could be used in alternative communication systems that employ a transmitter and a receiver communicating over a communication channel. Moreover, it is clear that each “bit” of a signal has a corresponding logical value and that various signals described here may use multi-bit data symbols based on different data encoding schemes, such as pulse amplitude modulation (e.g., PAM-4).

[0009] The effect of inter-symbol interference (ISI) generally increases with increasing transmission speed on channel 108. ISI is a form of signal distortion where one symbol interferes with subsequent symbols. This is an undesirable phenomenon because the preceding symbols have a noise-like effect, thus making communication less reliable. That is, the propagation of a pulse representing one or more segments of communication over its allocated time interval causes it to interfere with neighboring pulses. ISI is commonly caused by multi-path propagation or the inherent linear or non-linear frequency response of a communication channel, which causes successive symbols to "blur." Therefore, the presence of ISI in a communication system can introduce errors that propagate to the receiver output.Therefore, a design of transmit and receive filters generally minimizes the effects of ISI and thus delivers digital data with the smallest possible error rate at its destination.

[0010] Conventional SerDes architectures are generally limited by the coupling problem between the CDR and equalization matching. If the CDR and equalization are both matched from a final equalized node, the pulse response is ideally flat due to equalization; however, such a flat pulse response makes it difficult for baud-rate CDRs, typically used in such architectures, to find a stable reference point, as multiple points on the pulse response satisfy the convergence criterion. To address this problem, the CDR and equalization are matched using different nodes, with the CDR using a partially equalized node. This may decouple the CDR and equalization to solve the fully equalized, joint matching problem, but the pulse response at the partially equalized CDR node may not be symmetrical, potentially resulting in a suboptimal CDR reference point.Even if the CDR convergence point is optimal relative to the partially equalized CDR node, it may not be optimal relative to the fully equalized final node. Therefore, traditional SerDes architectures typically require CDR reference point adjustment mechanisms to achieve better spans, increasing the overall complexity of the architecture. The CDR reference point and BER spans tend to be sensitive to transmitter settings because they play a significant role in determining the pulse response shape, making link tuning a much more challenging task. Furthermore, because DFE is not limited to postcursor ISI, equalization tends to be dominated by FFE, making it more sensitive to noise and crosstalk.Therefore, limitations in traditional SerDes architecture include, but are not limited to: the coupling between the CDR and equalization, leading to uncertain CDR convergence points; a pulse response that may not be symmetrical at the CDR node, resulting in a suboptimal CDR reference point; traditional SerDes architecture typically requires CDR reference point adjustments for better spans; link spans of traditional SerDes architectures are sensitive to transmitter settings, and link tuning tends to be a complex task.

[0011] Fig. Figure 2 shows an example of a SerDes receiver architecture 200 which has an equalization data path to provide both precursor and postcursor ISI correction through a combination of a forward equalizer (FFE), a decision-feedback equalizer (DFE), and a precursor-capable multiple tap. -To achieve a decision forward equalizer (DFFE). The SerDes receiver architecture 200 can be implemented in receiver 112 and can, as in Fig. Figure 2 illustrates an analog front end (AFE) 204 comprising one or more continuous-time linear equalizers (CTLE) 208 and variable-gain amplifiers (VGA) 212. Since a serial data channel tends to attenuate higher frequencies of a signal more than lower frequencies, the CTLE 208 is included to amplify high frequencies of a received signal 202, which is received by the SerDes receiver architecture 200, in order to bring most of the frequency components of the received signal 202 to a similar or equal amplitude. However, amplifying signal frequencies also amplifies fluctuations and noise. The VGA 212 can be included to variably amplify the signal amplitudes over most of the frequencies.Therefore, the AFE 204 generally minimizes ISI introduced by the combined characteristics of the transmitter and channel, such as ISI due to the impulse response of the channel, thereby reducing ISI at the receiver.

[0012] The AFE 204 can provide the equalized signal to the analog-to-digital converter (ADC) 216 to convert the received and equalized signal into a digital signal for subsequent digital signal processing by a digital signal processor (DSP) 218. The DSP can include, but is not limited to, an FFE 220, a clock data acquisition (CDR) adaptation 224, a DFE 228, a DFFE 232, and an equalization adaptation 236. More specifically, the CDR adaptation 224 can tap at an intermediate node in the equalization data path between the DFE 220 and the DFE 228 to reduce latency, resulting in improved fluctuation tracking performance. The joint adjustment (e.g. CDR adjustment 224 and equalization adjustment 236), which is implemented as part of the SerDes receiver architecture 200, resolves possible negative interaction mechanisms between CDR adjustment 224 and equalization adjustment 236.This means that the unique combination of equalization provided by the SerDes receiver architecture 200, together with the CDR matching 224, achieves a symmetrical pulse response at the CDR node that is optimal for Mueller-Muller baud-rate CDR. Mueller-Muller CDR, sometimes referred to as MM CDR, is a common and popular type of baud-rate CDR. Since MM CDR is typically sensitive to the shape of the pulse response, the proposed SerDes receiver architecture 200 addresses this limitation by using "pulse shapes" of the signal, so that it is symmetrical regardless of the actual channel pulse response. MM CDR also suffers from problems related to finding a stable reference point when locked on a fully equalized node, since any point on the pulse response can be a potential reference point.The proposed SerDes receiver architecture 200 addresses this problem by introducing a residual ISI that is symmetrical with the postcursor ISI of the first tap equal to the precursor ISI of the first tap. This guarantees a stable CDR convergence point with improved timing spans. The residual ISI is fully compensated by the final equalization stages and therefore has no effect on the final bit error rate (BER) of the fully equalized signal used for decision-making. Furthermore, the SerDes receiver architecture 200 exhibits improved performance in the presence of noise and crosstalk compared to a traditional FFE-dominant architecture due to the additional use of the DFFE 232 for both precursor and postcursor ISI correction.The SerDes receiver architecture 200, as presented here, achieves robust performance with BER improvement over traditional architectures over a wider range of transmitter settings, as it is largely insensitive to channel pulse response due to its CDR pulse-shaping capability.

[0013] Unlike traditional SerDes architectures, in the SerDes receiver architecture 200 the DFE 228 cannot be part of the main signal data path. That is, in the equalization data path 221, as in Fig. As shown in Figure 2, the signal equalized by the DFFE 232 is indeed the output of the FFE 220. The DFE 228 only provides an initial set of preliminary decisions, corresponding to the FFE 220 output, for the DFFE 232 to process. Therefore, the DFE 228 can be omitted in some implementations. The DFE 228 can be used to start with a good BER at the input of the DFFE 232. If the DFE 228 is bypassed, additional DFFE 228 stages, such as those shown in Figure 2, can be used. Fig. Figure 5 shows how it can be used to achieve a desired BER (Berlin Brandenburg Airport). In principle, the DFE 228 (Device Function Index) can be bypassed, and its use can be determined by balancing implementation costs.

[0014] Similar to the DFE 228, the FFE 220 can also be omitted in some embodiments. The FFE 220 provides additional pre-equalization, resulting in a starting signal with a better SNR, which provides a better BER for preliminary decisions, requiring fewer DFFE stages overall. The FFE 220 can amplify noise, which can be addressed by completely removing the FFE 220; however, additional DFFE stage(s) can be used to achieve a desired BER if the FFE 220 is not included in Architecture 200.

[0015] According to examples in the present disclosure, the SerDes receiver architecture 200, which is described in Fig. The FFE-228 node is provided for CDR, or it uses it for this purpose, which has the advantage of providing sufficient equalization to reduce CDR noise and lower latency to improve fluctuation tracking. Therefore, the CDR adjustment 224 is, in principle, decoupled from the equalization adjustment 236, as they are accessed from different nodes; that is, the CDR adjustment 224 uses the FFE 220, while the equalization adjustment 236 uses the DFFE 236. Therefore, the SerDes receiver architecture 200 has the ability to adjust precursor and postcursor ISI correction at both the CDR FFE intermediate node, for example, the FFE node 220, and the final equalized DFFE node, for example, the DFFE node 232.As described later, this implementation provides the flexibility to form a symmetrical pulse response at the CDR node 224, independent of the transmitter settings, utilizing residual ISI from both precursor and postcursor taps 220, 232, which are fully compensated by subsequent DFFE stages. Since the SerDes receiver architecture 200 uses a multi-tap DFFE 232 topology with precursor taps, precursor ISI can be used together with postcursor ISI at the CDR node 224, resulting in a symmetrical pulse response optimized for MM-CDR.

[0016] The DFFE 232 removes residual ISI present at the CDR node 224, as it has the capability to correct both precursor and postcursor ISI. Furthermore, since significant signal equalization occurs after the FFE 228 with preliminary decisions based on the DFFE 232, the SerDes receiver architecture 200 is non-FFE-dominant and exhibits better performance in the presence of noise and crosstalk than a traditional FFE-dominant architecture. Robust performance is observed, with orders of magnitude of BER improvement over traditional architectures due to the factors mentioned above.In summary, the SerDes receiver architecture can improve 200 pulse shapes for MM-CDR; reduce latency and improve fluctuation tracking resulting from CDR tapping from an intermediate node in the equalization data path; reduce and / or eliminate coupling problems between CDR matching and equalization matching; provide a wider operating range of SerDes settings; do not require a special CDR reference point setting; improve crosstalk performance over FFE-dominant SerDes architectures; and provide robust performance while improving BER compared to traditional SerDes architectures.

[0017] The CDR pulse shaping features achieved via the SerDes receiver architecture 200 discussed above are described with reference to Fig. 3-4C is illustrated in more detail. According to the present disclosure, references to MM CDR and baud-rate CDR are to be understood as references to the phase error detector (PED) used in a CDR loop 224, and not to the entire signal processing loop as a whole. For example, a PED can compare a phase between input data and a recovered clock and provide information to set a sampling clock phase. While the present disclosure focuses primarily on MM-CDR, details discussed here can be generalized to other baud-rate CDRs, as they share similar convergence properties.

[0018] MM CDR clock recovery can be explained using a pulse response, as in Fig. Figure 3 shows the first precursor (304), the main cursor (308), and the first postcursor (312). Fig. 3 by h(τk - Tb), h(τk), and h(τk + Tb), which can also be denoted as h-1, ho, and h1, respectively, using a simpler notation. The clock phase conditions can be written as h-1 = h1 (offset condition); h-1 < h1 (early condition); and h-1 > h1 (late condition). An optimal scenario for MM CDR is to offset at the peak of the pulse response, ho, and since the offset condition is given by h-1 = h1, an optimal pulse response at the CDR node is a symmetric pulse response with an initial condition h-1 = h1. For a specific asymmetric pulse, as in Fig. 4A with an initial h-1 < h1 and Fig. As shown in 4B with an initial h-1 > h1, the CDR locks later or earlier than the determined peak of the response to ensure that residual h-1 = h1 results in a lower ho after CDR convergence, ultimately leading to smaller spans.

[0019] For an ideal square wave pulse response with h-1 = h1 = 0, as in Fig. As shown in Figure 4C, MM CDR has an unstable point of reference, since every point on the peak of the pulse response is a possible convergence point. This is due to the fact that even if CDR moves early or late, the CDR convergence criterion is satisfied as long as the CDR samples the peak of the pulse response. MM CDR can, in principle, be viewed as a peak detector, similar to other baud-rate CDRs; however, since a square-wave pulse response has multiple peaks, it is not actually an optimal pulse response for MM CDR, although fluctuation and noise can lead to a wide-open eye. Such a scenario can occur when a fully equalized node is sampled with MM CDR. Thus, an ideal node for MM CDR has partial equalization with residual h⁻¹ = h⁻¹.

[0020] Fig. Figure 5 shows a SerDes receiver architecture 500, which incorporates further aspects of the SerDes receiver architecture 218. Fig. 2 illustrated according to examples in the present disclosure. The SerDes receiver architecture 500 can initially receive a digital signal yk from an ADC, such as the ADC 216. The digital signal yk can be provided to an FFE 502, where the FFE 502 can be a limited impulse response (FIR) filter capable of correcting both precursor ISI and postcursor ISI. From the FFE 502, a precursor ISI and postcursor ISI-corrected signal can proceed to a transition 504, where it can be combined with a compensated postcursor ISI signal provided by a preliminary decision separator 506 and DFE FIR 508 to generate a further compensation signal. The signal that is provided to and equalized by the DFFE, such as the DFFE 510, can be the output of an FFE, such as the FFE 502.The DFE FIR 508 provides an initial set of preliminary decisions from the Preliminary Decision Separator Stage 506, corresponding to the FFE 502 output, for processing by the DFFE 510. The DFE FIR 508 can be used to provide an initial BER at the input of the DFFE 510. In some cases, the DFE 508 may be bypassed or otherwise not used; in such cases, additional DFFE 510 stages, such as DFFE 512 or DFFE 514, may be implemented to achieve a desired BER at the final output.

[0021] From the multi-state, multi-tap DFFEs 510-514, a fault at transition 516 can be determined based on setpoints 518. While DFFEs 510-514 in Fig. As illustrated in point 5, more or fewer DFFEs can be used. As further as shown in... Fig. As described in more detail in section 5, one or more LMS least squares coefficients 520 can be derived from the error and data can be provided by the DFFE 514; the one or more LMS coefficients 520 can be provided back to any of the DFFEs 510-514. Furthermore, LMS coefficients 522 and / or 524 can be provided to the DFFE FIR 508 and FFE 502. A CDR adjustment can occur at 528 and can be provided back to the ADC, such as ADC 216. Additional details of a DFFE are described in [reference missing]. Fig. 9-10 provided according to examples from the present revelation.

[0022] Fig. Section 6 provides additional details of an example of the FFE 502 according to examples in the present disclosure. More specifically, the FFE 502 can be a limited impulse response (FIR) filter that corrects both precursor ISI and postcursor ISI. As in Fig. Figure 6 shows a block diagram illustrating an FFE for a symbol with 'm' precursor taps (602A-602D) and 'n' postcursor taps (604A-604D), as well as multiple unit delays 606. The unit delays 606, for example z-1, required for an FFE implementation, can be implemented within the digital domain of a DSP SerDes architecture, such as the SerDes Receiver Architecture 200. While the FFE can provide high frequency gain to compensate for channel loss, correct both precursor ISI and postcursor ISI, and provide a parallel data path implementation, the FFE can also amplify crosstalk and noise and be prohibitively expensive to implement if multiple taps are required. However, the FFE 502 can provide an initial signal to the CDR and subsequent equalization stages.An initial signal, xk, can be input if one or more precursor signal components, derived from the precursor taps 602A-602D and delayed, for example, by z-1, and one or more postcursor signal components, derived from the postcursor taps 604A-604D and delayed, for example, by z-1, can be supplied to a summing component 608. The FFE 502 can output the signal x_ffek.

[0023] Fig. Sections 7A-7C show additional details of DFE implementations according to DFE 508, Decision Separation Stage 506 and Transition 204, as in Fig. Figure 5 shows examples from the present disclosure. More precisely, a DFE, such as DFE 508, is a filter that can use feedback of detected symbols to generate an estimate of an output, such as a channel output. Detected symbols are input into the DFE, such as DFE 508, so that the DFE generates an output that can be subtracted from the output of a linear equalizer, if one is present. The DFE, such as DFE 508, can perform postcursor ISI, as shown in Figure 5. Fig. Figure 4B shows, for example, that by including an FIR filter in a feedback loop, DFE can correct actual decisions from a decision separation stage. Because DFE uses past decisions in a feedback path, it can only correct postcursor ISI associated with these symbols. DFE has no ability to correct precursor ISI, as this would require knowledge of future samples.

[0024] Fig. Figure 7A illustrates a block diagram of a DFE in a 'direct feedback' configuration. That is, a signal yk can be supplied to a summing transition 702; the signal resulting from the summing transition 702 is supplied to the decision separator 704, where the decision separator 704 makes a symbolic decision. The decision separator 704 quantizes the input so that the ISI can be directly subtracted from the incoming signal yk via the feedback FIR filter 706.

[0025] Some DFE topologies speculatively pre-compute decisions and select one of the pre-computed decisions based on past symbols to eliminate the feedback path at decision separation stage 704. For example, a block diagram of a speculative 1-tap DFE in Fig. 7B for NRZ signaling and Fig. 7C illustrates PAM4 signaling. The speculative 1-tap DFE, which is shown in Fig. As illustrated in Figure 7B, it features summing transitions 708 and 710, decision separation stages 712 and 714, a multiplexer 716, and a latch or flip-flop 718. The number of separation stages for 1-tap DFE can be doubled for PAM4 via NRZ along with changing the associated multiplexer from 2-to-1 to 4-to-1, as shown in Figure 7B. Fig. 7C shown. That is, the number of separation stages 720, which is fed by inputs 722, can be compared to the NRZ signaling of Fig. 7B is doubled, which requires a multiplexer 724 with additional inputs to provide a selected signal to the flip-flop 726.

[0026] Based on examples from the present disclosure, a configuration of iterative decision forward equalizers that uses preliminary decisions is presented here. This configuration is less complex to implement than multi-sniff DFEs and achieves both multi-sniff precursor and postcursor ISI correction. Preliminary decisions can be used so that multiple iterations improve the quality of the preliminary decisions.

[0027] Fig. Figure 8 illustrates further aspects of a DFFE, such as the DFFE 510 from Fig. 5, according to some examples. In particular, it shows Fig. 8 an iteration base stage of a multi-tap DFFE configuration 800 with 'm' precursor and 'n' postcursor taps. The in Fig. The multi-tap DFFE configuration shown in Figure 8 is not subject to noise amplification or crosstalk as is the case with FFE, because DFFE uses decision outputs from separator stages as inputs to the FIR, unlike FFE, which uses actual analog signal inputs. The digital outputs of the preliminary decision separator stages are multiplied by the tap coefficients to reduce a significant amount of noise. Furthermore, since digital outputs are used as inputs to the multiplier, the multipliers essentially become adders, which tend to be easier to implement. More precisely, a signal xk can be input into precursor taps 804A-C, the cursor tap 804D, and the postcursor taps 804E-H (collectively taps 804) and can be delayed at each tap 804 by a measure z-1, as shown in delay elements 806. Each of the taps 804 is then fed into a preliminary decision separation stage 808.Each output of the preliminary decision separator 808 can be provided to multipliers 812, where each multiplier 812 multiplies the result of the preliminary decision separator 808 by a coefficient. For example, the preliminary decision separator 808 can quantize the sampled input from the filter taps 804A-804H, where the quantized value can be scaled by a filter tap coefficient provided by the multipliers 812. Each output of the multipliers 812 can be provided to an adder or combiner 816, where each output is effectively subtracted from the cursor tap 804D, providing an output that is precursor- and postcursor ISI-compensated.

[0028] The mathematical block diagram of a single-stage DFFE 902, corresponding to the example DFFE 510 from Fig. 5, is in Fig. Figure 9 illustrates this. As mentioned earlier, the decisions at the output of the first separation stage 904 are only preliminary. These decisions are then used in the FIR filter 906 to equalize the signal at the transition 908, which is then fed into the next separation stages, such as separation stage 910. The bit error rate (BER) of the decisions of the final stage, such as 910, can be shown to be lower or better than the BER of the preliminary decisions of the previous stage, such as 904. This property of DFFE can be used to cascade multiple stages and lower the BER to the desired value with each subsequent iteration. The lower the initial BER, the fewer stages of DFFE are required. Furthermore, because decisions are preliminary and are used as inputs in the forward path, as opposed to the feedback path of DFE, DFFE does not suffer from error propagation.More importantly, the complexity of the DFFE scales linearly with the number of taps, making it possible to implement multi-tap DFFE for both precursor and postcursor ISI in a DSP SerDes architecture. This allows for the implementation of higher-order floating taps to handle non-ideal channel behavior such as reflections. Advantages of DFFE include ISI cancellation without amplifying crosstalk or noise; implementation complexity that scales linearly with the number of taps; a parallel data-path DSP implementation; reduced or no error propagation, as exhibited by a DFE; reduced or no critical feedback path clocking challenges, as observed in DFEs; and the ability to replace FFE multipliers with adders in DFFE.

[0029] It can be shown that the quality of decisions at the initial separation stages, such as initial separation stage 910, is better than the quality of preliminary decisions at a preceding stage of separation stages, for example, preliminary decisions from decision separation stage 904. The reason is that if the separation stages of the first stage, such as separation stage 904, make the correct preliminary decisions, the separation stages of the initial stage, such as separation stage 910, will also make the correct decisions with a wider margin of error. However, if the preliminary decisions, for example from separation stage 904, are incorrect, separation stages of the initial stage, such as separation stage 910, do not always make incorrect decisions.This means that the final-stage decisions can be correct even if the preliminary decisions are flawed, because incorrect preliminary decisions can, in some cases, provide helpful ISI compensation, even if they are technically incorrect. The reason is that ISI is indeed helpful when there are no transitions in the data structure. For example, for a data structure of D. k-1 = D k improves the ISI of a D k-1 Symbol the signal levels for detecting a D k Symbols. Furthermore, if D k-1 If such a structure is faulty, ISI compensation helps in accordance with the incorrect D. k-1 during the restoration of the signal for the D k Symbol. For example, a simplified analysis is provided below:

[0030] Assume NRZ data transmission on a channel whose pulse response has a main cursor h0 and a first tap post-cursor h1. The signal level, X k , according to the D k The bit is provided in equation 1. Xk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)

[0031] The output signal level, Y k , according to the D k Bit after ISI compensation with correct detection of D k-1 is given by equation 2: Yk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)−h1⋅sgn(Dk−1) =>Yk=h0⋅sgn(Dk)

[0032] However, if there is an error in the detection of D k-1 The signal level, Y, is present. k , according to the D k Bit after ISI compensation with an incorrect preliminary decision given by equation 3: Yk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)−h1⋅sgn(Dk−1) =>Yk=h0⋅sgn(Dk)+2h1⋅sgn(Dk−1)

[0033] But if D k-1 = Dk , the signal level, Y k , following an incorrect preliminary decision by D k-1 actually positive for the correct detection of D k Bit restored as given by equation 4: Yk=h0⋅sgn(Dk)+2h1⋅sgn(Dk) =>Yk=(h0+2h1)⋅sgn(Dk)

[0034] It is therefore evident that there is a lower probability of error if the previous decision is incorrect. By extending the above analysis, we can conclude that in the DFFE topology, as in Fig. 8 and Fig. 9 shown, the BER of separation stages of the final stage, Dk1, is lower than the BER of the separation stages of the initial stage, Dk0.

[0035] The probability of error detection can be expressed as: Pe(Dk1)=Pe(Dk0)⋅Pe(Dk1,Dk0|e=1) where Pe(Dk1) for the probability of an error in Dk1 D k stands and Pe(Dk1,Dk0|e=1) for the probability of an error in Dk1 This appears when there is an error in Dk0 The equation above shows that Pe(Dk1)<Pe(Dk0)=> BER(Dk1) <BER(Dk0). This property of DFFE can be used to cascade multiple DFFE stages and progressively reduce the BER of each iteration until the desired BER value is reached, or until a stage is reached where no further BER reduction is possible because SNR is limited by noise and not ISI. A block diagram for a 2-stage DFFE 1002 is shown in Fig. Figure 10 shows that a first stage 1004 can have a preliminary decision separator 1006, which provides a preliminary decision to a first FIR filter 1008. An equalized signal from the first transition 1010 can be provided to the second stage 1012, which has a decision separator 1014 that can be considered a preliminary decision separator. The quantized decisions from the decision separator 1014 can be provided to a second FIR filter 1016. The equalized signal resulting from the second transition 1018 can be provided to the decision separator 1020.

[0036] The BER ratios of each level can be specified as follows. BER(Dk2) <BER(Dk1)<BER(Dk0)

[0037] The equation above can be generalized and extended to several levels.

[0038] According to examples in the present disclosure, decision separation stages, such as decision separation stages 904 and / or 910, are not inherently linear, but based on some simplifying assumptions, a linear model can be constructed for the purpose of analysis. A possible disadvantage of using decision separation stages, such as decision separation stages 904 and / or 910, is that they prevent noise from passing through, and therefore the separation stage can be considered an open circuit for noise analysis. It is evident that there is no noise amplification due to the use of separation stages in the FIR, and thus the case of signal equalization can be assumed for this analysis.

[0039] In a fully equalized case, the signal levels before and after the isolation stages are at their corresponding logical amplitude values. Therefore, the isolation stage can be considered a short circuit in such cases. More precisely, a scaling factor α can be used; but for the purpose of this analysis, α = 1.

[0040] Assuming an ideal feedback equalizer with 'm' precursor and 'n' postcursor taps, the equation for such an equalizer is given by equation 7: yk=xk−∑i=−mi=nhi⋅Dk−i,i≠k

[0041] This is similar to a DFE, except that the equation above also includes precursor tap correction, while DFE is limited to postcursor ISI correction. It must also be noted that there is no practical way to implement the equalizer above, as it requires the use of future symbols. This analysis simply serves to compare the performance of DFFE with such an ideal equalizer.

[0042] Therefore, a linearized model for such an ideal feedback equalizer is shown in the figures. The FIR 1102 in the feedback path of this ideal equalizer is similar to the one in [Figure 1]. Fig. 5 and Fig. 7A shown FIR and is given by equation 8: FIR=∑i=−mi=nhi⋅z−i+m,i≠0

[0043] The transfer function of this ideal equalizer, Ideal_Feedback_Eq(z), then follows from the linear model of Fig. 7A, as shown below in equation 9: Ideal_Feedback_Eq(z)=1 / (1+FIR)

[0044] Using a Taylor series expansion, the equation above can be expressed as Equation 10: Ideal_Feedback_Eq(z)=1−FIR+FIR2−FIR3+FIR4

[0045] Now, considering the linearized model of DFFE (such as the DFFE 510 from Fig. 5), which in Fig. As shown in Figure 12, the transfer function of DFFE, DFFE(z), can be given as DFFE(z) = 1 - FIR. Therefore, the DFFE transfer function lacks the higher-order terms of the ideal equalizer. However, by cascading multiple DFFE stages, any higher-order term can be achieved with each additional iteration. For example, a linearized model of a 2-stage DFFE, as shown in Figure 12, exhibits the following characteristics: Fig. Figure 13 shows a first stage 1302 and a second stage 1304. The transfer function of a 2-stage DFFE, DFFE2(z), is given by equation 11: DFFE2(z)=1−FIR⋅(1−FIR) =>DFFE2(z)=1−FIR+FIR2

[0046] Similarly, the transfer function of a 3-stage DFFE, DFFE, DFFE2(z), is given by equation 12: DFFE3(z)=1−FIR⋅(1−FIR+FIR2) =>DFFE3(z)=1−FIR+FIR2−FIR3

[0047] The analysis can be extended to show that in higher-order terms, an ideal equalizer can be implemented by adding appropriate stages of DFFE. For practical applications with a reasonable output SNR, the DFFE can achieve the same performance as an ideal feedback equalizer, even with precursor taps, within the first few iterations. However, one advantage of DFFE is that, while the ideal feedback equalizer is not implementable, DFFE is easy to implement, even with the inclusion of precursor taps.

[0048] DFFE, like the DFFE 510 from Fig. 5 is an iterative equalizer that can be cascaded multiple times to create a higher-order DFFE. To build a higher-order multi-tap DFFE, the multi-tap DFFE can be placed inside a single-stage DFFE, such as the one known as DFFE 800 in Fig. Figure 8 is shown and can be modified to fit the DFFE 1400 as shown in Fig. Figure 14 illustrates this by separating cursor path 1402 from precursor picks 1404 and postcursor picks 1406. Therefore, the cursor is provided by cursor path 1402 unchanged at each subsequent stage compared to the previous stage. For example, cursor path 1402 may be provided at the first stage 1504, the second stage 1508, and the third stage 1512. Back to Fig. 14. The precursor taps 1404 and postcursor taps 1406 can be provided at the preliminary decision separation stages 1408 of the current DFFE, scaled, and summed at transition 1410 to be provided as a single output. As in Fig. As shown in Figure 15, output 1506 from the first stage 1504 is provided at the second stage 1508, and output 1510 from the second stage 1508 is provided at the third stage 1512. Thus, by cascading three single-stage DFFE modules, as shown in Figure 15, the following can be achieved: Fig. As shown in Figure 15, a third-order DFFE can be realized.

[0049] The number of required DFFE stages can be a function of the BER of the initial decisions. The better the BER at the beginning, the fewer DFFE stages may be required. To improve the quality of the initial preliminary decisions, DFFE separation stage outputs can be used instead of raw separation stage outputs, which are found in Fig. 14 and Fig. 15 are shown. That is, a 3-stage DFFE 1600, as shown in Fig. As shown in Figure 16, DFE outputs 1602 are used as initial preliminary decisions in the first stage 1604. To accommodate the DFE separation stage outputs 1602, the single-stage DFFEs 1604, 1608, and 1612 were modified to take decisions as inputs using separation stages external to the DFFEs 1604, 1608, and 1612. The use of this cascaded DFFE configuration, such as the 3-stage DFFE 1600 as shown, not only eliminates residual ISI but also enables optimized pulse shapes for MM CDR, resulting in robust performance with less sensitivity to SerDes tuning. Therefore, one stage of the DFFE 1600, such as the DFFE 1604, 1608, and / or 1612, can be considered a DFFE 1700 in Fig. Figure 17 shows the DFFE 1700. The DFFE 1700 is the successor to the DFFE 1400. Fig. 14 is similar, but differs in that the decision separation stages 1408 of the DFFE 1400 are not included in the DFFE 1700. That is, decision separation stages, such as decision separation stages 1606 and 1610, are external to the DFFE 1604 and 1608 respectively, as in Fig. Figure 16 shows that the DFFE 1700 still separates the cursor path 1702 from the precursor taps 1704 and postcursor taps 1706.

[0050] One of the biggest challenges in integrating MM CDR with equalization blocks in SerDes is determining a common matching solution that resolves unwanted coupling mechanisms between the CDR and the equalization matching. The proposed SerDes Receiver Architecture 500, with its unique combination of CDR, equalization, and common matching, not only resolves any unwanted coupling between the CDR and the equalization matching, but the architecture also shapes the pulse response at the CDR node in such a way that it is optimal for both MM CDR and the entire SerDes span.

[0051] The adjustment of equalization blocks such as FFE, DFE, and DFFE is typically performed using the least-squares (LMS) algorithm, which minimizes the signal's error power relative to the equalized signal target levels. The objective of adjusting equalization tap coefficients is to eliminate any residual ISI at these tap positions. This discussion focuses on h-1 and h1, the first precursor tap ISI and first postcursor tap ISI, respectively, since MM CDR is predominantly affected by these. The stop condition for MM CDR is given by h-1 = h1. The MM CDR PED, mentioned here only for completeness, is implemented using the signal-level y(k)-based PED equation from Equation 13: (k−1)⋅[k]−(k)⋅[k−1] or error e(k) based PED equation of equation 14: [k−1]⋅[k]−[k]⋅[k−1] implemented.

[0052] To address coupling problems between CDR and equalization, various techniques have been used in the past, such as introducing residual ISI at the CDR node; however, such techniques affect the cost of impacting overall spans and the tuning complexity of determining how much residual ISI to introduce. The proposed SerDes Receiver Architecture 500 addresses these coupling problems by tapping CDR from an intermediate node in the equalization data path and subsequent equalization stages that compensate for both precursor and postcursor ISI. For example, referring again to Fig. In step 5, the CDR 526 is tapped between FFE 502 and junction 504, while the equalization stages, DFFE 510, DFFE 512, and DFFE 514, compensate for both precursor and postcursor ISI. Coupled with the ability to add or subtract ISI at both CDR 526 and the final equalized node, this provides a pulse response at CDR node 526 in a manner that is optimal for MM CDR but without residual ISI at the final equalized node.

[0053] Attributes of the proposed SerDes receiver architecture, which ensure optimized CDR pulse shapes, are summarized below. Specifically, the CDR is tapped, for example, from FFE node 526, followed by one or more DFFEs, such as DFFEs 510, 512, and 514, with the capability to compensate for both precursor ISI (h-1) and postcursor ISI (h1), so that MM CDR PED is used with a convergence condition of h-1 = h1. Furthermore, matching is driven by the final equalized node; that is, LMS matching is used to drive both the FFE and DFFE equalization.For example, as ISI is minimized at the FFE node using, for example, the LMS coefficients 524, the pulse response becomes more symmetrical to drive MM CDR towards a better convergence point; as the DFFE matching runs in parallel – providing, for example, LMS coefficients at DFFEs 510, 512, and 514 – the multi-stage DFFE eliminates residual ISI observed at CDR node 526, which is symmetrical in the sense of h-1 and h1 due to MM CDR matching; and the net result is a symmetrical pulse response at CDR node 526, which is nearly optimal for MM CDR, but without the downside of residual ISI at the final equalized node.

[0054] For reliable convergence, the matching loop gain of CDR is typically set higher than that of FFE, which in turn is set higher than that of DFFE. Additional details of the CDR pulse-shaping mechanisms, as highlighted above, are explained below.

[0055] Equalization is shared between FFE and DFFE, with an adjustment that drives both of their LMS coefficients, for example, such that the final ISI at the DFFE node is zero. That is, => h-1(DFFE) = 0, h1(DFFE) = 0 → driven by LMS adjustment.

[0056] This ensures that residual ISI exists at the FFE node, which also happens to be the CDR node. The magnitude of the residual ISI at FFE node 502 depends on the fitted FFE coefficients 524 and DFFE coefficients 520, which in turn are determined by the relative loop gains of an FFE and DFFE fit. With non-zero DFFE coefficients and a final ISI of zero, residual ISI may exist at FFE node 502, which the DFFE has compensated for. That is, => h-1(FFE) ≠ 0, h1(FFE) ≠ 0 → due to DFFZ shared fitting.

[0057] Since MM CDR adapts in parallel, a stop condition occurs at CDR node 526 where h-1 = h1. This means that => h-1(FFE) = h1(FFE) → driven by MM CDR

[0058] Therefore, there is a symmetrical pulse response with non-zero ISI at FFE node 502 or CDR node 526, which is ensured by the joint matching of MM CDR, FFE, and DFFE. That is, => h-1(FFE) = h1(FFE) ≠ 0 → driven by joint matching of NINI CDR, FFE, and DFFE.

[0059] This is an optimal condition for MM CDR. Even if the pulse response is asymmetrical before matching, the system converges with ISI being injected or removed at both the FFE node 502 (which is the CDR node 526) and the DFFE node (which is the final equalized node) such that there is a symmetrical pulse response with a non-zero ISI at the CDR node 526. In some cases, ISI is injected at the FFE node 502 to make the pulse response symmetrical and obtain an overall ISI of zero.

[0060] The symmetrical CDR pulse shapes can be effectively used to simplify matching and accelerate overall system convergence by forcing h-1 and h1 DFFE coefficients to be equal, and only one of them being matched or fixed.

[0061] The advantage of this CDR pulse-shaping procedure over previous CDR tuning mechanisms using residual ISI is that residual ISI at CDR node 526 is completely compensated by the subsequent DFFE stages 510, 512, and 514 with little or no effect on the overall BER. Furthermore, the residual ISI is introduced symmetrically with h-1 = h1, which is optimal for MM CDR. Because the pulse response is largely symmetrical, regardless of the extent of residual ISI at CDR node 526, CDR locks near the peak of the pulse response and is less sensitive to converged values ​​determined by the relative matching loop gains.

[0062] Another advantage is having a symmetrical pulse response at CDR node 526. The CDR reference point is determined by the pulse response at CDR node 526, and as such, even if the CDR node locks at an optimal point relative to the eye at CDR node 526, it is not necessarily optimal relative to the eye at the fully equalized node, for example, the output of DFFE 514. This may reduce time intervals at the fully equalized node, for example, the output of DFFE 514, even if the ISI is fully compensated. However, with a symmetrical pulse response at the partially equalized CDR node 526, the optimal CDR reference point, as determined by the partially equalized eye, tends to be quite close to the optimal reference point relative to the fully equalized eye.This is because when the partially corrected eye is superimposed on a fully corrected eye, the zero crossing points are the same. This can be deduced from a simplified analysis as shown below.

[0063] For a fully equalized eye, the zero crossing point is at half the UI point before or after the tip of the eye. For the partially equalized signal with a symmetrical pulse response, the pulse response value at half the UI point before the tip for the 0 → 1 transition can be approximated as shown in Equation 15: p0.5=h−0.5−h0.5(for 0→1 transition) where p0.5 is the signal value at half the UI point before the pulse peak, h-0.5 is half the UI precursor ISI value, and h0.5 is half the UI postcursor ISI value. For a symmetrical pulse response, we can assume h-0.5 equals ho.5. Therefore, as provided by Equation 16, p0.5=h−0.5−h0.5=0 (for 0→1 transition). Likewise, p0,5 = -h-0,5 + h0,5 = 0 (for → 1 transition).

[0064] Based on the equations above, the zero-crossing points for the partially corrected eye and the fully corrected eye lie in the same location when superimposed. Therefore, the optimal CDR reference points are similar for both eyes. This analysis is based on the simplified assumption that there is no ISI effect beyond the initial precursor and postcursor taps. However, since these are dominant ISI terms and CDR is primarily influenced by them, the conclusions remain valid.

[0065] While the least squares (LMS) based fitting is disclosed here, and while some embodiments may refer to the least squares (LMS) coefficients, coefficients may be derived by other means within the scope of the disclosure.

[0066] Fig. Figure 18 is a flowchart illustrating a method for generating data from an input signal received from a channel, according to some embodiments. The method could be compared with the one described in Fig. The SerDes receiver architecture 500 shown in section 5 can be implemented, although the illustrated procedure is applicable to other architectures. With reference to Fig. 5 in conjunction with Fig. In step 1810, samples are generated from the input signal using a sampling module implemented by the FFE 502. In step 1812, a preliminary decision separator 506 is applied to each of the generated samples, and the output of the preliminary decision separator is processed with one or more filter coefficients by one or more DFFEs 510, 512, 514 in step 1814. In step 1816, the resulting output from the filter sampling operation is combined at a summing transition 516.

[0067] In one example, a decision forward equalizer (DFFE) is provided. The DFFE can have multiple precursor taps configured to sample a received signal at various time delay measures, multiple postcursor taps configured to sample the received signal at various time delay measures, and a cursor tap configured to sample the received signal. Furthermore, the DFFE can have multiple preliminary decision separators configured to quantize outputs from the multiple precursor taps and multiple postcursor taps, and a summing element configured to combine scaled outputs provided by the multiple preliminary decision separators and the sampled signal received from the cursor tap.

[0068] In another example, a serializer / deserializer receiver is provided that includes a decision forward equalizer (DFFE). The DFFE can have multiple precursor taps, including a first precursor tap configured to sample a received signal and a second precursor tap configured to sample the received signal with a first delay. The DFFE can also include a cursor tap configured to sample the received signal with a second delay and multiple postcursor taps. The multiple postcursor taps include a first postcursor tap configured to sample the received signal with a third delay and a second postcursor tap configured to sample the received signal with a fourth delay.The DFFE can additionally include multiple preliminary decision separators, comprising a first preliminary decision separator configured to receive the sampled signal from the first precursor tap and provide a first quantized output to a first multiplier, a second preliminary decision separator configured to receive the sampled signal from the second precursor tap and provide a second quantized output to a second multiplier, a third preliminary decision separator configured to receive the sampled signal from the first postcursor tap and provide a third quantized output to a third multiplier, and a fourth preliminary decision separator configured to receive the sampled signal from the second postcursor tap and provide a fourth quantized output to a fourth multiplier.The DFFE can also include a summing element configured to subtract outputs from each of the first multiplier, second multiplier, third multiplier, and fourth multiplier from the sampled signal provided by the cursor tap, and to provide the difference as an equalized output signal.

[0069] In another example, a method for generating data from an input signal received by a channel is provided. The method may include generating samples from the input signal using a sampling module, applying a preliminary decision separation stage to each of the generated samples, processing the output of the preliminary decision separation stage using one or more filter coefficients, and combining the resulting output from the filter tap operations.

Claims

[1] Decision forward equalizer, exhibiting: multiple precursor taps configured to sample a received signal with different time delay measures; multiple postcursor taps configured to sample the received signal with different time delay measures; a cursor tap configured to sample the received signal; several preliminary decision separators configured to quantize outputs from the multiple precursor taps and multiple postcursor taps; and a summing element that is configured to combine scaled outputs provided by the multiple preliminary decision separator stages and the sampled signal received from the cursor tap. [2] Decision forward equalizer according to claim 1, wherein the received signal is an unequalized signal. [3] Decision forward equalizer according to claim 1, wherein the received signal is received by a forward equalizer. [4] Decision forward equalizer according to any of the preceding claims, wherein the difference provided by the summing element is an equalized signal. [5] Decision forward equalizer according to claim 4, further comprising: several second precursor taps configured to sample the equalized signal; several second postcursor taps configured to sample the equalized signal; a cursor tap configured to sample the equalized signal; several second preliminary decision separators configured to quantize outputs from the second multiple precursor taps and second multiple postcursor taps; and to combine a second summing element that is configured, scaled outputs provided by the second multiple preliminary decision separator stages, and the sampled equalized signal provided by the cursor tap. [6] Decision forward equalizer according to claim 5, wherein the output of the second summing element has a bit error rate that is smaller than the output of the first summing element. [7] Decision forward equalizer according to any of the preceding claims, wherein a number of postcursor taps is greater than a number of precursor taps. [8] Serializer / deserializer receiver comprising a decision forward equalizer, comprising a decision forward equalizer: multiple precursor taps, showing: a first precursor tap configured to sample a received signal, and a second precursor tap configured to sample the received signal with a first delay measure; a cursor tap configured to sample the received signal with a second delay measure; multiple postcursor taps, showing: a first postcursor tap configured to sample the received signal with a third delay measure, and a second postcursor tap configured to sample the received signal with a fourth delay measure; Several preliminary decision separation stages, exhibiting: a first preliminary decision separator stage configured to receive the sampled signal from the first precursor tap and provide a first quantized output to a first multiplier; a second preliminary decision separator stage configured to receive the sampled signal from the second precursor tap and provide a second quantized output to a second multiplier; a third preliminary decision separator stage configured to receive the sampled signal from the first postcursor tap and provide a third quantized output to a third multiplier; a fourth preliminary decision separator stage configured to receive the sampled signal from the second postcursor tap and provide a fourth quantized output to a fourth multiplier; and a summing element configured to subtract outputs from each of the first multiplier, second multiplier, third multiplier, and fourth multiplier from the sampled signal provided by the cursor tap, and to provide the difference as an equalized output signal. [9] Serializer / Deserializer receiver according to claim 8, wherein the first multiplier multiplies the first quantized output by a first coefficient, wherein the second multiplier multiplies the second quantized output by a second coefficient, wherein the third multiplier multiplies the third quantized output by a third coefficient and wherein the fourth multiplier multiplies the fourth quantized output by a first coefficient. [10] Serializer / deserializer receiver according to claim 8 or 9, further comprising a second differential forward equalizer coupled to the received signal and the equalized output signal. [11] Serializer / Deserializer receiver according to claim 10, wherein a summing element of the second differential forward equalizer is configured to subtract outputs provided by multiple multipliers of the second differential forward equalizer from the equalized output signal. [12] Serializer / deserializer receiver according to claim 11, wherein the summing element of the second differential forward equalizer is configured to provide a second equalized output signal as an output. [13] Serializer / deserializer receiver according to claim 12, wherein the second equalization output signal has a bit error rate that is smaller than the equalized output signal provided by the summing element. [14] Serializer / deserializer receiver according to any one of claims 8 to 13 above, wherein the received signal is an unequalized signal. [15] Serializer / deserializer receiver according to any one of claims 8 to 14 above, further comprising a third postcursor tap such that the number of postcursor taps is greater than the number of precursor taps. [16] Method for generating data from an input signal received from a channel, wherein the method is carried out by the decision forward equalizer according to any one of claims 1 to 7 and comprises the steps: Generating samples from the input signal using a sampling module; Applying a preliminary decision separation stage to each of the generated samples; Processing the output of the preliminary decision separation stage using one or more filter coefficients; and Combining the output from the filter operations. [17] Method according to claim 16, wherein each of the generated samples from the input signal is delayed relative to each other by a time delay measure. [18] Method according to claim 16 or 17, further comprising: Generating multiple first samples with multiple precursor taps; Generate multiple second samples using multiple postcursor taps, with each of the samples generated by the precursor taps and the postcursor taps being provided to the preliminary decision separator stage. [19] Method according to claim 18, further comprising providing the resulting output to a cursor tap between several second precursor taps and several second postcursor taps. [20] Method according to claim 18 or 19, wherein there are more postcursor taps than precursor taps.

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