Semiconductor device with a cut metal gate and a manufacturing process

Abstract

Procedure, comprehensive: Forming a fin (107) over a semiconductor substrate (101), Forming a metal gate (95) over the fin (107), Etching the metal gate (95) to form a trench (701) through the metal gate (95) and into the semiconductor substrate (101) between source / drain regions (901) of an n-type device (911) and a p-type device (913), and Deposition of a dielectric material (902) in the trench (701), wherein the dielectric material (902) extends into the semiconductor substrate (101) at an interface between the n-device (911) and the p-device (913); wherein the etching of the metal gate (95) in the semiconductor substrate (101) forms several separate recesses within the semiconductor substrate (101), the multiple recesses having a first recess in a first device area (106) for forming n devices and a second recess in a second device area (108) for forming p devices; wherein the dielectric material (902) is deposited with direct contact to an upper surface of the semiconductor substrate (101) between the first recess and the second recess.

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by lithography to pattern the various material layers to form circuit components and elements. US 2019 / 0165155A1 describes a semiconductor device comprising a first FinFET device, a second FinFET device, and a plurality of gate structures. A dielectric structure separates each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device.US 2019 / 0393324 A1 describes a method in which a first opening is created by means of an etching step and filled with dielectric material to form a first dielectric insulating layer. A second opening is created by means of a second etching step in which a contact connector is formed. DE 10 2018 128193 A1 describes a method in which a groove is formed in a gate stack of a semiconductor device and the groove is filled with dielectric material. DE 10 2019 115481 A1 describes a method for forming depressions, wherein a first depression extends into the substrate and a second depression is arranged between semiconductor fins.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, reducing the smallest feature sizes brings additional problems to light that must be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A-1B to 8A-8B show perspective views of cross-sections of resulting structures at intermediate steps in the formation of a semiconductor device according to some embodiments. Fig. Figure 9 shows a cross-sectional view of an anchored cut metal plug adjacent to source / drain areas, according to some embodiments. Fig. Figures 10A-10B show cross-sectional views of anchored cut metal connectors between devices according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0006] Embodiments are described below in relation to a process used to form an anchored cut-metal-gate (CMG) connector as part of a cut-metal-gate process.

[0007] With reference to Fig. 1A and Fig. Figure 1B shows perspective cross-sectional views of metal gates over semiconductor fins for a semiconductor device 100, such as a FinFET device. In one embodiment, the semiconductor device 100 has a substrate 101 with first grooves 103 formed therein. The substrate 101 can be a silicon substrate, although other substrates, such as semiconductor-on-insulator (SOI), strain-fit SOI, and silicon-germanium-on-insulator, could be used. The substrate 101 can be a p-type semiconductor, although in other embodiments it could be an n-type semiconductor.

[0008] Fig. 1A and Fig. Figure 1B further shows that the substrate 101 can be separated into a first device area 106 and a second device area 108 for forming different types of devices. For example, the first device area 106 can be used to form n devices, such as NMOS transistors (e.g., n-gate all-around transistors), and the second device area 108 can be used to form p devices, such as PMOS transistors (e.g., p-gate all-around transistors). However, p devices or n devices can be formed in either the first device area 106 or the second device area 108 based on a desired application. To separate the first device area 106 and the second device area 108, wells (not shown separately in Figure 1B) can be used. Fig. (shown in Figure 1B) within substrate 101 are formed using n-type and p-type dopants. To form the desired wells, the n-type and p-type dopants are implanted into substrate 101 depending on the features to be formed. For example, n-type dopants, such as phosphorus or arsenic, can be implanted to form n-type wells, while p-type dopants, such as boron, can be implanted to form p-type wells. The n-type and p-type wells can be formed using one or more implantation techniques, such as diffusion implantation, ion implantation (e.g., plasma doping, beamline implantation), selective implantation, deep-well implantation, and the like, or combinations thereof. Masking techniques can also be used to conceal certain areas (e.g.,to mask the second device areas 108) of the substrate, while other areas (e.g. first device areas 106) of the substrate 101 are exposed during a first tub implantation process (e.g. n tubs).

[0009] After the first basin implantation process is completed, the mask is removed to expose the previously masked areas (e.g., the second device area 108), and another mask can be positioned over the previously exposed areas (e.g., the first device area 106) during a second basin implantation process (e.g., p-basins). In some embodiments, further doping implantations can be performed to form deep basin implantation areas within the substrate 101.

[0010] The first trenches 103 can be formed as an initial step in the eventual formation of the first isolation regions 105. The first trenches 103 can be formed using a masking layer with a suitable etching process. For example, the masking layer can be a hard mask containing silicon nitride formed by a process such as chemical vapor deposition (CVD), although other materials, such as oxides, oxynitrides, silicon carbide, combinations of these or the like, and other processes, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitration, can be used.Once formed, the masking layer can be structured using a suitable photolithographic process to expose those sections of substrate 101 that will be removed to form the first trenches 103.

[0011] However, as a person skilled in the art will recognize, the processes and materials described above for forming the masking layer are not the only method that can be used to protect sections of the substrate 101 while other sections of the substrate 101 are exposed for the formation of the first trenches 103. Any suitable process, such as a structured and developed photoresist, can be used to expose sections of the substrate 101 that are to be removed to form the first trenches 103. All such methods are intended to be fully included in the scope of the present embodiments.

[0012] After a masking layer has been formed and structured, the first trenches 103 are formed in the substrate 101. The exposed substrate 101 can be removed using a suitable process, such as reactive ion etching (RIE), to form the first trenches 103 in the substrate 101, although any suitable process can be used. In one embodiment, the first trenches 103 can be formed such that they have a first depth of less than approximately 500 nm (5000 Å) from the surface area of ​​the substrate 101, such as approximately 250 nm (2500 Å).

[0013] However, as a person skilled in the art will recognize, the process described above for forming the first trenches 103 represents only one possible process and is not intended to be the only embodiment. Rather, any suitable process for forming the first trenches 103 may be used, and any suitable process comprising any number of masking and removal steps may be employed.

[0014] In addition to forming the first trenches 103, the masking and etching process also forms fins 107 from those sections of the substrate 101 that remain in an unremoved state. These fins 107 can be used, as discussed below, to form the channel region of multi-gate FinFET transistors. Although Fig. 1A and Fig. While 1B represents only six fins formed from substrate 101, any number of fins 107 can be used.

[0015] The fins 107 can be configured to have a width on the surface of the substrate 101 of between approximately 5 nm and approximately 80 nm, for example, approximately 30 nm. Furthermore, the fins 107 can be spaced apart from each other by a distance of between approximately 10 nm and approximately 100 nm, for example, approximately 50 nm. By spacing the fins 107 in this way, each fin 107 can form a separate channel region while remaining close enough to utilize a common gate (discussed below).

[0016] Although the foregoing description provides an exemplary embodiment, the fins 107 can also be structured by any suitable method. For example, the fins 107 can be structured using one or more photolithographic processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithographic and self-aligning processes, making it possible to create structures with, for example, smaller pitches than can otherwise be achieved using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to structure the fins 107.

[0017] After the first trenches 103 and the fins 107 have been formed, the first trenches 103 can be filled with a dielectric material, and the dielectric material can be recessed within the first trenches 103 to form the first insulation regions 105. The dielectric material can be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material can be formed after optional cleaning and lining of the first trenches 103 using either a chemical vapor deposition (CVD) process (e.g., the HARP process), a CVD process using high-density plasma, or another suitable formation method known in the art.

[0018] The first grooves 103 can be filled by overfilling the first grooves 103 and the substrate 101 with the dielectric material and then removing the excess material outside the grooves 103 and the fins 107 by a suitable process, such as chemical-mechanical polishing (CMP), etching, a combination of these, or the like. In one embodiment, the removal process also removes any dielectric material located above the fins 107, so that the removal of the dielectric material exposes the surface of the fins 107 for further processing steps.

[0019] After the first grooves 103 have been filled with the dielectric material, the dielectric material can then be recessed away from the surface of the fins 107. This recession can be carried out to expose at least one section of the sidewalls of the fins 107 adjacent to the upper surface of the fins 107. The dielectric material can be recessed using wet etching by immersing the upper surface of the fins 107 in an etchant, such as HF, although other etchants, such as H2, and other methods, such as reactive ion etching, dry etching with etchants such as NH3 / NF3, chemical oxide removal, or chemical dry cleaning, can also be used. The dielectric material can be spared from the surface of the fins 107 up to a distance of between approximately 5 nm (50 Å) and approximately 100 nm (1000 Å), such as approximately 54 nm (540 Å).Furthermore, the recess can also remove any remaining dielectric material arranged over the fins 107 to ensure that the fins 107 are exposed for further processing.

[0020] However, as a person skilled in the art will recognize, the steps described above can only be a part of the overall process sequence used for filling and voiding the dielectric material. For example, lining steps, cleaning steps, tempering steps, void-filling steps, combinations thereof, and the like can also be used to form the first trenches 103 and fill them with the dielectric material. All of the possible process steps are intended to be fully included in the scope of the present embodiment.

[0021] After the first insulation regions 105 have been formed, a dummy gate dielectric (or interface oxide), a dummy gate electrode over the dummy gate dielectric, gate sealing spacers 80, and gate spacers 86 can be formed over each of the fins 107. In one embodiment, the dummy gate dielectric can be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known and used in the prior art for forming a gate dielectric. Depending on the technique used to form the gate dielectric, the thickness of the dummy gate dielectric on the top surface of the fins 107 can differ from the thickness of the gate dielectric on the side surface of the fins 107.

[0022] The dummy gate dielectric can be a material such as silicon dioxide or silicon oxynitride, with a thickness ranging from approximately 0.3 nm (3 angstroms) to approximately 10 nm (100 angstroms), such as approximately 1 nm (10 angstroms). Alternatively, the dummy gate dielectric can be a material with a high permittivity (high-k) (e.g., with a relative permittivity greater than approximately 5), such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or zirconium oxide (ZrO₂), or combinations thereof, with an equivalent oxide thickness ranging from approximately 0.05 nm (0.5 angstroms) to approximately 10 nm (100 angstroms), such as approximately 1 nm (10 angstroms) or less. Furthermore, a combination of silicon dioxide, silicon oxynitride and / or high-k materials can also be used for the dummy gate dielectric.

[0023] The dummy gate electrode can be made of a conductive material and can be selected from a group that includes, for example, polysilicon (a dummy polysilicon (DPO)), tungsten (W), aluminum (Al), copper (Cu), AlCu, titanium (TiAlN), titanium (TaC), TaCN, TaSiN, manganese (Mn), zirconium (Zr), titanium (TiN), titanium (Ta), TaN, cobalt (Co), nickel (Ni), combinations of these, or the like. The dummy gate electrode can be deposited using chemical vapor deposition (CVD), sputtering, or other techniques known in the art for depositing conductive materials. The thickness of the dummy gate electrode can range from approximately 0.5 nm (5 Å) to approximately 20 nm (200 Å). The top surface of the dummy gate electrode can be non-planar and can be planarized prior to patterning or gate etching. At this point, ions may or may not be introduced into the dummy gate electrode. Ions can be introduced, for example, using ion implantation techniques.

[0024] After the dummy gate dielectric and dummy gate electrode have been formed, they can be structured to create a series of dummy gate stacks across the fins 107. The dummy gate stacks define several channel regions arranged on each side of the fins 107 beneath the dummy gate dielectric. The dummy gate stacks can be created by depositing and structuring a gate mask (not shown separately in Fig. 1A and Fig. (1B shown) on the dummy gate electrode, for example, using deposition and photolithography techniques known in the prior art. The gate mask can accommodate conventionally used masking and sacrificial materials, such as silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, but is not limited to these, and can be deposited to a thickness of between approximately 0.5 nm (5 Å) and approximately 20 nm (200 Å). The material layers of the dummy gate electrode and the dummy gate dielectric can be etched using a dry etching process to structure the materials into the dummy gate stacks.

[0025] After the materials have been structured into the dummy gate stacks, the gate sealing spacers 80 and the gate spacers 86 can be formed over the dummy gate stacks. The gate sealing spacers 80 and the gate spacers 86 are formed on opposite sides of the dummy gate stacks.

[0026] The gate sealing spacers 80 can be formed on exposed surfaces of the dummy gate stacks, the mask, and / or the fins 107. For example, the gate sealing spacers 80 can be formed along the sidewalls of the dummy gate stacks. Thermal oxidation or deposition followed by anisotropic etching can be used to form the gate sealing spacers 80. The gate sealing spacers 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0027] After forming the gate sealing spacers 80, implantations for weakly doped source / drain (LDD) regions (not explicitly shown) can be performed. Suitable lithographic techniques (e.g., masking) and materials (e.g., photoresist) can be used to expose selected areas of the existing structure in preparation for implantation of impurities within LDD regions. Suitable types of impurities (e.g., p-type and n-type) can be implanted into the exposed fins 107 in the selected regions, while the unselected regions are masked and protected during implantation. After implantation, the masks can be removed. Therefore, one or more regions with one or more types of impurities can be weakly doped using a range of suitable lithographic and implantation techniques.According to some embodiments, the lightly doped source / drain regions can have a concentration of impurities of approximately 10. 15 cm -3 up to about 10 19 cm -3 exhibit. A tempering process can be used to repair implant damage and to activate the implanted impurities.

[0028] The gatespacers 86 are formed along the sidewalls of the gate sealing spacers 80 opposite the dummy gate stacks. The gatespacers 86 can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gatespacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, SiCON, SiN, oxynitride, SiC, SiOC, a combination thereof, or the like, and can be formed by processes used to form such a spacer layer (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and any other suitable processes known in the prior art).

[0029] In one embodiment, the gatespacers 86 can be configured to have a thickness of between approximately 1 nm (10 Å) and approximately 10 nm (100 Å). Furthermore, gatespacers 86 of adjacent dummy gate stacks can be separated by a first spacing of between approximately 5 nm (50 Å) and approximately 50 nm (500 Å), such as approximately 20 nm (200 Å). However, any suitable thickness and spacing can be used.

[0030] Once the gatespacers 86 have formed, the fins 107 can optionally be removed and regrown from those areas not protected by the dummy gate stacks and the gatespacers 86. Removal of the fins 107 from these areas can be carried out by reactive ion etching (RIE) using the dummy gate stacks and the gatespacers 86 as hard masks, or by any other suitable removal process. Removal can continue until the fins 107 are either flush with or below the surface of the first isolation areas 105.

[0031] After these sections of the fins 107 have been removed, a hard mask (not shown separately) is arranged and structured to cover the dummy gate electrode in order to prevent growth on it during the regrowth of the source / drain areas 901 (in Fig. 1A-1B not shown, but below in Fig. (see Figure 9). In some embodiments, the source / drain regions 901 are regrown in contact with each of the fins 107. In some embodiments, the source / drain regions 901 can be regrown to form a stressor that will impart strain to the channel regions of the fins 107, which are arranged below the dummy gate stacks. In one embodiment, where the fins 107 are silicon and the FinFET is a p-type device, the source / drain regions 901 can be regrown using a selective epitaxial process with a material (e.g., silicon, silicon germanium, silicon phosphorus, and the like) that has a different lattice constant than the material of the channel regions. The epitaxial growth process can use precursors such as silane, dichlorosilane, germanium, and the like, and can last between approximately 5 minutes and approximately 120 minutes, as shown in Figure 9.The process can continue for approximately 30 minutes. In other embodiments, the source / drain regions 901 can comprise materials such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. However, any suitable materials may be used. Depending on the desired application, the epitaxial growth materials of the source / drain regions 901 of a device can be formed as separate, distinct epitaxial growth regions over each of the fins 107, or the separate, distinct epitaxial growth regions can be grown together to form a unified epitaxial growth structure.

[0032] After the source / drain regions 901 have been formed, dopants can be implanted into the source / drain regions 901 by implanting suitable dopants to complement the dopants in the fins 107. For example, p-dopants, such as boron, gallium, indium, or the like, can be implanted to form a PMOS device. In another embodiment, n-dopants, such as phosphorus, arsenic, antimony, or the like, can be implanted to form an NMOS device. These dopants can be implanted using the dummy gate stacks, the gate sealing spacers 80, and the gate spacers 86 as masks. It should be noted that a person skilled in the art will recognize that many other processes, steps, or the like can be used to implant the dopants.For example, a person skilled in the art will recognize that several implantation processes can be carried out using different combinations of spacers and liners to form the source / drain regions 901, which have a particular shape or characteristic suitable for a specific purpose. Any such processes, or any other suitable process, can be used to implant the dopants, and the foregoing description is not intended to limit the present embodiments to the steps presented above.

[0033] At this point, the hard mask that covered the dummy gate electrode during the formation of the source / drain regions 901 is also removed. In one embodiment, the hard mask can be removed, for example, using a wet or dry etching process that is selective with respect to the hard mask material. However, any suitable removal process can be used.

[0034] After the source / drain regions 901 have been grown and LDD regions have been suitably implanted, a contact etch stop layer (CESL) 87 is formed over the source / drain regions 901. The dielectric material of the CESL 87 can be conformally deposited over exposed surfaces in the source / drain regions 901 and along exposed sidewalls of the gate spacers 86 and exposed sidewalls of the gate sealing spacers 80 facing the source / drain regions 901, and over flat surfaces of the gate sealing spacers 80 and the dummy gate mask on the upper surface of the dummy gate stack. According to some embodiments, the CESL 87 can be formed using a chemical vapor deposition (CVD) process to expose the structure of one or more precursors and a plasma activation process carried out in a deposition chamber.The CVD process can be atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0035] According to some embodiments, the dielectric material of CESL 87 is conformally deposited as a complex compound comprising SiN (e.g., SiCN, SiOCN, or the like) or other suitable compounds, such as SiOC, and is formed to a thickness between approximately 2 nm (20 Å) and approximately 6 nm (60 Å), such as approximately 4 nm (40 Å). However, any suitable materials, compounds, and / or thicknesses can be used.

[0036] A dielectric intermediate layer (ILD) 119 (e.g., an ILDo layer) is then formed over the CESL 87. The ILD layer 119 can be made of a material such as silicon dioxide (SiO2) or boron phosphosilicate glass (BPSG), although any suitable dielectrics can be used. The ILD layer 119 can be formed over the CESL 87 and the source / drain regions 901 using a process such as PECVD, although other processes such as LPCVD can also be used. The ILD layer 119 can be formed to a thickness of between approximately 10 nm (100 Å) and approximately 300 nm (3,000 Å). However, any suitable thickness can be used.

[0037] After the ILD layer 119 has been formed, it can be planarized to prepare it for further processing. In one embodiment, the ILD layer 119 and the CESL 87 can be planarized using a planarization process, such as chemical-mechanical polishing (CMP), so that the ILD layer 119 and the CESL 87 are coplanar with the dummy gate stacks. Therefore, the top surfaces of the dummy gate electrodes, the gate sealing spacer 80, the gate spacer 86, the CESL 87, and the ILD layer 119 are coplanar. Accordingly, the top surfaces of the dummy gate electrodes are exposed by the ILD 119. In some embodiments, dummy gate masks or sections thereof may remain, in which case the planarization process flattens the upper surface of the ILD layer 119, the CESL 87, the gate sealing spacer 80 and the gate spacer 86 with the upper surfaces of the dummy gate masks.However, any other suitable method, such as one or more etching processes, can also be used.

[0038] After the ILD layer 119 has been planarized, components of the dummy gate stack (e.g., a remaining portion of the dummy gate mask, the dummy gate electrode, and the dummy gate dielectric) can then be removed. In one embodiment, one or more etching processes, such as one or more wet etching processes, can be used to remove these components of the dummy gate stack. However, any suitable removal process can be used.

[0039] After the dummy gate stack has been removed, the remaining openings can be refilled to form a metal gate stack 95. According to some embodiments, the metal gate stack 95 comprises a gate dielectric layer 92, a liner layer 94A, any number of exit work setting layers 94B, and a filler material 94C.

[0040] In some embodiments, the gate dielectric layer 92 is a high-k material, such as HfO. 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these or the like, deposited by a process such as atomic layer deposition, chemical vapor deposition, or the like. The gate dielectric layer 92 can be deposited to a thickness of between approximately 0.5 nm (5 Å) and approximately 20 nm (200 Å), although any suitable material and thickness may be used.

[0041] The liner layer 94A can be formed adjacent to the gate dielectric layer 92 and can be made of a metallic material such as TiSi, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The liner layer 94A can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between approximately 0.5 nm (5 Å) and approximately 20 nm (200 Å), although any suitable deposition process or thickness may be used. According to some embodiments, several liner layers can be formed adjacent to the gate dielectric layer 92.

[0042] The first work function setting layer 94B1 can be formed adjacent to the liner layer 94A and, in some embodiments, can be similar to the liner layer 94A. For example, the first work function setting layer 94B1 can be formed from a metallic material such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Furthermore, the first work function setting layer 94B1 can be formed using a deposition process such as…by atomic layer deposition, chemical vapor deposition, sputtering or the like, up to a thickness of between approximately 0.5 nm (5 Å) and approximately 20 nm (200 Å), although any suitable deposition process and any suitable thickness may be used.

[0043] The second output work setting layer 94B2 can be formed adjacent to the first output work setting layer 94B1. According to some embodiments, the second output work setting layer 94B2 can be similar to the liner layer 94A. For example, the second output work setting layer 94B2 can be formed from a metallic material such as TiAlC, TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Furthermore, the second output work setting layer 94B2 can be formed using a deposition process such as…by atomic layer deposition, chemical vapor deposition, sputtering or the like, up to a thickness of between approximately 0.5 nm (5 Å) and approximately 20 nm (200 Å), although any suitable deposition process or any suitable thickness may be used.

[0044] The filler material 94C fills a remnant of the opening left behind by the removal of the dummy gate electrode. In one embodiment, the filler material 94C is a metallic material, such as W, TiN, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, Ta, TaN, Co, Ni, combinations thereof, or the like, and can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to fill and / or overfill the opening left behind by the removal of the dummy gate electrode. In a particular embodiment, the filler material 94C can be deposited to a thickness of between approximately 0.5 nm (5 Å) and approximately 50 nm (500 Å), although any suitable material, deposition process, and thickness may be used.

[0045] After the opening left by the removal of the dummy gate electrode has been filled, the materials can be planarized to remove any material located outside the opening left by the removal of the dummy gate electrode. In one particular embodiment, the removal can be carried out using a planarization process, such as chemical-mechanical planarization (CMP), until the metal gate stack 95 has first heights H1 above the fins 107 of between approximately 40 nm (400 Å) and approximately 60 nm (600 Å), such as approximately 49 nm (490 Å). However, any suitable planarization and removal process and any suitable height can be used to form the metal gate stack 95.

[0046] After the metal gate stack 95 has been planarized, a first hard mask 301 can be formed over the structure. In one embodiment, the first hard mask 301 is a material, such as titanium nitride or tantalum nitride, formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The first hard mask 301 can be formed to a thickness of between approximately 3 nm and approximately 10 nm, such as 5 nm. However, any suitable material, deposition process, and thickness can be used.

[0047] After deposition of the first 301 hard mask, a backside cleaning process can be performed. This process can include one or more cleaning methods (e.g., surface cleaning, deoxidation, and / or surface activation) to remove any remaining CMP suspension and native oxide layers from the surfaces of the first 301 hard mask. A deoxidation process can also be used to remove native oxide layers. Combinations of these cleaning methods, or any other suitable cleaning methods, can also be employed.

[0048] Fig. Figure 1A shows in particular a cross-sectional view (X-section) of the semiconductor device 100, drawn through the metal gate stacks 95 of adjacent device regions in a region between adjacent fins 107 of the first device region 106 and the second device region 108 in a direction along the length of the fins 107 in the substrate 101. In one embodiment, the metal gate stack 95 has a first gate length of between approximately 40 nm (400 Å) and approximately 300 nm (3,000 Å), such as approximately 100 nm (1,000 Å). However, any suitable gate length can be used. Furthermore, the metal gate stack 95 in the first device area 106 can be assembled using materials (e.g., the gate dielectric layer 92, the liner layer 94A, the output work setting layers 94B, and the filler material 94C) that are suitable for forming, e.g.,The n-device can be formed, and can be formed in the second device area 108 using materials (e.g., the gate dielectric layer 92, the liner layer 94A, the output work setting layers 94B, and the filler material 94C) suitable for forming, e.g., the p-device. Fig. Figure 1A also shows a section line YY through the metal gate stack 95 of the second device area 108.

[0049] Fig. Figure 1B shows in particular a cross-sectional view (Y-section) of the semiconductor device 100, which extends along the length of the metal gate stack 95 of the second device area 108. Fig. 1A is drawn. Fig. Figure 1B further shows that the metal gate stack 95 can extend over the fins 107 of adjacent device areas (e.g., the second device area 108 and another of the first device areas 106). As can be seen, the metal gate stack 95 extends over several of the fins 107. Although six fins are shown, this number is for illustrative purposes only and is in no way intended to be limiting. Fig. Figure 1B also shows a section line XX through the metal gate stack 95 between adjacent fixture areas.

[0050] Fig. 2A and Fig. Figure 2B shows the formation of a second hard mask 303 over the first hard mask 301. In one embodiment, the second hard mask 303 can be a single layer of material, or it can be a composite layer of several materials, such as a double layer of materials. According to some embodiments, the materials of the second hard mask 303 are dielectric materials, such as silicon nitride (SiN) or silicon carbon nitride (SiCN). However, any suitable material or combination of materials can be used.

[0051] In embodiments where the second hard mask 303 has a double-material layer, a first sublayer of the double-material layer can be formed from a first dielectric material (e.g., silicon nitride (SiN)) using a deposition process such as ALD, CVD, or PVD, to a thickness of between approximately 30 nm and approximately 40 nm, such as approximately 34 nm. A second sublayer of the double-material layer can be formed with a second dielectric material, or either the same material (e.g., silicon nitride (SiN)) or a different material (e.g., silicon carbon nitride (SiCN)), using a deposition process such as ALD, CVD, or PVD, to a thickness of between approximately 30 nm and approximately 40 nm, such as approximately 34 nm. However, any suitable deposition process and any suitable thickness can be used.

[0052] After the second hard mask 303 has been formed, an optional surface treatment can be performed on the second hard mask 303 to help protect it and prepare it for further processing. In one embodiment, the optional surface treatment can be a descum treatment, such as plasma treatment, wherein the surface of the second hard mask 303 is exposed to a plasma of, for example, argon, nitrogen, oxygen, or a mixed Ar / N₂ plasma. 2 / The surface is exposed to an oxygen environment. An optional scrubbing cleaning process may also be performed. However, any suitable surface treatment, any suitable cleaning process, and any suitable combination thereof may also be used.

[0053] Fig. Figures 3A-3B show the arrangement of a first photoresist 401 over the second hard mask 303 and the subsequent exposure and development of the first photoresist 401 to structure it, forming a mask that is used for the subsequent structuring of the second hard mask 303. In one embodiment, the first photoresist 401 is a three-layer photoresist comprising a lower antireflective coating layer (BARC layer) 403, an intermediate mask layer 405, and an upper photoresist layer 407. Fig. Figures 3A-3B further show embodiments in which the first photoresist 401 is a three-layer photoresist that a first structure 350 is formed in the upper photoresist layer 407, for example, using extreme ultraviolet light (EUV light). However, any suitable type of photosensitive material, a combination of materials, and any suitable structuring process can be used.

[0054] Fig. Figures 4A-4B show that after structuring, the first structure 350 of the first photoresist 401 is then transferred to the second hard mask 303, whereby the first hard mask 301 is exposed by the first structure 350 of the second hard mask 303. In one embodiment, the transfer of the first structure 350 can take place, for example, using one or more anisotropic etching processes, such as one or more reactive ion etching processes, to sequentially etch through the mask interlayer 405, the BARC layer 403, and the second hard mask 303. According to some embodiments, the structure of the second hard mask 303 can have a first length L1 of between approximately 70 nm and approximately 150 nm, such as approximately 125 nm, and a first width W1 of between approximately 16 nm and approximately 30 nm, such as approximately 21 nm. However, any suitable process, width, and length can be used.

[0055] After the second hard mask 303 has been structured, the first photoresist 401 can also be removed if it has not already been removed during one or more etching processes. In one embodiment, the upper photoresist layer 407 can be removed using a thermal process, such as ashing, in which the temperature of the upper photoresist layer 407 is increased until it thermally decomposes and can be easily removed. After the upper photoresist layer 407 has been removed, the mask intermediate layer 405 and the lower antireflective coating layer (BARC layer) 403 can be removed using one or more etching processes.

[0056] If desired, wet cleaning can be performed during or after the removal of the first photoresist 401. In one embodiment, a solution such as an SC-1 or SC-2 cleaning solution can be used, although other solutions, such as a mixture of H₂SO₄ and H₂O₂ (e.g., sulfur peroxide mixture (SPM)), or a hydrofluoric acid solution (HF solution), can also be used. A charging process (e.g., nitrogen charging (N₂ charging)) can be used to rinse away any unwanted contaminants or reactants. However, any suitable solution or process can be used and is intended to be fully included within the scope of the embodiments.

[0057] Transition to Fig. Figures 5A-5B show the initial steps of a multi-stage etching and deposition process used to form a trench 701 (in Fig. 5A-5B not shown, but in Fig. (shown in Figures 6A-6B). In such a process, an initial masking layer 601 is deposited along the sidewalls of the first structure 350, and the deposition is followed by a dielectric breakdown process to expose the underlying material while leaving the masking layer 601 in place along the sidewalls. Once the sidewalls are protected by the masking layer 601 and the underlying material is exposed, another etching process is used to widen the trench 701 downwards without widening it laterally. Since some of the masking layer 601 may be consumed by the etching process, the multi-stage process (e.g.,Deposition of the masking layer, dielectric breakdown sets, and widening of the trench 701) are repeated to further widen the trench 701 with each repetition without increasing the width of the trench 701, as discussed in detail in the sections below.

[0058] If the deposition of the masking layer is considered first, in one embodiment the masking layer 601 can have a material similar to that of the second hard mask 303. Therefore, in an embodiment where the second hard mask 303 is made of silicon nitride (SiN), the masking layer 601 can also be made of silicon nitride (SiN). However, the masking layer 601 can also have other materials or compositions that differ from those of the second hard mask 303.

[0059] In one embodiment, the masking layer 601 can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, combinations thereof, or the like. According to some embodiments, the masking layer 601 can be formed as a conformal layer over the second hard mask 303, along vertical sidewalls of the first structure 350 formed in the second hard mask 303, and over the first hard mask 301 within the first structure 350. In some embodiments, the masking layer 601 is formed to a first thickness Th1 of between approximately 1.5 nm and approximately 7 nm, such as approximately 5 nm. For example, in one particular embodiment, the masking layer 601 is formed to a first thickness Th1 of between approximately 1.5 nm and approximately 7 nm, such as 5 nm.However, any suitable deposition process and any suitable thickness can be used.

[0060] Fig. Figures 5A-5B further show a continuation of the cut-metal-gate process that can be carried out after the masking layer 601 has been deposited. In one embodiment, the lower section of the masking layer 601 can be removed in an anisotropic etching process, while the vertical sections of the masking layer 601 remain along vertical sidewalls of the first structure 350 in the second hard mask 303. Therefore, the size of the first structure 350 is reduced by the thickness of the remaining sections of the masking layer 601, forming a second structure 550 in the second hard mask 303 and exposing the first hard mask 301 through the second structure 550. According to some embodiments, the second structure 550 in the second hard mask 303 has a second length L2 of between approximately 60 nm and approximately 140 nm, such as approximately 115 nm, and a second width W2 of between approximately 6 nm and approximately 20 nm, such as approximately 115 nm.approximately 11 nm. However, any suitable process, any suitable widths, and any suitable lengths can be used.

[0061] Fig. Figures 6A to 6C show the etching of a trench 701 through the underlying first hard mask 301 and the metal gate stack 95, for example, using a cycle of repeated deposition and etching processes (where the deposition of the masking layer 601 represents the initial deposition step of these cyclic deposition and etching processes). These figures show Fig. 6A and Fig. 6C the cross-sectional views at the end of the process, while Fig. 6B represents an intermediate step during the process prior to the removal of a second masking layer 703 (described below).

[0062] The second structure 550 is etched as an initial step (see Fig. 5B) first extended by the first hard mask 301. In one embodiment, the second structure 550 is extended by the first hard mask 301 using one or more direction-dependent etching processes, such as a reactive ion etching process, to expose the metal gate stack 95. However, any suitable method, such as a wet etch breakthrough, can be used to structure the first hard mask 301.

[0063] After the first hard mask 301 has been structured, the multi-stage etching and deposition process is then used to etch through the metal gate stack 95 and extend the second structure 550 into the substrate 101. For example, after the deposition of the masking layer 601, the multi-stage etching and deposition process can be continued with a dielectric breakdown process to expose the underlying material of the metal gate stack 95. According to some embodiments of the present disclosure, the multi-stage etching and deposition process (after the initial deposition of the masking layer 601) can be continued with an initial etching using process gases selected from, and not limited to, Cl₂, BCl₃, Ar, CH₄, CF₄, and combinations thereof. The initial etching of the metal gate stack 95 can be carried out at a pressure in the range of approximately 0.33 Pa (2.5 mTorr) to approximately 3.3 Pa (25 mTorr).An RF power is applied during the initial etching, and this RF power can range from approximately 250 watts to approximately 2,500 watts. A bias voltage ranging from approximately 25 volts to approximately 750 volts can also be applied. The initial etching process can be stopped when it has partially, but not completely, extended the second structure 550 through the metal gate stack 95.

[0064] Since the initial etching process also removes the masking layer 601 (albeit at a lower removal rate), a second deposition process is subsequently used to reshape the mask by forming a second masking layer 703 before further etching (described below) widens the second structure 550. In one embodiment, the second deposition process for forming the second masking layer 703 includes sidewall sections on the sidewalls of the trench 701 to protect the sidewalls so that the upper sections of the trench 701 are not widened laterally when the trench 701 is widened downwards. According to some embodiments of the present disclosure, the second deposition process for forming the second masking layer 703 is carried out using process gases containing SiCl₂, O₂, Ar, and the like.Therefore, the resulting second masking layer 703 contains SiO2 instead of, for example, silicon nitride, which may or may not be bonded to additional elements, such as carbon. However, in other embodiments, the second masking layer 701 can also be similar to the material of the masking layer 601, for example, by being silicon nitride. The resulting second masking layer 703 can be designed to have a thickness of between approximately 2 nm and approximately 4 nm, such as approximately 3 nm.

[0065] Next, another dielectric breakdown process is carried out, removing the lower portion of the formed second masking layer 703 from the bottom of the trench 701 in an anisotropic etching / bombardment process, which also removes the second masking layer 703 from other horizontal surfaces. According to some embodiments, a carbon-fluorine gas (such as C4F6) is used to etch the lower portion of the second masking layer. According to some embodiments, the thickness of the portion of the second masking layer 703 on the top surface of the second masking layer 703 and / or the thickness of the portions of the second masking layer 703 on the side walls of the trench 701 can also be reduced during the etching process.

[0066] After the second masking layer 703 has been formed, a further etching process is carried out to extend the trench 701 deeper into the metal gate stack 95. In one embodiment, the next etching process can be carried out as described above with respect to the initial etching process. However, any suitable etching process can be used.

[0067] According to some embodiments, the etching of the metal gate stack 95 utilizes multiple deposition-etch cycles, each cycle comprising a dielectric deposition process, a dielectric breakdown process, and an etching process to widen the trench 701 downwards. Each deposition-etch cycle results in the trench 701 being widened further downwards until the metal gate stack 95 is etched through. In some embodiments, the process can be repeated, for example, two to twenty times, such as 10 times, although any suitable number of repetitions may be used.

[0068] After the metal gate stack 96 has been etched through, the second structure 550 is further extended into and through the first isolation region 105. In one embodiment, the second structure 550 is extended using the deposition-etch cycles as described above. However, the etching chemistry can be modified as required based on the material of the first isolation region 105. Alternatively, any other suitable method for extending the second structure 550 through the first isolation region 105, such as direct etching without forming the second masking layer 703 to expose the underlying substrate 101, can be used.

[0069] After the isolation area 103 was etched through and the semiconductor substrate 101 was exposed, it finally shows Fig. 6B, that the second structure 550 is further extended into the semiconductor substrate to form the trench 701. As can be seen, this shows Fig. 6B is an intermediate step in the process after reshaping the second masking layer 703, but before removing the second masking layer. In one embodiment, the second structure 550 is extended using the deposition-etch cycles as described above. However, the etching chemistry can optionally be modified based on the material of the substrate 101.

[0070] According to some embodiments of the present disclosure, the etching process of substrate 101 can be carried out using process gases selected from, and not limited to, Cl₂, C₄F₆, BCl₃, N₂, O₂, HBr, and combinations thereof. The etching can be performed at a pressure in the range of approximately 0.7 Pa (5 mTorr) to approximately 7.0 Pa (50 mTorr). RF power is applied in the initial etching, and the RF power can be in the range of approximately 100 watts to approximately 2,400 watts. A bias voltage in the range of approximately 20 volts to approximately 1,000 volts can also be applied.

[0071] The repetitive deposition and etching cycles can be repeated as desired to extend the second structure 550 through the substrate 101. In some embodiments, the process can be repeated two to ten times, although any suitable number of repetitions can be used. Furthermore, any other suitable method for extending the second structure 550 through the substrate 101, such as direct etching without forming the second masking layer 703, can be used to form the lower section of the trench 701.

[0072] Fig. Figure 6C shows that, after the trench 701 has been formed using the second masking layer 703, any residues of the second masking layer 703 can be removed using several cycles of exposure followed by a tempering process. In an embodiment where the second masking layer 703 is silicon dioxide, the second masking layer 703 can be removed by introducing hydrofluoric acid (HF) and ammonia (NH3) as etchants into the second masking layer 703. The HF and NH3 can react with each other and with the oxide present in the second masking layer 703 to generate (NH4)2SiF6 on an area of ​​the second masking layer 703, which can then be heated using a tempering process to decompose the (NH4)2SiF6 into N2, H2O, SiF6, and NH3, all of which can be vapor and can be removed.In one embodiment of the tempering process, the second masking layer 703 can be heated to a temperature between approximately 80 °C and approximately 200 °C, such as approximately 100 °C, for between approximately 60 seconds and approximately 180 seconds. However, any suitable method for removing the second masking layer 703, such as a wet etching process, can also be used.

[0073] After removal of the second masking layer 703, an optional second wet cleaning may be performed to prepare the structure for subsequent processing. In one embodiment, a solution such as an SC-1 or SC-2 cleaning solution may be used, although other solutions, such as a mixture of H₂SO₄ and H₂O₂ (known as SPM), or a hydrofluoric acid solution (HF solution), may also be used. However, any suitable solutions or processes may be used and are intended to be fully included within the scope of the embodiments.

[0074] After the second masking layer 703 has been completely removed and cleaned, the trench 701 extends through the metal gate stack 95, the first isolation area 105, and into the substrate 101. According to some embodiments, the trench 701 is formed to a fourth width W4 on a plane of the upper surfaces of the fins, a fifth width W5 on a bottom surface of the trench 701 that is smaller than the fourth width W4, through a first depth D1 of the first isolation area 105, and through a second depth D2 into the substrate 101. According to some embodiments, the trench 701 is extended to the fourth width W4 of between approximately 14 nm and approximately 24 nm, the fifth width W5 of between approximately 1 nm and approximately 30 nm, such as approximately 15 nm, the first depth D1 of between approximately 30 nm and approximately 90 nm, such as approximately 40 nm, or such as approximately 80 nm, and the second depth D2 of between approximately 0 nm and approximately 40 nm, such asapproximately 30 nm, formed. However, any suitable widths and any suitable depths can be used for the fourth width W4, the first depth D1 and the second depth D2 of trench 701.

[0075] Fig. Figures 7A-7B show the filling of the trench 701 with a filler material 902 to complete the separation of the metal gate stack 95. In one embodiment, the filler material 902 can be a single layer of material, or it can be one or more layers of material, such as a bilayer. In one embodiment, one or each layer of material can be a material such as silicon nitride (SiN) or silicon carbon nitride (SiCN). However, any suitable material or combination of materials can be used. In some embodiments, the filler material 902 can be deposited using a deposition process such as ALD, CVD, or PVD to a thickness of between approximately 20 nm and approximately 50 nm, such as approximately 30 nm. However, any suitable deposition process and any suitable thickness for the filler material 902 can be used.

[0076] Fig. Figures 8A-8B show planarization of the filler material 902 and removal of the first hard mask 301. In one embodiment, the planarization can be a process, such as a chemical-mechanical polishing process, used to planarize the filler material 902 with the metal gate stack 95 and the first spacers. During the process, the first hard mask 301 is also removed. Therefore, an anchored cut-metal-gate connector 903 is formed through the metal gate stack 95, effectively "cutting" the metal gate stacks from one another, through the first insulation regions 105, and into the substrate 101 of the semiconductor device 100. According to some embodiments, the anchored CMG connector 903 is formed to a second height H2 of between approximately 60 nm and approximately 90 nm, such as approximately 75 nm. However, any suitable height can be used.

[0077] Furthermore, the chemical-mechanical polishing process used to remove excess filler material 902 can also be used to reduce the height of the metal gate stack 95 at this time. In one embodiment, the height of the metal gate stack 95 above the fins 107 can be reduced to a third height H3 of between approximately 20 nm (200 Å) and approximately 40 nm (400 Å). However, any suitable reduction in height can be used.

[0078] As in Fig. As can be seen in Figure 8A, the anchored CMG connector 903 can also extend into several trenches formed in substrate 101, as described above. These trenches are formed separately from one another, since the etching process (see above with reference to Figure 8A) Fig. (Described in sections 6A to 6C) the materials above the trenches (e.g., the metal gate stacks 95) are etched faster than the material between the trenches (e.g., the ILD layer 119). Therefore, the anchored CMG connector 903 can extend continuously from the inside of one trench in substrate 101 to the inside of a second trench in substrate 101.

[0079] Fig. Figure 9 shows a cross-sectional view according to some embodiments, drawn through the source / drain regions 901 of two adjacent devices of the first device region 106 and the second device region 108 during an operation. In one particular embodiment, an n-device 911 (e.g., an NMOS device) can be formed in the first device region 106, and a p-device 913 (e.g., a PMOS device) can be formed in the second device region 108 adjacent to the n-device 911, and they are separated by the anchored CMG connector 903 of the semiconductor device 100. The source / drain regions 901 can be formed using the spacers 86 and coated with the CESL 87 and embedded in the ILD layer 119 using the materials and processes discussed above. Fig. 1A and Fig. 1B, which were discussed in detail, will be embedded.

[0080] After the source / drain regions 901 and the metal gate stacks 95 have been formed in the first device regions 106 and the second device regions 108, the anchored CMG connector 903 can be formed as described above. When forming the opening 701 through the metal gate stacks 95 as described above, the opening 701 can, according to some embodiments, also be formed through the ILD layer 119, the CESL 87, and the first insulation regions 105 and into the substrate 101 between the source / drain regions 901 of adjacent devices in one or more of the first device regions 106 and the second device regions 108. According to some embodiments, the opening 701 can be formed into the substrate 101 at an interface between a first doped region 905 (e.g., p-tub) of the n-device 911 and a second doped region 907 (e.g.,n-tub) of the p-device 913 are cut and the anchored CMG connector 903 is formed within the opening 701 as described above and in . Fig. 9 shown.

[0081] According to embodiments disclosed herein, the anchored CMG connector 903 provides high resistance to reduce leakage current (e.g., E breakdown current), represented by the direction arrow 909, at an interface between doped regions within the semiconductor device 100 during operation. For example, the anchored CMG connector 903 can trap negative electrons in an anchored region 915 at the interface between a first doped region 905 (e.g., p-well) of the n-device 911 and a second doped region 907 (e.g., n-well) of the p-device 913. As the depth of the anchored CMG connector 903 into the substrate 101 increases (e.g., the second depth D2), a greater resistance is provided by the CMG connector 903 at these interfaces.Therefore, the anchored CMG connector 903 provides a further reduction in leakage current, thereby enabling an improved threshold voltage (improved V-trigger performance) of the semiconductor device 100.

[0082] Such improved V-trigger performance can be seen in V-trigger test results. For example, in some embodiments using the process described above, the V-trigger can be increased to between approximately 1740 mV and approximately 1970 mV. This is much higher than baseline measurements, where the embodiments do not use values ​​between approximately 1620 mV and 1850 mV. Therefore, an increase of approximately 120 mV can be achieved.

[0083] Fig. 10A and Fig. Figure 10B shows cross-sectional views, each drawn through the source / drain regions 901 or the metal gate stacks 95 of three adjacent devices according to some other embodiments during operation of the semiconductor device 100. The three adjacent devices (running from left to right) include the first p-device 913 (e.g., PMOS) formed in the second device region 108, the n-device 911 (e.g., NMOS) formed in the first device region 106, and a second p-device 1013 (e.g., PMOS) formed in another of the second device regions 108. Fig. 10A and Fig. Figure 10B further shows the formation of source / drain contact structures 1001, conductive source / drain connectors 1009, and gate contact structures 1011 according to some embodiments. The conductive source / drain connectors 1009 and the gate contact structures 1011 provide an external connection to the source / drain regions 901 and the metal gate stacks 95 of the three adjacent devices.

[0084] Fig. Figure 10A further shows that, according to a particular embodiment, the source / drain regions 901 in the first p-device 913 are formed as a unified epitaxial growth structure over the fins 107, the epitaxial growth material of the source / drain regions 901 in the second p-device 1013 is formed as a unified epitaxial growth structure over the fins 107, and the epitaxial growth regions of the source / drain regions 901 in the n-device 911 are formed as individual epitaxial growth regions that remain separate from each other.

[0085] Fig. Figure 10A further shows two of the anchored CMG connectors 903, which are formed adjacent to the source / drain regions 901 of the three adjacent devices, according to some embodiments. A first connector of the anchored CMG connectors 903 is formed adjacent to the first p-device 913 and is embedded in the substrate 101 of the first p-device 913. A second connector of the anchored CMG connectors 903 is embedded in the substrate 101 at an interface between the n-device 911 and the second p-device 1013, according to some embodiments. Therefore, during operation of the semiconductor device 100, the second connector of the anchored connectors 903 provides a higher resistance to reduce a leakage current (e.g., E-breakdown current) between the n-device 911 and the second p-device 913, as indicated by the directional arrow 909.Therefore, during operation of the semiconductor device 100, electrons are trapped in the anchored area 915 at the interface between the first doped area 905 (e.g. p-well) of the n-device 911 and a second doped area 907 (e.g. n-well) of the p-device 1013).

[0086] The source / drain contact structures 1.001 can be formed by initially forming a first insulating layer 1.003 (e.g., an etch stop layer) over the planar surfaces of the ILD layer 119 and the anchored CMG connectors 903. In some embodiments, the first insulating layer 1.003 can be formed by overfilling the openings 701 with material from the anchored CMG connectors 903 and reducing the height of the overfill material to a desired height of the first insulating layer 1.003. In other embodiments, a further dielectric layer is formed over the planar surfaces of the ILD layer 119 and the anchored CMG connectors 903 using any of the materials (e.g., SiN) and processes (e.g.,The first insulating layer 1003 is deposited by plasma-enhanced chemical vapor deposition (PECVD) and / or chemical-mechanical planarization (CMP), which are suitable for depositing and planarizing the anchored CMG connectors 903, as described above. According to some embodiments, the first insulating layer 1003 can be formed to a thickness of between approximately 1 nm (10 Å) and approximately 20 nm (200 Å), such as approximately 5 nm (50 Å). However, any other suitable materials, processes, and / or thicknesses can be used.

[0087] After the first insulating layer 1.003 has been formed, a second ILD layer 1.005 is deposited over the first insulating layer 1.003 using any of the materials and any of the methods used to form the ILD layer 119. In some embodiments, the second ILD layer 1.005 can be formed to a thickness between approximately 1 nm (10 Å) and approximately 50 nm (500 Å), such as approximately 10 nm (100 Å). However, any suitable materials, any suitable deposition methods, and any suitable thicknesses can be used to form the second ILD layer 1.005.

[0088] After the second ILD layer 1.005 has formed, a masking layer (in Fig. (10A-10B not shown separately) are deposited and structured using a photolithographic process to form openings through the masking layer and expose areas of the second ILD layer 1005 in regions overlying the source / drain regions 901. Openings are formed in these regions using the mask and one or more suitable etching processes (e.g., anisotropic reactive ion etching (RIE)) and one or more process gases (e.g., carbon- and fluorine-containing gases, such as CF4, CH2F2, CHF3, or the like) to remove material overlying the source / drain regions 901. In some embodiments, during the removal of the first ILD layer 119, the material of the anchored CMG connector 903 adjacent to one or more of the source / drain regions 901 may also be etched, resulting in the retraction of the anchored CMG connector 903.After the openings have been formed and the source / drain areas 901 have been exposed, the masking layer is removed, for example, by means of an ashing process, and an optional cleaning process can be carried out in the openings before the formation of the source / drain contact structures 1001.

[0089] According to some embodiments, the source / drain contact structures 1.001 are formed in the openings by depositing one or more conductive materials, such as a liner (e.g., a diffusion barrier layer, an adhesive layer, or the like) and a conductive material. Examples of materials that can be used for the liner include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and examples of materials that can be used for the conductive material include tungsten, copper, a copper alloy, silver, gold, cobalt, aluminum, nickel, or the like. These materials can be deposited using electroplating, electroless plating, printing, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. After the conductive material has been deposited, a planarization process, such as…A CMP is performed to remove excess material from an area of ​​the second ILD layer 1005 and to planarize the source / drain contact structures 1001 with the second ILD layer 1005. If desired, an optional silicide can be formed along areas of the source / drain regions 901 prior to the formation of the source / drain contact structures 1001. Therefore, the source / drain contact structures 1001 are physically and electrically coupled over the source / drain regions 901 to the exposed portions of the epitaxial growth material of the source / drain regions 901. In some embodiments, the source / drain contact structures 1001 can be formed over and connected to the anchored cut-metal-gate connector 903.001 over the source / drain areas 901 in different device areas can be formed using different materials and different processes, or they can be formed using the same materials and the same processes.

[0090] Fig. Figure 10A shows that, according to some embodiments, one of the source / drain contact structures 1001 is formed over and physically connected to both of the combined epitaxial growth structures 901 of the first p-device 913 and one of the individual epitaxial growth structures 901 of the n-device 911. Another of the source / drain contact structures 1001 is formed over and physically connected to the anchored cut-metal-gate connector 903, and is formed over and physically connected to both of the combined epitaxial growth structures 901 of the second p-device 1013 and one of the individual epitaxial growth structures 901 of the n-device 911.

[0091] After the source / drain contact structures 1.001 have been planarized with the second ILD layer 1.005, the conductive source / drain connectors 1009 are formed over the source / drain contact structures 1.001. The conductive source / drain connectors 1.009 can be formed by first forming a second insulating layer 1.007 (e.g., a second etch stop layer) and a third ILD layer 1011 over the planar surfaces of the source / drain contact structures 1.001 and the second insulating layer 1.005. The second insulating layer 1.007 and the third ILD layer 1.011 can be formed similarly to the first insulating layer 1.003 and the second ILD layer 1.005, although any suitable materials and methods can be used.

[0092] After the second insulating layer 1.007 and the third ILD layer 1011 have been deposited, the second insulating layer 1.007 and the third ILD layer 1011 can be structured to expose sections of the source / drain contact structures 1.001. The openings can be formed through the third ILD layer 1011 and the second insulating layer 1.007 by using any of the etching processes and process gases suitable for forming the openings for the source / drain contact structures 1.001, as described above. In some embodiments, the structuring process for exposing the source / drain contact structures 1.001 can also be used to expose areas of the source / drain contact structures 1.001 in preparation for forming the gate contact structures 1011 (as in Fig. (10B). The conductive source / drain connectors 1.009 can be formed over the exposed areas of the source / drain contact structures 1.001. The conductive source / drain connectors 1.009 can be formed using any of the materials and processes suitable for forming the source / drain contact structures 1.001, as described above. According to some embodiments, the gate contact structures 1011 and the source / drain contact connectors 1.009 have a barrier layer and a conductive material.

[0093] Fig. Figure 10B also shows the formation of the gate contact structures 1011 over the metal gate stacks 95 according to some embodiments. In one embodiment, the gate contact structures 1011 can be formed either with the source / drain contact plugs 1009 or otherwise using processes and materials similar to the source / drain contact plugs 1009 (e.g., a photolithographic masking and etching process followed by a conductive filling process). According to some embodiments, the first p-device 913 and the n-device 911 can share a common gate stack formed over the fins 107 of both devices, as shown in Fig. 10B is shown. Therefore, a single gate contact structure 1011 can be used as an external connection with the gate electrodes of both the first p-device 913 and the n-device 911. Fig.Figure 10B further shows that according to some embodiments the CMG connector 903 can be used to separate the metal gate stacks 95 of the n-device 911 from the metal gate stacks 95 of the second p-device 913.

[0094] According to one embodiment, a method comprises forming a fin over a semiconductor substrate; forming a metal gate over the fin; etching the metal gate to form a trench through the metal gate and into the semiconductor substrate; and depositing a dielectric material in the trench, wherein the dielectric material extends into the semiconductor substrate at an interface between an n-type device and a p-type device. In one embodiment, the trench extends no more than 40 nm into the semiconductor substrate after etching the metal gate. In another embodiment, the method comprises etching the metal gate into the semiconductor substrate and forming multiple recesses within the semiconductor substrate. In yet another embodiment, the etching of the metal gate further comprises a series of deposition-etching processes.In one embodiment, performing the series of deposition-etching processes includes depositing a dielectric sidewall liner prior to performing an etching process. In another embodiment, the method further includes planarizing the dielectric material. In another embodiment, the deposition of the dielectric material includes depositing silicon nitride.

[0095] According to one embodiment, the method comprises structuring a semiconductor substrate to form an insulating region and a fin within the semiconductor substrate; forming a metal gate stack over the fin and over the insulating region; performing multiple etching cycles to remove portions of the metal gate stack, the insulating region, and the semiconductor substrate to form an opening through the metal gate stack, the insulating region, and into the semiconductor substrate, wherein performing the multiple etching cycles separates a first portion of the metal gate stack and a second portion of the metal gate stack; and depositing a dielectric material to fill the opening. In one embodiment, the method further comprises performing the multiple etching cycles, depositing a liner, and etching through a portion of the liner.In one embodiment, performing the multiple etching cycles further comprises widening the openings after etching through the section of the liner. In one embodiment, the opening comprises a first recess within the semiconductor substrate and a second recess within the semiconductor substrate, the second recess being separate from the first recess. In one embodiment, the method further comprises planarizing the dielectric material with a top surface of the metal gate stack. In one embodiment, after planarizing the dielectric material, the dielectric material is continuous from a point within the first recess to a point within the second recess.In one embodiment, a width of the opening is formed at a height of an upper surface of the fin up to a first width, and a width at a height of the semiconductor substrate is formed up to a second width, which is smaller than the first width.

[0096] According to one embodiment, a semiconductor device comprises: a first gate electrode of an n-type device over a first fin over a semiconductor substrate; a second gate electrode of a p-type device over a second fin over the semiconductor substrate; and a cut-metal-gate connector that separates the first gate electrode from the second gate electrode, the cut-metal-gate connector extending into the semiconductor substrate at an interface between the n-type and the p-type devices. In one embodiment, the cut-metal-gate connector extends less than 40 nm into the semiconductor substrate. In another embodiment, the device further comprises an insulating region between the first fin and the second fin, the cut-metal-gate connector extending through the insulating region. In another embodiment, a source / drain contact structure of the n-type device is formed over the cut-metal-gate connector.In one embodiment, the cut-metal-gate connector comprises silicon nitride. In another embodiment, the device comprises a FinFET transistor configured with a first gate electrode having a V-trigger of between approximately 1850 mV and 1970 mV.

Claims

[1] Procedure, encompassing: Forming a fin (107) over a semiconductor substrate (101), Forming a metal gate (95) over the fin (107), Etching the metal gate (95) to form a trench (701) through the metal gate (95) and into the semiconductor substrate (101) between source / drain regions (901) of an n-type device (911) and a p-type device (913), and Deposition of a dielectric material (902) in the trench (701), wherein the dielectric material (902) extends into the semiconductor substrate (101) at an interface between the n-device (911) and the p-device (913); wherein the etching of the metal gate (95) in the semiconductor substrate (101) forms several separate recesses within the semiconductor substrate (101), the multiple recesses having a first recess in a first device area (106) for forming n devices and a second recess in a second device area (108) for forming p devices; wherein the dielectric material (902) is deposited with direct contact to an upper surface of the semiconductor substrate (101) between the first recess and the second recess. [2] Method according to claim 1, wherein the trench (701) extends no more than 40 nm into the semiconductor substrate (101) after etching the metal gate (95). [3] Method according to any of the preceding claims, wherein the etching of the metal gate (95) further comprises carrying out a series of deposition etching processes. [4] Method according to claim 3, wherein performing the series of deposition etching processes comprises depositing a dielectric sidewall liner (601, 703) prior to performing an etching process. [5] Method according to any of the preceding claims, further comprising planarizing the dielectric material (902). [6] Method according to any of the preceding claims, wherein the deposition of the dielectric material (902) deposits silicon nitride. [7] Procedures, comprehensive: Structuring a semiconductor substrate (101) to form an isolation region (105) and a fin (107) in the semiconductor substrate (101), Forming a metal gate stack (95) over the fin (107) and over the isolation area (105), Performing multiple etching cycles to remove sections of the metal gate stack (95), the isolation region (105) and the semiconductor substrate (101) to form an opening (701) through the metal gate stack (95), through the isolation region (105) and into the semiconductor substrate (101) between the source / drain regions (901) of adjacent n and p devices (911, 913), wherein performing the multiple etching cycles separates a first section of the metal gate stack (95) and a second section of the metal gate stack (95) and wherein the opening (701) has: a first recess within the semiconductor substrate (101) in a first device area (106) for forming n devices, and a second recess within the semiconductor substrate (101) in a second device area (108) for forming p-devices, wherein the second recess is separated from the first recess, and the procedure further includes: Deposition of a dielectric material (902) to fill the opening (701), wherein the dielectric material (902) is deposited with direct contact to an upper surface of the semiconductor substrate (101) between the first recess and the second recess. [8] The method of claim 7, wherein performing the multiple etch cycles further comprises: Deposition of a liner (601, 703), and Etching through a section of the liner (601, 703). [9] Method according to claim 8, wherein carrying out the multiple etching cycles further comprises widening the opening after etching through the section of the liner (601, 703). [10] Method according to any one of claims 7 to 9, further comprising planarizing the dielectric material (902) with an upper surface of the metal gate stack (95). [11] Method according to claim 10, wherein after planarizing the dielectric material (902) the dielectric material (902) is continuous from a point inside the first recess to a point inside the second recess. [12] Method according to any one of claims 7 to 11, wherein the width of the opening (701) at a height of an upper surface of the fin (107) is formed to a first width (W4), and the width at a height of the semiconductor substrate (101) is formed to a second width (W5) which is smaller than the first width (W4). [13] Semiconductor device (100), comprising: a first gate electrode (95) of an n-device (911) over a first fin (107) over a semiconductor substrate (101), a second gate electrode (95) of a p-device (913) over a second fin (107) over the semiconductor substrate (101), and a cut-metal-gate connector (903) that separates the first gate electrode (95) from the second gate electrode (95), wherein the cut-metal-gate connector (903) extends into the semiconductor substrate (101) between source / drain regions (901) of the n-device (911) and the p-device (913) at an interface between the n-device (911) and the p-device (913), wherein the cut-metal-gate connector (903) comprises several sections within the semiconductor substrate (101) separated from each other by a section of the semiconductor substrate (101), the several sections having a first section in a first device area (106) for forming n devices and a second section in a second device area (108) for forming p devices; wherein the cut metal gate connector (903) has direct contact with an upper surface of the semiconductor substrate (101) between the first section and the second section. [14] Semiconductor device (100) according to claim 13, wherein the cut metal gate connector (903) extends less than approximately 40 nm into the semiconductor substrate (101). [15] Semiconductor device (100) according to one of claims 13 to 14, which further comprises an isolation area (105) between the first fin (107) and the second fin (107), wherein the cut-metal-gate connector (903) extends through the isolation area (105). [16] Semiconductor device (100) according to one of claims 13 to 15, wherein a source / drain contact structure (901) of the n-device (911) is formed over the cut metal gate connector (903). [17] Semiconductor device (100) according to any one of claims 13 to 16, wherein the cut-metal-gate connector (903) comprises silicon nitride. [18] Semiconductor device (100) according to any one of claims 13 to 17, wherein a FinFET transistor formed with the first gate electrode (95) has a threshold voltage of between approximately 1850 mV and 1970 mV.

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