Semiconductor device and method for its manufacture

Abstract

Semiconductor device (200), comprising: a first plurality of GAA devices (250), gate-all-around devices, in a first device surface (10), each of the first plurality of GAA devices (250) comprising: a first vertical stack of channel elements (239-1) extending along a first direction, and a first plurality of inner spacers (230) which are nested with the first vertical stack of channel elements (239-1), a first gate structure (224A, 244B) above and around the first vertical stack of channel elements (239-1); and a second plurality of GAA devices (260) in a second device surface (20), each of the second plurality of GAA devices (260) comprising: a second vertical stack of channel elements (239-2) extending along a second direction, and a second plurality of inner spacers (230) which are nested with the second vertical stack of channel elements (239-2), a second gate structure (224C, 244D) above and around the second vertical stack of channel elements (239-2), wherein each of the first plurality of GAA devices (250) has a first channel length, wherein each of the second set of GAA devices (260) has a second channel length that is smaller than the first channel length, wherein the first plurality of inner spacers (230) and the second plurality of inner spacers (230) extend inwards to substantially the same extent; where each of the first gate structures (224A, 244B) has: a first upper gate feature (244A) arranged above a topmost channel element (239) of the first vertical stack of channel elements (239-1), and a plurality of first lower gate features (244B) arranged between two adjacent channel elements (239) of the first vertical stack of channel elements (239-1), where each of the second gate structures (224C, 244D) has: a second upper gate feature (244C) arranged above a topmost channel element (239) of the second vertical stack of channel elements (239-2), and a plurality of second lower gate features (244D) arranged between two adjacent channel elements (239) of the second vertical stack of channel elements (239-2), wherein the first upper gate feature (244A) has a first length (L1) along the first direction, wherein the second upper gate feature (244C) has a second length (L3) along the second direction, where the first length (L1) and the second length (L3) are essentially identical.

Description

BACKGROUND

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Over the course of IC development, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be created using a manufacturing process) has decreased. This downward scaling process generally offers advantages by increasing production efficiency and reducing associated costs. However, such downward scaling has also increased the complexity of machining and manufacturing ICs.

[0002] For example, with the evolution of integrated circuit (IC) technologies toward smaller technology nodes, multi-gate devices were introduced to improve gate control by increasing gate-channel coupling, thereby reducing reverse current and short-channel effects (SCEs). A multi-gate device generally refers to a device with a gate structure, or a portion thereof, that extends over more than one side of a channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around transistors (GAA transistors) (both also referred to here as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high-power, low-leakage-current applications.A FinFET has an elevated channel surrounded on more than one side by a gate (for example, the gate surrounds a top and side walls of a "fin" of semiconductor material extending from a substrate). Compared to planar transistors, such a configuration offers better channel control and drastically reduces SCEs (particularly by reducing leakage current below a threshold, i.e., coupling between a source and drain of the FinFET in the "off" state). A GAA transistor has a gate structure that can extend, partially or completely, around a channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor can be formed from nanowires, nanolayers, other nanostructures, and / or other suitable structures.In some implementations, such a channel region has multiple nanostructures (extending horizontally, thus providing horizontally oriented channels) that are vertically stacked. Such a GAA transistor can be referred to as a vertically stacked horizontal GAA transistor (VGAA transistor).

[0003] Several processes have been developed to fabricate different GAA transistors with varying threshold voltages in different device areas. These different voltages allow for stepwise activation of transistors in different device areas. It has been observed that these conventional processes can cause gate edge roughness and reduce process stability. Therefore, while conventional GAA devices are generally adequate for their intended purposes, they are not satisfactory in every respect. From US Publication 2018 / 0082902A1, a fabrication method for producing nano-sheet GAA transistors with different threshold voltages is known, where the GAAs have different channel lengths and the same physical gate stack length. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A, Fig. 1B and Fig. 1C jointly show a flowchart of a method for forming a semiconductor device with multiple device surfaces according to one or more aspects of the present disclosure. Fig. Figures 2, 3, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, 14A-14B, 15, 16, 17, 18, 19, 20, 21 and 22A-22B show cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 1A-1C, according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative expressions such as "below," "under," "lower," "above," "above," and the like may be used herein to facilitate description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative expressions are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive expressions used herein may be interpreted accordingly. Furthermore, when a number or range of numbers is described by "about," "approximately," and the like, the term is intended to include numbers that lie within + / - 10% of the number described, unless otherwise specified.For example, the term "about 5 nm" covers the dimensional range from 4.5 nm to 5.5 nm.

[0007] The present disclosure relates in general to multiple gate transistors and manufacturing processes and in particular to the fabrication of gate all-around transistors (GAA transistors) in various device areas of a semiconductor device.

[0008] Multiple-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multiple-gate devices can be p-metal-oxide semiconductor devices or n-metal-oxide semiconductor devices. Examples of multiple-gate transistors include FinFETs, due to their fin-like structure, and gate-all-around (GAA) devices. A GAA device includes any device whose gate structure, or a portion thereof, is formed on four sides of a channel region (e.g., surrounding a portion of a channel region).Embodiments of the present disclosure may include channel regions arranged in nanowire channels, rod-shaped channels, nanolayer channels, nanostructure channels, columnar channels, pin-shaped channels, and / or other suitable channel configurations. Devices according to the present disclosure may include one or more channel regions (e.g., nanowires, nanolayers, nanostructures) linked by a single, continuous gate structure. However, a person skilled in the art would recognize that the teachings in the present disclosure can be applied to a single channel (e.g., a single nanowire, a single nanolayer, a single nanostructure) or to any number of channels.An average person with expertise in this field can identify other examples of semiconductor devices that could benefit from aspects of the present disclosure.

[0009] With decreasing fin widths in FinFETs, channel width variations could cause undesirable variability and mobility loss. GAA transistors are being investigated as an alternative to FinFETs. In a GAA transistor, the transistor's gate is formed around the entire channel, so the channel is surrounded or encased by the gate. Such a transistor has the advantage of improving the electrostatic control of the channel by the gate, thereby also mitigating leakage currents. A GAA transistor incorporates various spacers, such as inner spacers and gate spacers (also called outer spacers, top spacers, or main spacers). Inner spacers serve to reduce capacitance and prevent leakage current between the gate structure and source / drain features. During the formation of a GAA transistor, gate spacers act as a mask during the formation of source / drain trenches.During the gate replacement process, gate spacers serve to maintain the integrity of the gate trenches after dummy gate stacks have been removed to make room for metal gate stacks. Methods according to the present disclosure are designed for fabricating GAA transistors with different threshold voltages by forming gate spacers of varying thicknesses in different areas.

[0010] In Fig. 1A-1C describes a method 100 for forming a semiconductor device with multiple device surfaces of multi-gate devices. As used here, the term "multi-gate device" is used to describe a device (e.g., a semiconductor device) that has at least some gate material arranged on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device, wherein gate material is arranged on at least four sides of at least one channel of the device. The channel region may be referred to as a nanowire, a nanolayer, a nanostructure, a channel element, or a semiconductor channel element, which, as used here, has channel regions of different geometries (e.g., cylindrical, rod-shaped, layered) and different dimensions.

[0011] As with the other process implementations and exemplary devices discussed here, it is clear that parts of the workpiece 200, which is in Fig. Figures 2, 3, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, 14A-14B, 15, 16, 17, 18, 19, 20, 21, and 22A-22B are shown and can be manufactured using a CMOS technology process sequence. Some processes are only briefly described here. After completion of the manufacturing process, the workpiece 200 is transformed into a semiconductor device 200. In this sense, the workpiece 200 can be referred to as the semiconductor device 200 in an appropriate context. Furthermore, the exemplary semiconductor devices may have various other devices and features, such as other types of devices containing additional transistors, bipolar transistors, resistors, capacitors, inductors, diodes, fuses, SRAM and / or other logic circuits, etc., but are simplified for a better understanding of the inventive concepts of the present disclosure.In some embodiments, the exemplary devices feature a multitude of semiconductor devices (e.g., transistors), including n-GAA transistors, p-GAA transistors, PFETs, NFETs, etc., which may be interconnected. Furthermore, it is noted that the process steps of Method 100, including all descriptions given with reference to the figures, are described below. Fig. 2, 3, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-108, 11A-11B, 12A-12B, 13A-13B, 14A-14B, 15, 16, 17, 18, 19, 20, 21 and 22A-22B, as well as the rest of the procedure and exemplary figures provided in this revelation, are only examples.

[0012] With reference to Fig. 1A, Fig. 2 and Fig. Section 3 comprises the process 100 block 102, where an epitaxial stack 204 is formed over a substrate 202. The epitaxial stack 204 has first semiconductor layers 206 and second semiconductor layers 208, which are stacked vertically in an alternating configuration. A workpiece 200 is in Fig. Figure 2 shows the workpiece 200 having a substrate 202, which can be a semiconductor substrate such as a silicon substrate. The substrate 202 can have various layers, including conductive or insulating layers, formed on a semiconductor substrate. The substrate 202 can have different doping configurations, depending on design requirements, as is known in the art. For example, different doping profiles (e.g., n-wells, p-wells) can be formed on the substrate 202 in areas designed for different device types (e.g., n-GAA transistors, p-GAA transistors). The appropriate doping can involve ion implantation of dopants and / or diffusion processes. The substrate 202 can have insulating features located between the areas that provide for different device types. The substrate 202 can also contain other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond.Alternatively, the substrate 202 can contain a compound semiconductor and / or an alloy semiconductor. Furthermore, the substrate 202 can optionally contain an epitaxial layer (epi-layer), can be stretched to increase performance, can contain a silicon-on-insulator (SOI) structure, and / or can include other suitable enhancement features. In one embodiment of method 100, an anti-punch-through implant (APT implant) is implemented. The APT implant can be implemented in a region located below the channel area of ​​a device to prevent, for example, punch-through or unwanted diffusion.

[0013] The epitaxial stack 204 has first semiconductor layers 206, between which second semiconductor layers 208 are located. The epitaxial stack 204 can also be referred to as a layer stack 204. As in Fig. As shown in Figure 2, the first semiconductor layers 206 and the second semiconductor layers 208 are arranged alternately and epitaxially along the Z-direction, so that they are nested. The compositions of the first semiconductor layers 206 and the second semiconductor layers 208 are different. In one embodiment, the first semiconductor layers 206 can be made of silicon germanium (SiGe) and the second semiconductor layers 208 can be made of silicon (Si). However, other embodiments are possible, including those that provide a first semiconductor composition and a second semiconductor composition with different oxidation rates and / or different etch selectivity.For example, both the first semiconductor layers 206 and the second semiconductor layers 208 can contain other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. For example, epitaxial growth of the layers of the epitaxial stack 204 can be carried out by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers, such as the second semiconductor layers 208, contain the same material as the substrate 202.In some embodiments, the first semiconductor layers 206 and second semiconductor layers 208 are essentially free of dopants (i.e., they have an extrinsic dopant concentration of about 0 cm). -3 up to about 1×10 17 cm -3 on), where, for example, no intentional doping is performed during the epitaxial growth process.

[0014] It is stated here that three (3) layers of the first semiconductor layers 206 and three (3) layers of the second semiconductor layers 208 are arranged alternately, as shown in Fig. 2 as also shown in other figures. It is clear that any number of epitaxial layers can be formed in the epitaxial stack 204. The number of layers depends on the desired number of channel elements for the device 200. In some embodiments, the number of second semiconductor layers 208 is between 2 and 10.

[0015] In some embodiments, each of the first semiconductor layers 206 has a thickness in the range of about 2 nanometers (nm) to about 6 nm, such as 3 nm in one specific example. The first semiconductor layers 206 can be of substantially uniform thickness. In some embodiments, each of the second semiconductor layers 208 has a thickness in the range of about 6 nm to about 12 nm, such as 9 nm in one specific example. In some embodiments, the second semiconductor layers 208 of the epitaxial stack 204 are of substantially uniform thickness. As described in more detail below, the second semiconductor layers 208, or portions thereof, can serve as channel element(s) for a subsequently formed multi-gate device, and the thickness is chosen based on device performance considerations.The first semiconductor layers 206 in the channel region(s) can eventually be removed and serve to define a vertical distance between adjacent channel region(s) for a subsequently formed multi-gate device, and the thickness is chosen based on considerations of device performance. Therefore, the first semiconductor layers 206 can also be referred to as sacrificial layers 206, and the second semiconductor layers 208 can also be referred to as channel layers 208.

[0016] With reference to Fig. 1A, Fig. 3, Fig. 4A, Fig. 4B, Fig. 5A and Fig. 5B, the procedure 100 comprises a block 104 where fin elements 211 are formed from the epitaxial stack 204. Referring first to Fig. 3. A fin top hard mask layer 210 can be deposited over the workpiece 200. The fin top hard mask layer 210 can be a single layer or a multiple layer. In some implementations, the fin top hard mask layer 210 can contain silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or a combination thereof. In embodiments where the fin top hard mask layer 210 is a multiple layer, the fin top hard mask layer 210 can have a silicon oxide layer deposited on the epitaxial stack and a silicon nitride layer deposited on the silicon oxide layer. The fin top hard mask layer 210 is used in a structuring process to structure the fin top hard mask layer 210 to form fin elements 211, which are in Fig. 4A and Fig. Figure 4B illustrates this. For example, the structuring process may include a lithography process (e.g., photolithography or E-beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure bake-out, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. The structuring process may be performed on the workpiece 200 until fin elements 211 extend from the substrate 202. In some embodiments, the structuring also etches into the substrate 202, such that each of the fin elements 211 has a lower section formed from the substrate 202 and an upper section from the epitaxial stack 204.The upper section features each of the epitaxial layers of the epitaxial stack 204, including sacrificial layers 206 and channel layers 208. In some embodiments, the fin elements 211 can be fabricated using dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than are otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers, or spikes, can then be used to structure the fin elements 211 by etching the epitaxial stack 204. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As in . Fig. 4A and Fig. As shown in Figure 4B, fin elements 211 extend longitudinally along the X-direction.

[0017] It will now be on Fig. 5A and Fig. Reference is made to Section 5B. Once the fin elements 211 are formed, an insulating feature 212 is formed between adjacent fin elements 211. The insulating feature 212 can also be referred to as a shallow trench insulation (STI) feature 212. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202, with the trenches between fin elements 211 being filled with the dielectric material. In some embodiments, the dielectric layer can contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials.In various examples, the dielectric layer can be deposited by a CVD process, a subatmospheric CVD process (SACVD process), a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or another suitable process. The deposited dielectric material is then thinned and planarized, for example, by a chemical-mechanical polishing (CMP) process. The planarized dielectric layer is further deepened by a dry etching process, a wet etching process, and / or a combination thereof to form the STI features 212. After deepening, at least the upper portions of the fin elements 211 protrude above the STI features 212. In some embodiments, the dielectric layer (and the subsequently formed STI features 212) can have a multilayered structure, for example, it can have one or more lining layers.

[0018] In some embodiments not shown separately in this disclosure, dielectric fins can also be formed at block 104 of process 100. In one exemplary process for forming dielectric fins, a slot extending parallel to the fin elements 211 is formed within the dielectric material for the STI feature 212, and dielectric fin material is then deposited into the slot. The dielectric fin material is distinct from the dielectric material forming the STI features 212. This allows the dielectric layer for the STI features 212 to be selectively etched, producing the dielectric fins that rise above the STI features 212. In some embodiments, the dielectric fin material can comprise silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, zirconium oxide, or other suitable materials.In embodiments employing dielectric fins, these fins are positioned between the fin elements 211 and serve to separate source / drain features of adjacent devices. The dielectric fins may also be referred to as dummy fins or hybrid fins. In some alternative embodiments, an upper portion of the dielectric fins can be removed during a gate-cutting process and replaced by an inverted material feature, which may be different from or the same as that of the dielectric fins. When formed, the dielectric fins limit the formation of epitaxial source / drain features and prevent unwanted fusion between adjacent epitaxial source / drain features.

[0019] With further reference to Fig. 1A, Fig. 6A, Fig. 6B, Fig. 7A and Fig. 7B comprises method 100 and a block 106 where dummy gate stacks 220 are formed over channel areas 30 of the fin elements 211. In some embodiments, a gate replacement process (or gate load process) is used, where the dummy gate stacks 220 serve as placeholders for metal gate stacks and are to be removed and replaced by the metal gate stacks in a subsequent process. Other processes and configurations are possible. It is now referred to Fig. 6A and Fig. Reference is made to Figure 6B. To form dummy gate stacks 220, a dielectric dummy layer 214, which may be made of silicon oxide, silicon nitride, or another suitable dielectric material, is first deposited over the workpiece 200 by a CVD process, a sub-atmospheric CVD process (SACVD process), a flowable CVD process, or an ALD process, containing the fin elements 211. The dielectric dummy layer 214 can be used to prevent damage to the fin elements 211 from subsequent processes (e.g., formation of the dummy gate stack). A dummy gate material layer 216, which may be made of polysilicon, is then deposited over the dielectric dummy layer 214. For structuring purposes, a gate top hard mask 218 can be deposited over the dummy gate material layer 216.The gate deck hard mask 218 can be a single layer or a multiple layer and can contain silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, or a combination thereof. In cases where the gate deck hard mask 218 is a multiple layer, it contains a silicon oxide layer deposited on the dummy gate material layer 216 and a silicon nitride layer deposited on the silicon oxide layer. The gate deck hard mask 218, the dummy gate material layer 216, and the dielectric dummy layer 214 are patterned in a structuring process that may include a lithography process (e.g., photolithography or E-beam lithography), followed by photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure bake-out, photoresist development, rinsing, and drying (e.g.,The etching process may include spin drying and / or hard baking), other suitable lithographic techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.

[0020] With reference to Fig. 7A and Fig. 7B Dummy gate stacks 220 are formed over the substrate 202 and are deposited at least partially over the fin elements 211. After structuring, the dummy gate material layer 216 is formed into a dummy electrode 216. The sections of the fin elements 211 that lie beneath the dummy gate stacks 220 constitute the channel region 30 of the fin element 211. The dummy gate stacks 220 can also define source / drain regions (S / D regions) 40 adjacent to and on opposite sides of the channel region 30. As shown in Fig. As shown in Figure 7A, each of the channel regions 30 can lie along the X-direction between two source / drain regions 40. In some embodiments, after formation of the dummy gate stack 220, the dielectric dummy layer 214 is removed from the source / drain regions 40 of the fin elements 211. That is, the dielectric dummy layer 214 that is not covered by the dummy electrode 216 is removed. The removal process can include wet etching, dry etching, and / or a combination thereof. The etching process is selected such that it selectively etches the dielectric dummy layer 214 without substantially etching the fin elements 211, the gate cover hard mask 218, and the dummy electrode 216. As shown in Figure 7A, the dielectric dummy layer 214 is selectively etched without substantially etching the fin elements 211, the gate cover hard mask 218, and the dummy electrode 216. Fig. As shown in Figure 7A, the dummy gate stacks 220 are arranged in the workpiece 200 with a uniform division P.

[0021] With reference to Fig. 1A, Fig. 8A and Fig. In 8B, the method 100 comprises a block 108 in which a gate spacer layer 221 is arranged over the substrate 202, containing over the dummy gate stacks 220. In some embodiments, spacer material for forming the gate spacer layer 221 is conformally deposited over the workpiece 200, containing over the top surfaces and side walls of the dummy gate stacks 220. The term "conformally" can be used here to simply describe a layer that has substantially uniform thickness over different regions. The gate spacer layer 221 may have a single-layer structure or may contain multiple layers. In some embodiments described in Fig. 8A and Fig. As shown in Figure 8B, the gate spacer layer 221 contains a single-layer structure. The gate spacer layer 221 can contain silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, other suitable dielectric material, or a combination thereof. The spacer material can be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric CVD (SACVD), flowable CVD, ALD, or another suitable process. The spacer material is then back-etched in an anisotropic etching process to form the gate spacer layer 221. The anisotropic etching process exposes sections of the fin elements 211 that are adjacent to and not covered by the dummy gate stack 220 (e.g., in source / drain regions 40). Although in Fig. 8A and Fig. Not explicitly shown in 8B, sections of the spacer material directly above the dummy gate stack 220 can be partially or completely removed by this anisotropic etching process, while the gate spacer layer 221 can remain on side walls of the dummy gate stack 220.

[0022] With reference to Fig. 1A, Fig. 9A and Fig. In 9B, the method 100 comprises a block 110 where a structural layer 224 is selectively formed over the gate spacer layer 221 in the first surface 10, while the gate spacer layer 221 is exposed in the second surface 20. In some embodiments, the structural layer 224 can be formed from a dielectric material or a polymeric material. For example, such a dielectric material can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or another suitable dielectric material. Such a polymeric material can be a photoresist material or polyimide. In some implementations, the polymeric material can contain fluorine and carbon in the form of a fluorocarbon functional group (CF3). x , x = 1, 2 or 3) or a functional carbon chloride group (CCl x, x = 1, 2 or 3). The structural layer 224 can be deposited using a chemical vapor deposition (CVD) process or a spin-on coating process. Compared to the unprotected / uncovered spacer layer 221 on dummy gate stacks 220 in the second face, the structural layer 224 in the first face 10 provides additional etch resistance to the gate spacer layer 221 on dummy gate stacks 220 in the first face 10. As subsequently described in conjunction with Fig. 12A and Fig. As described in 12B, such additional etch resistance can cause a thicker first gate spacer layer 222 in the first area 10 and a thinner second gate spacer layer 222' in the second area 20.

[0023] With reference to Fig. 1A, Fig. 10A and Fig. In 10B, the process 100 comprises a block 112 where source / drain grooves 227 or 227' are formed in the fin elements 211 using the first gate spacer layer 222, the structure layer 224, and the second gate spacer layer 222' as an etching mask. In some embodiments, source / drain regions 40 of the fin elements 211 in the first surface 10 are recessed to form first source / drain grooves 227, and source / drain regions 40 of the fin elements 211 in the second surface 20 are recessed to form second source / drain grooves 227'. Although not explicitly shown, a photolithography process and at least one hard mask can be used to perform operations in block 112. For example, the dry etching process can use an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g.,HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof are implemented. As described above in conjunction with Block 110, the etching in Block 112 etches and removes the structure layer 224 before the first gate spacer layer 222 is etched. The implementation of the structure layer 224 slows down the thinning of the gate spacer layer 221 in the first area 10, resulting in the first gate spacer layer 222 being thicker than the second gate spacer layer 222'. In some embodiments, the first gate spacer layer 222 has a first thickness T1 and the second gate spacer layer 222' has a second thickness T2. In some cases, the first thickness T1 is greater than the second thickness T2, with a difference between about 0.5 nm and about 5 nm.Due to the thickness difference between the first gate spacer layer 222 and the second gate spacer layer 222' and the uniform spacing P across the workpiece 200, the first source / drain grooves 227 in the first surface 10 are narrower than the second source / drain groove 227' in the second surface 20. The first source / drain grooves 227 in the first surface 10 have a first spacing S1 along the X-direction, and the second source / drain groove 227' in the second surface 20 has a second spacing S2 along the X-direction. The second spacing S2 is greater than the first spacing S1. In some cases, the first spacing S1 is between approximately 10 nm and approximately 40 nm, and the second spacing S2 is between approximately 15 nm and approximately 45 nm. In some embodiments, shown in . Fig. 10A and Fig. In 10B, the upper section of the fin elements 211 is sunken to expose the sacrificial layers 206 and the channel layers 208. In some implementations, at least one section of the lower section of the fin elements 211 is also sunken. That is, the first source / drain trenches 227 and the second source / drain trench 227' may extend below the lowest sacrificial layer 206 in the first area 10 and the second area 20. After completion of operations in block 112, the source / drain areas 40 of the fin elements 211 are at the same level as, or lower than, the upper surface of the STI features 212.

[0024] Alternative configurations of establishments in Block 110 and Block 112 are described in Fig. 11A, Fig. 11B, Fig. 12A and Fig. Figure 12B shows that in these alternative embodiments, no structural layer 224 is selectively deposited in the first surface 10. Instead, after the formation of the gate spacer layer 221 over the workpiece 200 in block 108, the first source / drain grooves 227 in the first surface 10 and the second source / drain groove 227' in the second surface 20 are formed separately. As shown in Fig. 11A and Fig. As shown in Figure 11B, a first photoresist layer 226-1 is selectively deposited in the first surface 10, and the fin elements 211 in the second surface 20 of the workpiece 200 are anisotropically etched in a first back-etching process to form the second source / drain groove 227'. Then, as shown in Fig. 12A and Fig. As shown in Figure 12B, a second photoresist layer 226-2 is selectively deposited in the second area 20, and the fin elements 211 in the first area 10 of the workpiece 200 are anisotropically etched in a second back-etch process to form the first source / drain grooves 227. The parameters of the first and second back-etch processes can differ, such that the first back-etch process etches the gate spacer layer 221 in the second area 20 faster than the second back-etch process etches the gate spacer layer in the first area 10. For example, the first back-etch process can involve a different etchant, a lower process pressure, a higher preload, a higher plasma density, a more reactive etchant, or a higher temperature than the second back-etch process.

[0025] With reference to Fig. 1A, Fig. 13A and Fig. 13B comprises method 100 block 114, where the first semiconductor layers 206 in the fin elements 211 are recessed in the first surface 10 and second surface 20 to form internal spacer recesses 228. In some embodiments, shown in Fig. 13A and Fig. In 13B, the sacrificial layers 206, which are exposed in the first source / drain trenches 227 and the second source / drain trench 227', are selectively and partially deepened to form internal spacer depressions 228, while the exposed channel layers 208 remain essentially unetched. In an embodiment where the channel layers 208 consist essentially of Si and the sacrificial layers 206 consist essentially of SiGe, the selective deepening of the sacrificial layers 206 may include a SiGe oxidation process followed by SiGe oxide removal. In these embodiments, the SiGe oxidation process may involve the use of ozone. In some embodiments, the selective deepening may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layers 206 are deepened is controlled by the duration of the etching process.In some embodiments, the selective dry etching process may include one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. As in . Fig. 13A and Fig. As shown in Figure 13B, the internal spacer recesses 228 extend inwards from the first source / drain grooves 227 in the first surface 10 or from the second source / drain groove 227' in the surface. In some embodiments, the selective wet etching process may include a hydrofluoride (HF) or NH4OH etchant. Although the first gate spacer layer 222 in the first surface 10 and the second gate spacer layer 222' in the second surface 20 have different thicknesses, the internal spacer recesses 228 have substantially uniform dimensions over the workpiece 200. That is, the internal spacer recesses 228 in the first surface 10 and the internal spacer recesses 228 in the second surface 20 extend inwards into the sacrificial layers 206 to substantially the same extent.

[0026] With reference to Fig. 1B, Fig. 14A and Fig. In 14B, the method 100 comprises a block 116 where internal spacers 230 are formed in the internal spacer recesses 228. In some embodiments, an internal spacer layer can be deposited over the workpiece 200 by CVD, PECVD, LPCVD, ALD, or another suitable method. The internal spacer layer can be formed from aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, low-k material, another suitable metal oxide, or a combination thereof.In some implementations, the inner spacer layer can be conformally deposited over the top surface of the gate top hard mask 218, the top surfaces and sidewalls of the first gate spacer layer 222, the top surfaces and sidewalls of the second gate spacer layer 222', and sections of the substrate 202 exposed in the first source / drain trenches 227 and the second source / drain trench 227'. Subsequently, the deposited inner spacer layer can be back-etched to form inner spacers 230 in the inner spacer recesses 228. In the back-etching process, the inner spacer layer is removed outside the inner spacer recesses 228.

[0027] With reference to Fig. 1B and Fig. In section 15, the method 100 comprises a block 118 where the epitaxial source / drain features 232 are located in the first source / drain trenches 227 and the second source / drain trenches 227'. Since the formation of the epitaxial source / drain features 232 is essentially the same over the entire workpiece 200, the formation of the epitaxial source / drain feature 232 in the first surface 10 and the second surface 20 is summarized in Fig. Figure 15 shows that, although not shown separately in the figures of this disclosure, the epitaxial source / drain features 232 can comprise an epitaxial n-source / drain feature for n devices and an epitaxial p-source / drain feature for p devices. In some embodiments, epitaxial n-source / drain features of n devices can be formed jointly in the workpiece 200, while epitaxial p-source / drain features of p devices can be formed jointly in the workpiece 200 in a preceding or subsequent process. The epitaxial source / drain features 232 can be formed using suitable epitaxial processes, such as CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. Exemplary epitaxial n-source / drain features may include Si, GaAs, GaAsP, SiP or other suitable material.The epitaxial n-source / drain features can be doped in situ during the epitaxial process by introducing dopant species containing n-dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the n-epitaxial source / drain features are not doped in situ, an implantation process (i.e., a transition implantation process) is performed to dope the epitaxial n-source / drain features. Exemplary epitaxial p-source / drain features can contain Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material. The epitaxial p-source / drain features can be doped in situ during the epitaxial process by introducing dopant species containing p-dopants, such as boron or BF₂, and / or other suitable dopants, including combinations thereof.If the p-epitaxial source / drain features are not doped in situ, an implantation process (i.e., a transitional implantation process) is performed to dope the epitaxial p-source / drain features.

[0028] With reference to Fig. 1B and Fig. In section 16, the process 100 comprises a block 120 where an interlayer dielectric layer (ILD layer) 236 is formed over the epitaxial source / drain features 232. Since the formation of the ILD layer 236 is essentially the same over the entire workpiece 200, the formation of the ILD layer 236 in the first surface 10 and the second surface 20 is summarized in Fig. Figure 16 shows that in some embodiments, a contact etch stop layer (CESL layer) 234 is first deposited on the epitaxial source / drain features 232. In some examples, the CESL 234 comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 234 can be formed by ALD, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. Then, the ILD layer 236 is deposited over the CESL 234. In some embodiments, the ILD layer 236 contains materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon oxide such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.The ILD layer 236 can be deposited by a PECVD process or another suitable deposition technique. In some embodiments, after the formation of the ILD layer 236, the workpiece 200 can be annealed to improve the integrity of the ILD layer 236. After deposition and annealing of the ILD layer 236, the workpiece 200 is planarized, for example, by a chemical-mechanical polishing process (CMP process), to form a flat surface for further processing.

[0029] With reference to Fig. 1B and Fig. In section 17, the process 100 comprises a block 122 where the dummy gate stacks 220 are removed to form gate trenches 238. Since the removal of the dummy gate stacks 220 is essentially the same over the entire workpiece 200, the removal of the dummy gate stacks 220 in the first surface 10 and the second surface 20 is summarized in Fig. Figure 17 shows that in the illustrated embodiment, an etching process completely removes dummy gate stacks 220 to expose sacrificial layers 206 and channel layers 208 in channel regions 30. The etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. The etching process can be selected to be selective for the dummy gate stacks 220 and essentially not etch the CESL 234 and the ILD layer 236. In some implementations, shown in Fig. 17, both the dummy gate stack 220 and the dielectric dummy layer 214 are removed from channel area 30 to expose the sacrificial layers 206 and channel layers 208 in channel areas 30.

[0030] With reference to Fig. 1B and Fig. In section 18, the process 100 comprises a block 124 where the second semiconductor layers 208 are dissolved in the channel regions of the fin elements 211 to form channel elements 239. Since the solution of the second semiconductor layers 208 is essentially the same over the entire workpiece 200, the solution of the second semiconductor layers 208 in the first area 10 and the second area 20 is summarized in Fig. Figure 18 shows that in the illustrated embodiment, an etching process selectively etches the first semiconductor layer 206 (i.e., sacrificial layers 206) with minimal or no etching of second semiconductor layers 208 (i.e., channel layers 208) and, in some embodiments, minimal or no etching of the first gate spacer layer 222, the second gate spacer layer 222', and / or the inner spacers 230. Various etching parameters can be adjusted to achieve selective etching of the first semiconductor layers 206, such as etchant composition, etch temperature, etch solution concentration, etch time, etch pressure, source power, RF bias, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof.For example, an etchant is selected for the etching process that etches the material of the first semiconductor layers 206 (in the illustrated embodiment, silicon germanium) at a higher rate than the material of the second semiconductor layers 208 (in the illustrated embodiment, silicon) (i.e., the etchant has high etch selectivity with respect to the material of the first semiconductor layers 206). The etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, a dry etching process (such as a RIE process) uses a fluorine-containing gas (for example, SF6) to selectively etch the first semiconductor layers 206 (i.e., sacrificial layers 206).In some embodiments, the ratio of the fluorine-containing gas to an oxygen-containing gas (for example, O₂ or O₃), an etching temperature, and / or an RF power can be adjusted to selectively etch silicon germanium or silicon. In some embodiments, a wet etching process uses an etching solution containing ammonium hydroxide (NH₄OH) and water (H₂O) to selectively etch the first semiconductor layers 206 (i.e., sacrificial layers 206). In some embodiments, a chemical vapor-phase etching process using hydrochloric acid (HCl) selectively etches the first semiconductor layers 206 (i.e., sacrificial layers 206). After completion of the operations in block 124, the channel layers 208 are suspended in the channel regions 30 and can be referred to as channel elements 239. As will be explained in more detail below in conjunction with... Fig. 22A and Fig. As described in 22B, channel elements 239 in the first surface 10 can have a greater channel length along the X direction than those in the second surface 20 due to the thicker first gate spacer layer 222 in the first surface 10.

[0031]

[0031] With reference to Fig. 1C and Fig. 19 The method 100 comprises a block 126 where a gate dielectric layer 242 is formed around the channel elements 239. Since the formation of the gate dielectric layer 242 is essentially the same over the entire workpiece 200, the formation of the gate dielectric layer 242 in the first surface 10 and the second surface 20 is summarized in Fig. Figure 19 shows that in some embodiments, an interface layer 240 can be formed on the channel elements 239 to provide adhesion between the channel elements 239 and the gate dielectric layer 242. In some implementations, the interface layer 240 can contain a dielectric material such as silicon dioxide, hafnium silicate, or silicon oxynitride. The interface layer 240 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer 242 is deposited over and around the channel element(s) 239 and can contain one or more high-k dielectric materials. High-k dielectric materials, as used and described here, contain dielectric materials with a high dielectric constant, for example, greater than that of thermal silicon dioxide (~3.9).Exemplary high-k dielectric materials for the gate dielectric layer 242 can include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3Si3N4, oxynitrides (SiON), other high-k dielectric materials, or combinations thereof. The gate dielectric layer 242 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0032]

[0032] With reference to Fig. 1C and Fig. In section 20, the process 100 comprises a block 128 where metal gate stacks 244 are formed. Since the formation of the metal gate stacks 244 is essentially the same over the entire workpiece 200, the formation of the metal gate stacks 244 in the first surface 10 and the second surface 20 is summarized in Fig. Figure 20 shows that, although not shown separately, the metal gate stacks 244 can have one or more exit work layers and one or more metal fill layers. In some implementations, different exit work layer stacks can be formed in n-device and p-device regions. In these implementations, while n-device regions and p-device regions may share certain common exit work layers, n-device regions may have one or more exit work layers that are not present in the p-device regions. Similarly, in alternative implementations, p-device regions may have one or more exit work layers that are not present in the n-device regions.The P-exit work layer contains any suitable p-exit work material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-exit work materials, or combinations thereof. The N-exit work layer contains any suitable n-exit work material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-exit work materials, or combinations thereof. It is noted that p-exit work layers are not limited to use in p-type equipment, and n-exit work layers are not limited to use in n-type equipment. P-exit work layers and n-exit work layers can be applied in n-device regions and p-device regions to achieve a desired threshold stress. In some embodiments, the metal gate stack 244 may have one or more metal filler layers.For example, a CVD or PVD process deposits one or more metal filler layers onto n-exit work layer(s) and p-exit work layer(s) such that the metal filler layer fills all remaining sections of gate trenches 238. The metal filler layer may contain a suitable conductive material, such as Al, W, and / or Cu. The metal filler layer may additionally or generally contain other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0033]

[0033] With reference to Fig. 1C and Fig. In section 21, the process 100 comprises a block 130 where the workpiece 200 is planarized to provide a flat surface. Since the planarization in block 130 is essentially the same over the entire workpiece 200, the planarization in the first surface 10 and the second surface 20 is summarized in Fig. Figure 21 shows that in some embodiments, planarization is performed to remove excess interface layer 240, gate dielectric layer 242, and the metal gate stack 244 above the workpiece 200. For example, planarization may include a CMP process and may be performed until a cover surface of an ILD layer 236 is substantially in the same plane as a cover surface of the metal gate stack 244.

[0034]

[0034] It will now be on Fig. 22A and Fig. Reference is made to 22B. After completion of the operations in block 130, a first GAA transistor 250, shown in Fig. 22A, in the first area 10 of the semiconductor device 200 are formed and a second GAA transistor 260, shown in Fig. 22B, can be formed in the second area 20 of the semiconductor device 200. As in Fig. As shown in Figure 22A, the first gate spacer layer 222 with the greater initial thickness T1 leads to first channel elements 239-1 of a first width W1 along the X direction. Due to the thicker first gate spacer layer 222, each metal gate stack 244 in the first face 10 has a first upper gate feature 2,4,4A, which is arranged on the uppermost channel element 239, and first lower gate features 244B, each of which is inserted / arranged between two adjacent channel elements 239. The first upper gate feature 244A has a first gate length L1, and each of the first lower gate features 244B has a second gate length L2. The epitaxial source / drain feature 232 in the first face 10 has a second width W2. Since the dummy gate division P is uniform over the workpiece 200, P is equal to the sum of the first width W1 and the second width W2 in the first surface 10.In some embodiments, P is between about 30 nm and about 60 nm; W1 is between about 16 nm and about 46 nm; W2 is between about 9 nm and about 40 nm; L1 is between about 5 nm and about 20 nm; and L2 is between about 6 nm and about 30 nm. As in . Fig. As shown in Figure 22B, the second gate spacer layer 222' with the smaller second thickness T2 leads to second channel elements 239-2 of a third width W3 along the X direction. Each metal gate stack 244 in the second surface 20 has a second upper gate feature 244C, which is arranged on the uppermost channel elements 239, and second lower gate features 244D, each of which is inserted / arranged between two adjacent channel elements 239. The second upper gate feature 244C has a third gate length L3, and each of the second lower gate features 244D has a fourth gate length L4. The epitaxial source / drain feature 232 in the second surface 20 has a fourth width W4. Since the dummy gate division P is uniform over the workpiece 200, P is equal to a summation of the third width W3 and the fourth width W4 in the second surface 20.In some embodiments, P is between about 30 nm and about 60 nm; W3 is between about 15 nm and about 45 nm; W4 is between about 10 nm and about 40 nm; L3 is between about 5 nm and about 20 nm; and L4 is between about 5 nm and about 20 nm. In embodiments described in . Fig. As shown in Figure 22B, the third gate length L3 is essentially identical to the fourth gate length L4.

[0035]

[0035] It can be seen that, with the exception of the first upper gate feature 244A, the first GAA transistor 250 is characterized by the second gate length L2. The second GAA transistor 260 is characterized by the third gate length L3. In embodiments described in Fig. 22A and Fig. As shown in Figure 22B, the second gate length L2 can be larger than the third gate length L3, with a difference of between approximately 1 nm and approximately 10 nm. It has been observed that the leakage current of a GAA transistor can decrease with increasing gate length, and the threshold voltage of the GAA transistor can increase with increasing leakage current. Since the second gate length L2 of the first GAA transistor 250 is larger than the third gate length L3 of the second GAA transistor 260, the first GAA transistor 250 exhibits a lower leakage current and a higher threshold voltage than the second GAA transistor 260. In some cases, the first GAA transistor 250 exhibits a first threshold voltage (VT1), and the second GAA transistor 260 exhibits a second threshold voltage (VT2).By implementing both the first GAA transistors 250 in the first area 10 and the second GAA transistors 260 in the second area 20, the semiconductor device 200 according to the present disclosure can have GAA transistors with different threshold voltages - the first threshold voltage (VT1) and the second threshold voltage (VT2).

[0036]

[0036] With reference to Fig. In 1C, process 100 comprises a block 132 where further processes are carried out. Manufacturing can continue to produce the semiconductor device 200. For example, various contacts can be formed to facilitate the operation of GAA transistors in the semiconductor device 200. For example, one or more ILD layers, similar to ILD layer 236, and / or CESL layers can be formed over the substrate 202 (in particular over ILD layer 236 and metal gate stacks 244). Then, contacts can be formed in ILD layer 236 and / or ILD layers arranged over ILD layer 236. For example, contacts are each electrically and / or physically coupled to metal gate stacks 244, and contacts are each electrically and / or physically coupled to source / drain regions of the GAA transistors. Since the epitaxial source / drain features 232 in the first surface 10 (along the X-direction, which in Fig. 22A and Fig.(as shown in Figure 22B) are narrower than those in the second area 20, the source / drain contacts for first GAA transistors 250 in the first area 10 can be narrower than the source / drain contacts for second GAA transistors 260 in the second area 20. Contacts contain a conductive material such as aluminum, aluminum alloy (such as aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. In some embodiments, a metal silicide layer can be formed at the interface between the epitaxial source / drain features 232 and the source / drain contact. The metal silicide may contain nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide or combinations thereof.In some implementations, ILD layers arranged above ILD layer 236 and the contacts (which extend, for example, through ILD layer 236 and / or the other ILD layers) are a section of a multilayer interconnect structure (MLI structure).

[0037]

[0037] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Semiconductor device (200), comprising: a first plurality of GAA devices (250), gate-all-around devices, in a first device surface (10), each of the first plurality of GAA devices (250) comprising: a first vertical stack of channel elements (239-1) extending along a first direction, and a first plurality of inner spacers (230) which are nested with the first vertical stack of channel elements (239-1), a first gate structure (224A, 244B) above and around the first vertical stack of channel elements (239-1); and a second plurality of GAA devices (260) in a second device surface (20), each of the second plurality of GAA devices (260) comprising: a second vertical stack of channel elements (239-2) extending along a second direction, and a second plurality of inner spacers (230) which are nested with the second vertical stack of channel elements (239-2), a second gate structure (224C, 244D) above and around the second vertical stack of channel elements (239-2), wherein each of the first plurality of GAA devices (250) has a first channel length, wherein each of the second set of GAA devices (260) has a second channel length that is smaller than the first channel length, wherein the first plurality of inner spacers (230) and the second plurality of inner spacers (230) extend inwards to substantially the same extent; where each of the first gate structures (224A, 244B) has: a first upper gate feature (244A) arranged above a topmost channel element (239) of the first vertical stack of channel elements (239-1), and a plurality of first lower gate features (244B) arranged between two adjacent channel elements (239) of the first vertical stack of channel elements (239-1), where each of the second gate structures (224C, 244D) has: a second upper gate feature (244C) arranged above a topmost channel element (239) of the second vertical stack of channel elements (239-2), and a plurality of second lower gate features (244D) arranged between two adjacent channel elements (239) of the second vertical stack of channel elements (239-2), wherein the first upper gate feature (244A) has a first length (L1) along the first direction, wherein the second upper gate feature (244C) has a second length (L3) along the second direction, where the first length (L1) and the second length (L3) are essentially identical. [2] Semiconductor device (200) according to claim 1, wherein each of the plurality of first lower gate features (244B) has a third length (L2) along the first direction, wherein each of the multiple second lower gate features (244D) has a fourth length (L4) along the second direction, where the third length (L2) is greater than the fourth length (L4). [3] Semiconductor device (200) according to claim 2, wherein the fourth length (L4) is substantially identical to the first length (L1). [4] Semiconductor device (200) according to claim 2 or 3, where the third length (L2) is between approximately 6 nm and approximately 30 nm, where the fourth length (L4) is between about 5 nm and about 20 nm. [5] Semiconductor device (200) according to any one of the preceding claims 2 to 4, wherein each of the first plurality of GAA devices (250) further comprises a first gate spacer (222) arranged along the first upper gate feature (244A), wherein each of the second plurality of GAA devices (260) further comprises a second gate spacer (222') arranged along the second upper gate feature (244C), wherein the first gate spacer (222) has a first thickness (T1), wherein the second gate spacer (222') has a second thickness (T2) that is smaller than the first thickness (T1). [6] Semiconductor device (200) according to claim 5, wherein the difference between the first thickness (T1) and the second thickness (T2) is between about 0.5 nm and about 5 nm. [7] Semiconductor device (200) according to any one of the preceding claims, wherein the first plurality of GAA devices (250) has a first gate division (P), wherein the second plurality of GAA devices (260) has a second gate division (P) that is identical to the first gate division (P). [8] Semiconductor device (200) according to any one of the preceding claims, wherein each of the first plurality of GAA devices (250) has a first source / drain feature (232), wherein each of the second set of GAA devices (260) has a second source / drain feature (232), where a width (W2) of the first source / drain feature (232) along the first direction is smaller than a width (W4) of the second source / drain feature (232) in the second direction. [9] Semiconductor device (200) according to any one of the preceding claims, wherein each of the first plurality of GAA devices (250) has a first threshold voltage (VT1), wherein each of the second set of GAA devices (260) has a second threshold voltage (VT2) which is smaller than the first threshold voltage (VT1). [10] Semiconductor device (200), comprising: a first plurality of GAA devices (250), gate-all-around devices, in a first device surface (10), each of the first plurality of GAA devices (250) comprising: a first vertical stack of channel elements (239-1) extending along a first direction, a first plurality of inner spacers (230) which are nested with the first vertical stack of channel elements (239-1), a first upper gate feature (244A) arranged above a topmost channel element (239) of the first vertical stack of channel elements (239-1), and a plurality of first lower gate features (244B) arranged between two adjacent channel elements (239) of the first vertical stack of channel elements (239-1); and a second plurality of GAA devices (260) in a second device surface (20), each of the second plurality of GAA devices (260) comprising: a second vertical stack of channel elements (239-2) extending along a second direction, a second plurality of inner spacers (230) which are nested with the second vertical stack of channel elements (239-2), a second upper gate feature (244C) arranged above a topmost channel element (239) of the second vertical stack of channel elements (239), and a plurality of second lower gate features (244D) arranged between two adjacent channel elements (239) of the second vertical stack of channel elements (239-2), wherein the first upper gate feature (244A) has a first length (L1) along the first direction, wherein the second upper gate feature (244C) has a second length (L3) along the second direction, where the first length (L1) and the second length (L3) are essentially identical, wherein each of the plurality of first lower gate features (244B) has a third length (L2) along the first direction, wherein each of the multiple second lower gate features (244D) has a fourth length (L4) along the second direction, where the third length (L2) is greater than the fourth length (L4), wherein the first plurality of inner spacers (230) and the second plurality of inner spacers (230) extend inwards to substantially the same extent. [11] Semiconductor device (200) according to claim 10, wherein the fourth length (L4) is substantially identical to the first length (L1). [12] Semiconductor device (200) according to claim 10 or 11, wherein each of the first plurality of GAA devices (250) further comprises a first gate spacer (222) arranged along the first upper gate feature (244A), wherein each of the second plurality of GAA devices (260) further comprises a second gate spacer (222') arranged along the second upper gate feature (244C), wherein the first gate spacer (222) has a first thickness (T1), wherein the second gate spacer (222') has a second thickness (T2) which is smaller than the first thickness (T1). [13] Semiconductor device (200) according to any one of the preceding claims 10 to 12, wherein the first plurality of GAA devices (250) has a first gate division (P), wherein the second plurality of GAA devices (260) has a second gate division (P) that is identical to the first gate division (P). [14] Semiconductor device (200) according to any one of the preceding claims 10 to 13, wherein each of the first plurality of GAA devices (250) has a first source / drain feature (232), wherein each of the second set of GAA devices (260) has a second source / drain feature (232), where a width (W2) of the first source / drain feature (232) along the first direction is smaller than a width (W4) of the second source / drain feature (232) in the second direction. [15] Method for manufacturing a semiconductor device (200), comprising: Forming, on a substrate (202), a layer stack (204) comprising a plurality of first semiconductor layers (206) nested with a plurality of second semiconductor layers (208); Forming a first plurality of fin elements (211) from the layer stack (204) in a first area (10) of the substrate (202); Forming a second plurality of fin elements (211) from the layer stack (204) in a second area (20) of the substrate (202); Forming a first plurality of dummy gate stacks (220) over the first plurality of fin elements (211); Forming a second plurality of dummy gate stacks (220) over the second plurality of fin elements (211); Deposition of a spacer layer (221) over the first plurality of dummy gate stacks (220) and the second plurality of dummy gate stacks (220); selective deposition of a polymeric layer (224) over the spacer layer (221) arranged over the first plurality of dummy gate stacks (220), while the spacer layer (221) arranged over the second plurality of dummy gate stacks (220) is not covered by the polymeric layer (224); and Etching the spacer layer (221) over the first plurality of dummy gate stacks (220) and the second plurality of dummy gate stacks (220), wherein the polymeric layer (224) slows down the thinning of the spacer layer (221) in the first area (10), such that a first gate spacer layer (222) in the first area (10) is thicker than a second gate spacer layer (222') in the second area (20), using the first gate spacer layer (222), the polymer layer (224) and the second gate spacer layer (222') as an etching mask: forming a first plurality of source / drain trenches (227) in the first surface (10) to expose sidewalls of the first plurality of fin elements (211), and forming a second plurality of source / drain trenches (227') in the second surface (20) to expose sidewalls of the second plurality of fin elements (211); and Partial etching of the plurality of first semiconductor layers (206) in the first plurality of fin elements (211) and the second plurality of fin elements (211) to form internal spacer recesses (228), wherein the internal spacer recesses (228) in the first plurality of fin elements (211) and the second plurality of fin elements (211) extend inwards to substantially the same extent. [16] Method according to claim 15, wherein the polymeric layer (224) contains carbon and fluorine. [17] Method according to claim 15 or 16, wherein the first gate spacer layer (222) has a first thickness (T1) and the second gate spacer layer (222') has a second thickness (T2), where the first thickness (T1) is greater than the second thickness (T2), and where the difference between the first thickness (T1) and the second thickness (T2) is between 0.5 nm and about 5 nm. [18] Method according to any one of claims 15 to 17, wherein the first plurality of source / drain trenches (227) in the first area (10) has a first distance (S1) along a first direction (X) between side walls of the first gate spacer layer (222') and the second plurality of source / drain trenches (227)' in the second area (20) has a second distance (S2) along the first direction (X) between side walls of the second spacer layer (222'), wherein the second distance (S2) is greater than the first distance (S1), such that the first plurality of source / drain trenches is narrower than the second. [19] Method according to claim 18, wherein the first distance (S1) is between 10 nm and 40 nm and the second distance (S2) is between 15 nm and 45 nm.

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