LEVEL CONVERTERS AND LEVEL CONVERTER METHOD

Abstract

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

Description

BACKGROUND

[0001] Many electronic devices, such as desktop computers, laptops, tablets, and smartphones, use multiple integrated circuits, often in conjunction with several discrete semiconductor devices, to process and store information. Some electronic devices use multiple voltage levels to power their various integrated circuits and discrete semiconductor devices. Voltage level converters can be used to convert and adapt the voltage levels of digital signals between integrated circuits using different voltages.

[0002] US 9,806,716 B2 describes an output signal generation circuit for converting an input signal from a source voltage range into an output signal for a target voltage range, wherein the target voltage range is operated with a supply voltage that exceeds a load threshold of components within the output signal generation circuit. The output signal generation circuit may include a level-shifting circuit that is operated with the supply voltage and configured to generate the output signal for the target voltage domain at an output node as a function of the input signal.The output signal generation circuit can also include a tracking circuit connected to at least one component of the level conversion circuit to ensure that a voltage drop across the at least one component does not exceed the load threshold, with the tracking circuit additionally introducing a delay when the output signal changes in response to a change in the input signal.

[0003] EP 2 908 434 A1 describes a level shifter and high-voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage fluctuations of the input and output signals. The level shifter comprises a driver circuit and a latch. The driver circuit receives an input signal with a first voltage range and provides a drive signal with a second voltage range. The first and second voltage ranges can cover positive and negative voltages or different ranges of positive voltages. The latch receives the driver signal and provides an output signal with the second voltage range. The driver circuit generates a control signal with a full voltage range based on the input signal and then generates the drive signal based on the control signal.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, several features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced for clarity. Fig. Figure 1 is a circuit diagram of an example of a level converter according to some embodiments. Fig. Figure 2 is a circuit diagram illustrating the level converter, including alternative examples of an input circuit and a delay circuit, according to some embodiments. Fig. Figure 3 is a circuit diagram illustrating the level shifter, including an alternative example of a cross-latch circuit, according to some embodiments. Fig. Figure 4 is a circuit diagram illustrating the level converter, including alternative examples of the input circuit and the delay circuit, according to some embodiments. Fig. Figure 5 is a circuit diagram illustrating the level converter, including an alternative example of the input circuit, according to some embodiments. Fig. Figure 6 is a circuit diagram illustrating the level shifter, including an alternative example of the cross-latch circuit, according to some embodiments. Fig. Figure 7 is a circuit diagram illustrating the level shifter, including another alternative example of the cross-latch circuit, according to some embodiments. Fig. 8 is a circuit diagram showing the level converter of the Fig. Figure 2 illustrates various NMOS and PMOS components, which are identified according to some embodiments. Fig. Figure 9 is a block diagram illustrating aspects of a symmetrical layout of the level converter. Fig. 8 illustrated according to some embodiments. Fig. Figure 10 is a block diagram that shows aspects of another symmetrical layout for the level converter of the Fig. 8 illustrated according to some embodiments. Fig. Figure 11 is a block diagram illustrating aspects of an asymmetrical layout for the level converter of the Fig. 8 illustrated according to some embodiments. Fig. Figure 12 is a flowchart illustrating a level conversion method according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of the implementation of various features of the presented subject matter. Specific examples of the components and arrangements are described below to simplify the present disclosure. The formation of a first feature over or on top of a second feature in the description that follows may, for example, include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the FIGS. The device may also be oriented differently (rotated by 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] Fig. Figure 1 is a block diagram illustrating aspects of an overload level converter 100 according to disclosed embodiments. The level converter 100 comprises a cross-latch circuit 110, an input circuit 120, and a delay circuit 130. The input circuit receives complementary input signals I and IN in a first voltage domain A and is therefore connected to VDDA and VSSA voltage signals. The cross-latch circuit 110 operates in a second voltage domain B and is therefore connected to VDDB and VSSB voltage signals. In some implementations, the first voltage levels VDDA and VSSA may be equal to 1.8 V and 0 V (ground), respectively, while the second voltage levels VDDB and VSSB may be equal to 3.3 V and 1.8 V, respectively. In other examples, VDDA and VSSA may be the same at 1.2V and 0V (ground), respectively, while the second voltage levels VDDB and VSSB may be the same at 1.8V and 0.6V, respectively.In other words, the second and third voltage levels, VDDA and VSSB, are at the same voltage level, and effectively the level converter 100 is connected to receive three voltage levels: VSSA, VDDA / VSSB, and VDDB. Other voltage levels are within the scope of disclosure.

[0009] The cross-latch circuit 110 provides complementary output signals Z and ZN. A cross-latch circuit generally operates in a single voltage domain (VDD, VSS). Thus, the output signals Z and ZN oscillate between low and high states within this single voltage domain. Disclosed embodiments employ the cross-latch circuit 110 in an overdrive level converter circuit. Therefore, the input signals I and IN are in the lower, first voltage domain and thus oscillate between the VDDA and VSSA voltage levels, while the outputs Z and ZN are converted to the higher, second voltage domain and thus oscillate between VDDB and VSSB.

[0010] To provide improved performance and reliability, a follow-up circuit 130 outputs overdrive or tracking signals to the cross-latch circuit 110 based on the input signals I and IN, instead of directly inputting the complementary input signals I and IN in the first voltage domain to the cross-latch circuit 110. Specifically, the follow-up circuit 130 is configured to provide tracking signals to the cross-latch circuit 110 that are either the greater of the control signal A and the VSSB voltage level, or the greater of the control signal B and the VSSB voltage level. In other words, the tracking signals are provided in the second voltage domain, even though the control signals A and B could also be in the first or second voltage domain.

[0011] In the illustrated example, input terminals 202 and 204 receive complementary input signals I and IN, respectively, in the first voltage domain, while output terminals 102 and 104 provide complementary output signals Z and ZN in the second voltage domain. As shown in Fig. As shown in Figure 1, the input circuit 120 is connected between input terminals 202 and 204, which receive signals in the first (lower) voltage domain A, and output terminals 102 and 104, which output signals in the second (higher) voltage domain B. The control signals A and B, which are outputs at nodes 206 and 208 respectively, can therefore oscillate between the lower VSSA signal of the first voltage domain and the high VDDB signal of the second voltage domain.

[0012] The cross-latch circuit 110 features a first transistor pair consisting of a first transistor 210 and a second transistor 212 connected in series, and a second transistor pair consisting of a third transistor 214 and a fourth transistor 216 connected in series. The first and third transistors 210 and 214 are PMOS transistors in the illustrated example, and the second and fourth transistors 212 and 216 are NMOS transistors. The two transistor pairs are connected between the VDDB and VSSB voltage rails. In the example shown, the gate terminal of transistor 216 is connected to the output terminal 102, which is located at a connection of the source / drain terminals of the first transistor pair 210, 212, while the gate terminal of transistor 212 is connected to the output terminal 104, which is located at a connection of the source / drain terminals of the second transistor pair 214, 216.

[0013] The level shifter 100 further comprises the input circuit 120, which includes transistors 218 and 220 connected in series between output terminal 102 and input terminal 202, and transistors 222 and 224 connected in series between output terminal 104 and input terminal 204. In the illustrated example, transistors 218 and 222 are PMOS transistors, and transistors 220 and 224 are NMOS transistors. Control signals A and B at the respective nodes 206 and 208 are received by the delay circuit 130, which is connected to the gate terminals of the PMOS transistors 214 and 210 of the latch circuit 110. The tracking circuit is configured in particular such that the gate of the PMOS transistor 210 receives tracking signals which are higher than the control signal B or VSSB, while the gate of the PMOS transistor 214 receives the higher than the control signal A or VSSB.

[0014] The gate terminals of NMOS transistors 220 and 224 are coupled to receive the VDDA voltage signals, and the gate terminals of PMOS transistors 218 and 220 are coupled to receive the VSSB voltage signals. As mentioned above, VDDA and VSSB are the same voltage level in some embodiments. For example, when the input signal I transitions from logic high to low in the first voltage domain, the input signal I at input terminal 202 is at the VSSA voltage level. NMOS transistor 220 turns on with the VDDA signal at its gate and pulls the control signal A at node 206 low (VSSA).

[0015] The follow-up circuit 130 is configured such that the PMOS transistor 214 of the cross-latch 110 receives the higher of the control signal A or VSSB. Accordingly, the gate of the PMOS transistor receives the low VSSB signal (logic low in the second voltage domain) and switches on the PMOS transistor 214. This pulls the ZN signal logic high in the second voltage domain (VDDB) at output terminal 104. The high ZN signal further switches on the NMOS transistor 212 and pulls the Z signal low in the second voltage domain (VSSB) at output terminal 102. The low Z signal then switches off the NMOS transistor 216 to keep the ZN output signal high.

[0016] As mentioned above, the PMOS transistors 210, 214 of the cross-latch circuit 110 are controlled by the follow-up circuit 130, with the gate of the PMOS transistor 210 receiving the higher of the control signal B or VSSB, and the gate of the PMOS transistor 214 receiving the higher of the control signal A or VSSB. Fig. Figure 2 shows an exemplary level converter 200 and illustrates further aspects of an embodiment of the follow-up circuit 130a, which is configured to compare the A and B signals with VSSB and output the corresponding tracking signals C and D to the PMOS transistors 214 and 210 respectively.

[0017] The in Fig. The 2 shown cross-latch shifter 110 is the one in Fig. The circuit shown in Figure 1 is similar and thus includes the first transistor 210 and the second transistor 212 connected in series, and the third transistor 214 and a fourth transistor 216 connected in series. The first and third transistors 210 and 214 are PMOS transistors, and the second and fourth transistors 212 and 216 are NMOS transistors. The two transistor pairs are connected between the VDDB and VSSB voltage rails. The gate terminal of transistor 216 is connected to output terminal 102, while the gate terminal of transistor 212 is connected to output terminal 104. The PMOS transistors 210 and 214 each receive the D and C tracking signals from the follow-up circuit 130a, as described in more detail below.

[0018] Similar to the ones in Fig. The input circuit 120 shown includes the input circuit 120a in Fig. 2. The PMOS transistor 218 and the NMOS transistor 220 are connected between output terminal 102 and input terminal 202, and the PMOS transistor 222 and NMOS transistor 224 are connected between output terminal 104 and input terminal 204. The gates of the PMOS transistors 218 and 222 are connected to the VSSB signal, and the gates of the NMOS transistors 220 and 224 are connected to the VDDA signal. Additionally, a PMOS transistor 318 is connected between control node 206 and the PMOS transistor 218, and an NMOS transistor 320 is connected between control node 206 and the NMOS transistor 220. Similarly, a PMOS transistor 322 is connected between the control node 208 and the PMOS transistor 222, and an NMOS transistor 324 is connected between the control node 208 and the NMOS transistor 224.

[0019] As above in conjunction with Fig. As mentioned in point 1, the overrun circuit 130a is in Fig. 2 configured such that the gate of PMOS transistor 210 receives the higher of the control signal B or VSSB, while the gate of PMOS transistor 214 receives the higher of the control signal A or VSSB. The tracking circuit 130a comprises a cross-coupled PMOS transistor pair 332, comprising PMOS transistors 332a and 332b, configured to output a tracking signal C that is higher than the control signal A or VSSB, and a cross-coupled PMOS transistor pair 334, comprising PMOS transistors 334a and 334b, configured to output a tracking signal D that is higher than the control signal B or VSSB. Accordingly, the source terminals of PMOS transistors 332a and 334a are coupled to receive the VSSB signal, while the source terminals of PMOS transistors 332b and 334b ​​are coupled to receive the control nodes 206 and 208 respectively, in order to receive the control signals A and B.The tracking signal C is received at the gate of PMOS transistor 214 and the tracking signal D is received at the gate of PMOS transistor 210.

[0020] The in Fig. The embodiment shown in Figure 2 includes additional cross-coupled transistor pairs for generating the control signals A and B. In particular, cross-coupled NMOS transistor pairs 336 and 340 provide respective control signals at the gates of the PMOS transistors 318 and 322. The cross-coupled NMOS transistor pair 336 comprises NMOS transistors 336a and 336b, whose drains are connected to the control signal A and VSSB, respectively. The cross-coupled NMOS transistor pair 340 comprises NMOS transistors 340a and 340b, whose drains are connected to the control signal B and VSSB, respectively. The sources of the cross-coupled transistor pairs 336 and 340 are connected to the gates of the PMOS transistors 318 and 322, respectively.

[0021] Cross-coupled PMOS transistor pairs 338 and 342 provide respective control signals to the gates of NMOS transistors 320 and 324. Cross-coupled PMOS transistor pair 338 comprises PMOS transistors 338a and 338b, whose drains are connected to control signal A and VDDA, respectively. Cross-coupled PMOS transistor pair 342 comprises PMOS transistors 342a and 342b, whose drains are connected to control signal B and VDDA, respectively. The sources of cross-coupled transistor pairs 338 and 342 are connected to the gates of NMOS transistors 320 and 324, respectively.

[0022] Thus, when the input signal I transitions from logic high to low in the first voltage domain, for example, at input terminal 202, it is at the VSSA voltage level (e.g., 0V). The series-connected NMOS transistors 220 and 320 turn on and pull the control signal A at node 206 low (VSSA). This low control signal A, along with VSSB, is fed into the cross-coupled PMOS transistor pair 332 to output the tracking signal C at the VSSB voltage level to the gate of PMOS transistor 214. This pulls the ZN signal logic high in the second voltage domain (VDDB) at output terminal 104. The high ZN signal further turns on NMOS transistor 212 and pulls the Z signal low in the second voltage domain (VSSB) at output terminal 102. The low Z signal also switches off the NMOS transistor 216 to keep the ZN output signal in its high state.

[0023] Fig. Figure 3 shows another exemplary level converter 300, illustrating further aspects of an embodiment of the cross-latch circuit 110a. Fig. 3. The control signals C and D are received at the gates of each of the latch transistors 210, 212, 214, and 216. In contrast, the Fig. In example 2, the output terminals 102 and 104 are cross-coupled with the gates of the NMOS transistors 216 and 212, respectively. Thus, the tracking signals C or D control the transistors in the circuit shown. Fig. In the 3 shown example, each of the latch transistors 210, 212, 214 and 216 is directly connected to increase the operating speed of the level converter 300.

[0024] As in the Fig. In the example shown, the input signals I and IN are received at input terminals 202 and 204 of input circuit 120a. Cross-latch circuit 110a has PMOS transistor 210 and NMOS transistor 212 connected in series, and PMOS transistor 214 and NMOS transistor 216 connected in series. The two transistor pairs are connected between the VDDB and VSSB voltage rails. As mentioned above, the gate terminals of transistors 210 and 212 are connected to receive the tracking signal D, and the gate terminals of transistors 214 and 216 are connected to receive the tracking signal C.

[0025] PMOS transistors 218 and 318 are connected between output terminal 102 and control node 206, and PMOS transistors 222 and 322 are connected between output terminal 104 and control node 208. NMOS transistors 220 and 320 are connected between control node 206 and input terminal 202, and NMOS transistors 224 and 324 are connected between control node 208 and input terminal 204. The gates of PMOS transistors 218 and 222 are connected to the VSSB signal, and the gates of NMOS transistors 220 and 224 are connected to the VDDA signal. The gates of PMOS transistors 318 and 322 are connected to the outputs of the cross-coupled NMOS pairs 336 and 340, respectively. The gates of the NMOS transistors 320 and 324 are connected to the outputs of the cross-coupled PMOS pairs 338 and 342 respectively.

[0026] The cross-coupled PMOS transistor pairs 332 and 334 are connected to control nodes 206 and 208, respectively, and configured to output the tracking signals C and D. When the input signal I transitions from logic high to low in the first voltage domain, the input signal I at input terminal 202 is at the VSSA voltage level (e.g., 0V). The series-connected NMOS transistors 220 and 320 turn on and pull the control signal A at node 206 low (VSSA). This low control signal A, along with VSSB, is fed into the cross-coupled PMOS transistor pair 332 to output the tracking signal C at the VSSB voltage level to the gates of PMOS transistor 214 and NMOS transistor 216. This turns on the PMOS transistor 214 and turns off the NMOS transistor 216, which pulls the ZN signal to a logic high in the second voltage domain (VDDB) at the output terminal 104.The tracking signal D turns on the NMOS transistor 212 and turns off the PMOS transistor 210, which pulls the Z signal lower into the second voltage domain (VSSB) at the output terminal 102.

[0027] Fig. Figure 4 illustrates an exemplary level converter 400, which in Fig. The cross-latch circuit 110 shown in Figure 1 includes an input circuit 120b and a delay circuit 130b according to further embodiments. As in the one shown in Fig. The example shown includes the 110 cross-latch circuit. Fig. 4. The PMOS transistor 210 and NMOS transistor 212 are connected in series, and the PMOS transistor 214 and NMOS transistor 216 are connected in series. The two transistor pairs are connected between the VDDB and VSSB voltage rails. The gate terminal of transistor 216 is connected to output terminal 102, while the gate terminal of transistor 212 is connected to output terminal 104. The PMOS transistors 210 and 214 receive the control signals D and C, respectively, from the delay circuit 130b.

[0028] The input circuit 120b in Fig. 4 features PMOS transistors 218 and 318 connected between output terminal 102 and control node 206, and PMOS transistors 222 and 322 connected between output terminal 104 and control node 208. NMOS transistors 220 and 320 are connected between control node 206 and input terminal 202, and NMOS transistors 224 and 324 are connected between control node 208 and input terminal 204. The gates of PMOS transistors 218 and 222 are connected to the VSSB signal, and the gates of NMOS transistors 220 and 224 are connected to the VDDA signal.

[0029] In the overrun circuit 130b in Fig. 4 are the cross-coupled transistor pairs connected to the gates of PMOS transistors 318 and 322, and the gates of NMOS transistors 320 and 324 are omitted. Instead, the gates of PMOS transistors 318 and 322 of input circuit 120b are connected to receive the VSSB signal, and the gates of NMOS transistors 320 and 324 are also connected to receive the VDDA signals. Some alternative embodiments can eliminate transistors 318, 320, 322, and 324.

[0030] As with the overrun circuit 130a in Fig. In section 3, the follow-up circuit 130b features the cross-coupled PMOS transistor pairs 332 and 334, which are connected to and configured with control nodes 206 and 208, respectively, to output the tracking signals C and D. When the input signal I transitions from logic high to low in the first voltage domain, the input signal I at input terminal 202 is at the VSSA voltage level (e.g., 0V). The NMOS transistors 220 and 320, connected in series, turn on and pull the control signal A at node 206 low (VSSA). This low control signal A, along with VSSB, is fed into the cross-coupled PMOS transistor pair 332 to output the tracking signal C at the VSSB voltage level to the gate of PMOS transistor 214. This switches on the PMOS transistor 214 and pulls the ZN signal logically high in the second voltage domain (VDDB) at the output terminal 104.The tracking signal D further switches off the PMOS transistor 210 and pulls the Z signal in the second voltage domain (VSSB) low at output terminal 102. Output terminals 102 and 104 are cross-coupled with the gates of the NMOS transistors 216 and 212, respectively, to hold the Z and ZN signals.

[0031] Fig. Figure 5 illustrates another embodiment of a level shifter 500 in which the cross-latch circuit 110a and the delay circuit 130b are coupled to an input circuit 120c. The input circuit 120c comprises the PMOS transistors 218 and 318, which are connected between the output terminal 102 and the control node 206, and the PMOS transistors 222 and 322, which are connected between the output terminal 104 and the control node 208. The NMOS transistors 220 and 320 are connected between the control node 206 and the input terminal 202, and the NMOS transistors 224 and 324 are connected between the control node 208 and the input terminal 204. The gates of the PMOS transistors 218, 318, 222 and 322 are connected to the VSSB signal and the gates of the NMOS transistors 220, 320, 224 and 324 are connected to the VDDA signal.

[0032] Additionally, the input circuit has 120c diodes connected between control nodes A and B and their respective transistors 320 and 324. In the Fig. The 5 illustrated examples are the diode-switched NMOS transistors 354, 356, although other diode structures also fall within the scope of the disclosure.

[0033] As mentioned above, in the cross-latch circuit 110a, the control signals C and D are received at the gates of the latch transistors 210, 212, 214, and 216, respectively. The tracking signals C or D in the example shown thus directly control each of the latch transistors 210, 212, 214, and 216 to increase the operating speed of the level shifter 100. The cross-coupled PMOS transistor pairs 332 and 334 of the follow-up circuit 130b are connected to the control nodes 206 and 208, respectively, and configured to output the tracking signals C and D.

[0034] Fig. Figure 6 illustrates another example in which the input circuit 120c and delay circuit 130b are used with another exemplary cross-latch circuit 110b. The input circuit 120c in Fig. 6 features PMOS transistors 218 and 318 connected between output terminal 102 and control node 206, and PMOS transistors 222 and 322 connected between output terminal 104 and control node 208. NMOS transistors 220 and 320 are connected between control node 206 and input terminal 202, and NMOS transistors 224 and 324 are connected between control node 208 and input terminal 204. The gates of PMOS transistors 218, 318, 222, and 322 are connected to the VSSB signal, and the gates of NMOS transistors 220, 320, 224, and 324 are connected to the VDDA signal. The cross-coupled PMOS transistor pairs 332 and 334 of the tracking circuit 130b are connected to the control nodes 206 and 208, respectively, and configured to output the tracking signals C and D. The tracking signals C and D are received at the gates of each of the cross-latch transistors 210, 212, 214, and 216.Diodes are connected between control nodes A and B and the respective transistors 320 and 324. In the [section / document]... Fig. The diodes illustrated in Figure 6 are the diode-switched NMOS transistors 354, 356, although other diode structures also fall within the scope of the disclosure.

[0035] The cross-latch circuit 110b further comprises NMOS transistors 350 and 352. Transistor 350 is connected in series between NMOS transistor 212 and the VSSB rail, and transistor 352 is connected in series between NMOS transistor 216 and the VSSB rail. The gates of NMOS transistors 350 and 352 are cross-coupled to output terminals 104 and 102, respectively, to maintain signals Z and ZN in their complementary states.

[0036] Fig. Figure 7 illustrates another example, in which the input circuit 120c and delay circuit 130b are used with yet another exemplary cross-latch circuit 110c. The input circuit 120c has the PMOS transistors 218 and 318 connected between the output terminal 102 and the control node 206, and the PMOS transistors 222 and 322 connected between the output terminal 104 and the control node 208. NMOS transistors 220 and 320 are connected between the control node 206 and the input terminal 202, and NMOS transistors 224 and 324 are connected between the control node 208 and the input terminal 204. The gates of the PMOS transistors 218, 318, 222 and 322 are connected to the VSSB signal and the gates of the NMOS transistors 220, 320, 224 and 324 are connected to the VDDA signal.

[0037] The cross-coupled PMOS transistor pairs 332 and 334 of the tracking circuit 130b are connected to the control nodes 206 and 208, respectively, and configured to output the tracking signals C and D. The tracking signals C and D are received at the gates of each of the cross-latch transistors 210, 212, 214, and 216. The diode-switched NMOS transistors 354 and 356 are connected between the control nodes A and B and the respective transistors 320 and 324, although other diode configurations are also within the scope of this disclosure.

[0038] The cross-latch circuit 110c further comprises NMOS transistors 360 and 362. Transistor 360 is connected in parallel between NMOS transistor 212 and the VSSB rail, and transistor 362 is connected in series between NMOS transistor 216 and the VSSB rail. The gates of NMOS transistors 360 and 362 are cross-coupled to output terminals 104 and 102, respectively, to maintain signals Z and ZN in their complementary states.

[0039] FIGS. 8 to 11 show exemplary level converter layouts according to some embodiments. Fig. Figure 8 illustrates the level converter 200 of the Fig. 2, wherein the cross-coupled PMOS transistor pairs 338 and 342 of the follow-up circuit 130a are designated as "TP1" and the cross-coupled PMOS transistor pairs 332 and 334 of the follow-up circuit 130a are designated as "TP2". The NMOS transistor pairs 336 and 340 of the follow-up circuit 130a are in Fig. 8 is designated as "TN1". The PMOS transistors 218, 318, 222 and 322 of input circuit 120a are designated as P1 and the NMOS transistors 220, 320, 224 and 324 of input circuit 120a are designated as N1. The PMOS transistors 210 and 214 of cross-latch circuit 110 are designated as Mp1 and the NMOS transistors 212 and 216 of cross-latch circuit 110 are designated as Mn1.

[0040] Fig. Figure 9 shows an exemplary symmetrical layout 900 for the level converter 200, wherein the transistors NT1, TP1, P1, N1, Mp1, Mn1 and TP2 are arranged symmetrically horizontally on both sides of a center line 910. Fig. Figure 10 illustrates another symmetrical layout 1000 in which the transistors NT1, TP1, P1, N1, Mp1, Mn1, and TP2 are arranged symmetrically vertically on both sides of the centerline. Additionally, in some examples, the NMOS and PMOS components may be grouped together on their respective sides of the centerline 910 to simplify the manufacturing process. This is shown in the example layout 1000, where the PMOS transistors TP2, TP1, P1, and Mp1 are all located in the upper section 1010 of the layout 1000, while the NMOS transistors Mn1, N1, and TN1 are all located in the lower section 1012 of the layout 1000. Furthermore, the transistors NT1, TP1, P1, N1, Mp1, Mn1, and TP2 can be rearranged to other layout positions as long as the symmetry is maintained. Such symmetrical layouts are balanced and allow the outputs to switch at the same speed, thus improving performance. Fig. Figure 11 illustrates an example of an asymmetrical layout, where NMOS and PMOS components are not necessarily arranged symmetrically around a center line. Such asymmetrical layouts may be suitable, for example, for lower-speed implementations. Other symmetrical and asymmetrical layouts are within the scope of this disclosure.

[0041] Fig. Figure 12 is a flowchart illustrating an example of a level-shifting method 1200 according to some embodiments. The method 1200 could be implemented in conjunction with any of the exemplary level-shifting circuits disclosed herein. With reference to Fig.In step 12, in conjunction with FIGS. 1 to 7, the first and second input signals I and IN, respectively, exhibiting first and second voltage levels VSSA and VDDA, are received at the input terminals 202 and 204 of the level converter 100. In the illustrated example, the second voltage level VDDA is higher than the first voltage level VSSA. A first control signal A with the first voltage level VSSA, based on the first input signal I, is generated in step 1220. In step 1230, a second control signal B is generated based on the second input signal IN. The second control signal B is at a fourth voltage level VDDB, which is higher than the second voltage level VDDA.

[0042] In step 1240, a first tracking signal C, based on the first control signal A, is provided to a cross-latch circuit 120. The first tracking signal C has a third voltage level, VSSB, which is higher than the first voltage level, VSSA. In step 1250, a second tracking signal D, based on the second control signal B, is provided to the cross-latch circuit 120. The second tracking signal D has a fourth voltage level, VDDB. A first output signal Z, based on the second tracking signal D, which has the third voltage level, VSSB, is output by the cross-latch circuit 120 in step 1260, and a second output signal ZN, based on the first tracking signal C, which has the fourth voltage level, VDDB, is output by the cross-latch circuit 120 in step 1270.

[0043] The high-speed overload level converter device described in the preceding embodiments uses a cross-latch to perform the level conversion. This allows the structure to be used for 2xVDD and 3xVDD applications. Embodiments disclosed herein can, for example, provide higher switching speeds while maintaining or improving system reliability. Some examples provide operating speeds at 250 MHz.

[0044] According to some disclosed examples, a level shifter includes an input circuit with first and second input terminals configured to receive complementary input signals with a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit. The cross-latch circuit has first and second output terminals configured to provide complementary output signals with a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first and fourth voltage levels based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit and configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals.The first tracking signal is the larger of the first control signal and the third voltage level, and the second tracking signal is the larger of the second control signal and the third voltage level.

[0045] Other disclosed examples include a level shifter having first and second input terminals configured to receive complementary first and second input signals in a low-voltage domain, and first and second output terminals configured to provide complementary first and second output signals corresponding to the first and second input signals in a high-voltage domain. An input circuit is connected between the first and second input terminals and the first and second output terminals. The input circuit has first and second control nodes configured to output first and second control signals in the high- and low-voltage domains based on the first and second input signals. A cross-latch circuit is coupled to the input circuit and the first and second output terminals and includes first and second input terminals.A tracking circuit is coupled to the first and second control nodes and the first and second input terminals of the cross-latch circuit. The tracking circuit is configured to provide first and second tracking signals to the first and second input signals of the cross-latch circuit in the high-voltage domain, based on the first and second control signals.

[0046] According to further examples, a method involves receiving first and second input signals with respective first and second voltage levels, where the second voltage level is higher than the first. A first control signal is generated where the first voltage level is based on the first input signal, and a second control signal is generated where the fourth voltage level is higher than the second voltage level based on the second input signal. A first tracking signal is provided to a cross-latch circuit, which has a third voltage level higher than the first voltage level based on the first control signal. A second tracking signal is provided to the cross-latch circuit, where the fourth voltage level is based on the second control signal.A first output signal is provided by the cross-latch circuit, where the third voltage level is based on the second tracking signal, and the cross-latch circuit provides a second output signal, where the fourth voltage level is based on the first tracking signal.

Claims

[1] Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB). [2] Level converter according to claim 1, wherein the cross-latch circuit (110) comprises: a first PMOS transistor (210) and a first NMOS transistor (212) connected in series between a first voltage rail configured to receive the fourth voltage level (VDDB) and a second voltage rail configured to receive the third voltage level (VSSB), wherein a connection between the first PMOS transistor (210) and the first NMOS transistor (212) forms the first output terminal (102); a second PMOS transistor (214) and a second NMOS transistor (216) connected in series between the first voltage rail and the second voltage rail, wherein a connection of the second PMOS transistor (214) and the second NMOS transistor (216) forms the second output terminal (104), wherein a gate terminal of the first PMOS transistor (210) is connected to receive the second tracking signal, and a gate terminal of the second PMOS transistor (214) is connected to receive the first tracking signal. [3] Level converter according to claim 2, wherein the first output terminal (102) is connected to a gate terminal of the second NMOS transistor (216), wherein the second output terminal (104) is connected to a gate terminal of the first NMOS transistor (212). [4] Level shifter according to claim 2 or 3, wherein a gate terminal of the first NMOS transistor (212) is connected to receive the second tracking signal, and a gate terminal of the second NMOS transistor (216) is connected to receive the first tracking signal. [5] Level converter according to claim 4, wherein the cross-latch circuit (110) comprises: a third NMOS transistor (350) connected in series with the first NMOS transistor (212) between the first NMOS transistor (212) and the second voltage rail; and a fourth NMOS transistor (352) which is connected in series with the second NMOS transistor (216) between the second NMOS transistor (216) and the second voltage rail, wherein a gate terminal of the third NMOS transistor (350) is connected to the second output terminal (104), and a gate terminal of the fourth NMOS transistor (352) is connected to the first output terminal (102). [6] Level converter according to claim 4, wherein the cross-latch circuit (110) comprises: a third NMOS transistor (350) connected in parallel with the first NMOS transistor (212) between the first NMOS transistor (212) and the second voltage rail; and a fourth NMOS transistor (352) connected in parallel with the second NMOS transistor (216) between the second NMOS transistor (216) and the second voltage rail, wherein a gate terminal of the third NMOS transistor (350) is connected to the second output terminal (104), and a gate terminal of the fourth NMOS transistor (352) is connected to the first output terminal (102). [7] Level converter according to one of the preceding claims, wherein the input circuit (120) comprises: a first PMOS transistor (218) and a first NMOS transistor (220) connected in series between the first output terminal (102) and the first input terminal (202), wherein a connection of the first PMOS transistor (218) and the first NMOS transistor (220) forms the first control node (206), wherein a gate terminal of the first PMOS transistor (218) is connected to the third voltage level (VSSB), and wherein a gate terminal of the first NMOS transistor (220) is connected to the second voltage level (VDDA); a second PMOS transistor (222) and a second NMOS transistor (224) connected in series between the second output terminal (104) and the second input terminal (204), wherein a connection of the second PMOS transistor (222) and the second NMOS transistor (224) forms the second control node (208), wherein a gate terminal of the second PMOS transistor (222) is connected to the third voltage level (VSSB), and wherein a gate terminal of the second NMOS transistor (224) is connected to the second voltage level (VDDA). [8] Level converter according to claim 7, wherein the input circuit (120) comprises: a third PMOS transistor (318) connected in series between the first PMOS transistor (218) and the first control node (206); a fourth PMOS transistor (322) connected in series between the second PMOS transistor (222) and the second control node (208); a third NMOS transistor (320) connected in series between the first NMOS transistor (220) and the first control node (206); and a fourth NMOS transistor (324) connected in series between the second NMOS transistor (224) and the second control node (208). [9] Level shifter according to claim 8, wherein the gate terminals of the third PMOS transistor (318) and the fourth PMOS transistor (322) are connected to the third voltage level (VSSB), and wherein the gate terminals of the third NMOS transistor (320) and the fourth NMOS transistor (324) are connected to the second voltage level (VDDA). [10] Level converter according to one of the preceding claims, wherein the follow-up circuit (130) comprises: a first cross-coupled PMOS transistor pair (332) comprising a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the first control node (206), and an output terminal configured to output the first tracking signal; a second cross-coupled PMOS transistor pair (334) comprising a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the second control node (208), and an output terminal configured to output the second tracking signal. [11] Level converter according to claim 10, wherein the follow-up circuit (130) comprises: a first cross-coupled NMOS transistor pair (336) comprising a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the first control node (206), and an output terminal; and a second cross-coupled NMOS transistor pair (340) having a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the second control node (208), and an output terminal, wherein the input circuit (120) has: a third PMOS transistor (318) connected in series between the first PMOS transistor (218) and the first control node (206), wherein the third PMOS transistor (318) has a gate terminal connected to the output terminal of the first cross-coupled NMOS transistor pair (336); and a fourth PMOS transistor (322) connected in series between the second PMOS transistor (222) and the second control node (208); wherein the fourth PMOS transistor (322) has a gate terminal connected to the output terminal of the second cross-coupled NMOS transistor pair (340). [12] Level converter according to claim 10 or 11, wherein the follow-up circuit (130) comprises: a third cross-coupled PMOS transistor pair (338) comprising a first input terminal connected to the second voltage level (VDDA), a second input terminal connected to the first control node (206), and an output terminal; and a fourth cross-coupled PMOS transistor pair (342) comprising a first input terminal connected to the second voltage level (VDDA), a second input terminal connected to the second control node (208), and an output terminal, wherein the input circuit (120) has: a third NMOS transistor (320) connected in series between the first NMOS transistor (220) and the first control node (206), wherein the third NMOS transistor (320) has a gate terminal connected to the output terminal of the third cross-coupled PMOS transistor pair (338); a fourth NMOS transistor (324) connected in series between the second NMOS transistor (224) and the second control node (208), wherein the fourth NMOS transistor (324) has a gate terminal connected to the output terminal of the fourth cross-coupled PMOS transistor pair (342). [13] Equipping level converters: a first input terminal (202) and a second input terminal (204) set up to receive complementary first and second input signals in a low-voltage domain; a first output terminal (102) and a second output terminal (104) are provided to supply complementary first and second output signals corresponding to the first and second input signals in a high-voltage domain; an input circuit (120) connected between the first input terminal (202) and the second input terminal (204), and the first output terminal (102) and the second output terminal (104), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output first and second control signals in the high-voltage domain and the low-voltage domain based on the first and second input signals; a cross-latch circuit (110) coupled to the input circuit (120) and the first output terminal (102) and the second output terminal (104), wherein the cross-latch circuit (110) has a first input terminal and a second input terminal; and a tracking circuit (130) coupled to the first control node (206) and the second control node (208) and the first input terminal and the second input terminal of the cross-latch circuit (110), wherein the tracking circuit (130) is configured to provide first and second tracking signals to the first input terminal and a second input terminal of the cross-latch circuit (110) in the high-voltage domain based on the first and second control signals. [14] Level converter according to claim 13, wherein the low-voltage domain has a first voltage level (VSSA) and a second voltage level (VDDA) which is higher than the first voltage level (VSSA), where the high-voltage domain has a third voltage level (VSSB) and a fourth voltage level (VDDB) that is higher than the second voltage level (VDDA). [15] Level converter according to claim 14, wherein the second voltage level (VDDA) and the third voltage level (VSSB) are the same. [16] Level converter according to claim 14 or 15, wherein the cross-latch circuit (110) comprises: a first PMOS transistor (210) and a first NMOS transistor (212) connected in series between a first voltage rail configured to receive the fourth voltage level (VDDB) and a second voltage rail configured to receive the third voltage level (VSSB), wherein a connection of the first PMOS transistor (210) and the first NMOS transistor (212) forms the first output terminal (102), wherein a gate terminal of the first PMOS transistor (210) is connected to receive the second tracking signal; a second PMOS transistor (214) and a second NMOS transistor (216) connected in series between the first voltage rail and the second voltage rail, wherein a connection of the second PMOS transistor (214) and the second NMOS transistor (216) forms the second output terminal (104), wherein a gate terminal of the second PMOS transistor (214) is connected to receive the first tracking signal. [17] Level converter according to claim 16, wherein the input circuit (120) comprises: a first PMOS transistor (218) and a first NMOS transistor (220) connected in series between the first output terminal (102) and the first input terminal (202), wherein a connection of the first PMOS transistor (218) and the first NMOS transistor (220) forms the first control node (206), wherein a gate terminal of the first PMOS transistor (218) is connected to the third voltage level (VSSB), and wherein a gate terminal of the first NMOS transistor (220) is connected to the second voltage level (VDDA); and a second PMOS transistor (222) and a second NMOS transistor (224) connected in series between the second output terminal (104) and the second input terminal (204), wherein a connection of the second PMOS transistor (222) and the second NMOS transistor (224) forms the second control node (208), wherein a gate terminal of the second PMOS transistor (222) is connected to the third voltage level (VSSB), and wherein a gate terminal of the second NMOS transistor (224) is connected to the second voltage level (VDDA), including the overrun circuit (130): a first cross-coupled PMOS transistor pair (332) comprising a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the first control node (206), and an output terminal configured to output the first tracking signal; and a second cross-coupled PMOS transistor pair (334) having a first input terminal connected to the third voltage level (VSSB), a second input terminal connected to the second control node (208), and an output terminal for outputting the second tracking signal. [18] Level shifter according to claim 17, wherein the input circuit (120), the cross-latch circuit (110) and the follow-up circuit (130) comprise multiple PMOS devices and multiple NMOS devices, and wherein the PMOS devices and the NMOS devices are arranged symmetrically in or on a substrate. [19] Level conversion procedures including: Receiving a first input signal and a second input signal having a first voltage level (VSSA) and a second voltage level (VDDA), where the second voltage level (VDDA) is higher than the first voltage level (VSSA); Generating a first control signal with the first voltage level (VSSA) based on the first input signal; Generating a second control signal with a fourth voltage level (VDDB) that is higher than the second voltage level (VDDA), based on the second input signal; Providing an initial tracking signal to a cross-latch circuit (110) that has a third voltage level (VSSB) higher than the first voltage level (VSSA) based on the first control signal; Providing a second tracking signal to the cross-latch circuit (110) which has the fourth voltage level (VDDB) based on the second control signal; Output of a first output signal through the cross-latch circuit (110), which has the third voltage level (VSSB), based on the second tracking signal; and Output of a second output signal through the cross-latch circuit (110) which has the fourth voltage level (VDDB) based on the first tracking signal. [20] Level conversion method according to claim 19, wherein the second voltage level (VDDA) and the third voltage level (VSSB) are the same.

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