Hierarchical density uniformity for surface planarization of semiconductor structural elements

Abstract

Procedure that includes: Dividing initial layout data into several raster regions; Determining an initial structure density value for each of the plurality of raster regions under a first division plane; Obtaining a planned structure density value of a first raster region of the plurality of raster regions by adjusting an initial structure density value of the first raster region based on an initial structure density value of a second raster region of the plurality of raster regions under the first division plane; Determining second layout data of the first raster region based on the planned structure density value; and Forming a plurality of structural elements on a surface of a wafer (202, 212, 222, 232, 242) based at least in part on the second layout data of the first raster region.

Description

BACKGROUND

[0001] In flip-chip techniques, metal pads are formed on a top surface of a wafer containing integrated circuits (ICs) in relation to the ICs formed on the wafer. Solder bumps or copper bumps are deposited on the metal pads. The ICs are then separated from the wafer as IC dies. The separated IC dies are flipped over and positioned on a carrier substrate so that the solder bumps face the connectors on the carrier substrate. The solder bumps are then remelted using, for example, a thermosonic bonding or, alternatively, a reflow soldering process, so that the ICs are firmly coupled to the carrier substrate. Electrical connections are formed between the molten solder bumps and the connectors. The small space between the IC die and the underlying carrier substrate is underfilled with an electrically insulating adhesive.

[0002] A fan-out wafer-level package ("WLP") can be used to encapsulate a single die, multiple dies side by side, or multiple dies in a vertical package-on-package ("POP") configuration. The POP configuration in fan-out WLPs is achieved by interconnect structure elements, such as a via, that vertically connect multiple dies.

[0003] In fan-out WLPs, verified "good dies" are positioned on a carrier wafer. Layers of interconnect structure elements are formed, connecting the die to the associated I / O pads and between the various interconnect layers themselves. The interconnects are formed by wafer-level processes, using photoresist and photolithography processes similar to front-end wafer fabrication processes. Therefore, vertical alignments between or among successive layers of interconnects must be managed.

[0004] CoWoS is a wafer-level multi-chip packaging technology that arranges multiple IC blocks, or chiplets, side by side on a silicon interposer for better density and higher interconnect performance. The chiplets are bonded to a silicon interposer through microbumps, forming a chip-on-wafer (CoW). The CoW is then thinned to expose the TSV perforations. Cu bumps are formed on the other side of the silicon interposer. The silicon interposer is then singulated to obtain IC dies. A CoWoS package is completed by bonding an IC die to a package substrate.

[0005] Flip-chip techniques, fan-out WLP techniques, CoWoS techniques, or similar techniques, in which metal bumps or balls are coupled to a carrier substrate with connectors, generally require very flat mounting surfaces on the side of the metal bumps or balls and on the side of the carrier substrate. Planarization on the side of the metal bumps or balls is difficult to arrange or maintain. Uneven heights on the metal bumps or balls can cause cold solder joints, i.e., the metal bumps or balls are separated from the connectors on the carrier substrate. US 5,552,996 A discloses a conventional method for controlling the fabrication of an integrated semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. Throughout the drawings, identical reference numerals indicate similar elements or acts unless the context indicates otherwise. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or reduced as necessary for clarity of discussion. Fig. 1 is an example wafer-level package; Fig. 2A-2C show example scenarios of two wafers coupled together; Fig. 3 is an exemplary system; Fig. 4 is an example controller; Fig. 5 is an example operation process of the controller; Fig. 6 is an exemplary computer system for implementing the controller; Fig. 7 is an exemplary separation grid of a wafer surface; and Fig. Figure 8 is an example structure density smoothing process with a downsampling path and an upsampling path. DETAILED DESCRIPTION

[0007] The present disclosure describes techniques for managing the planarization of features formed on a semiconductor wafer. The inventors of the disclosed techniques observed a correlation between a density of microbump structures formed within a given surface sampling region, referred to as "feature density," and a height of the formed microbumps in the given surface region. "Feature density" refers to the ratio between the total surface area of ​​the microbumps formed in a surface region and a surface area of ​​the surface sampling region. The disclosed techniques achieve relative planarization of the microbump structures formed on a wafer surface by adjusting the feature density of the microbumps formed in different regions of the wafer surface. The feature density is adjusted in various ways.For example, the surface area of ​​a microbump formed within a given wafer surface region can be increased or decreased to change the feature density. In another example, a dummy microbump can be inserted into a given wafer surface region to increase the feature density.

[0008] The feature density information of a scan region is first obtained from the information about the physical layout design of the microbumps on a wafer surface. For a given scan, the layout is divided into several scan regions of a specific size. The feature density information is obtained for each scan region.

[0009] After the feature density information for each sample region is obtained, a feature density planning operation is performed to adjust, or "plan," the feature density in each sample region. The planning includes a local correction operation and a global correction operation. The local correction operation includes a local convolution operation to smooth, or "blur," the feature density information of a sample region based on the feature density information of neighboring sample regions. In one embodiment, the smoothing operation is implemented by a Gaussian filter and a gradient-aware correction kernel. The neighboring sample regions can be selected based on various criteria. In one embodiment, a 3×3 pooling criterion is used, where a target sample region and eight surrounding sample regions form a 3×3 pooled patch.The structure density of the target sample region is smoothed based on the structure density of the eight surrounding sample regions using Gaussian smoothing. The pool patch can also be defined as 4×4, 5×5, 6×6, or other pool patch sizes.

[0010] The local convolution operation can be performed at different sample sizes according to a downsampling path, where the size of a sample region increases sequentially. A structure density of a larger sample region is first obtained by mean pooling the smoothed / corrected structure density of the smaller sample regions contained within the larger sample region. After obtaining the initial structure density information of each of the larger sample regions, a local convolution operation is performed to smooth the obtained initial structure density.

[0011] The global correction follows an upsampling path, with the size of the sample region decreasing sequentially. Through the upsampling path or the global corrections, the smoothed structure density information of a larger sample region is incorporated into the correction of the structure element density of a smaller sample region.

[0012] For local or global corrections, a lower density limit and an upper density limit are used to restrict the adjustment of the feature density. If the desired feature density corrections for a sample region are beyond the lower density limit or the upper density limit, a dummy microbump feature can be added to the sample region or other sample regions to influence the feature density in the sample region or other sample regions.

[0013] After the microbump density is corrected or planned for the entire wafer, this corrected density information is used to update the microbump layout design on the wafer. The microbumps are formed on the wafer based on the updated layout design.

[0014] Fig. 1 is an exemplary CoWoS package 10. The package 10 includes a die 100 and a package substrate 102. The die 100 includes chiplets 106, 104 positioned side by side on a silicon interposer 110, forming a chip-on-wafer (CoW) die. The silicon interposer 110 includes a metal redistribution layer (RDL) 112 including a plurality of metal layers facing the chiplets 106, 104. In one embodiment, the metal RDL 112 includes three copper damascene layers and a single aluminum layer. The chiplets 106, 104 are each connected to the metal RDL 112 via a plurality of microbumps 120. In some embodiments, microbumps 120 include two portions 122, 124. Portions 122 are formed on surfaces of chiplets 106, 104. Portions 124 are formed on the surface of RDL 112.The parts 122, 124 are coupled together, for example, through a reflow process, to form the microbumps 120. In some embodiments, each of the parts 122, 124 may include a chip interconnect bump (C2 bump), for example, a copper-to-Cu post and a solder cap over the Cu post. In one embodiment, the microbump 120 includes only one of the parts 122 or the parts 124. The silicon interposer 110 includes through-silicon vias (TSVs) 130 for connecting the RDL 112 to interconnect features on a bottom surface 132 of the silicon interposer 110, for example, the C4 bumps 142.

[0015] The die 100 is connected to a top surface 140 of the package substrate 102 by controlled collapsed chip connection (C4) bumps 142. The C4 bumps are formed on the bottom surface 132 of the silicon interposer as a sequence of solder metallization, resist overlay, and solder bump mask.

[0016] Solder bumps 144 are formed on a bottom surface 146 of the package substrate 102. The CoWoS package 10 is connected to a printed circuit board (PCB) 150 by the solder bumps 144.

[0017] In Fig. 1, for simplicity and for the purpose of illustration, the connecting bumps or beads 120, 142, 144 are illustrated as being coupled to a flat surface, without limiting the scope of the disclosure. Fig. 2 shows that a first wafer 202, 232 having interconnect bumps or beads 204, 234 can be coupled to a second wafer 212, 222, 242 having various corresponding interconnect structures 214, 224, 244. For example, Fig. 2A, the second wafer 212 includes interconnect pad features 214 for connecting to the interconnect bumps or beads 204 of the first wafer 202. The interconnect pad 214 may have a larger interface area than the interconnect bumps or beads 204. Fig. 2B shows that the second wafer 222 includes lead wire features 224 for connecting to the interconnect bumps or balls 204 of the first wafer 202. The interconnect pad 214 may have a smaller interface than the interconnect bumps or balls 204 and may be embedded in the solder material of the interconnect bumps or balls 204 (shown in dashed lines for illustrative purposes) when the first wafer 202 and the second wafer 222 are coupled together. Fig. Figure 2C shows that the first wafer 232 has different types of interconnect pad features 234, 236 on the same surface to be connected to corresponding interconnect structures 246, 244 on the second wafer 242. In all examples of Figures 2A-2C, the height H1 (only in Fig. 2A) of the connecting bumps or beads 204, 234, 236 on the first wafer 204, 232 to the height H2 (only in Fig. 2A) of the interconnect structures 214, 224, 244, 246 on the second wafer 212, 222, 242 are aligned to complete the connections between the first wafer 202, 232 and the corresponding second wafer 212, 222, 242. The imperfections at height H1 or height H2 may cause cold joint issues if the corresponding interconnect bumps 204, 234, 236 do not properly contact or couple to the corresponding interconnect structures 214, 224, 244, 246.

[0018] In many application scenarios, a perfect height H1 means that all interconnect bumps or beads 204, 234, 236 on a respective first wafer 202, 232 are substantially at the same level. A perfect height H2 means that all interconnect structures 214, 224, 244, 246 on a respective second wafer 212, 222, 242 are substantially at the same level. However, the disclosure is not limited by this example. In other examples, the height H1 and the corresponding height H2 are considered together in the planarization design of the interconnect bumps or beads, and the interconnect bumps or beads 204, 234, 236 on a same first wafer 204 may have a different height H1, in particular if the corresponding interconnect structures 214, 224, 244, 246 on a corresponding second wafer 212, 222, 242 have a different height H2.The techniques described herein can be used to design and form interconnect bumps or beads on the first wafer and / or the interconnect structures on the second wafer with appropriate heights H1, H2.

[0019] Fig. 3 is an exemplary feature manufacturing system 300. The control system 300 includes a manufacturing controller 310, a feature database 320, and a manufacturing tool set 330. The manufacturing tool set 330 includes various tools for different processes in forming a feature on a wafer. For example, the tool set 330 for forming a microbump on a wafer surface may include tools for implementing seed layer sputtering, photoresist patterning, electroplating, photoresist removal, seed layer etching, interconnect bump reflow, flux cleaning, etc. One or more of the tools may be controlled by the manufacturing controller during the microbump formation process.For example, the controller 310 may control a scanner machine 332 to pattern a photoresist layer 352 formed over a seed layer 354 on a wafer 202 to expose the seed layer in a desired manner to form microbumps thereon. In one embodiment, for example, the controller 310 may control the scanner to form openings 356 with a controlled side surface size D1 in the photoresist layer 352 to expose the underlying seed layer 354. The controlled sizes D1 of the openings 356 correlate with heights of the conductive structures (not shown for simplicity), such as microbumps, formed in the openings 356. Thus, by controlling the sizes D1 of the openings 356 formed in the photoresist layer 352, the controller 310 controls the heights of the microbumps.In another example, the controller 310 may also control the number and / or positions of the openings 356 formed in the photoresist layer 352 to control the number and positions of the microbumps.

[0020] The feature database 320 may store data about layers of features formed on a semiconductor wafer. For example, the feature database 320 may store data from integrated circuit layouts of layers formed in front-end-of-line (FEOL), middle-of-line (MOL), or back-end-of-line (BEOL) manufacturing processes, layouts of features formed in an encapsulation process, for example, C4 bump formation, and / or layouts of features formed during preparation of a wafer or die for an encapsulation process, for example, the formation of TSVs or microbumps. In one embodiment, the data in the feature database 320 is in a graphics database system (GDS) format, for example, GDSII, OASIS, or OASIS.MASK.The feature database 320 may contain feature layout data in several different formats for different layers formed on a wafer. Furthermore, the controller 310 may operate with several different feature databases 320 for different layers in different semiconductor manufacturing processes. For example, layout data created in the OASIS.MASK format may be used specifically for controlling photoresist formation.

[0021] The controller 310, the structural element database 320, and the tool set 330 may be electrically or communicatively coupled to each other via a network 340. The network 340 may be any wired or wireless network, such as the Internet, intranet, cellular, short-range wireless communication, near-field communication, and other suitable networks. Both the controller 310 and the structural element database 320 may be implemented by one or more physical computing machines or by one or more virtual machines. The functions of the controller 310 or the structural element database 320 may be implemented by a single physical or virtual computing device or by multiple physical or virtual devices in a distributed computing environment.

[0022] Fig. 4 shows details of an exemplary controller 310. As in Fig. As shown in Figure 4, the controller 310 includes a processing unit 410 and a memory unit 420. In one embodiment, the processing unit 410 may be an application-specific instruction set processor (ASIP) that is specially configured and includes specific instruction sets for controlling semiconductor wafer manufacturing processes. For example, the instruction set of the processing unit 410 is designed to enable efficient and fast processing of instructions for the specific application of controlling wafer manufacturing processes. The processing unit 410 may also include configurable instruction sets such that the processing units 410 can operate with different feature databases for controlling different manufacturing processes or different semiconductor products with different layer layouts.For example, the processing unit 410 may include multiple cores dedicated to different static logic and / or configurable logic.

[0023] The storage unit 420 may be system memory that stores, among other things, application-specific instructions intended for the functions and / or applications they respectively implement. For example, the application-specific instructions are provided as separate modules for implementing a structure extraction unit 422, a density planning unit 424, a structure element layout correction unit 430, a layout generation unit 434, and an implementation unit 436. The density planning unit 424 may include a reference planning unit 426 and a dummy structure planning unit 428. The structure element layout correction unit 430 may include or cooperate with a rule engine 432.

[0024] The controller 310 may also include an interface unit 440, a communication unit 450, and other components 460. The 440 may include any human-machine interface devices and related components that enable the controller 310 to receive input from an operator. The communication unit 450 may include any human-machine communication devices, for example, an RF component or a wired data port, that enable the controller 310 to communicate with the structural element database 320 and / or the tool set 330.

[0025] The structure extraction unit 422, the density planning unit 424, the structure element layout correction unit 430, the layout generation unit 434, and the implementation unit 436 each contain dedicated computer-executable instructions. When executed by the processing unit 410, these instructions configure the processing unit 410 to implement the functions of each of the structure extraction unit 422, the density planning unit 424, the structure element layout correction unit 430, the layout generation unit 434, and the implementation unit 436.

[0026] Controller 310 and its components may be located on a single computing device or may be located on multiple computing devices operating together in a distributed computing environment. For example, the processing units and structure extraction unit 422, density planning unit 424, structure element layout correction unit 430, layout generation unit 434, and implementation unit 436 may be located on different computing devices and operate together to form a virtual controller 310. A virtual controller 310 may include multi-layer virtualization, such as a virtual machine at an application layer and virtual memory.

[0027] Fig. 5 illustrates an operation 500 of the controller 310. In Fig. 5, an exemplary microbump (µbump) formation process is used to illustrate the operation of controller 310. It should be noted that controller 310 and its components or functions may be used to control the formation of other layers or features on a wafer. For example, similar operations may be used to control the formation of other C2 bumps, C4 bumps, or solder bumps on a die, a carrier wafer, an interposer substrate, or even a printed circuit board.

[0028] The exemplary µbump formation process begins with the receipt of an incoming wafer that has completed the front-end manufacturing processes, including the FEOL, MOL, and BEOL processes. On the received wafer, for example, wafer 202 of Fig. 3, a sequence of operations such as seed layer sputtering, photoresist patterning, electroplating, photoresist removal, seed layer etching, reflow, and flux cleaning is performed to complete the formation of microbumps. After the microbumps are formed, the wafer can be cut into dies to complete the encapsulation process.

[0029] Operation 500 may be used to control the photoresist patterning process, which determines the size and positions of the microbumps formed over the seed layer.

[0030] In the example operation 510, the controller 310 obtains the GDS data regarding the microbumps from the feature database 320. The GDS data provides the layout design of the microbumps based on the chip product design and manufacturing process applicable to the wafer.

[0031] In the example operation 520, the feature density extraction unit 422 obtains the feature density of the microbumps formed on various surface grid regions. For example, a target surface of the wafer 202 where the microbumps are to be formed is segmented into multiple grid regions of, for example, substantially the same dimensions. The layout of the microbumps is mapped into each of the grid regions to obtain the number, type, and / or size of the microbumps to be formed in each of the grid regions. The feature densities of the microbumps are obtained for each of the grid regions. In one embodiment, a feature density of a grid region is evaluated based on a ratio between a total surface area of ​​the microbumps in the grid region and a surface area of ​​the grid region.The surface of a microbump may be selected as a surface of the top surface, a surface of the bottom surface, or a surface of a cross-sectional plane between the top and bottom surfaces of the microbump, or any combination or average thereof.

[0032] The following algorithm (1) can be used to calculate the structure density: ρ(x,y)=1w2∫∫−w / 2w / 2M(x,y)dxdy where w denotes the size of a grid region, ρ denotes the structure density, and M is a function of position (x,y). M takes either the values ​​0 or 1, where 0 indicates no structure and 1 indicates structure is present at position (x,y).

[0033] In one embodiment, for each raster region, the edge regions surrounding the raster region are also considered when evaluating the feature density value. Considering the edge regions of a raster region helps eliminate arbitrary noise or inconsistencies caused by the arbitrary division of the target surface of the wafer 202 into raster regions. For example, in one embodiment, a subpixel smoothing technique may be used in both the x-axis and y-axis directions of a lateral XY plane of the target surface to improve the assessment of the feature density of a target raster region by considering the edge region features. The following algorithm (2) may be used to perform subpixel smoothing: ρfinal=14ε2∫∫−εερ(x−α,y−β)dαdβ

[0034] In the example operation 530, the density planning unit 424 adjusts the feature density of each raster region. In one example, the adjustment is determined based on the feature density of neighboring raster regions. That is, the feature density value of a given raster region is smoothed or averaged based on the feature density of the neighboring raster regions. Any averaging or smoothing techniques may be used, and all are included in the disclosure. In one embodiment, Gaussian smoothing and a gradient-aware correction kernel may be used to blur or smooth the feature density differences between a raster region and its neighboring raster regions. Mathematically, Gaussian smoothing is implemented by convolving the feature density value of a raster region with a Gaussian function.The gradient-aware correction kernel is used in Gaussian smoothing to reduce the differences in structure density between neighboring raster regions.

[0035] Smoothing of the structure density based on neighboring raster regions can be performed at multiple levels of division or rasterization of the target surface. The structure density smoothing operations at the different rasterization levels can be performed sequentially. A structure smoothing result obtained from an earlier rasterization level can be incorporated into the structure smoothing operation for a later rasterization level in the sequence. In a downsampling path or downsampling sequence, the size of a raster region, the raster size, progressively increases. In an upsampling path or upsampling sequence, the raster size progressively decreases.

[0036] In the example operation 530, the downsampling path and / or the upsampling path may be used in implementing feature density smoothing. In a case where both the downsampling path and the upsampling path are used, a sequential order is chosen between the downsampling path and the upsampling path. The selection may be based on a weight assigned to a global correction approach and a local correction approach. A downsampling path is executed before an upsampling path if it is determined that correction or smoothing based on feature density information of local neighboring regions (local corrections) is more important than correction or smoothing based on feature density information of a larger portion of the wafer (global correction).On the other hand, an upsampling path is executed before a downsampling path if it is determined that the global correction is more important than the local correction. Whether the global correction or the local correction is more important can be determined based on product or process designs of specific integrated circuits or other semiconductor products, all of which are within the scope of the disclosure.

[0037] In some examples, during density planning, the dummy structure planning unit 428 may add a dummy bump to a region or remove a dummy bump from a region. A dummy bump is a structure composed of similar or identical materials and processes as a microbump structure, while the dummy bump does not serve any electrical connection purposes. For example, a dummy bump does not establish any additional electrical connections between the first wafer 202 and the second wafer 212, 222 other than those established by one or more existing microbumps. Adding or removing a dummy bump to a region increases or decreases its structure density. In one embodiment, the size, for example, the surface area of ​​the dummy bump, may be different from that of a microbump in the same region.In some embodiments, the addition or removal of a dummy bump is performed based on the microbump feature density value determined in operation 520. For example, one or more dummy bumps may be added to a region if the region's feature density value is lower than an expected value for the region. One or more dummy bumps may be removed from a region if the region's feature density value is greater than an expected value for the region.

[0038] After a dummy bump is added to or removed from a region, the structure density smoothing operations can be performed again to plan the structure density.

[0039] In one embodiment, the feature density planning or alignment of the microbumps 204 on the first wafer 202 may also be performed based on the corresponding interconnect features 214, 224 of the second wafer 212, 222. For example, in a case where the interconnect features 214, 224 on the second wafer 212, 222 have an unequal height H2, the corresponding microbumps 204 on the first wafer 202 may also have an unequal height H1, such that each microbump 204 may be properly connected to a corresponding interconnect feature 214, 224. For example, an interconnect feature 214 of a larger height H2 fits a microbump 204 with a smaller height H1, while an interconnect feature 214 of a smaller height H2 fits a microbump 204 with a larger height H1.The reference planning unit 426 may obtain the information about the height H2 of the corresponding second wafer 212, 222 and determine the information about the matching height H1 based on the obtained information about the height H2. The information about the matching height H1, for example, the height variations between the microbumps 204, may be used to adjust the feature density of each grid region, since the feature density correlates with the heights of the microbumps 202.

[0040] After the structure density of each raster region has been adjusted based on the operation of the reference planning unit 426, the structure density smoothing operations may be performed again to plan the structure density. The example operations 520, 530 may be performed iteratively until the expected structure density values ​​are reached for each individual region or until other conditions for terminating the iteration are met. For example, the iteration may be terminated when the total number of iteration rounds has reached a threshold.

[0041] In the example operation 540, the feature layout correction unit 430 may adjust the layout of the microbumps 204 formed on the first wafer 202 based on the planned feature density of the grid regions. The adjustment may include adjusting the surface area of ​​each microbump 202 in each grid region. Note that the feature density of a grid region is determined as a ratio between the total surface area of ​​the microbumps in the grid region and the surface area of ​​the grid region. In some embodiments, the surface area of ​​the microbumps in a grid region is determined or adjusted based on the planned feature density for the grid region. For example, a higher feature density of a grid region generally indicates that the total surface area of ​​the microbumps in the grid region is larger.In a case where a raster region A and a raster region B have the same planned feature density and raster region A has fewer microbumps than raster region B, the surface area of ​​the microbumps in raster region A will be larger than the surface area of ​​the microbumps in raster region B. In a case where a raster region A and a raster region B have the same number of microbumps and raster region A has a larger feature density than raster region B, the surface area of ​​the microbumps in raster region A will be larger than the surface area of ​​the microbumps in raster region B. Furthermore, dummy bumps can be added to or removed from a raster region in feature density planning and need to be implemented in layout correction.

[0042] In some embodiments, the feature layout correction unit 430 may also adjust a position of a microbump on the surface of the first wafer 202. Adjusting the microbump position may change the feature density in the relevant grid region. Adjusting the microbump position may make the feature density values ​​of adjacent grid regions more consistent with each other, so that the corresponding heights of the microbumps formed in the relevant grid regions are more consistent.

[0043] In one embodiment, the feature layout correction 430 may apply a rule when adjusting the layout. The one or more rules may provide constraints on the adjustment of the surface area or surface size of a microbump. For example, a rule may provide that the surface area of ​​a microbump must not be smaller than a threshold value, such that proper connection to the corresponding connecting features 214, 224 is ensured. A rule may also provide that a space between two adjacent microbumps must not be smaller than a threshold value, such that an undesirable short-circuit fault is avoided. The feature layout correction 430 may retrieve rules from the rule engine 432.

[0044] In the example operation 550, the layout generation unit 434 adjusts or generates the process parameters to achieve the corrected layout of the microbumps 204 formed on the first wafer 202. The process parameters include all parameters related to the layout of the microbumps 204. For example, in the example scenario of forming microbumps, the parameters of the photoresist structures may be adjusted according to the surface size of the microbumps and the positions of the microbumps 204 formed on the first wafer 202.

[0045] In the example operation 560, the implementation unit 436 controls the tool set 330 in forming the microbumps 204 based on the parameters generated by the layout generation unit 434. For example, the implementation unit 436 may control the operation of the scanner 332 in forming a patterned photoresist layer containing openings 356 to expose the seed layer 354 for forming the microbumps 202. The sizes and positions of the openings 356 are controlled by the layout parameters generated by the layout generation unit 434.

[0046] After the patterned photoresist layer is formed, microbumps are formed on the base of the patterned photoresist layer. For example, the microbumps are formed in the openings 356 of the patterned photoresist layer. Fig. 5 is an illustrative example process of forming the microbumps, but this does not limit the scope of the disclosure.

[0047] For example, electrodeposited solder bumps with very close pitches are formed on the seed layer exposed through the openings of the patterned photoresist layer. The photoresist layer is then removed. The wafer is then reflowed at a temperature above the melting point of the solder to complete the metallic bonding of the microbumps to underlying metal pads and to transform the microbumps from their deposited form into a spherical shape, signaling the completion of microbump formation. After the microbump formation, the wafer is cut into individual chips, which then undergo subsequent encapsulation processes such as bonding processes of Fig. 2. Some exemplary reflow processes coat the wafer with a flux and then reflow the wafer in a nitrogen environment. Such a flux-based reflow process may include a flux cleaning operation, since the decomposition of organic fluxes can leave residues and generate volatiles that are contaminants on the wafer. Some reflow processes do not include fluxes, and there is no flux cleaning operation. Other methods for forming microbumps based on the patterned photoresist layer are also possible and fall within the scope of the disclosure.

[0048] Fig. 6 shows a processor-based device 604 suitable for implementing various embodiments described herein. For example, the processor-based device 604 may be configured for the computer systems of the customer 110, the platform 120, the publisher 130, and / or the content provider 140 of Fig. 1. Although not required, some embodiments will be described in the general context of processor-executable instructions or processor-executable logic, such as program application modules, objects, or macros, executed by one or more processors. Those skilled in the art will appreciate that the described embodiments, as well as other embodiments, may be practiced with various processor-based system configurations, including handheld devices such as smartphones and tablet computers, wearable devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (PCs), network PCs, minicomputers, mainframe computers, and the like.

[0049] The processor-based device 604 may, for example, take the form of a smartphone or tablet computer that includes one or more processors 606, a system memory 608, and a system bus 610 that couples various system components, including the system memory 608, to the processor(s) 606. The processor-based device 604 is occasionally referred to in the singular herein, but this is not intended to limit the embodiments to a single system, as certain embodiments involve more than one system or other networked computing device. Non-limiting examples of commercially available systems include, but are not limited to, ARM processors from a variety of different manufacturers, Core microprocessors from Intel Corporation, USA, PowerPC microprocessors from IBM, and Sparc microprocessors from Sun Microsystems, Inc., PA-RISC series microprocessors from Hewlett-Packard Company, and 68xxx series microprocessors from Motorola Corporation.

[0050] The one or more processors 606 may be any logical processing unit, for example, one or more central processing units (CPUs), microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc. Unless otherwise described, the structure and operation of the Fig. 6 are of a conventional type. Consequently, such blocks need not be described in detail here, as they will be understood by those skilled in the art.

[0051] System bus 610 may use any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 608 includes read-only memory (ROM) 612 and random access memory (RAM) 614. A basic input / output system (BIOS) 616, which may be part of ROM 612, contains basic routines that assist in transferring information between elements within processor-based device 604, such as during boot-up. Some embodiments may use separate buses for data, instructions, and power.

[0052] The processor-based device 604 may also include one or more solid-state memories, for example, flash memory or a solid-state drive (SSD) 618, which provides non-transitory storage of computer-readable instructions, data structures, program modules, and other data for the processor-based device 604. Although not shown, the processor-based device 604 may utilize other non-transitory computer- or processor-readable media, for example, a hard disk drive, an optical disk drive, or a memory card media drive.

[0053] System memory 608 may store program modules such as an operating system 630, one or more application programs 632, other programs or modules 634, drivers 636, and program data 638.

[0054] The application programs 632 may, for example, include panning / scrolling 632a. Such panning / scrolling logic may include, among other things, logic that determines when and / or where a pointer (e.g., finger, stylus, cursor) enters a user interface element having a region including a central portion and at least one edge. Such panning / scrolling logic may include, among other things, logic that determines a direction and a rate at which at least one element of the user interface element should appear to move and causes a display to be updated to cause the at least one element to appear to move in the particular direction at the determined rate. The panning / scrolling logic 632a may, for example, be stored as one or more executable instructions.The pan / scroll logic 632a may include processor and / or machine-executable logic or instructions for generating user interface objects using data characterizing the movement of a pointer, for example, data from a touch-sensitive display or from a computer mouse or trackball or other user interface device.

[0055] The system memory 608 may also include communications programs 640, for example, a server and / or a web client or browser, to enable the processor-based device 604 to access and exchange data with other systems, such as user computer systems, websites on the Internet, corporate intranets, or other networks, as described below. The communications program 640 in the illustrated embodiment is markup language-based, such as Hypertext Markup Language (HTML), Extensible Markup Language (XML), or Wireless Markup Language (WML), and operates with markup languages ​​that use syntactically delimited characters added to the data of a document to represent the structure of the document. A number of servers and / or web clients or browsers are available on the open market, such as those from Mozilla Corporation of California and Microsoft of Washington.

[0056] The operating system 630, the application programs 632, other programs / modules 634, drivers 636, program data 638 and server and / or browser 640 are in Fig. 6 as being stored in system memory 608, but they may also be stored on any of a wide variety of non-transitory processor-readable media (e.g., hard disk, optical drive, SSD, and / or flash memory).

[0057] A user can enter commands and information via a pointer, for example, via input devices such as a touchscreen 648, via a finger 644a, a stylus 644b, or via a computer mouse or trackball 644c that controls a cursor. Other input devices may include a microphone, a joystick, a gamepad, a tablet, a scanner, a biometric scanning device, etc. These and other input devices (i.e., I / O devices) are coupled to the one or more processors 606 via an interface 646, such as a touchscreen controller and / or a Universal Serial Bus (USB) interface that couples user input to the system bus 610, although other interfaces such as a parallel port, a game port, a wireless interface, or a serial port may also be used.The touchscreen 648 may be coupled to the system bus 610 via a video interface 650, such as a video adapter, to receive image data or image information for display via the touchscreen 648. Although not shown, the processor-based device 604 may also include other output devices such as speakers, a vibrator, a haptic actuator or haptic engine, etc.

[0058] The processor-based device 604 operates in a networked environment and uses one or more of the logical connections to communicate with one or more remote computers, servers, and / or devices over one or more communication channels, for example, one or more networks 614a, 614b. These logical connections may support any known method that allows computers to communicate, for example, over one or more LANs and / or WANs, such as the Internet and / or cellular networks. Such network environments are well known in wired and wireless enterprise computer networks, intranets, extranets, the Internet, and other types of communication networks, including telecommunications networks, cellular networks, paging networks, and other mobile networks.

[0059] When used in a network environment, the processor-based device 604 may include one or more network, wired, or wireless communication interfaces 652a, 656 (e.g., network interface controllers, cellular devices, Wi-Fi radios, or Bluetooth radios) for establishing communication over the network, e.g., the Internet 614a or the cellular network.

[0060] In a networked environment, program modules, application programs, or data, or portions thereof, may be stored in a server computer system (not shown). Those skilled in the art will recognize that the Fig. 6 are only some examples of ways to establish communication between computers and that other connections, including wireless, may also be used.

[0061] For simplicity, the processor(s) 606, the system memory 608, and the network and communication interfaces 652a, 656 are illustrated as being communicatively coupled to one another via the system bus 610, thereby providing connectivity between the components described above. In alternative embodiments of the processor-based device 604, the components described above may also be implemented in a manner other than Fig. 6. For example, one or more of the components described above may be directly coupled to other components or may be coupled to each other via intermediate components (not shown). In some embodiments, the system bus 610 is omitted, and the components are directly coupled to each other using suitable interconnections.

[0062] Fig. 7 shows an exemplary division grid 700 of a wafer with n×m grid regions and an exemplary mask structure (M) 720 for a grid region. Each of the n×m grid regions has a grid size of w.

[0063] Fig. 8 shows an exemplary structure density smoothing process 800 that includes a downsampling path 810 and an upsampling path 850 for structure density smoothing.

[0064] The exemplary structure density smoothing process 800 of Fig. 8 is used here with reference also to Fig. 7. In the exemplary structure density smoothing, Gaussian smoothing is used as an exemplary smoothing technique, which does not limit the scope of the disclosure. Other image smoothing techniques, such as order statistical smoothing (mean, median) or low-pass Butterworth smoothing, may also be used for structure density smoothing at any level of division grids.

[0065] Fig. Figure 8 shows the feature density smoothing process on a single die as an illustrative example. Similar feature density smoothing operations can be performed symmetrically on multiple dies or can be performed on a full wafer, for example, a 300 mm wafer or a 450 mm wafer.

[0066] Process 800 begins the downsampling path 810. At a first raster level 812, the raster size w = 500 µm. A raster region contains an area of ​​500 µm × 500 µm. The initial structure density ρ(x, y) of a raster region M(x, y) is determined using the algorithms (1), (2) described here. Using the initial structure density values ​​for all obtained raster regions, the local structure density correction is calculated according to the following algorithms: ρn'=K∗(G∗ρn) Gσn×σn(i,j)=12πσne−(i−io)2+(j−jo)22σn;io=jo=⌈σn2⌉ K=f1(ρn,∇ρn) where: ρ ndenotes an initial structure density value of a raster region M(x, y) on a raster level n where the downsampling path begins; ρ n ' denotes the structure density after the local correction; K denotes a gradient-aware correction kernel; ∇ρ n the 2D gradient of ρ n denoted; σ n a cluster size of σ n × σ n neighboring raster regions used in the local correction, for example, σ n = 3 indicates that 9 adjacent raster regions, including the raster region M(x, y), are used in the local correction.

[0067] On a second rasterization level 814, the raster size is increased to w = 1500 µm. A raster region contains an area of ​​1500 µm × 1500 µm. Due to the increased size, a raster region of the second raster level 814 can contain multiple raster regions of the first raster level 812. In one embodiment, the region size of the second raster level 814 is the same as the size of the cluster of neighboring raster regions used in the local correction operation of the first raster level 812. Thus, a raster region of the second raster level 814 contains 9 neighboring raster regions of the first raster level 812, that is, σ n= 3. The initial structure density of a raster region of the second raster level 814 is determined based on the corrected structure density value of the raster regions of the first raster level 812 included in the raster region of the second raster level 814. In one embodiment, the following algorithm is used to determine the initial structure density value of a raster region of the second raster level 814: ρn+1(x,y)=1σn2∑(x',y')∈N(x,y)ρn'(x'.y') where ρ n+1 (x,y) denotes an initial structure density value of a raster region on a raster level n+1 and ρ n (x', y') denotes a locally corrected structure density value of a raster region of raster level n contained in the raster region on raster level n+1.

[0068] If the initial structure density values ​​for all raster regions on the second raster level 814 are obtained using algorithm (6), the local structure density correction for the second raster level 814 is calculated using algorithms (3), (4) and (5).

[0069] After the local corrections for the raster level 814 are completed, the downsampling path proceeds to a third raster level 816, where the raster size is further increased to w = 4500 µm or three times the raster size of the second raster level 814, that is, σ n = 3. Similar operations to those on the second raster level 814 are performed on the third raster level 816 based on the locally corrected structure density values ​​of the second raster level 814.

[0070] The local correction operations are further performed on each of the raster planes 818, 820 along the downsampling path 810 until the raster size reaches a threshold, for example, w = 40.5 mm on the raster plane 820. After the local correction operation for the raster plane 820 is completed, the upsampling path 850 begins.

[0071] Along the upsampling path 850, the raster size decreases in the order of raster levels 820, 818, 816, 814, and 812. At each raster level, the structure density of a raster region is determined based on the locally corrected structure density of the downsampling path 810 and a global correction factor. The global correction factor is determined based on the structure density value of a raster region of a larger raster size w. In one embodiment, the following algorithm is used to determine a corrected structure density value in the upsampling path 850: ρn''=ρn'+f2(ρln,ρun,ΔGn) , where ρ n' denotes the structure density after local correction in the downsampling path; ρln,ρun a structural density lower limit and a structural density upper limit; and ΔGn a global correction factor at raster level n based on the structure density values ​​of raster level n+1.

[0072] The ΔGn can be determined using the following algorithm: ΔGn=ρn+1'−ρn+1

[0073] In one embodiment, the structure density lower limit and / or the structure density upper limit may be retrieved or determined based on rules stored in the rule engine 432.

[0074] In the exemplary process 800, the downsampling path 810 is executed before the upsampling path 850. As described herein, this sequential order emphasizes the influence of the local neighboring raster regions compared to the global influence. In a scenario where the global influence is more important than the local influence, a reverse sequential order may be followed between the downsampling path 810 and the upsampling path 850.

[0075] Although not required, the implementations are described in the general context of computer-executable instructions, such as program application modules, objects, or macros, stored on computer- or processor-readable storage media and executed by a computer or processor. Those skilled in the art will appreciate that the illustrated embodiments, as well as other implementations, may be practiced with other system configurations and / or other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (PCs), network PCs, minicomputers, mainframes, and the like.The implementations may be practiced in distributed computing environments in which tasks or modules are executed by spatially remote processing devices linked together via a communications network 150, such as the Internet. In a distributed computing environment, program modules may be located in both local and spatially remote storage devices.

[0076] The above detailed description has set forth various implementations of the devices and / or processes by way of block diagrams, flowcharts, and examples. To the extent that such block diagrams, flowcharts, and examples contain one or more functions and / or operations, it will be apparent to those skilled in the art that each function and / or operation within such block diagrams, flowcharts, or examples may be implemented individually and / or collectively by a wide variety of hardware, software, firmware, or virtually any combination thereof. In one implementation, the subject matter discussed herein may be implemented by application-specific integrated circuits (ASICs).However, one skilled in the art will recognize that the implementations disclosed herein, in whole or in part, may equally well be implemented in standard integrated circuits as one or more computer programs running on one or more computers (e.g., one or more programs running on one or more computer systems), as one or more programs running on one or more controllers (e.g., microcontrollers), as one or more programs running on one or more processors (e.g., microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and / or writing code for the software and / or firmware would be well within the skill of one of ordinary skill in the art in light of this disclosure.

[0077] Those skilled in the art will recognize that many of the methods or algorithms set forth herein may employ additional actions, omit some actions, and / or perform actions in a different order than that specified.

[0078] Furthermore, one skilled in the art will appreciate that the mechanisms taught herein may be distributed as a program product in a variety of different forms, and that an illustrative implementation applies equally regardless of the specific type of signal-carrying medium used to actually accomplish the distribution. Examples of signal-carrying media include, but are not limited to, the following: recordable media such as floppy disks, hard disks, CD-ROMs, digital tapes, and computer memory.

[0079] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0081] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent to those skilled in the art that the disclosure may be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring essential aspects of the descriptions of the embodiments of the present disclosure.

[0082] Unless the context requires otherwise, throughout this specification and in the following claims, the word "comprise" and its variations, such as "comprises" and "comprising," are to be construed in an open, inclusive sense, that is, as "including, but not limited to."

[0083] The use of ordinal numbers such as “first”, “second” and “third” does not necessarily imply a ranking, but merely needs to distinguish between multiple instances of an action or structure.

[0084] Whenever this specification refers to "a particular embodiment" or "an embodiment," it means that a particular structural element, structure, or feature described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in a particular embodiment" or "in an embodiment" in various places in this specification are not necessarily all referring to the same embodiment. Moreover, the particular structural elements, structures, or features may be combined in one or more embodiments in any suitable manner.

[0085] For the purposes of this specification and the appended claims, the singular forms "a" and "an" include the plural senses unless the context clearly requires otherwise. It should also be noted that the term "or" is generally used to include "and / or" unless the context clearly requires otherwise.

[0086] The present disclosure can be further understood from the description of the following embodiments.

[0087] In one method embodiment, first layout data is received. The first layout data represents a plurality of features to be formed on a surface of a wafer. The surface includes a plurality of raster regions below a first dividing plane. For each of the plurality of raster regions below the first dividing plane, an initial feature density value is determined. A planned feature density value of a first raster region of the plurality of raster regions is obtained by adjusting an initial feature density value of the first raster region based on an initial feature density value of a second raster region of the plurality of raster regions below the first dividing plane. Second layout data of the first raster region is determined based on the planned feature density value. The plurality of features is formed on the surface of the wafer based at least in part on the second layout data of the first raster region.

[0088] In one system embodiment, a system includes a wafer processing tool configured to form a plurality of interconnect features on a wafer surface, a database configured to store design data of the plurality of interconnect features, and a processor-based controller configured to control the wafer processing tool to form the plurality of interconnect features on the wafer surface.The processor-based controller is adapted to perform actions including: dividing the wafer surface into a plurality of first raster regions below a first dividing plane; determining a first feature density value for a first raster region of the plurality of first raster regions; adjusting the first feature density value of the first raster region based on a second feature density value of a second raster region of the plurality of first raster regions; determining layout data of the first raster region based on the adjusted first feature density value of the first raster region; and controlling the wafer processing tool such that a plurality of interconnect features are formed on the surface of the wafer based at least in part on the layout data of the first raster region.

[0089] In another method embodiment, first layout data is received. The first layout data indicates a plurality of discrete conductive structures formed on a surface of a first substrate. The plurality of discrete conductive structures includes a first discrete conductive structure formed in a first region on the surface. A feature density value of the first region is determined. A height value of the first discrete conductive structure is determined. The feature density value of the first region is adjusted based on the height value of the first discrete conductive structure. A layout of the first grid region is determined based on the adjusted feature density value. The plurality of discrete conductive structures are formed on the surface based at least in part on the layout of the first grid region.

[0090] The various embodiments described above may be combined to obtain additional embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications referenced in this specification and / or listed in the application data sheet are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified, as necessary, to utilize concepts from the various patents, applications, and publications to obtain additional embodiments.

Claims

[1] Procedure which includes: Dividing initial layout data into several raster regions; Determining an initial structure density value for each of the plurality of raster regions under a first division plane; Obtaining a planned structure density value of a first raster region of the plurality of raster regions by adjusting an initial structure density value of the first raster region based on an initial structure density value of a second raster region of the plurality of raster regions under the first division plane; Determining second layout data of the first raster region based on the planned structure density value; and Forming a plurality of structural elements on a surface of a wafer (202, 212, 222, 232, 242) based at least in part on the second layout data of the first raster region. [2] The method of claim 1, wherein the initial structure density value is determined based on the first layout data. [3] The method of claim 2, wherein the initial structure density value is determined based on the first layout data with respect to the first raster region and an edge area adjacent to the first raster region. [4] The method of claim 1, wherein the initial structure density value is determined based on a structure density value of a third raster region under a second division plane, and the third raster region overlaps with the first raster region. [5] The method of claim 4, wherein the third raster region includes the first raster region. [6] The method of claim 4, wherein the third raster region is included in the first raster region. [7] The method of any preceding claim, wherein determining the second layout data of the first raster region based on the planned structure density value includes determining a surface region of a structure element in the first raster region. [8] The method of any preceding claim, wherein obtaining the planned structure density value of the first raster region of the plurality of raster regions further includes adding a structure element to the first raster region. [9] The method of any preceding claim, wherein obtaining the planned feature density value of the first raster region of the plurality of raster regions further includes removing a feature from the first raster region. [10] A method according to any one of the preceding claims, wherein adjusting the initial feature density value of the first raster region based on the initial feature density value of the second raster region includes a Gaussian smoothing calculation. [11] A method according to claim 10, wherein the Gaussian smoothing computation uses a gradient-aware correction kernel. [12] System that includes: a wafer processing tool configured to form a plurality of interconnect structure elements on a wafer surface; a database (320) configured to store design data of the plurality of interconnection structure elements; and a processor-based controller (310) adapted to control the wafer processing tool to form the plurality of interconnect structure elements on the wafer surface, including the following actions: Dividing the wafer surface into a plurality of first raster regions under a first dividing plane; Determining a first structure density value for a first raster region of the plurality of first raster regions; Adjusting the first structure density value of the first raster region based on a second structure density value of a second raster region of the plurality of first raster regions; Determining layout data of the first raster region based on the adjusted first structure density value of the first raster region; and Controlling the wafer processing tool such that the plurality of interconnect structure elements are formed on the surface of the wafer (202, 212, 222, 232, 242) based at least in part on the layout data of the first raster region. [13] The system of claim 12, wherein the actions further comprise: Dividing the wafer surface into a plurality of second raster regions under a second dividing plane; Determining a third structure density value for a third raster region of the plurality of second raster regions; and Adjusting the third structure density value of the third raster region based on a fourth structure density value of a fourth raster region of the plurality of second raster regions. [14] The system of claim 13, wherein the third raster region includes the first raster region and the third feature density value of the third raster region is determined based on the adjusted first feature density value. [15] The system of claim 13 or 14, wherein the third raster region includes the first raster region, and wherein adjusting the first feature density value of the first raster region is based on the adjusted third feature density value of the third raster region. [16] Procedure which includes: Dividing initial layout data into several raster regions; Determining a structure density value of a first raster region of the plurality of raster regions; Determining a height value of a first discrete conductive structure in the first grid region; Adjusting the structure density value of the first raster region based on the height value of the first discrete conductive structure; Determining a layout of the first raster region based on the adjusted structure density value; and Forming a plurality of discrete conductive structures on a surface of a first substrate based at least in part on the layout of the first grid region. [17] The method of claim 16, wherein the height value of the first discrete conductive structure is a relative height value with respect to another of the plurality of discrete conductive structures. [18] The method of claim 16 or 17, wherein the height value is determined based on a surface layout of a second substrate configured to be coupled to the first substrate through the surface of the first substrate. [19] The method according to any one of claims 16 to 18, wherein the structure density value of the first raster region is determined on the basis of the first layout data. [20] The method of claim 19, wherein the structure density value is determined based on the first layout data with respect to the first raster region and an edge area adjacent to the first raster region.

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