storage device

Abstract

Storage device (10) comprising: a peripheral circuit area (200) containing a first substrate (210) and circuit elements (220) on the first substrate (210), the circuit elements (220) comprising a series decoder (31); a cell array area (CA) comprising: word lines (130A, 130B) stacked on a second substrate (110A, 110B) on the peripheral circuit area (200), and channel structures (150A, 150B) extending in a direction perpendicular to an upper surface of the second substrate (110A, 110B) and penetrating the word lines (130A, 130B); and a cell contact area (CT1, CT2) containing cell contacts (160A, 160B) connected to the word lines (130A, 130B), wherein the cell contact area (CT1, CT2) is positioned on both sides of the cell array area (CA) in a first direction parallel to the upper surface of the second substrate (110A, 110B), wherein the cell contact area (CT1,CT2) comprises a first cell contact area (CT1) and a second cell contact area (CT2), wherein the first (CT1) and second cell contact areas (CT2) have different lengths relative to each other in the first direction, wherein both the first (CT1) and the second cell contact area (CT2) contain: first pads (PAD1) having different lengths relative to each other in the first direction, and second pads (PAD2) that differ from the first pads (PAD1), wherein the cell contacts (160A, 160B) are connected to the word lines (130A, 130B) in the first pads (PAD1), the number of second pads (PAD2) contained in the first cell contact area (CT1) is greater than the number of second pads (PAD2) contained in the second cell contact area (CT2), the series decoder (31) first pass-through elements (221) and second pass-through elements (222) which are connected to the word lines (130A, 130B) are connected, contains,each of the first through-elements (221) is connected to one of the word lines, and each of the second through-elements (222) is connected to two or more word lines below the word lines (130A, 130B), and each of the word lines (130A, 130B) connected to the first through-elements (221) has a higher resistance than any of the word lines (130A, 130B) connected to the second through-elements (222).

Description

Cross-reference to similar applications

[0001] This application claims priority to Korean Patent Application No. 10-2019-0095526, filed on August 6, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. background

[0002] The present disclosure relates to memory devices.

[0003] A memory device may provide functions for writing and erasing data or for reading written data. Memory devices can be divided into non-volatile memory devices and volatile memory devices. Non-volatile memory devices retain their stored data even if their power supplies are interrupted. Data storage capacity required for memory devices tends to increase. Accordingly, various methods have been proposed to increase integration density of a memory device. Summary

[0004] Embodiments provide a memory device having an increased integration density by forming a cell region included in the memory device such that they are asymmetric in at least one direction among directions parallel to a top surface of a substrate.

[0005] According to some embodiments, a memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including word lines stacked on a second substrate on the peripheral circuit region and channel structures extending in a direction perpendicular to a top surface of the second substrate and penetrating the word lines; and a cell contact region including cell contacts connected to the word lines and located on both sides of the cell array region in a first direction parallel to the top surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths from each other in the first direction.Each of the first and second cell contact regions includes first pads that have different lengths from each other in the first direction, and second pads that are different from the first pads. The cell contacts are connected to the word lines in the first pads. The number of second pads included in the first cell contact region is greater than the number of second pads included in the second cell contact region.

[0006] According to some embodiments, a memory device includes a peripheral circuit region including via elements on a first substrate; and a plurality of cell regions on a second substrate over the peripheral circuit region, each of the plurality of cell regions including at least one memory block. Each of the plurality of cell regions includes a cell array region in which a plurality of wordlines are connected to the via elements and a plurality of channel structures penetrate the wordlines, and a cell interconnect region in which the wordlines extending from the cell array region are connected to a plurality of cell contacts.At least one of the via elements is commonly connected to a pair of word lines included in a pair of cell regions adjacent to each other among the cell regions, and the pair of word lines is on the same plane from an upper surface of the second substrate.

[0007] According to some embodiments, a memory device includes a peripheral circuit region including via elements; and a plurality of cell regions, each of the plurality of cell regions including a cell array region including word lines stacked on a substrate above the peripheral circuit region and channel structures penetrating the word lines. Each of the plurality of cell regions includes a first cell region and a second cell region adjacent to each other in a first direction parallel to a top surface of the substrate, and a third cell region and a fourth cell region adjacent to each other in the first direction. A distance between the cell array region of the first cell region and the cell array region of the second cell region is different from a distance between the cell array region of the third cell region and the cell array region of the fourth cell region. List of characters

[0008] For a clearer understanding of the above and other aspects, features and advantages of the present disclosure, the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 and Fig. 2 are schematic representations of a memory device according to some embodiments; Fig. 3 and Fig. 4 illustrates a connection relationship between a memory cell array and pass elements in a memory device according to some embodiments; Fig. 5 is a schematic top view of a memory device according to some embodiments; Fig. 6A and Fig. 6B Areas of Fig. 5 show the storage devices shown; Fig. 7A and Fig. 7B illustrates a portion of a memory device according to some embodiments; Fig. 8A and Fig. 8B illustrates a portion of a memory device according to some embodiments; Fig. 9 and Fig. 10 illustrates a schematic configuration of a memory device according to some embodiments; Fig. 11 to Fig. 14 are schematic plan views of a memory device according to some embodiments; Fig. 15 a cross-sectional view along line II' in Fig. 11 is; Fig. 16 a cross-sectional view along line II-II' in Fig. 11 is; Fig. 17 a cross-sectional view along line III-III' in Fig. 12 is; Fig. 18A and Fig. 18B is a schematic representation of Fig. 17 passage elements shown are; Fig. 19 and Fig. 20 are cross-sectional views illustrating a cell contact area of ​​a memory device according to some embodiments; Fig. 21 is a cross-sectional view illustrating a cell array region of a memory device according to some embodiments; Fig. 22 to Fig. 24B enlarged views of an area in Fig. 21 are; Fig. 25 is a cross-sectional view illustrating a cell array region of a memory device according to some embodiments; Fig. 26A, Fig. 26B, Fig. 27A and Fig. 27B enlarged views of an area in Fig. 25 are; and Fig. 28 is a schematic block diagram of an electrical device including a memory device according to some embodiments. Detailed description

[0009] Embodiments are described below with reference to the accompanying drawings.

[0010] Fig. 1 and Fig. 2 are schematic block diagrams of a memory device according to some embodiments.

[0011] Referring to Fig. 1 may be a storage device 10 a memory cell array 20 and a peripheral circuit 30 included. The peripheral circuit 30 can have a row decoder 31 , a voltage generator 32 , a page buffer 33 , an input / output circuit 34 , a control logic 35 and similar. The memory cell array 20 may contain a plurality of memory cells and may be divided into a plurality of memory blocks. The plurality of memory cells may be connected by a string selection line SSL, word lines WL and a ground selection line GSL with the row decoder 31 connected, and by bit lines BL with the page buffer 33 In embodiments, a plurality of memory cells arranged in the same row may be connected to the same word line WL connected, and a plurality of memory cells arranged in the same column can be connected to the same bit line BL be connected.

[0012] The row decoder 31 can have an address decoder ADDR, which is used by the control logic 35 or similar, to generate a voltage to drive the word lines WL to generate and transmit. The row decoder 31 can be used in response to a control of the control logic 35 a word line voltage generated by the voltage generator 32 is generated into the word lines WL As an example, the row decoder 31 through passage elements of a passage element unit 31A with the word lines WL connected and can transfer the word line voltage into the word lines WL enter if the through elements of the through element unit 31A be switched on.

[0013] The page buffer 33 is through bit lines BL with the memory cell array 20 and can read data stored in memory cells or write data to the memory cells. The page buffer 33 may include a column decoder and a sense amplifier. The column decoder may include at least a section of bit lines BL of the memory cell array 20and the sense amplifier can read data of a memory cell connected to a bit line selected by the column decoder during a read operation.

[0014] The input / output circuit 34 can receive data DATA and transfer the received data DATA to the page buffer during a programming operation 33 and can transfer data DATA that is transmitted through the page buffer 33 from the memory cell array 20 be read, output to an external unit during a read operation. The input / output circuit 34 can pass an address or an instruction received from an external memory controller to the control logic 35 transmitted.

[0015] The tax logic 35 can perform operations of the row decoder 31 , the voltage generator 32 , the page buffer 33and the like. In some embodiments, the control logic 35 operate according to a control signal and an external voltage transmitted from an external memory controller or similar.

[0016] The voltage generator 32 can control voltages for the operation of the storage device 10 , for example, a programming voltage, a reading voltage, an erase voltage, a pass voltage, and the like, using an external input power supply voltage. A voltage generator 32 generated voltage can be applied to the peripheral circuit 30 or by the row decoder 31 or similar into the memory cell array 20 be entered.

[0017] As an example, a programming voltage may be input to a selected wordline connected to a selected memory cell to which data is to be written during a programming operation. A pass voltage lower than the programming voltage may be input to wordlines connected to unselected memory cells included in a single memory cell string that share a channel region with the selected memory cells.

[0018] In some embodiments, during a read operation, a read voltage may be input to a selected word line connected to a selected memory cell from which data is to be read, and a pass voltage may be input to a non-selected word line connected to non-selected memory cells that share a channel region with the selected memory cell. In some embodiments where each of the memory cells stores data having a plurality of bits, the row decoder may 31 input a plurality of read voltages with differing strengths into a selected word line.

[0019] Referring to Fig. 2, the memory cell array 20 a plurality of memory blocks BLK1 until BLKn Each of the memory blocks BLK1 until BLKn may include word lines stacked in a third direction (a Z-axis direction) and channel structures extending in the third direction (the Z-axis direction) on a plane defined by a first direction (an X-axis direction) and a second direction (a Y-axis direction). The word lines and the channel structures may provide three-dimensionally arranged memory cells. Each of the memory blocks BLK1 until BLKn may include bit lines extending in the first direction (the X-axis direction) or the second direction (the Y-axis direction) and connected to the channel structures. As an example, the memory blocks BLK1 until BLKn in the memory cell array 20 be arranged in the first direction (the X-axis direction) and the second direction (the Y-axis direction).

[0020] Fig. 3 and Fig. 4 illustrate a connection relationship between a memory cell array and pass elements in a memory device according to some embodiments.

[0021] Referring to Fig. 3 a single memory block BLK a plurality of memory cell chains S and at least one section of the memory cell chains S can share word lines WL1 to WLn and bit lines BL1 to BL3.

[0022] Each of the memory cell chains S can have a plurality of memory cells MC which are connected between the first and second string selection transistors SST1 and SST2 and a ground selection transistor GST The first and second string selection transistors SST1 and SST2 can be connected in series. The second string selection transistor above SST2 can be connected to one of the bit lines BL1 to BL2. The ground select transistor GST can be connected to a common source line CSL.

[0023] The majority of memory cells MC can be switched between the first and second string selection transistors SST1 and SST2 and the ground selection transistor GST connected in series. In embodiments, the number of string selection transistors SST1 and SST2 and the ground selection transistor GST be changed differently. The memory cell chains S can further contain at least one dummy memory cell.

[0024] Gate electrodes of the majority of memory cells MC can be connected to the word lines WL1 to WLn. A gate electrode of the ground select transistor GST may be connected to the ground selection line GSL and gate electrodes of the first and second string selection transistors SST1 and SST2 can be connected to the string selection lines SSL11 to SSL23.

[0025] The word lines WL1 to WLn, the ground selection line GSL and the string selection lines SSL11 to SSL23 can be connected to a pass element unit PTU , the passage elements PT A programming operation, a reading operation, an erasing operation and the like can be performed on a plurality of memory cells MC by voltages GS, S1 to Sn, and SS11, which are input to the word lines WL1 to WLn, the ground selection line GSL and the string selection lines SSL11 to SSL23, while the pass elements PT are switched on. In some Fig. 3 shown embodiments, passage elements PT , which are in the block BLK word lines WL1 to WLn contained in the block may not be shared by word lines contained in another block.

[0026] Referring to Fig. 4 can be a first memory block BLK1 and a second memory block BLK2 at least one of the passage elements. In some Fig. 4 shown embodiments, the passage element unit PTU first passage elements PT1 and at least one second passage element PT2 and the second passage element PT2 can be from at least one of the word lines WL1 to WLn of the first memory block BLK1 and the second memory block BLK2 be shared. Referring to Fig. 4, the second passage element PT2 with a first word line WL1 of the first memory block BLK1 and a first word line WL1 of the second memory block BLK2 be connected together.

[0027] The pass elements connected to the word lines WL1 to WLn of the first memory block BLK1 can be switched on and off by a first block selection signal BS1 and pass elements connected to the word lines WL1 to WLn of the second memory block BLK2 connected, can be switched on and off by a second block selection signal BS2. In embodiments, the first block selection signal BS1 and the second block selection signal BS2 can be the same or different from each other. If the first block selection signal BS1 and the second block selection signal BS2 are the same, the signals in the through element unit PTU The through-elements contained in the circuit can be switched on and off simultaneously. This allows the first memory block BLK1 and the second memory block BLK2 be driven simultaneously.

[0028] Fig. 5 is a schematic top view of a memory device according to some embodiments.

[0029] Referring to Fig. 5 can be a storage device 40 According to some embodiments, a plurality of cell areas 50 The majority of cell areas 50 can be on a substrate 41 Each of the cell areas 50 can have word lines arranged in a direction perpendicular to a top surface of the substrate 41 stacked, channel structures extending in a direction perpendicular to the upper surface of the substrate 41 and include cell contacts connected to the word lines and the like.

[0030] Each of the cell areas 50may include a cell array region in which channel structures are mounted, and a cell contact region extending from the cell array region in which word lines and cell contacts are connected. For example, the cell contact region may be arranged around the cell array region in a direction parallel to the upper surface of the substrate. 41 Accordingly, cell contact areas can be adjacent to each other at a boundary of the cell areas 50 be appropriate.

[0031] In the storage device 40 according to the Fig. 5, a peripheral circuit area can be located under the substrate 41 , on which the cell areas 50 The peripheral circuitry region may include at least a portion of circuits for driving devices mounted in the cell regions 50contained memory cells, for example a row decoder, a voltage generator, a page buffer, an input / output circuit and control logic.

[0032] The row decoder may contain pass-through elements connected to word lines of the cell areas 50 In some embodiments, at least one word line may be located in cell areas 50 different from each other, share through elements. The cell contact region arranged around the cell array region may have an asymmetric structure such that at least one word line is located under cell regions 50 word lines that are adjacent to each other share through elements. This will be explained below with reference to Fig. 6A and Fig. 6B described in more detail.

[0033] Fig. 6A and Fig. 6B show areas of the Fig. 5 shown storage devices. As an example, Fig. 6A an enlarged view of an area A1 in Fig. 5 and Fig. 6B may show an enlarged view of an area A2 in Fig. 5. Referring to Fig. 6A and Fig. 6B, the storage device 40 Cell areas 50 and vertically stacked peripheral circuit areas 60 As an example, the cell ranges 50 above the peripheral circuit area 60 be appropriate.

[0034] Each of the cell areas 50 can form a first cell contact area 51 , a second cell contact area 52 and a cell array area 53 , which is placed in between. The cell array area 53may include word lines stacked on top of each other, channel structures penetrating the word lines, and the like. Each of the first and second cell contact regions 51 and 52 may be an area in which word lines extending from the cell array area 53 and cell contacts are connected to each other, and can be on both sides of the cell array area 53 be mounted in a first direction (an X-axis direction).

[0035] In some embodiments, the first cell contact region 51 and the second cell contact area 52 have lengths that differ from each other in the first direction (the X-axis direction). For example, a length L1 of the first cell contact area 51 be greater than a length L2 of the second cell contact area 52 in the first direction (the X-axis direction).

[0036] Referring to Fig. 6A, which is an enlarged view of the area A1 in Fig. 5 shows, the first cell contact areas 51 adjacent to each other between the cell areas 50 Referring to Fig. 6B, which is an enlarged view of the area A2 in Fig. 5 shows, second cell contact areas 52 adjacent to each other between the cell areas 50 Thus, a distance between cell array areas 53 that are located in the cell areas 50 which are adjacent to each other in the storage device 40 are contained, depending on a position of it differ from each other. In the Fig. 6A, a first distance DC1 between the cell array areas 53 be greater than a second distance DC2 between the cell array areas 53 in the Fig. 6b shown embodiments.

[0037] In some embodiments, pass elements connected to word lines in the peripheral circuit area 60 under each of the first and second cell contact areas 51 and 52 The word lines and the through elements can be arranged in the first cell contact area 51 and second cell contact area 52 In some embodiments, at least a portion of the cell contacts connected to the word lines in the second cell contact region 52 connected to one of the through elements. Accordingly, the number of through elements that can be connected in the peripheral circuit area 60 are reduced and an area of ​​the second cell contact area 52 can be reduced to increase the integration density of the memory device 40 to increase.

[0038] Fig. 7A and Fig. 7B illustrate a portion of a memory device according to some embodiments.

[0039] Fig. 7A may be a cross-sectional view illustrating a portion of a memory device according to some embodiments, and Fig. 7B may be an equivalent circuit diagram that Fig. 7A. As an example, in the documents referred to in Fig. 7A and Fig. 7B described embodiments, first contact areas correspond to areas that are adjacent to each other, as in Fig. 6A described above.

[0040] Firstly, referring to Fig. 7A, a memory device may include a peripheral circuit area 200 and a cell range 100 , which is located above the peripheral circuit area 200 The peripheral circuit area 200 can be a first substrate 210, a plurality of circuit elements 220 which are on the first substrate 210 is formed, lower connecting lines 230 which are connected to the circuit elements 220 and contain a lower interlayer dielectric. The interlayer dielectric 240 may be attached to the circuit elements 220 and the lower connecting lines 230 and may contain an insulating material such as silicon oxide, silicon nitride and / or the like.

[0041] The cell area 100 can create a first cell range 100A and a second cell range 100B contain, and the first cell range 100A and the second cell range 100B can have the same structure. The structure of the cell range is shown below 100 with reference to the first cell range 100A As an example, both the first cell range 100Aas well as the second cell area 100B provide at least one memory block.

[0042] The first cell area 100A a second substrate can 110A which is deposited on the lower interlayer dielectric 240 A plurality of word lines 131A until 136A ( 130A ) can be deposited on the second substrate 110A in a third direction (a Z-axis direction) perpendicular to an upper surface of the second substrate 110A be stacked. String selection lines 141A until 142A ( 140A ) and a ground selection line 120A can be placed above and below the word lines 130A The channel structure 150A may extend in a third direction to form the word lines 130A , the string selection lines 140A and the ground selection line 120A to penetrate. The channel structure 150Acan be a data storage layer 151A , a channel layer 152A , a hidden insulating layer 153A and similar, and the channel structure 152A can be done by a bit line contact BLC with a bit line BL electrically connected. In some embodiments, the bit line may BL in a second direction (a Y-axis direction). A region in which the channel structure 150A and the bit line BL can be defined as a cell array area CA.

[0043] The word lines 130A may extend in the first direction (the X-axis direction) and may be provided with a plurality of cell contacts 161A until 164A ( 160A ) in a first cell contact region CT1 adjacent to the cell array region CA in the first direction. In some embodiments, the word lines 130Awith lengths that differ from each other, extending in the first and second directions to form pads PAD1 and PAD2 The cell contacts 160A and the word lines 130A can be found on the pads PAD1 and PAD2 be connected to each other.

[0044] Referring to Fig. 7A, the first cell contact area CT1 first pads PAD1 and second pads PAD2 with an area that differs from an area of ​​the first pads PAD1 Each of the second pads PAD2 may have an area larger than an area of ​​each of the first pads PAD1 . In some embodiments, a length of each of the second pads PAD2 in the first direction be greater than a length of each of the first pads PAD1 in the first direction.

[0045] Vertical contact holes 181A until 184A ( 180A) can be found in at least one section of the pads PAD1 and PAD2 be mounted to pass through a section of the word lines 130A and the second substrate 110A with lower connecting lines 104 a peripheral circuit area P to be connected. The pads PAD1 and PAD2 in which the vertical contact holes 180A can be installed in positions that differ from the positions of the pads PAD1 and PAD2 , with which the cell contacts 160A and the word lines 130A connected, be distinguished, be attached in the second direction.

[0046] The vertical contact holes 180A can be connected by upper connecting lines 170A with the cell contacts 160A connected. The second pads PAD2 and the word lines 130A and the vertical holes 180A which are under the second pads PAD2 can be electrically isolated from each other. As an example, the vertical contact holes 180A through an area in which sacrificial layers are used to form the word lines 130 not be removed but remain, to lower connecting lines 230 extend.

[0047] Fig. 7B can be an equivalent circuit diagram of the Fig. 7A. Referring to Fig. 7B can be any of the first cell range 110A and the second cell range 110B memory cells MC , a ground selection transistor GST , a first string selection transistor SST1 , a second string selection transistor SST2 and similar. The ground select transistor GST can be connected to a common source line CSL and the second string selection transistor SST2 can be connected to a bit line BL be connected.

[0048] In the Fig. 7A and Fig. 7B, the first cell area 110A and the second cell range 110B possibly no passage elements PT . Referring to Fig. 7B, through elements connected to the memory cells MC are connected, the ground selection transistor GST , the first string selection transistor SST1 and the second string selection transistor SST2 in the first cell area 110A from the second cell range 110B be isolated.

[0049] The passage elements PT that start with the first cell range 110A can be controlled by a first block selection signal BS1 and the through elements PT that are connected to the second cell range 110Bcan be controlled by a second block selection signal BS2. After setting the first block selection signal BS1 and the second block selection signal BS2, the first cell area 110A and the second cell range 110B driven simultaneously or independently.

[0050] Fig. 8A and Fig. 8B illustrate a portion of a memory device according to some embodiments.

[0051] Fig. 8A may be a cross-sectional view illustrating a portion of a memory device according to some embodiments, and Fig. 8B may be an equivalent circuit diagram that Fig. 8A. The storage device according to the figures with reference to Fig. 8A and Fig. 8B, the memory device can be configured according to the embodiments described with reference to Fig. 7A and Fig. 7B described embodiments. However, the Fig. 8A from the area shown in Fig. 7A. For example, second contact areas in the memory device may differ according to some embodiments with reference to Fig. 8A and Fig. 8B correspond to regions that are adjacent to each other, as described with reference to Fig. 6B described above.

[0052] Referring to Fig. 8A, a memory device may include a peripheral circuit area 200 and a cell range 100 , which is located above the peripheral circuit area 200 The peripheral circuit area 200 can be a first substrate 210 , a plurality of circuit elements 220 which are on the first substrate 210 is formed, lower connecting lines 230 which are connected to the circuit elements 220connected, a lower interlayer dielectric 240 and similar. The peripheral circuit area 200 can extend continuously from an area of Fig. 7A shown storage device.

[0053] The cell area 100 can create a second cell range 100B and a third cell range 100C and the second cell range 100B and the third cell area 100C may have the same structure as the one with reference to Fig. First cell area described in 7A 100A . A cell array area CA and a second cell contact area CT2, which is located in the cell area 100 are included with reference to the Fig. 8A shown second cell area 100B described in detail.

[0054] The second cell range 100B a second substrate can 11 0Bwhich is deposited on the lower interlayer dielectric 240 is attached, and a plurality of word lines 131B until 136B ( 130B ) can be deposited on the second substrate 110B in a third direction (a Z-axis direction) perpendicular to an upper surface of the second substrate 110B be stacked. String selection lines 141B until 142B ( 140B ) and a ground selection line 120B can be placed above and below the word lines 130B A channel structure 150B can extend in the third direction and can connect the word lines 130B , the string selection lines 140B and the ground selection line 120B penetrate. The channel structure 150B can be a data storage layer 151B , a channel layer 152B , a hidden insulating layer 153B and similar, and the channel structure 152Bcan be done by a bit line contact BLC with a bit line BL electrically connected. In some embodiments, the bit line may BL in a second direction (a Y-axis direction). A region in which the channel structure 150B , the bit line BL and the like are attached, can be defined as a cell array area CA.

[0055] The word lines 130B may extend in the first direction (the X-axis direction) and may be provided with a plurality of cell contacts 161B until 164B ( 160B ) in a second cell contact region CT2 adjacent to the cell array region CA in the first direction. In some embodiments, the word lines 130B with lengths that differ from each other, extending in the first and second directions to form pads PAD1 and PAD2 The cell contacts160B and the word lines 130B can be found on a section of the pads PAD1 and PAD2 be connected to each other.

[0056] Similar to the one with reference to Fig. 7A, the second cell contact region CT2 may comprise at least a second pad PAD2 , which differs from the first pads PAD1 The second pad PAD2 may have an area larger than an area of ​​each of the first pads PAD1 In some embodiments, a length of the second pad PAD2 in the first direction be greater than a length of each of the first pads PAD1 in the first direction.

[0057] Referring to Fig. 7A and Fig. 8A, the first cell contact area CT1 in the second cell area 110B included number of second pads PAD2 be larger than the second cell contact area CT2 in the second cell area 110B included number of second pads PAD2 . Accordingly, the second cell contact region CT2 may extend such that it is relatively shorter than the first cell contact region CT1 in the first direction, and the integration density of the cell regions 100A , 100B and 100C can be increased.

[0058] As an example, the cell areas 100B and 100C , which are inserted adjacent to each other with the second cell contact region therebetween, share at least one of the passage elements. Referring to Fig. 8A circuit elements 220 first passage elements 221 and second passage elements 222 In the second cell range 100B contained word lines 130B at least one section of the word lines 130Bthe second passage elements 222 with in the third cell area 100C The word lines that share the second pass elements 222 divide, can be mounted at the same height in a third direction.

[0059] Referring to Fig. 8A, the second cell contact region CT2 may have common vertical contact holes 181B until 183B ( 180B ) containing the lower connecting lines connected to the second passage elements 222 connected, with some cell contacts 161B until 163B under the cell contacts 160B connect. The common vertical contact holes 180B can be connected by common upper connecting lines 171B until 173B ( 170B ) with at least a section of the word lines of the second cell area 100B and the third cell range 100Cbe connected together. The common upper connecting lines 171B until 173B may be located at positions that differ from each other in the second direction to be electrically isolated from each other. The common vertical contact holes 180B can be added to the peripheral circuit area 200 extend without affecting the second substrate 110B to penetrate.

[0060] Among the cell contacts 160B a specific cell contact can 164B through an individual vertical contact hole 291B with the first passage elements 21 of the peripheral circuit area 200 The individual vertical contact hole 291B can be connected by an individual upper connecting line 292B with cell contact 164B As an example, the individual vertical contact hole 291B of at least one of the pads PAD1 and PAD2 to the peripheral circuit area 200 extend.

[0061] As in Fig. 8A, in the second cell contact area CT2 a section of the adjacent cell areas 100B and 100C contained word lines with the common vertical contact holes 180B be connected to form two passage elements 222 Accordingly, the number of second pads PAD2 which are used to separate from the individual vertical contact holes 291B to the peripheral circuit area 200 to extend, and an area of ​​the second cell contact region CT2 can be reduced to increase an integration density of the memory device 100 to increase.

[0062] Fig. 8B can be an equivalent circuit diagram of the Fig. 8A. Referring to Fig. 8B can be any of the second cell range 110B and the third cell range 110C memory cells MC , a ground selection transistor GST , a first string selection transistor SST1 , a second string selection transistor SST2 and similar. The ground select transistor GST can be connected to a common source line CSL and the second string selection transistor SST2 can be connected to a bit line BL be connected.

[0063] Passage elements PT1 and PT2 , which are equipped with memory cells MC Depending on whether they are connected to a second cell range 110B and a third cell area 110C common, into first passage elements PT1 and second passage elements PT2 For example, the first passage elements PT1 with memory cells MC from the second and third cell range 110B and 110C be connected and the second passage elements PT2 can be used with a section of in the second and third cell range 110B and 110C contained memory cells MC be connected together.

[0064] If a control operation on the third cell range 100C carried out, the second passage elements PT2 using a first block selection signal BS1. The second cell area 100B and the third cell area 100C However, by controlling a through the first passage elements PT1 that are connected to the second cell range 100B connected to the second cell area 100B input voltage independently of each other. In embodiments, the second cell area 100B and the third cell area 100Cbe driven simultaneously.

[0065] Fig. 9 and Fig. 10 show a schematic configuration of a memory device according to some embodiments.

[0066] Firstly, referring to Fig. 9 may be a storage device 300 a peripheral circuit area P and cell areas C1 and C2 The storage device 300 may have a cell-on-peripheral (COP) structure in which the cell areas C1 and C2 above the peripheral circuit area P For example, the cell areas C1 and C2 above the peripheral circuit area P in a third direction (a Z-axis direction). The peripheral circuit area P may comprise a plurality of circuit elements formed on a first substrate 301formed, and can be integrated into a first peripheral circuit area P1 and a second peripheral circuit area P2 be divided into.

[0067] The cell areas C1 and C2 can create a first cell area C1 and a second cell range C2 that are arranged in a first direction (an X-axis direction). The first cell range C1 and the second cell range C2 can each be in second substrates 302 and 303 , which differ from each other. Both the first cell area C1 as well as the second cell area C2 may include a cell array region CA, a first cell contact region CT1 disposed on both sides of the cell array region CA in the first direction, and a second cell contact region CT2. The first cell region C1 and the second cell range C2may have the same structure and may be arranged such that they are horizontally symmetrical or substantially symmetrical with respect to a boundary between the first cell area C1 and the second cell range C2 are.

[0068] Referring to the first cell range C1 the cell array area CA can store a first memory block BLK1 and a second memory block BLK2 , which are divided in a second direction (a Y-axis direction). As an example, the first memory block BLK1 and the second memory block BLK2 be divided by a word line intersection extending in the first direction.

[0069] Word lines of the first memory block BLK1 may extend in the first direction to form a first connection area CR1 , which is contained in a first cell contact region CT1, and a second connection region CR2 , which is contained in a second cell contact region CT2. In addition, word lines of the second memory block BLK2 extend in the first direction to form a first connection area CR1 , which is contained in a second cell contact region CT2, and a second connection region CR2 which is contained in a first cell contact region CT1.

[0070] The first connection area CR1 and the second connection area CR2 may include first pads and second pads provided by word lines. In the first connection area CR1 the first pads and the second pads may form steps in the first direction and the second direction, that is, they may have different depths in the first direction and the second direction. In the second connection area CR2 The first pads and the second pads may form a step in the first direction. In some embodiments, each of the first pads may be shorter than each of the second pads in the first direction.

[0071] In one example, word lines of the first memory block BLK1 with a plurality of cell contacts in the first connection area CR1 of the first cell contact area CT1. At least a portion of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection area CR1 of the first cell contact area CT1, can be connected to through elements of the first peripheral circuit area P1in the second connection area CR2 of the first cell contact area CT1.

[0072] A plurality of vertical contact holes connected to through elements may be formed in at least a portion of the first pads and the second pads in the second connection region CR2 of the first cell contact region CT1. In some embodiments, the vertical contact holes may be connected to at least a portion of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection area CR1 of the first cell contact region CT1 extending in the second direction may be connected by upper connecting lines.

[0073] The cell contacts that are connected to the word lines of the first memory block BLK1 in the first connection area CR1 of the second cell contact region CT2 can be connected to through elements of a first peripheral circuit region P1 in the second connection area CR2 of the second cell contact area CT2 or a boundary area between the first cell area C1 and the second cell range C2 A plurality of vertical contact holes connected to through elements may be formed in the second connection region CR2 the second cell contact area CT2 and a boundary area BA be provided.

[0074] Among the plurality of vertical contact holes, the vertical contact holes formed in the second connection region CR2 of the second cell contact area CT2, with at least a portion of the cell contacts connected to the word lines of the second memory block BLK2 in the first connection area CR1 of the second cell contact area CT2, by upper connecting lines which are arranged above the first cell area C1 Under the vertical contact holes, the vertical contact holes located in the boundary area BA are attached, with the cell contacts connected to the word lines of the second memory block BLK2 in the first connection area CR1 of the second cell contact area CT2, by upper connecting lines which are arranged above the first cell area C1 are attached.

[0075] The vertical contact holes located in the boundary area BA can be connected to a section of the word lines of the second memory block BLK2 and a section of the word lines of the fourth memory block BLK4 connected together. A section of the word lines of the second memory block BLK2 and the fourth memory block BLK4 Through-elements can pass through the vertical contact holes located in the boundary area BA This allows the number of second pads PAD2 in the second cell contact area CT2 adjacent to the boundary area BA be reduced and a distance between the first cell area C1 and the second cell range C2 can be reduced to increase the integration density of the memory device 300 to increase.

[0076] In the Fig. 9, a portion of the through elements arranged under the second cell contact areas CT2 may be formed by different memory blocks BLK1 until BLK4 contained word lines. Thus, the number of through elements disposed under the first cell contact region CT1 may be greater than the number of through elements disposed under the second cell contact region CT2.

[0077] Referring to Fig. 10 may be a storage device 300A a peripheral circuit area P and cell areas C1 and C2 included. Configurations of the peripheral circuit area P and the cell areas C1 and C2 may be used by those who, with reference to Fig. 9. However, a first cell area C1 and a second cell range C2 together on a second substrate 302 Thus, the particles in a border area BA formed vertical contact holes through the second substrate 302 with through elements of the first peripheral circuit area P1 be connected. In the border area BA a substrate insulating layer may be provided to protect the vertical contact holes and the second substrate 302 to be electrically isolated from each other.

[0078] Fig. 11 to Fig. 14 are schematic top views of a memory device according to some embodiments. Fig. 15 is a cross-sectional view along line II' in Fig. 11 and Fig. 16 is a cross-sectional view along line II-II' in Fig. 11. Fig. 17 is a cross-sectional view along line III-III' in Fig. 12 and Fig. 18A and Fig. 18B are schematic representations of Fig. 17 passage elements shown.

[0079] Referring to Fig. 11 and Fig. 12 may be a storage device 400 a first memory block 410 and a second memory block 420 Both the first memory block 410 as well as the second memory block 420may include a cell array region CA and a first cell contact region CT1 and a second cell contact region CT2 disposed on both sides of the cell array region CA in a first direction (an X-axis direction). The first memory block 410 and the second memory block 420 may be adjacent to each other in a second direction (a Y-axis direction).

[0080] Both the first cell contact region CT1 and the second cell contact region CT2 may have a first connection region CR1 and a second connection area CR2 included. Referring to Fig. 11 and Fig. 12, the first cell contact area CT1 of the first memory block 410 a first connection area CR1 protrude and the second cell contact area CT2 of the first memory block 410 can have a second connection area CR2 The first cell contact area CT1 of the second memory block 420 can have a second connection area CR2 and the second cell contact area CT2 of the second memory block 420 can have a first connection area CR1 provide.

[0081] First pads PAD1 and second pads PAD2 can be found in the first connection area CR1 and in the second connection area CR2 In the first connection area CR1 the first pads can PAD1 and the second pads PAD2 Steps in the first direction and a second direction. In the second connecting area CR2 the first pads can PAD1 and the second pads PAD2 Form steps in the first direction.

[0082] Each of the second pads PAD2 may have an area larger than an area of ​​each of the first pads PAD1 As an example, the second pads PAD2 extend so that they are longer than the first pads PAD1 in the first direction. The Fig. 11 and Fig. 12 first pads shown PAD1 and second pads PAD2 can be embodiments and lengths of the first pads PAD1 and the second pads PAD2 can be changed in different ways. As an example, the length of each of the second pads PAD2 in the first direction at least 10 times the length of each of the first pads PAD1 be in the first direction.

[0083] The first memory block 410 and the second memory block 420 can have a plurality of word lines WL which are stacked in a third direction (a Z-axis direction). In the cell array region CA, a plurality of channel structures CH be provided to extend in the third direction and the word lines WL to penetrate. The majority of word lines WL can be achieved by word line cuts WC into a first memory block 410 and a second memory block 420 be divided into.

[0084] First cutting lines CL1 and second cutting lines CL2 can be used between word line cuts WC that are closest to each other in the second direction. The first cut lines CL1 can be formed in the cell array area CA as well as in the cell contact areas CT1 and CT2, while the second cut lines CL2 can only be formed in the cell contact areas CT2. In the Fig. 11 and Fig. In the embodiments shown in 12, the second cutting lines CL2 possibly not in the second connection area CR2 formed.

[0085] In the first pads PAD1 and the second pads PAD2 which are in the first connection area CR1 formed, the word lines can WL with cell contacts CC At least one section of the cell contacts CC may be provided with at least a portion of a plurality of vertical contact holes VV , which in the second connection area CR2 In the cell array region CA, the vertical contact holes VV connected to the cell array region CA and circuit elements under the contact regions CT1 and CT2. As an example, the vertical contact holes VV connected to through-holes located under the contact areas CT1 and CT2. The number and arrangement of the vertical contact holes VV is not limited to those who Fig. 11 and Fig. 12 and the vertical contact holes VV can be found in the second connection area CR2 The number and arrangement of the vertical contact holes VV can be used with regard to routing of the word lines WL be determined.

[0086] As described above, the second cut lines CL2 under the first and second cutting lines CL1 and CL2 possibly not in the second connection area CR2 Accordingly, a process of introducing phosphoric acid through grooves to form the word line cuts WC and the first and second cutting lines CL1 and CL2 to provide victim layers with word lines WL to replace, possibly not in a section of the second connection area CR2 The vertical contact holes VV may extend in the third direction into an area in which the word lines WL are not formed and the sacrificial layers remain to be connected to underlying through elements.

[0087] Referring to Fig. 11, the first cell contact area CT1 can have five second pads PAD2 arranged in the first direction. Referring to Fig. 12, a second cell contact area CT2 can have three second pads PAD2 arranged in a first direction. Accordingly, the first memory block 410 and the second memory block 420 have a structure that is asymmetric to a cell array region CA in the first direction.

[0088] Referring to Fig. 11 and Fig. 12 can be placed under the second pads contained in the first cell contact area CT1 PAD2 a section of second pads PAD2 which is far away from the cell array area CA, in the second cell contact area CT2 with regard to routing of cell contacts CC , which are connected to the word lines WL connected, and vertical contact holes VV that are connected to the cell contacts CC connected, can be omitted. In some embodiments, when the channel structures CH lower channel structures and upper channel structures connected to each other in the third direction, second pads contained in the second cell contact region CT2 PAD2 only by upper word lines penetrated by the upper channel structures. For example, lower word lines penetrated by the lower channel structures may only cover the first pads PAD1 provide.

[0089] Since the number of second pads contained in the second cell contact area CT2 PAD2 is smaller than the number of the first cell contact area CT1, no additional process for providing vertical contact holes is required VV to the cell contacts CC and interconnect the vias. In some embodiments, vertical contact holes VV between the second cell contact areas CT2 adjacent to each other in the first direction in order to be connected to the cell contacts CC The through elements arranged between the second cell contact areas CT2 adjacent to each other in the first direction may be commonly connected to at least a portion of word lines among word lines of memory blocks that are different from each other in order to avoid a connection problem of the cell contacts CC and the passage elements. This will be explained below with reference to Fig. 13 and Fig. 14 described.

[0090] Referring to Fig. 13 and Fig. 14, the storage device 400 first to fourth memory blocks 410 until 440 A first connection area CR1 of the first memory block 410 and a first connection area CR1 of the third memory block 430 may be adjacent to each other in the first direction, and a second connecting region CR2 of the second memory block 420 and a second connection area CR2 of the fourth memory block 440 may be adjacent to each other in the first direction.

[0091] Passage elements PT1 and PT2 can be switched between a first cell range 400A , which contains the first memory block 410 and the second memory block 420 and a second cell area 400B , which contains the third memory block 430 and the fourth memory block 440The passage elements PT1 and PT2 can be located in a peripheral circuit area that is divided into cell areas 400A and 400B is attached, and can be the first passage elements PT1 and second passage elements PT2 contain.

[0092] At least one section of the second passage elements PT2 can at least a section of the word lines WL of the first memory area 410 and at least one section of the word lines WL of the third memory area 430 The second passage elements PT2 can be switched between the second connection area CR2 of the first cell range 400A and the second connection area CR2 of the second cell range 400B be appropriate to reduce the complexity of the interconnection lines that connect at least a portion of the word lines WL and the second passage elements PT2 connect with each other, to reduce.

[0093] In the Fig. 13 shown embodiments, the first cell area 400A and the second cell range 400B on various second substrates 401A and 401B Meanwhile, the first cell area 400A and the second cell range 400B in the Fig. 14 embodiments shown on a second substrate 401 Accordingly, the second passage elements PT2 connected vertical contact holes VV in the Fig. 14 embodiments shown, the second substrate 410 In some embodiments, a substrate insulating layer 403 on the second substrate 401 be formed in such a way that the vertical contact holes VV and the second substrate 401A are isolated from each other.

[0094] Fig. 15 can be a cross-sectional view along line II' in Fig. 11. Referring to Fig. 15 and Fig. 16 together with Fig. 11, the storage device 400 a peripheral circuit area P and a cell area C above the peripheral circuit area P included. The peripheral circuit area P can be a first substrate 405 and circuit elements formed on the first substrate 405 For example, the circuit elements contained in a series decoder may contain pass elements 406 be and with word lines WL electrically connected and can be provided with a lower interlayer dielectric 408 be covered.

[0095] The cell region C can be in a second substrate 401on the lower interlayer dielectric 408 be formed. In Fig. 15 the cross section along line II' can be Fig. 11 the second connection area CR2 the storage device 400 correspond. Second cutting lines CL2 may not be educated and victim groups SL may not be removed but remain in the second connection area CR2 . Accordingly, as in Fig. 15, the victim layers SL and the insulating layers IL alternately on the second substrate 401 The sacrificial layers SL and the insulating layers IL may contain insulating materials that differ from one another.

[0096] In the second connection area CR2 the victim groups SL and the insulating layers IL the first pads PAD1 and the second pads PAD2 A length D1 from each of the first pads PAD1 may be less than a length of each of the second pads PAD2 in the first direction (the X-axis direction). Vertical contact holes VV can be found in the second pads PAD2 formed and can become the peripheral circuit area P extend to connect with the passage elements 406 In an area surrounded by the vertical contact holes VV penetrated, the second substrate 401 made of an insulating material.

[0097] Fig. 16 can be a cross-sectional view along line II-II' in Fig. be 11 and Fig. 17 shows a cross-sectional view along line III-III' in Fig. 12. Referring to Fig. 11 and Fig. 12 can Fig. 16 is a cross-sectional view showing a portion of the second connection area CR2 of the first cell contact area CT1, and Fig. 17 may be a cross-sectional view showing a portion of the second connecting region CR2 of the second cell contact area CT2.

[0098] In some embodiments, the second connection region CR2 of the first cell contact area CT1 and the second connection area CR2 of the second cell contact region CT2 have structures that differ from each other. Referring to Fig. 16 and Fig. 17 the second connection area CR2 of the first cell contact area CT1 and the second connection area CR2 of the second cell contact region CT2 have structures which extend at a specific height from an upper surface of the second substrate 401or less, from each other. Such a structural difference can be caused by a difference between the number of the second connection area CR2 of the first cell contact area CT1 contained second pads PAD2 and the number of in the second connection area CR2 of the second cell contact area CT2 contained second pads PAD2 caused.

[0099] In some embodiments, the number of the second connection area CR2 of the first cell contact area CT1 contained second pads PAD2 be greater than the number of in the second connection area CR2 of the second cell contact area CT2 contained second pads PAD2 . Since the second connection area CR2 of the first cell contact area CT1 the larger number of second pads PAD2 as the second connection area CR2 of the second cell contact region CT2, the first cell contact region CT1 may extend such that it is longer than the second cell contact region CT2 in the first direction. Accordingly, a length of at least one of the word lines extending to the first cell contact region CT1, a first side of the cell array region CA, in the first direction may differ from a length of at least one of the word lines WL extending to the second cell contact region CT2, a second side of the cell array region CA, in the first direction. For example, a bottom word line WL extend in the first direction such that it is longer than the second cell contact region CT2 in the first cell contact region CT1.

[0100] As an example, a difference between the number of the second connection area CR2 of the first cell contact area CT1 contained second pads PAD2 and the number of in the second connection area CR2 of the second cell contact area CT2 contained second pads PAD2 two or more. In some embodiments, a length of the second cell contact region CT2 in the first direction may be greater than 0.6 times the length and less than 0.9 times the length of the first cell contact region CT1 in the first direction. In some embodiments, a length of each of the second pads PAD2 in the first direction greater than or equal to 10 times the length of each of the first pads PAD1 in the first direction. Compared with the first cell contact region CT1, the number of second pads included in the second cell contact region CT2 PAD2 be reduced by two or more to obtain the length reduction effect described above.

[0101] Referring to Fig. 17 the passage elements 406 and 407a first passage element 406 and a second passage element 407 The second passage element 407 can be outside the second connection area CR2 of the second cell contact region CT2 in the first direction and can have at least two word lines WL through vertical contact holes VV The second passage element 407 can be used with two or more word lines WL connected and the number of in the second connection area CR2 of the second cell contact area CT2 contained second pads PAD2 can be reduced. Thus, the integration density of the memory device 400 be increased.

[0102] Since the second passage element 407 with two or more word lines WL connected to the two or more word lines WL simultaneously, the second passage element 407 have a shape and / or a size that differs from a shape of the first passage element 406 differentiate. Referring to Fig. 18A and Fig. 18B, both the first passage element 406 as well as the second passage element 407 a gate G and a source area S and a drainage area D on opposite sides adjacent to the gate G As an example, a gate length Lg2 of the second pass element 407 be greater than a gate length LG1 of the first pass element 406 In some embodiments, a length H2 of the source region S and the drain area D of the second passage element 407 in the second direction be greater than a length H1 of the source region S and the drain area Dof the first passage element 406 in the second direction.

[0103] Fig. 19 and Fig. 20 are cross-sectional views illustrating a cell contact area of ​​a memory device according to some embodiments.

[0104] Referring to Fig. 19 may be a storage device 500 a peripheral circuit area P and a cell area C stacked in a third direction (a Z-axis direction). The peripheral circuit area P can be a first substrate 505 , circuit elements 506 and 507 which are on the first substrate 505 formed, a lower interlayer dielectric 508 , which the circuit elements 506 and 507 and the like. As an example, the circuit elements 506 and 507through elements contained in a series decoder.

[0105] A cell range C can contain a first cell range 500A and a second cell range 500B In addition, the cell region C may contain a plurality of second substrates 501A and 501B and a majority of victim groups SL and a plurality of insulating layers IL , which are deposited on the plurality of second substrates 501A and 501B are stacked. The sacrificial layers SL and the insulating layers IL may provide steps in a first direction (an X-axis direction) and a second direction (a Y-axis direction) and the first pads PAD1 and the second pads PAD2 can be formed by the steps. Each of the first pads PAD1 may have a length that is shorter than a length of each of the second pads PAD2 in the first direction.

[0106] In the Fig. In the embodiments shown in Figure 19, the sacrificial layers SL may be layers that remain in a word line formation process and are not removed. The sacrificial layers SL can remain in an area where a plurality of vertical contact holes VV is formed. In an area where the vertical contact holes VV are not formed, the victim layers SL be replaced by word lines. The vertical contact holes VV can be reached by the victim layers SL and the insulating layers IL with the passage elements 506 and 507 be connected.

[0107] As an example, at least one of the vertical contact holes VV through the victim layers SL and the insulating layers IL in the second pads PAD2 with the first passage element 506At least one of the vertical contact holes VV can be connected to the second passage element 507 in a border area BA between the second substrate 501A of the first cell range 500A and the second substrate 501B of the second cell range 500B be connected.

[0108] The second passage element 507 can be through a vertical contact hole VV , an upper connecting line UW and a cell contact CC with a pair in the first cell range 500A and in the second cell area 500B word lines contained in the device. As an example, the pair of word lines may be mounted at the same height in a third direction. In the Fig. 19, the pair of word lines can be arranged backwards to the sacrificial layers SL be mounted in a second direction.

[0109] Referring to Fig. 20 may be a storage device 600 a peripheral circuit area P and a cell area C. Configurations of the peripheral circuit area P and cell range C may be those described above with reference to Fig. 19 described storage device 500 For example, cell range C may contain a first cell range 600A and a second cell range 600B adjacent to each other in a first direction.

[0110] In the Fig. 20 embodiments shown, the first cell area 600A and the second cell range 600B on a second substrate 601 For example, the second substrate can 601 from the first cell area 600A to the second cell area 600B At least one of the vertical contact holes VV a substrate insulating layer 603 , which are in the border area BA between the first cell range 600A and the second cell range 600B is formed, to reach the peripheral circuit area P to extend.

[0111] Each word line in the memory devices 500 and 600 can have essentially the same thickness as any sacrificial layer SL A gate length of each memory cell may be determined by the thickness of each word line, and characteristics of each memory cell may vary depending on the thickness of each word line. In embodiments, the thickness of each word line may vary depending on whether each word line is independently connected to first through elements. 506 and 606 connected or second passage elements 507 and 607with at least one of the other word lines, wherein the word lines in a cell area C are arranged in a third direction or the like.

[0112] Fig. 21 is a cross-sectional view illustrating a cell array region of a memory device according to some embodiments.

[0113] Referring to Fig. 21 may be a storage device 700 a peripheral circuit area P and contain a cell area C and the cell area C can be arranged above the peripheral circuit area P The peripheral circuit area P contains a first substrate 701 , circuit elements 702 which are on the first substrate 701 are formed, lower connecting lines 703 which are connected to the circuit elements 702 connected, a lower interlayer dielectric 704and the like. As an example, the circuit elements 702 provide a page buffer or something similar.

[0114] Cell range C can contain word lines WL , which are on a second substrate 710 are stacked, channel structures CH , which the word lines WL penetrate, and word line cuts WC , which the word lines WL into a number of areas. The word lines WL can be alternated with the insulating layers IL stacked and may extend in a first direction (an X-axis direction) and a second direction (a Y-axis direction) to form pads with steps. As described above in various embodiments, the pads may include first pads and second pads, and each of the first pads may have a length that is shorter than a length of each of the second pads in the first direction. As an example, the Fig. 21 shown storage device 700 the first cell contact area and the second cell contact area described above with reference to Fig. 11 and Fig. 12, and the first cell contact region and the second cell contact region may be disposed on both sides of a cell region C in the first direction.

[0115] The canal structures CH can be connected via a bit line contact BLC with a bit line BL be connected. In Fig. 21 canal structures CH which are mounted at the same position in the first direction as with a bit line BL However, the position of the channel structures CH not limited to this. The bit line contact BLC an upper interlayer dielectric 705 penetrate the canal structures CH and the bit line BL to connect with each other.

[0116] The second substrate 710 can first to third layers 711 until 713 The channel structures CH , which are located between the word line cuts WC can be removed by the first to third layers 711 until 713 connected to each other to be connected to a single common source line. The following is the Fig. 21 shown storage device 700 with reference to Fig. 22 to Fig. 24 described in detail.

[0117] Fig. 22 to Fig. 24 are enlarged views of an area in Fig. 21.

[0118] Fig. 22 shows an enlarged view of area B in Fig. 21. Referring to Fig. 22 can be a second substrate 710 first to third layers 711 until 713 A channel structure CH can be a data storage layer 720 , a channel layer 730 , a hidden insulating layer 740 and similar.

[0119] Each of the first to third layers 711 until 713 of the second substrate 710 may contain polysilicon doped with impurities having a first conductivity type. As an example, the first to third layers 711 until 713 doped with N-type impurities. Referring to Fig. 21 can the first layer 711 and the second layer 712 under the first to third layers 711 until 713 through word line cuts WC be isolated from each other in a second direction. Accordingly, channel structures CH , which is located between a pair of word line cuts WC adjacent to each other in a second direction, through the second substrate 710 be connected to each other.

[0120] The data storage layer 720 can have a plurality of layers 721 until 723 As an example, the data storage layer 720 a barrier layer 721 , a charge storage layer 722 and a tunnel layer 723 The number, the order of attachment, the material of the data storage layer 720 contained layers 721 until 723can be changed in different ways. The channel layer 730 can be formed from a semiconductor material, for example polysilicon or similar, and an interior of the channel layer 730 can be covered with a hidden insulation layer 740 , such as silicon oxide or similar.

[0121] Fig. 23A and Fig. 23B can provide an enlarged view of the areas C1 and C2 in Fig. 21. Referring to Fig. 23A and Fig. 23B can be a channel structure CH Word lines WL and insulating layers IL penetrate and the word lines WL and the insulating layers IL can be cut by a word line WC be divided into a number of areas.

[0122] In the storage device 700 according to the Fig. 21 shown embodiments, the channel structures CH and the word line cuts WC have a shape in which widths thereof in a third direction (a Z-direction) towards the second substrate 710 For example, side surfaces of the channel structures CH and the word line cuts WC in a cross-section may not be completely perpendicular to an upper surface of the second substrate 710 and may have a slightly slanted shape. Referring to Fig. 23A and Fig. 23B, the word line cut WC on: A first width Y1 in an area C1 , which is mounted at a relatively higher position, and a second width Y2, which is smaller than the first width Y1, in a range C2 , which is mounted at a relatively lower position.

[0123] Accordingly, as in Fig. 23A and Fig. 23B, a first width W1the wording WL , which are in the area C1 is attached, be smaller than a second width of the word line WL , which are in the area C2 Due to the difference in width, the resistance of the word line WL in the area C1 be higher than a resistance of the word line WL in the area C2 . In some embodiments, a connection relationship between word lines WL and through elements with regard to a resistance difference between the word lines WL be determined.

[0124] The storage device 700 According to some embodiments, first through elements and second through elements arranged in the peripheral circuit area P are mounted, and each of the second pass elements can be provided with at least two word lines WLAs described above, each of the second pass elements of word lines WL which are mounted at the same height in cell areas that are different from each other. On the other hand, each of the first pass elements can be connected to a single word line WL be connected.

[0125] In some embodiments, the second pass elements may be provided with word lines WL be associated with a relatively lower resistance. For example, word lines WL in the area C1 with a relatively higher resistance in the Fig. 23A and Fig. 23B shown embodiments may be connected to through elements, and word lines WL in the area C2 with a relatively lower resistance may be connected to second pass elements. In a cell region C of the memory device 700the number of word lines WL connected to the first pass elements must be greater than the number of word lines WL which are connected to the second passage elements.

[0126] In some embodiments, at least a portion of the word lines WL formed to have thicknesses different from each other in order to avoid resistance characteristic deviation of the word lines WL to reduce. Referring to Fig. 24A and Fig. 24B can word lines WL in an area C1 formed to have a first thickness T1, and word lines WL in an area C2 may be formed to have a second thickness T2. The first thickness T1 may be higher than the second thickness T2.

[0127] Therefore, in the Fig. 24A and Fig.24B, a difference between a resistance of the word lines WL in the area C1 and a resistance of the word lines WL in the area C2 If necessary, the word lines can be WL in the area C1 also be connected to the second pass elements. As an example, the word lines WL in the area C1 be connected to the second pass elements and the word lines WL in the area C2 can be connected to the first passage elements.

[0128] Alternatively, in contrast to the Fig. 24A and Fig. 24B, each of the word lines WL in the area C2 formed to have a thickness higher than a thickness of each of the word lines WL in the area C1 , and the word lines WLin the area C2 can be connected to the second pass elements. Since the resistance of the word lines WL in the area C2 connected to the second passage members, a load of the second passage members can be reduced, and according to embodiments, the second passage members can be formed to have the same size as the first passage members.

[0129] Fig. 25 is a cross-sectional view illustrating a cell array region of a memory device according to some embodiments.

[0130] Referring to Fig. 25 may be a storage device 800 a peripheral circuit area P and contain a cell area C and the cell area C can be arranged above the peripheral circuit area P be appropriate. A configuration of the peripheral circuit area Pcan configure the peripheral circuit area P in the with reference to Fig. 21 described storage device 700 be similar.

[0131] Cell range C can contain word lines LWL , DWL and UWL , which are on a second substrate 810 are stacked, channel structures CH , which the word lines LWL , DWL and UWL penetrate, and word line cuts WC , which the word lines LWL , DWL and UWL into a plurality of areas. The second substrate 810 can first to third layers 811 until 813 and the configuration of the second substrate 810 may with reference to the with reference to Fig. 22 described contents can be understood.

[0132] The word lines LWL , DWL and UWLlower word lines can LWL , at least one dummy word line DWL and upper word lines UWL contain the lower word lines LWL can be removed from an upper surface of the second substrate 810 be stacked and lower channel structures CH2 extending from an upper surface of the second substrate 810 extend from, the lower word lines can LWL penetrate. The upper word lines UWL can be found on the lower word lines LWL be stacked and upper channel structures CH1 which extend from the lower canal structures CH2 extend from the top, the upper word lines UWL penetrate.

[0133] The dummy word line DWL can be switched between the lower word lines LWL and the upper word lines UWL As an example, a boundary area between the upper channel structures CH1 and the lower canal structures CH2 in the dummy word line DWL According to embodiments, a further dummy word line DWL be added at different positions.

[0134] In the Fig. 25 shown storage device 800 According to embodiments, the channel structures CH by dividing the channel structures CH into upper canal structures CH1 and lower canal structures CH2 On the other hand, the word line cuts WC simultaneously. Thus, each of the upper word lines UWL on a plane parallel to a first direction (an X-axis direction) and a second direction (a Y-axis direction) have an area smaller than an area of ​​each of the lower word lines LWL , and a resistance of the upper word lines UWLcan be increased. This will be explained below with reference to Fig. 26 and Fig. 27 described in detail.

[0135] Fig. 26A, Fig. 26B, Fig. 27A and Fig. 27B are enlarged views of an area in Fig. 25.

[0136] Fig. 26A and Fig. 26B can provide an enlarged view of the areas E1 and E2 in Fig. 21. Referring to Fig. 26A may have an upper channel structure CH1 upper word lines UWL and insulating layers II penetrate and the upper word lines UWL and the insulating layers II can be cut by a word line WC be divided into a number of areas. Similarly, with reference to Fig. 26B, a lower channel structure CH2 lower word lines LWL and insulating layers II penetrate and the lower word lines LWL and the insulating layers II can be cut by a word line WC be divided into a number of areas.

[0137] Each of the upper channel structures CH1 and the lower canal structures CH2 can be a data storage layer 820 , a channel layer 830 , a hidden insulating layer 840 and similar. The data storage layer 820 can be a barrier layer 821 , a charge storage layer 822 , a tunnel layer 823 and similar.

[0138] As an example, a height from a lower floor of the upper channel structure CH1 to an area E1 a height of a lower surface of the lower channel structure CH2 to an area E2 be the same. Thus, the upper channel structure CH1 and the lower channel structure CH2the substantially equal size in each of the areas E1 and E2 However, the word line cut WC are formed in one process in the entire cell area C and a width of the word line cut WC can be directed in one direction to the second substrate 810 be gradually reduced. With reference to Fig. 26A and Fig. 26B, a first width Y1 of the word line cut WC in the area E1 be greater than a second width Y2 of the word line cut WC in the area E2 .

[0139] Accordingly, the first width W1 the upper word lines UWL in the area E1 be smaller than the second width W2 the lower word lines LWL in the area E2 and the upper word lines UWL may have a relatively higher resistance than the lower word lines LWLIn some embodiments, the upper word lines UWL be connected to the first through elements and at least a portion of the lower word lines LWL may be connected to the second pass elements with respect to resistance characteristics. Each of the first pass elements may be an element connected to one of the upper and lower word lines UWL and LWL and each of the second pass elements may be an element connected to two or more lower word lines LWL that are different from each other. Two or more lower word lines LWL connected to each of the second passage elements may be contained in cell ranges C that are different from each other.

[0140] In the Fig. 27A and Fig. 27B, at least a portion of the upper word lines UWL have a thickness that is higher than a thickness of the lower word lines LWL . Referring to Fig. 27A and Fig. 27B, each of the upper word lines UWL have a first thickness T1 and each of the lower word lines LWL may have a second thickness T2 which is smaller than the first thickness T1. Thus, the resistance of the upper word lines UWL be reduced and the upper word lines UWL can be connected to the second through elements if necessary. The thicknesses of the upper word lines UWL and the lower word lines LWL can be changed in different ways. For example, the thickness of the lower word lines LWL connected to the second passage members may be increased to reduce a load on the second passage members and improve drive characteristics.

[0141] Fig.28 is a schematic block diagram of an electrical device including a memory device according to some embodiments.

[0142] An electronic device 1000 according to the Fig. 28 shown embodiments contain a display 1010 , a sensor unit 1020 , a memory 1030 , a communication unit 1040 , a processor 1050 , a port 1060 and the like. The electronic device 1000 may further include a power supply, an input / output device, and the like. Fig. 28 components shown, the port 1060 be provided to the electronic device 1000 to communicate with a video card, a sound card, a memory card, a USB device, and the like. The electronic device 1000can be a comprehensive concept that includes a typical desktop computer or laptop as well as a smartphone, a tablet, a wearable smart device, and the like.

[0143] The processor 1050 can perform specific arithmetic operations, instructions, tasks, and the like. The processor 1050 can be a central processing unit (CPU), a microprocessor unit (MCU) or a system-on-chip (SoC) and can be connected via a bus 1070 with the display 1010 , the sensor unit 1020 , the memory 1030 , the communication unit 1040 and other devices connected to the port 1060 are connected, communicate.

[0144] The memory 1030 may be a storage medium configured to store data necessary for operations of the electronic device 1000 used to store multimedia data or similar. The memory1030 may contain volatile memory, such as random access memory (RAM), or non-volatile memory, such as flash memory or similar. The memory 1030 may include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. In the Fig. 28 shown embodiments, the memory 1030 a storage device according to various above with reference to Fig. 1 to Fig. 27 described embodiments.

[0145] As described above, according to embodiments, a memory device may include a peripheral circuit region and a cell region disposed above the peripheral circuit region. The cell region may include a cell array region in which channel structures are disposed, and contact regions in which cell contacts connected to word lines are disposed. The contact regions may extend from a cell array in directions parallel to a top surface of a substrate in which the cell region is formed and may have lengths that differ from each other in at least one of the directions parallel to the top surface of the substrate. In addition, at least a portion of the cell contacts may share via elements formed in the peripheral circuit region. Thus, an integration density of the memory device can be increased.

[0146] Although embodiments have been shown and described above, it will be apparent to a person skilled in the art that modifications and variations may be made without departing from the scope of the present inventive concept as defined in the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 1020190095526

[0001]

Claims

[1] Storage device comprising: a peripheral circuit portion including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array area containing: Word lines stacked on a second substrate on the peripheral circuit area, and Channel structures extending in a direction perpendicular to a top surface of the second substrate and penetrating the word lines; and a cell contact region including cell contacts connected to the word lines and located on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths from each other in the first direction, where both the first and second cell contact regions contain: first pads which have different lengths to each other in the first direction, and second pads that are different from the first pads, the cell contacts are connected to the word lines in the first pads, and the number of second pads contained in the first cell contact region is greater than the number of second pads contained in the second cell contact region. [2] The memory device according to claim 1, wherein a length of the first cell contact region in the first direction is greater than a length of the second cell contact region. [3] The memory device according to claim 1, wherein a sum of areas of the first pads and second pads included in the first cell contact region is larger than a sum of areas of the first pads and second pads included in the second cell contact region. [4] The memory device according to claim 1, wherein a sum of the number of the first pads and the number of the second pads included in the first cell contact region is greater than a sum of the number of the first pads and the number of the second pads included in the second cell contact region. [5] The memory device of claim 1, wherein the row decoder includes first pass elements and second pass elements connected to the word lines, and wherein each of the first pass elements is connected to one of the word lines and each of the second pass elements is connected to two or more word lines among the word lines. [6] The memory device according to claim 5, wherein the two or more word lines connected to one of the second via elements are at the same height in a direction perpendicular to the upper surface of the second substrate. [7] The memory device of claim 5, wherein at least one of the second passage elements has an area greater than or equal to an area of ​​each of the first passage elements. [8] The memory device of claim 5, wherein the number of word lines connected to the first pass elements is greater than the number of word lines connected to the second pass elements. [9] The memory device of claim 5, wherein each of the word lines connected to the first pass elements has a higher resistance than a resistance of each of the word lines connected to the second pass elements. [10] The memory device of claim 5, wherein each of the word lines connected to the first via elements has a thickness different from a thickness of each of the word lines connected to the second via elements. [11] The memory device of claim 5, wherein each of the channel structures includes a lower channel structure extending from the upper surface of the second substrate and an upper channel structure extending from the lower channel structure, and the word lines include lower word lines and upper word lines, the lower channel structure penetrating the lower word lines and the upper channel structure penetrating the upper word lines, and at least one of the lower word lines is connected to at least one of the second via elements. [12] The memory device of claim 11, wherein the upper word lines are connected to the first pass elements. [13] The memory device of claim 11, wherein at least a portion of the upper word lines has a thickness that is greater than a thickness of the lower word lines. [14] The memory device of claim 11, wherein the word lines include at least one dummy word line between the lower word lines and the upper word lines and adjacent to a boundary between the lower channel structure and the upper channel structure. [15] The memory device of claim 11, wherein the upper word lines provide the first pads and the second pads and the lower word lines provide only the first pads. [16] The memory device of claim 1, wherein the cell contact region includes upper interconnection lines connected to the cell contacts and vertical contact holes connected to the upper interconnection lines and extending to the peripheral circuit region in the first direction perpendicular to the upper surface of the second substrate. [17] The memory device of claim 16, wherein the vertical contact holes penetrate at least one of the second pads. [18] The memory device of claim 16, wherein the second substrate includes a plurality of second substrates, and at least one of the vertical contact holes is between the second substrates. [19] The memory device according to claim 18, wherein the cell array region includes a first cell array region and a second cell array region adjacent to the first cell array region in the first direction, and the first cell array region and the second cell array region include the second substrates different from each other. [20] The memory device according to claim 19, wherein at least one through element among the through elements included in the row decoder and connected to the word lines does not overlap the second substrates in the first direction. [21] Storage device comprising: a peripheral circuit region including through elements on a first substrate; and a plurality of cell regions on a second substrate above the peripheral circuit region, each of the plurality of cell regions containing at least one memory block, wherein each of the plurality of cell ranges contains: a cell array region in which a plurality of word lines are connected to the through elements and a plurality of channel structures penetrate the word lines, and a cell connection region in which the word lines extending from the cell array region are connected to a plurality of cell contacts, and at least one of the through elements is commonly connected to a pair of word lines included in a pair of cell regions adjacent to each other among the cell regions, and the pair of word lines are on the same plane from an upper surface of the second substrate. [22] The memory device of claim 21, wherein each of the cell regions includes a first cell contact region on a first side of the cell array region and a second cell contact region on a second side of the cell array region opposite to the first side, and an area of ​​the first cell contact region covering the upper surface of the second substrate is larger than an area of ​​the second cell contact region covering the upper surface of the second substrate. [23] The memory device of claim 22, wherein in the pair of cell regions, the number of via elements under the first cell contact region is greater than the number of via elements under the second cell contact region. [24] The memory device of claim 22, wherein at least one of the word lines extends a first length in the first side of the cell array region and extends a second length shorter than the first length in the second side of the cell array region. [25] Storage device, comprising: a peripheral circuit area containing through elements; and a plurality of cell ranges, each of the plurality of cell ranges including a cell array range including: Word lines stacked on a substrate above the peripheral circuit area, and Channel structures that penetrate the word lines; wherein each of the plurality of cell regions includes a first cell region and a second cell region adjacent to each other in a first direction parallel to a top surface of the substrate and a third cell region and a fourth cell region adjacent to each other in the first direction, and a distance between the cell array area of ​​the first cell area and the cell array area of ​​the second cell area is different from a distance between the cell array area of ​​the third cell area and the cell array area of ​​the fourth cell area.

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