Smooth Transition Techniques for an H-Bridge Converter

The control circuit for H-bridge converters addresses voltage and current spikes by alternating control modes and using a soft start/stop sequence, ensuring stable energy management during power transitions.

DE102020110676B4Active Publication Date: 2025-06-26ANALOG DEVICES INT UNLTD CO
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
DE102020110676
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2019-05-02
Filing Date
2020-04-20
Publication Date
2025-06-26
Estimated Expiration
2040-04-20

AI Technical Summary

Technical Problem

H-bridge converters experience uncontrollable voltage or current spikes during startup and shutdown, leading to dissipation of residual system energy.

Method used

Implementing a control circuit that alternates between dual half-bridge and full-bridge control modes during startup and shutdown, using a ramp signal to manage voltage and current transitions, ensuring a predetermined differential voltage and current are applied to the load, and employing a soft start/stop sequence to minimize energy dumping.

Benefits of technology

Reduces chaotic voltage and current transients, effectively managing energy dissipation and preventing voltage spikes, thereby stabilizing the system during power-up and power-down processes.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 00000000_0000_ABST
    Figure 00000000_0000_ABST
Patent Text Reader

Abstract

Method (600) for connection control and handoff of an H-bridge converter (101) coupled to a load (102), wherein the H-bridge converter comprises a first half-bridge (104) coupled to the load at a first node and a second half-bridge (105) coupled to the load at a second node, wherein each half-bridge comprises a first switch (M1, M3) coupled in series at a first bridge node to a second switch (M2, M4), and wherein each half-bridge is connected between a first power rail (V IN1 ) and a second busbar (V IN2 ), the method comprising: Varying a reference voltage between a first level and a second level during a first interval; controlling an output voltage of each of the first half-bridge (104) and the second half-bridge (105) independently during the first interval based on the reference voltage; and Controlling the first half-bridge (104) and the second half-bridge (105) as a full H-bridge during a second timed interval.
Need to check novelty before this filing date? Find Prior Art

Description

TECHNICAL FIELD OF REVELATION

[0001] The present disclosure relates to circuits and, more particularly, to the startup and shutdown of H-bridge circuits. TECHNICAL BACKGROUND

[0002] H-bridge converters can be used for a wide range of applications, including, but not limited to, a driver circuit for a low-dropout switching power supply, a driver for a load such as a motor load, other inductive loads, a resistive load, a capacitive load, or a combination thereof. During H-bridge startup and shutdown, a system may experience voltage or current spikes. During shutdown, residual system energy may dissipate uncontrollably.

[0003] US 2005 / 0 128 775 A1 describes a DC-AC converter parallel operation system and a control IC therefor.

[0004] US 7 023 187 B2 describes an integrated circuit for generating multiple DC output voltages. SUMMARY OF REVELATION

[0005] The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings, which are not necessarily drawn to scale, like numerals in different views may describe similar components. Like numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in this document. Fig. 1 generally illustrates a system having example control circuitry in accordance with the present subject matter. Fig. 2A generally illustrates an example control circuitry or controller for providing a soft start or soft stop of an H-bridge. Fig. Figure 2B illustrates an example of a ramp signal generator. Fig. Figure 3 graphically illustrates a plot of the ramp signal over a working interval of an example H-bridge converter. Fig. Figure 4 generally illustrates an example PWM controller. Fig. 5A and Fig. 5B illustrate example inductor waveforms of the H-bridge over intervals having transitions between a full H-bridge control and dual half-bridge control mode. Fig. 6 generally illustrates a flowchart of an example method for operating an H-bridge converter. DETAILED DESCRIPTION

[0007] The inventors of the present invention have identified improved techniques for operating an H-bridge converter. In certain examples, the techniques may reduce or eliminate chaotic voltage and current transients associated with conventional methods of starting up and shutting down a half-bridge converter. In certain examples, control of the bridge of the H-bridge converter may alternate between dual half-bridge control and full-bridge control during start-up, during shutdown, or during both start-up and shutdown. In certain examples, the H-bridge may apply and maintain a predetermined differential voltage and current to a load during start-up and shutdown while ramping up each supply rail of the load to a predetermined voltage.In certain examples, the predetermined voltage at the end of a power-up may be half the supply voltage of the H-bridge converter. In certain examples, the predetermined voltage at the end of a power-down may be zero volts or system ground.

[0008] Fig. 1 generally illustrates a system 100 including example control circuitry in accordance with the present subject matter. The system may include an H-bridge converter 101 and a load 102 connected to load supply rails or output voltage nodes (V OUT1 , V OUT2) of the H-bridge converter 101. The H-bridge converter 101 may comprise an H-bridge 103 with a first half-bridge 104 and a second half-bridge 105 and control circuitry 106. Each half-bridge 104, 105 may comprise a first or upper power transistor (M1, M3), a second or lower power transistor (M2, M4), and optionally an inductor-capacitor (LC) filter 107, 108. Each upper power transistor (M1, M3) may be connected in series with a corresponding lower power transistor (M2, M4) between the supply rails (V IN1 , V IN2 ) of the H-bridge converter 101. A node (A, B) common to each coupled pair of upper and lower transistors (M1 and M2, M3 and M4) may be coupled to the load 102. In certain examples, the common node (A, B) may be coupled to the load via the inductor (L1, L2) of the respective LC filter 107, 108.

[0009] The control circuitry 106 may include drivers 110, 111, 112, 113 for power transistors, a controller 114, and sensing circuitry for providing feedback information to the controller 114. In certain examples, the sensing circuitry may include, for example, voltage dividers 115, 116 to generate a representation (V FB1 , V FB2 ) of the output voltage (V OUT1 , V OUT2 ) at each output voltage node of the H-bridge 103. In some examples, the sensing circuitry may include an amplifier 117 to provide a representation (V FB ) of the differential voltage between the output voltage nodes of the H-bridge 103. In certain examples, the inputs of the amplifier 117 may be coupled to the voltage dividers 115, 116. In certain examples, the sensing circuitry may include a current sensor 118 for providing a representation (I FB) of the current level at the load 102, a direction of the current at the load 102, or a level of the current at the load 102 and a direction of the current at the load 102.

[0010] Controller 114 may receive information from the sensing circuitry and provide control signals to the power switches (M1, M2, M3, M4) via drivers 110, 111, 112, 113. In certain examples, controller 114 may receive command information from a host (not shown) for application to load 102. In certain examples, the command information may take the form of a command voltage to apply to load 102 or a command current to apply to load 102. Controller 114 may control drivers 110, 111, 112, 113 in response to the command information, in response to a feedback error derived from the command information, or a combination thereof.In certain examples, such as when powering up or powering down the H-bridge 103, the controller 114 may disconnect control from the host to provide a proper power-up or power-down sequence or to avoid or reduce the need to dump power on the load 102 and deal with the resulting voltage spikes, current spikes, and ringing that may be common.

[0011] In certain examples, an example controller 114 may control the H-bridge by varying the voltage (V OUT1 , V OUT2 ) at the output node together to a predetermined voltage level between the voltage level of the first supply rail (V IN1 ) and the voltage level of the second supply rail (V IN2). The change may be accomplished by applying no voltage or current to the load 102. After the output nodes settle at the predetermined voltage level, the controller 114 may couple to and respond to the command information from the host.

[0012] In certain examples, an example controller 114 may control the H-bridge 103 by disconnecting a control setpoint from the host, controlling the output nodes to a predetermined voltage that applies no voltage or current to the load 102, allowing the system to settle at the predetermined voltage, and then changing the voltage at the output nodes together to ground, the voltage level of one of the supply rails (V IN1 , V IN2) or a voltage level that reduces stored electrical energy in the system. In certain examples, the shutdown sequence may be triggered by a command or signal from the host or a system condition such as an undervoltage condition of the supply rails (V IN1 , V IN2 ) can be initiated.

[0013] In certain examples, a portion of each startup and shutdown sequence may be performed using independent half-bridge control of the first half-bridge 104 and the second half-bridge 105. A second portion of each startup and shutdown sequence may be performed using full-bridge control of the H-bridge 103. In half-bridge control, the voltage or current at the output node (e.g., V OUT1) in the first half-bridge 104 can be controlled only using the power switches (M1, M2) of the first half-bridge 104. In certain examples, the output voltage or output current of the output node (e.g., V OUT1 ) of the first half-bridge 104 using feedback information such as the feedback information (V FB1 ), derived from the first voltage divider 115, to a reference signal, such as a reference signal generated by the H-bridge converter. Furthermore, in half-bridge control, the voltage or current at the output node (e.g., V OUT2 ) of the second half-bridge 105 using only the power switches (M3, M4) of the second half-bridge 105. In certain examples, the output voltage or output current of the output node (e.g., V OUT2) of the second half-bridge 105 using feedback information such as the feedback information (V FB2 ), derived from the second voltage divider 116, to a reference signal, such as a reference signal generated by the H-bridge converter. In certain examples, when the independent control of the half-bridges 104, 105 shares a common clock signal, the voltages (V OUT1 , V OUT2 ) at the output node by interconnecting the first and fourth power switches (M1, M4), for example based on a first state of a PWM signal, and interconnecting the second and third power switches (M2, M3), for example, based on a second state of a PWM signal.

[0014] During full-bridge control, the differential voltage (V OUT1 - V OUT2) or the differential current of the output nodes of the H-bridge 103 can be controlled using the power transistors (M1, M2, M3, M4) of both half-bridges 104, 105. In certain examples, in the full-bridge control or the full-H-bridge control, the first and third power switches (M1, M3) can be interconnected based on a first state of a PWM signal, and the second and fourth power switches (M2, M4) can be interconnected based on a second state of the PWM signal.

[0015] Fig. 2A generally illustrates an example control circuitry or controller 114 for providing a soft start or soft stop of an H-bridge. The controller 114 may include a switch controller 220, a pulse width modulation (PWM) controller, one or more amplifiers 221, 222, 223, one or more comparators 224, 225, and an oscillator circuit 226. A first amplifier 221 may provide a first command error signal derived from command information (V REF ) of a host and feedback information (V FB or I FB ) from the H-bridge. The switch controller 220 can respond to the first command error signal (E F) when the switch controller 220 controls the H-bridge as a full H-bridge and outside of the example startup and shutdown sequences discussed above. The second and third amplifiers 222, 223 and first and second comparators 224, 225 can provide status signals to the switch controller 220 for sequencing control of the H-bridge during the startup and shutdown sequence.

[0016] One portion of each of the startup and shutdown sequences comprises controlling each half of the H-bridge, sometimes referred to as dual half-bridge control. A second portion of each of the startup and shutdown sequences comprises controlling the H-bridge as a full H-bridge with a predetermined differential output voltage. In certain examples, a ramp signal (SS) received by the first and second comparators 224, 225 may provide sequencing signals for changing control of the H-bridge between dual half-bridge control, full H-bridge control with a predefined command signal (0 V), and full H-bridge control responsive to host command information (V REF ) answers, deliver.

[0017] Fig. 2B illustrates an example of a ramp signal generator 230. The ramp signal generator 230 may be part of the controller 114 or the control circuitry. In certain examples, the ramp signal generator 230 may include a first current source 231, a second current source 232, a first switch 233, a second switch 234, and a capacitor 235. During a startup sequence, the first switch 233 may couple the first current source 231 to a first node of the capacitor 235 to begin charging the capacitor 235. While the capacitor 235 is charging, a voltage across the capacitor, the ramp signal (SS), may boost the input voltage.After the boot sequence, but before a shutdown sequence, the first node of capacitor 235 may be disconnected from both the first power source 231 and the second power source 232, and the voltage across capacitor 235 may remain at a charged voltage level, or the voltage level to which capacitor 235 was charged at the end of the boot sequence. In some examples, capacitor 235 may remain connected to first power source 231 at the end of the boot sequence to maintain a certain charge voltage on capacitor 235.

[0018] During a shutdown sequence, the first switch 233 may disconnect the capacitor 235 from the first power source 231, if not already disconnected, and the second switch 234 may couple the second power source 232 to the first node of the capacitor 235 to begin discharging the capacitor 235, resulting in a voltage across the capacitor, the ramp signal (SS), stepping down the input voltage. After the shutdown sequence, the first node of the capacitor 235 may be disconnected from both the first power source 231 and the second power source 232, and the voltage across the capacitor 235 may remain at a discharged voltage level or the voltage level to which the capacitor 235 was discharged at the end of the shutdown sequence. In some examples, the capacitor 235 may remain connected to the second power source 232 at the end of the shutdown sequence to maintain some discharge voltage on the capacitor 235.

[0019] Fig. Figure 3 graphically illustrates a plot of the ramp signal (SS) over an operating interval of an example H-bridge converter. At t0, the controller may have supplied power or may receive an enable signal indicating, for example, that a host is attempting to control a load to initiate the startup sequence. At t0, the first switch of the ramp signal generator may close, and the first current source may begin charging the capacitor. Referring to Fig. 2A, the ramp signal (SS) may be received by the second and third error amplifiers 222, 223 and compared with a representation of an output node voltage (V OUT1 , V OUT2 ) of each of the half-bridges are summed. The resulting error signals (E1, E2) of the amplifiers 222, 223 can be used by the switching controller 220 to control each half-bridge individually such that the output voltages (V OUT1 , V OUT2) of each of the half-bridges with the ramp signal (SS). In certain examples, the feedback control of the half-bridges ensures that the load receives very little voltage or very little current, since the output nodes of each half-bridge are regulated with the ramp signal (SS). At t1, the first comparator of the control circuitry can provide an indication of when the level of the ramp signal (SS) exceeds a first threshold (V th1 ). In certain examples, the first threshold (V th1 ) correspond to an end of the first portion of the startup sequence and the beginning of the second portion. In certain examples, although not limited as such, the first threshold (V th1 ) a voltage (V OUT1 , V OUT2 ) of each output node of the half-bridges when applied to a supply rail at approximately one half of the differential supply voltage (V in1 - V in2 ) of the H-bridge converter.

[0020] At t1, the controller can ramp to or above the first threshold (V th1) may switch control to full H-bridge control and may regulate to provide zero volts to the load. A zero-volt reference (0 V), via a switch 227 controlled by the output of the second comparator 225, may be coupled to an input of the first error amplifier 221 to provide a command setpoint for the switching controller during full H-bridge control. In certain examples, the oscillator circuit 226 may include a first clock signal (CLK) and a second clock signal (CLK25). The second clock signal (CLK25) may be offset from the first clock signal (CLK) by one-quarter the period of the H-bridge switching frequency. The first clock signal (CLK) may be used to synchronize and step through switching logic for each half-bridge when the H-bridge is in a dual half-bridge control mode. When the controller responds to the ramp signal (SS) at or above the first threshold (V th1) to full H-bridge control, the controller 114 may use both the first clock signal (CLK) and the second clock signal (CLK25) to transition and step through the switching logic into and out of full-bridge control.

[0021] In some examples, the ramp signal (SS) may continue to increase at the end of the first portion of the startup sequence and may be used to time the second portion of the startup sequence. When referring to Fig. 2 and Fig. 3 at t2 the ramp signal (SS) reaches the second threshold value (V th2 ), the output of the second comparator 225 can disconnect the zero-volt reference from an input of the first error amplifier 221 via the switch 227 and can provide host command information (V REF ) to the input of the first error amplifier 221 to complete the startup sequence. The host can use the host command information (V REF) use the H-bridge under full H-bridge control to control the load via output voltage control or output current control.

[0022] At t3, the shutdown sequence may be initiated. The shutdown sequence may be initiated by a number of events, including, but not limited to, a host command such as a disable command or a disable signal, a loss of supply voltage, as indicated by an undervoltage signal, or a combination thereof. Upon initiation of the shutdown sequence, the ramp signal generator may begin discharging the capacitor. At t4, if the voltage level of the ramp signal falls below the second threshold (V th2 ), the host command information (V REF) from the first error amplifier 221 and replaced by the zero voltage reference (0 V) via the switch 227 controlled by the output of the second comparator 225. Between t4 and t5, the ramp signal (SS) can be used to provide a settling interval for the system. At t5, if the voltage of the ramp signal (SS) falls below the first threshold (V th1), an output of the first comparator 224 may initiate a transition of the switching controller 220 from the full H-bridge control mode to the dual half-bridge control. In certain examples, the transition between full-bridge and half-bridge control may occur upon a transition of the second clock signal (CLK25) to assist in synchronizing the switching of each half-bridge. Additionally, at t5, a feedback control response may be sent from the first amplifier 221 to the error signals (E1, E2) generated by the second and third amplifiers 222, 223. Between t5 and t6, each half-bridge may be individually controlled, synchronized via the first clock (CLK), such that the voltage (V OUT1 , V OUT2) of each output node follows the ramp signal (SS) to a value that discharges electrical energy from the converter. In certain examples, after the ramp signal (SS) has been fully discharged, the controller 114 may electrically couple the output nodes and the corresponding supply lines of the load together. For an inductive load, such as, for example, a motor load, coupling or shorting the supply lines of the load together may provide an electronic brake and may prevent the load from developing or storing electrical energy after shutdown.

[0023] Fig. 4 generally illustrates an example PWM controller 420. The PWM controller 420 is an example of a switching controller and may include first switching logic 431 for individually controlling at least two half-bridges, second switching logic 432 for full H-bridge control, a multiplexer 433 for coupling the outputs of the switching logic 431, 432 to the control nodes or drivers of the power transistors of the bridge, and control logic 434 for controlling the multiplexer 433. In certain examples, the first switching logic 431 may receive the first clock signal (CLK) and the error information (E1, E2) from the second and third amplifiers ( Fig. 2; Fig. 222, Fig. 223). The first switching logic 431 may include switching logic for servo-controlling a voltage of an output node of a half-bridge to a reference signal via an error amplifier. In some examples, the first switching logic 431 may include switching logic for individually controlling each half-bridge of the H-bridge. In certain examples, the switching logic for each half-bridge is synchronized using the first clock signal (CLK). The second switching logic 423 may receive the first clock signal (CLK) and the error information (E F ) from the first amplifier ( Fig. 2; Fig. 221). The second switching logic 432 may control the H-bridge in a full-bridge control mode. The multiplexer 433 may receive the outputs from the switching logic 431, 432 and a control input from the control logic 434 to couple the corresponding set of inputs to the output of the multiplexer 433. The output of the multiplexer 433 may provide control signals (TG1, BG1, TG2, BG2) for the power transistors (M1, M2, M3, M4). In certain examples, the control logic 434 may include a flip-flop or a latch that is responsive to an output of the first comparator ( Fig. 2, Fig. 224) and the second clock signal (CLK25) responds.

[0024] Fig. 5A and Fig. 5B illustrate example inductor waveforms (I L1 , I L2 ) of the H-bridge over intervals exhibiting transitions between full-H-bridge control and half-bridge control modes. Fig. Figure 5A generally illustrates the inductor waveforms (I L1 , I L2 ) during a soft start-up of an H-bridge converter according to the example of Fig. 1. Soft start-up involves using a dual half-bridge controller until the output voltage of each half-bridge reaches a value defined by a first threshold (V th1 ) is reached compared to the ramp signal (SS). At t1, when the output voltage of each half-bridge reaches the predetermined level and at a desired transition of the second clock signal (CLK25), the control of the H-bridge can switch to a full H-bridge control mode and the current (I L1 , I L2 ) of each inductor can be calculated in terms of phase compared to the current (I L1 , I L2 ) of each inductor during the dual half-bridge control interval. In the example shown by Fig. 5A the offset can be about 25% of the switching period.

[0025] Fig. Figure 5B generally illustrates a soft turn-off of an H-bridge converter according to the example of Fig. 1. A soft shutdown can continue full H-bridge control for a settling interval because the differential output voltage setpoint for the H-bridge is set to a zero voltage reference. The timing of the settling interval can be provided by the ramp signal (SS) when the ramp signal (SS) is ramped to the first threshold (V th1 ) drops. At t5, when the voltage of the ramp signal (SS) exceeds the first threshold (V th1) is reached and upon a desired transition of the second clock signal (CLK25), the control of the H-bridge can change from a full-bridge control mode to a dual half-bridge control mode, where each half-bridge can be controlled independently using the first clock signal (CLK). During half-bridge control, the ramp signal (SS) can be used as a representative setpoint for the output voltage of each half-bridge. When the ramp signal (SS) goes to zero, the voltage of each half-bridge output can be changed to zero volts or any other disabled voltage.

[0026] Fig. 6 generally illustrates a flowchart of an example method 600 for operating an H-bridge converter. In particular, the flowchart illustrates example techniques for soft transitions of an H-bridge converter. At 601, a reference voltage of the H-bridge converter may be varied to support a soft transition of the converter. The soft transition may be a soft start-up transition when the converter is powered up and control is passed to a host at the end of the transition. The soft transition may be a soft shutdown when power is removed from the converter or when the host is disabled, such as by a power loss. At 603, each half-bridge of the H-bridge controller may be individually controlled, and the voltage at the output of each half-bridge may be servo-switched or gated to the varied reference voltage during the first interval.At 605, the controller can alternate between dual half-bridge control of the first interval and full-bridge control of a second interval. At the beginning or end of the second interval, a setpoint reference for the full-bridge differential voltage or current can be exchanged between a zero reference of the converter and a command message from a host.

[0027] During a soft-start sequence, the reference voltage may be increased from a shutdown value; the first interval may precede the second interval; and the exchange of the setpoint reference from the converter's zero reference to the host's command information may occur at the end of the second interval. During a soft shutdown, the exchange of the setpoint reference from the host's command information to the converter's zero reference may occur at the beginning of the second interval; the second interval may precede the first interval; and the reference voltage may be decreased to the shutdown value. In certain examples, during shutdown, the load's supply lines may be shorted together to provide an electronic brake and may prevent the load from developing or storing electrical energy after shutdown.In certain examples, the load supply lines can be isolated using the lower switches (. Fig. 1; M2, M4) are short-circuited together or to ground. Various notes & examples

[0028] Within the present disclosure, techniques for powering up and powering down an H-bridge are provided. In one example, a method may include varying an internal reference voltage of the H-bridge between a first level and a second level during a first interval; controlling an output voltage of each of a first half-bridge and the H-bridge and a second half-bridge of the H-bridge independently during the first interval based on the reference voltage; and controlling the first half-bridge and the second half-bridge as a full H-bridge during a second timed interval.

[0029] The above detailed description incorporates references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples."

[0030] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with executable instructions to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code such as microcode, assembly language code, higher-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be tangibly stored on one or more transient, non-transitory, or non-transitory tangible computer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or memory sticks, random access memories (RAMs), read-only memories (ROMs), and the like.

Claims

[1] Method (600) for connection control and handoff of an H-bridge converter (101) coupled to a load (102), wherein the H-bridge converter comprises a first half-bridge (104) coupled to the load at a first node and a second half-bridge (105) coupled to the load at a second node, wherein each half-bridge comprises a first switch (M1, M3) coupled in series at a first bridge node to a second switch (M2, M4), and wherein each half-bridge is connected between a first power rail (V IN1 ) and a second busbar (V IN2 ), the method comprising: Varying a reference voltage between a first level and a second level during a first interval; controlling an output voltage of each of the first half-bridge (104) and the second half-bridge (105) independently during the first interval based on the reference voltage; and Controlling the first half-bridge (104) and the second half-bridge (105) as a full H-bridge during a second timed interval. [2] The method of claim 1, wherein controlling an output voltage of each of the first half-bridge (104) and the second half-bridge (105) independently during the first interval comprises: Servo-controlling a voltage level of the first node to the reference voltage during the first interval; and Servo controlling a voltage level of the second node to the reference voltage during the first interval. [3] The method of claim 2, wherein controlling the first half-bridge (104) and the second half-bridge (105) as a full H-bridge during a second timed interval comprises servo-controlling a differential voltage between the first node and the second node to zero volts during the second timed interval. [4] A method according to claim 2 or 3, wherein the first interval occurs when the reference voltage is below a first threshold. [5] The method of claim 4, wherein the second interval occurs when the reference voltage is above the first threshold. [6] A method according to any one of the preceding claims, wherein the first interval precedes the second interval to provide a soft start of the H-bridge converter (101). [7] The method of any one of claims 1 to 6, wherein the second interval precedes the first interval to provide a soft stop of the H-bridge converter (101). [8] Method according to one of the preceding claims, wherein a voltage difference between the first busbar (V IN1 ) and the second busbar (V IN2 ) provides a supply voltage for the H-bridge converter (101); wherein the first level of the reference voltage indicates a voltage level of the second power rail; and where the second level of the reference voltage indicates half of the supply voltage. [9] A method according to any one of the preceding claims, comprising, at a transition of independently controlling each of the first half-bridge (104) and the second half-bridge (105) during the first interval to controlling the first half-bridge and the second half-bridge as a full H-bridge during a second timed interval, adjusting a switching sequence of one of the first half-bridge or the second half-bridge with an offset of a switching cycle of the first interval. [10] A method according to any one of the preceding claims, wherein servo-controlling the voltage level of the first node comprises energizing a first LC circuit (107) coupled between the bridge node (A) of the first half-bridge (104) and the load (102). [11] A method according to any one of the preceding claims, wherein servo-controlling the voltage level of the first node comprises energizing a second LC circuit (108) coupled between the bridge node (B) of the second half-bridge (105) and the load (102). [12] H-bridge converter (101) comprising a first half-bridge (104) configured to couple to a load (102) and a second half-bridge (105) configured to couple to the load, each half-bridge comprising a first switch (M1, M3) coupled in series to a bridge node with a second switch (M2, M4) between a first power rail (V IN1 ) and a second busbar (V IN2 ), wherein the H-bridge converter further comprises: a first error amplifier (223) configured to receive a representation of a first output voltage of the first half-bridge (104) and a first reference; a second error amplifier (222) configured to receive a representation of a second output voltage of the second half-bridge (105) and the first reference; and a controller (220) configured to control the first and second switches (M1, M2, M3, M4) of the first half-bridge (104) and the second half-bridge (105) of the H-bridge converter based on an output of the first error amplifier (223) and an output of the second error amplifier (222); wherein the H-bridge converter is further configured to: Varying a reference voltage between a first level and a second level during a first interval; controlling an output voltage of each of the first half-bridge (104) and the second half-bridge (105) independently during the first interval based on the reference voltage; and Controlling the first half-bridge (104) and the second half-bridge (105) as a full H-bridge during a second timed interval. [13] The H-bridge converter (101) of claim 12, wherein the controller (114, 220) comprises a ramp circuit configured to adjust a level of the first reference when the H-bridge converter powers up and when the H-bridge converter powers down, the ramp circuit configured to charge a ramp capacitor during a power-up interval and discharge the ramp capacitor during a power-down interval; and wherein a voltage across the ramp capacitor is the first reference (SS). [14] The H-bridge converter (101) of claim 13, comprising a controller (114, 220) configured to control each half-bridge (104, 105) independently during the startup interval and during the shutdown interval. [15] H-bridge converter (101) according to claim 14, comprising a first mode change comparator (224) configured to compare the first reference (SS) and a first ramp threshold (V TH1 ); and wherein the controller (220) is further configured to switch between independent half-bridge control of the first half-bridge (104) and the second half-bridge (105) and full H-bridge control of the first half-bridge and the second half-bridge in response to an output of the first mode change comparator (224). [16] H-bridge converter (101) according to claim 15, comprising a second mode change comparator (225) configured to compare the first reference (SS) and a second ramp threshold (V TH2 ) to receive; and wherein the controller (220) is further configured to switch between a first H-bridge reference and a second H-bridge reference in response to an output of the second mode change comparator (225); and wherein the first H-bridge reference and the second H-bridge reference define a desired current or voltage to be applied by the H-bridge converter to the load (102). [17] The H-bridge converter (101) of claim 16, wherein the first H-bridge reference is a zero current or zero voltage reference. [18] H-bridge converter (101) according to one of claims 12 to 17, comprising: a first inductor-capacitor circuit (107) coupled between the bridge node (A) of the first half-bridge (104) and the load (102); and a second inductor-capacitor circuit (108) coupled between the bridge node (B) of the second half-bridge (105) and the load (102). [19] H-bridge converter system (100), comprising: a first half-bridge (104) comprising a first switch (M1) coupled in series to a first bridge node with a second switch (M2), wherein the first half-bridge is designed to be connected between a first busbar (V IN1 ) and a second busbar (V IN2 ), wherein the first bridge node is configured to supply power to a load (102); a second half-bridge (105) comprising a third switch (M3) coupled in series to a second bridge node with a fourth switch (M4), wherein the second half-bridge is designed to be connected between the first busbar (V IN1 ) and the second busbar (V IN2 ), wherein the second bridge node is configured to supply power to the load (102); means for alternating a reference voltage between a first level and a second level during a first interval; first means (431) for controlling each of the first half-bridge (104) and the second half-bridge (105) independently during the first interval, the first means for controlling comprising: means for servo-controlling a voltage level of a first output node of the first half-bridge (104) to a reference voltage during the first interval; means for servo-controlling a voltage level of a second output node of the second half-bridge (105) to the reference voltage during the first interval; second means (432) for controlling the first half-bridge (104) and the second half-bridge (105) as a full H-bridge during a second timed interval; and Means for servo-controlling a differential voltage between the first output node and the second output node to zero volts during the second interval. [20] The H-bridge converter system of claim 19, comprising means for servo-controlling a voltage differential of the first output node and the second output node in response to a command input during a third interval. [21] The H-bridge converter system of claim 20, comprising, at a transition of controlling each of the first half-bridge (104) and the second half-bridge (105) independently during the second interval to control the first half-bridge and the second half-bridge as a full H-bridge during the second timed interval, means for adjusting a switching sequence of one of the first half-bridge or the second half-bridge with an offset of a switching cycle of the first interval.

Citation Information

Patent Citations

  • Dc-ac converter parallel operation system and controller ic therefor

    US20050128775A1

  • Integrated circuit for generating a plurality of direct current (DC) output voltages

    US7023187B2