SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A method for manufacturing a semiconductor device comprising a field effect transistor, hereinafter referred to as FET, the method comprising: Forming a sacrificial region (20, 212) in a substrate (10, 200, 210, 310); Forming a fin structure (220, 225, 235, 315) by patterning the substrate (10, 200, 210, 310) and the sacrificial region (20, 212); Forming a space (100) by at least partially etching the sacrificial region (20, 212), wherein an impurity-containing region comprising an impurity in an amount higher than the substrate (10, 200, 210, 310) is arranged between the space (100) and the substrate (10, 200, 210, 310); Forming an insulating layer (30, 230, 330) over the substrate (10, 200, 210, 310) and an embedded insulating layer (270, 300) by filling the space (100) with an insulating material; and Forming a gate structure (44) and a source / drain region.

Description

BACKGROUND

[0001] Reducing parasitic capacitance is one of the key technologies for reducing power consumption in semiconductor devices. Existing complementary metal-oxide-semiconductor field-effect transistors (CMOS FETs) feature diffuse source / drain (S / D) structures that introduce parasitic capacitance between the S / D region and the substrate.

[0002] US 2017 / 0 179 299 A1 discloses a semiconductor device. US 9 984 936 B1 discloses a method for manufacturing a semiconductor device. US 10 164 041 B1 discloses a method for forming a GAA FinFET. US 2016 / 0 315 149 A1 discloses a semiconductor structure comprising a fin structure.

[0003] The invention is defined in the independent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following detailed description is best understood when read in conjunction with the accompanying figures. It should be emphasized that, in accordance with industry standard practice, various features are not drawn to scale and are for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily enlarged or reduced to clarify the explanation. Fig. 1A shows a top view, and Fig. 1B, Fig. 1C, Fig. 1D and Fig. 1E show cross-sectional views of a semiconductor device according to embodiments of this disclosure. Fig. 2A, Fig. 2B and Fig. 2C show cross-sectional views of a semiconductor device according to embodiments of this disclosure. Fig. 3 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 4 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 5 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 6 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 7 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 8 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 9 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 10 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 11 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 12 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 13 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 14 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 15 shows a cross-sectional view of one of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. Fig. 16 shows a cross-sectional view of a semiconductor device according to an embodiment of this disclosure. Fig. 17 shows a plan view of a semiconductor device according to an embodiment of this disclosure. Fig. 18A, Fig. 18B, Fig. 18C and Fig. 18D show various views of semiconductor devices according to another embodiment of this disclosure. Fig. 19A and Fig. 19B show various views of semiconductor devices according to another embodiment of this disclosure. Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24A and Fig. 24B show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. Fig. 25A, Fig. 25B, Fig. 25C, Fig. 25D and Fig. 25E show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. Fig. 26A, Fig. 26B, Fig. 26C, Fig. 26D and Fig. 26E show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. Fig. 27, Fig. 28, Fig. 29 and Fig. 30 show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. Fig. 31A and Fig. 31B show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. Fig. 32A, Fig. 32B, Fig. 32C, Fig. 32D and Fig. 32E show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to another embodiment of this disclosure. DETAILED DESCRIPTION

[0005] It should be understood that the following disclosure provides many different embodiments or examples for implementing various functions of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired device characteristics.Furthermore, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. Various features may be arbitrarily referenced at different scales for simplicity and clarity. In the accompanying drawings, some layers / features may be omitted for simplicity.

[0006] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. Furthermore, the term "made of" can mean either "comprising" or "consisting of."Furthermore, in the following manufacturing process, one or more operations may be present in / between the described operations, and the order of the operations may be changed. In this disclosure, the term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one of A, one of B, and one of C unless otherwise described. Materials, configurations, dimensions, methods, and / or operations that may be the same as or similar to those described with one embodiment may be employed in the other embodiments, and a detailed description thereof may be omitted.

[0007] Disclosed embodiments relate to a semiconductor device and its fabrication method, in particular to source / drain regions of a field-effect transistor (FET). The embodiments disclosed herein generally apply not only to a planar FET, but also to other FETs, such as a fin FET and a gate-all-around FET.

[0008] Fig. 1A shows a top view, Fig. Figure 1B shows a cross-sectional view corresponding to the line X1-X1 (along the X direction, i.e., source-to-drain) of Fig. 1A, and Fig. 1C, Fig. 1D and Fig. 1E show cross-sectional views showing line Y1-Y1 (along the Y direction, i.e. extending the gate) from Fig. 1A, in a semiconductor device according to embodiments of this disclosure.

[0009] As shown, a FET is formed over a substrate 10. The FET includes a gate dielectric layer 42 disposed over a channel region 12 of the substrate 10 and a gate electrode layer 44. Gate sidewall spacers 46 are disposed on opposite side surfaces of the gate electrode layer 44.

[0010] The substrate 10 is, for example, a p-silicon or germanium substrate with an impurity concentration in the range of approximately 1 × 10 15 cm -3 up to approx. 1 × 10 16 cm -3 In some embodiments, a p+ silicon substrate is used. In other embodiments, the substrate is an n-type silicon or germanium substrate with an impurity concentration in the range of approximately 1 × 10 15 cm -3 up to approx. 1 × 10 16 cm -3 .

[0011] Alternatively, substrate 10 may comprise another elemental semiconductor, such as germanium; a compound semiconductor, including Group IV-IV compound semiconductors such as SiC, SiGe, and SiGeSn; or combinations thereof. In one embodiment, substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. Substrate 10 may include various regions appropriately doped with impurities (e.g., p- or n-type conductivity).

[0012] The gate dielectric layer 42 comprises one or more layers of dielectrics, such as silicon oxide, silicon nitride, or a higher-k dielectric, another suitable dielectric, and / or combinations thereof. Examples of high-k dielectrics include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titania, hafnia-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectrics, and / or combinations thereof. The gate dielectric layer is formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or other suitable methods and / or combinations thereof. The thickness of the gate dielectric layer is in the range of about 1 nm to about 20 nm in some embodiments and may be in the range of about 2 nm to about 10 nm in other embodiments.

[0013] The gate electrode layer 44 includes one or more conductive layers. In some embodiments, the gate electrode layer 44 is made of doped polysilicon. In other embodiments, the gate electrode layer 44 includes metallic material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate length (along the X-direction) is in the range of about 20 nm to about 200 nm, and in other embodiments, in the range of about 40 nm to about 100 nm.

[0014] In certain embodiments of this disclosure, one or more work-function matching layers are interposed between the gate dielectric layer 42 and a body metal gate electrode 44. The work-function matching layer is composed of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work-function matching layer, and for a p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work-function matching layer. When metallic materials are used as the gate electrode layer, gate exchange technology is used to fabricate the gate structure.

[0015] The gate sidewall spacers 46 include one or more layers of insulating material, such as SiO2, SiN, SiON, SiOCN, or SiCN, formed by CVD, PVD, ALD, e-beam evaporation, or another suitable process. A low-k dielectric may be used as the sidewall spacers. The sidewall spacers 46 are formed by forming a cap layer of insulating material over the gate electrode layer 44 and performing anisotropic etching. In one embodiment, the sidewall spacer layers are made of silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN.

[0016] The FET from Fig. 1A to 1C also includes source / drain diffusion regions 50 and source / drain extension regions 55. The source / drain diffusion regions 50 are n+ or p+ regions formed, for example, by one or more ion implantation operations or thermal diffusion operations. The source / drain extension regions 55 are n-, n-, p-, or p- regions formed, for example, by one or more pocket conversions. The source / drain extension regions 55 are formed under the gate sidewall spacers 46, as shown in Fig. 1B. In some embodiments, the source / drain diffusion regions 50 include one or more epitaxial semiconductor layers forming a raised source / drain structure.

[0017] The FET from Fig. 1A to 1C further includes isolation isolation regions 30, also referred to as shallow trench isolation (STI) regions, for electrically isolating the FET from other electrical devices formed on the substrate 10. The isolation isolation regions 30, in some embodiments, include one or more silicon-based insulation layers.

[0018] The FET from Fig. 1A to 1C include air spacers (air gaps) 110 in the spaces 100 having a rectangular cross-section beneath the source / drain diffusion regions 50. The air spacers 110 are, in some embodiments, surrounded by the insulating material forming the isolation region 30. The air spacers 110 may eliminate or suppress connection capacitances between the source / drain diffusion regions 50 and the substrate 10. In some embodiments, no air spacer is disposed beneath the channel region.

[0019] In some embodiments, the width W11 in the X-direction of the space 100 is in a range of about 100 nm to about 500 nm, and in other embodiments, in a range of about 200 nm to about 400 nm. A ratio of the width W12 in the X-direction of the air spacer 110 to the width W11 (W12 / W11) is in a range of 0.5 to 0.95 in some embodiments, and in a range of about 0.7 to 0.9 in other embodiments.

[0020] In some embodiments, the depth D11 in the Z-direction of the space 100 is in a range of about 10 nm to about 200 nm, and in other embodiments, in a range of about 30 nm to about 100 nm. A ratio of the depth D12 in the Z-direction of the air spacer 110 to the depth D11 of the space 100 (D12 / D11) is in a range of about 0.5 to about 0.9 in some embodiments, and in a range of about 0.6 to about 0.8 in other embodiments. An aspect ratio of the width W11 of the space 100 to the depth D11 (W11 / D11) of the space 100 is in a range of about 1 to about 10 in some embodiments, and in a range of about 2 to about 5 in other embodiments.

[0021] In some embodiments, an aspect ratio (W11 / D11) of the space 100 is in a range of about 2 to about 10, and in other embodiments, in a range of about 3 to about 8. In some embodiments, an aspect ratio (W12 / D12) of the air spacer 110 is in a range of about 2 to about 10, and in other embodiments, in a range of about 3 to about 8.

[0022] As in Fig. 1C, the space 100 and / or the air spacer 110 are continuously arranged along the Y-direction under the source / drain diffusion region 50 with a substantially constant depth D12. In other embodiments, the space 100 and / or the air spacer 110 are discontinuous along the Y-direction. In some embodiments, the depth D11 of the space 100 and / or the depth D12 of the air spacer 110 decreases as the distance from the isolation region 30 to the central portion increases, as shown in Fig. 1D. In some embodiments, two spaces 100 formed from the left side and from the right side do not meet, and they are formed as in Fig. 1E shown separated by a portion of the substrate 10.

[0023] Fig. Figure 2A shows a cross-sectional view corresponding to the line X1-X1 (along the X direction, i.e., source-to-drain) of Fig. 1A, and Fig. 2B and Fig. 2C show a cross-sectional view showing line Y1-Y1 (along the Y-direction, ie extending the gate) from Fig. 1A, in a semiconductor device according to embodiments of this disclosure. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanation may be omitted.

[0024] In the embodiments from Fig. 2A to 2C, the space 100 and the air spacer 110 have a triangular shape or a trapezoidal shape.

[0025] In some embodiments, the width W21 in the X-direction of the space 100 is in a range of about 100 nm to about 500 nm, and in other embodiments, in a range of about 200 nm to about 400 nm. A ratio of the width W22 in the X-direction of the air spacer 110 to the width W21 (W22 / W21) is in a range of about 0.5 to about 0.95 in some embodiments, and in a range of about 0.7 to about 0.9 in other embodiments.

[0026] In some embodiments, the depth D21 in the Z-direction of the space 100 at the entrance of the space 100 (an edge of the insulation layer 30) is in a range of about 10 nm to about 200 nm, and in other embodiments, in a range of about 30 nm to about 100 nm. A ratio of the greatest depth D22 in the Z-direction of the air spacer 110 to the depth D21 of the space 100 (D22 / D21) is in a range of about 0.5 to about 0.9 in some embodiments, and in a range of about 0.6 to 0.8 in other embodiments. In some embodiments, a ratio of the smallest depth D 23in the Z-direction of the air spacer 110 to the greatest depth D22 (D23 / D22) of the air spacer 110 in some embodiments in a range of about 0.1 to about 0.9, and in other embodiments in a range of about 0.4 to about 0.8. A ratio of the width W21 of the space 100 to the depth D2 of the space 100 (W21 / D21) is in a range of about 1 to about 10 in some embodiments and in a range of about 2 to about 5 in other embodiments. In some embodiments, a ratio of the smallest depth D24 in the Z direction of the space 100 to the largest depth D21 (D24 / D21) of the space 100 is in a range of about 0 to about 0.8 in some embodiments and in a range of about 0.4 to about 0.6 in other embodiments.

[0027] In some embodiments, the angle θ between the bottom surface of the space 100 and the horizontal line (parallel to the top surface of the substrate 10) is greater than 0 degrees to 60 degrees or less. In other embodiments, the angle θ is in a range of approximately 15 degrees to 45 degrees.

[0028] As in Fig. 2B, the space 100 and / or the air spacer 110 are continuous along the Y-direction under the source / drain diffusion region 50. In some embodiments, the depth D11 of the space 100 and / or the depth of the air spacer 110 becomes smaller as the distance from the isolation region 30 to the central portion of the source / drain region 50 increases, as shown in Fig. 2B. In other embodiments, the space 100 and / or the air spacer 110 are interrupted along the Y-direction, as shown in Fig. 2C shown.

[0029] Fig. Figures 3 to 12 show cross-sectional views of the various steps for fabricating a FET device according to an embodiment of this invention. It should be understood that further operations may be performed before, during, and after the methods of Fig. 3 to 12, and that some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanation may be omitted.

[0030] As in Fig. 3, a cap layer 15 is formed over the substrate 10. The cap layer 15 comprises a single silicon oxide layer. In other embodiments, the cap layer 15 comprises a silicon oxide layer and a silicon nitride layer formed over the silicon oxide layer. The silicon oxide layer may be formed using thermal oxidation or a CVD process. The CVD process includes plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), and high-density plasma CVD (HDPCVD). Atomic layer deposition (ALD) may also be used. The thickness of the cap layer 15 is in the range of about 5 nm to about 50 nm in some embodiments and in the range of about 10 nm to about 30 nm in other embodiments.

[0031] In some embodiments, one or more alignment key structures are formed on the substrate 10 before or after forming the cap layer 15.

[0032] By using one or more lithography operations, a photoresist pattern is formed as a first mask pattern 18 over the cover layer 15 as in Fig. 4. The width and location of the first mask pattern 18 are substantially the same as the width and location of the subsequently formed gate electrode. The lithography operation, in some embodiments, is performed using the equipment key patterns formed on the substrate 10. In some embodiments, the thickness of the photoresist pattern 18 is in a range of approximately 100 nm to 1000 nm.

[0033] After forming the first mask structure 18, one or more ion implantation operations 19 are performed to form sacrificial regions 20 containing dopants as shown in Fig. 5. In some embodiments, arsenic ions (As) are implanted (doped) into the substrate 10. Ions of other dopant elements, such as P, As, Sb, Ge, N, and / or C, may also be used. In some embodiments, an acceleration voltage of the ion implantation 19 is in a range of about 0.5 keV to about 10 keV, and in other embodiments, in a range of about 2 keV to about 8 keV. A dose amount of the ions is in some embodiments in a range of about 5 × 10 13 ions / cm 2 up to approx. 5 × 10 15 ions / cm 2 , and in other embodiments in a range of approximately 1 × 10 14 ions / cm 2 up to approx. 1 × 10 15 ions / cm 2. In some embodiments, the sacrificial regions 20 have a depth in a range of about 5 nm to about 80 nm, and in other embodiments, the depth is in a range of about 20 nm to about 50 nm.

[0034] In some embodiments, after the ion implantation operations and the removal of the mask layer 18, a thermal process 21, such as an annealing process, is performed, as shown in Fig. 6. In certain embodiments, the thermal process is performed using rapid thermal annealing (RTA) 21 at a temperature in a range of about 900°C to about 1050°C for about 1 second to about 10 seconds in a protective gas environment, such as an N2, Ar, or He environment.

[0035] In some embodiments, an impurity concentration of the sacrificial layer 20 is in a range of approximately 1 × 10 19 atoms / cm 3 up to approx. 5 × 10 21 atoms / cm 3, and in other embodiments in a range of approximately 1 × 10 20 atoms / cm 3 up to approx. 1 × 10 21 atoms / cm 3 ,

[0036] After the annealing operation 21, the cover layer 15 is removed using wet and / or dry etching operations.

[0037] Then, as in Fig. 7, an epitaxial semiconductor layer 25 is formed over the substrate 10, which includes the sacrificial layer 20. In some embodiments, the epitaxial semiconductor layer 25 comprises one of Si, SiGe, and Ge. In certain embodiments, Si is epitaxially formed as the epitaxial semiconductor layer 25. The epitaxial semiconductor layer 25 may be grown at a temperature of about 600 to 800°C under a pressure of about 666.612 Pascals to 6666.12 Pascals using a Si-containing gas such as SiH4, Si2H6, and / or SiCl2H2. A Ge-containing gas such as GeH4, Ge2H6, and / or GeCl2H2 is used for the cases of SiGe or Ge. In some embodiments, the epitaxial semiconductor layer 25 is doped with n-type or p-type impurities. The thickness of the epitaxial semiconductor layer 25 is in the range of about 5 nm to about 100 nm in some embodiments and is in the range of about 10 nm to about 30 nm in other embodiments.

[0038] A second mask structure 27 is then formed over the epitaxial semiconductor layer 25, as shown in Fig. 8. In some embodiments, the second mask structure 27 is a photoresist structure. In other embodiments, the second mask structure 27 is a hard mask structure composed of one or more layers of silicon oxide, silicon nitride, and SiON. In some embodiments, one or more capping layers are formed between the second mask structure 27 and the epitaxial semiconductor layer 25. The capping layer is composed of silicon oxide, silicon nitride, and / or SiON. In certain embodiments, the capping layer comprises a silicon oxide layer formed on the epitaxial semiconductor layer 25 and a silicon nitride layer formed on the silicon oxide layer.

[0039] Subsequently, trenches 35 are formed by etching the epitaxial semiconductor layer 25, the sacrificial layer 20 and the substrate 10, as shown in Fig. 9. In some embodiments, plasma dry etching is used. In some embodiments, the etching gas comprises a halogen-containing gas such as HBr. In some embodiments, the HBr gas is diluted with a shielding gas such as He and / or Ar. In some embodiments, a ratio of HBr gas to diluent gas is in a range of about 0.3 to about 0.7, and in other embodiments, the ratio is in a range of about 0.4 to about 0.6. Other gases suitable for etching silicon may be used.

[0040] Next, as in Fig. 10, the sacrificial layer 20 is etched laterally to form spaces 100, as in Fig. 10. In some embodiments, plasma dry etching is used. In some embodiments, the etching gas comprises a chlorine-containing gas, such as HCl, Cl2, CF3Cl, CCl4, or SiCl4. In some embodiments, the chlorine-containing gas is diluted with a shielding gas such as He and / or Ar. In some embodiments, a ratio of chlorine-containing gas to diluent gas is in a range of about 0.3 to about 0.7, and in other embodiments, the ratio is in a range of about 0.4 to about 0.6. In some embodiments, one or more other gases, such as O2, are added. Other gases suitable for etching silicon may be used. In some embodiments, a further wet etching operation is performed using an aqueous solution of tetramethylammonium hydroxide (TMAH).

[0041] The etching of the sacrificial layer 20 with dopants, such as As, is selective for the silicon substrate 10 and the epitaxial semiconductor layer 25. The etch selectivity is in some embodiments from about 10 to about 100. In some embodiments, the sacrificial layer 20 is further fully etched, as in Fig. 10. In other embodiments, the sacrificial layer 20 is only partially etched and therefore part of the sacrificial layer 20 comprising the dopant residues around the space 100. In such a case, an impurity-containing layer with a higher dopant concentration than the substrate 10 and / or the epitaxial semiconductor layer 25 is arranged around the space 100.

[0042] In some embodiments, after forming the spaces 100, end portions of the epitaxial semiconductor layer 25 bend upwards over the spaces 100 and form a concave curved shape, as shown by the broken line in Fig. 10. In other embodiments, the end portions of the epitaxial semiconductor layer 25 bend downward over the spaces 100 and form a convex curved shape.

[0043] In some embodiments, less etching gas reaches one end of a long distance in the space, and therefore the etch rate becomes lower as the distance from the trench increases. In such a case, as in Fig. 1D, the depth in the Z-direction and / or the width in the X-direction as the distance from the trench increases along the Y-direction, and in some embodiments, two spaces formed from the left side and from the right side do not meet and are separated by a portion of the substrate, as in Fig. 1E shown.

[0044] After the spaces 100 are formed, the insulation insulating layer 30 is formed in the trenches 35 and the spaces 100, as shown in Fig. 11. An insulating material for the insulating insulation layer 30 comprises one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or low-k dielectric. The insulating insulation layer is formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, flowable dielectrics may be deposited instead of silicon oxide. Flowable dielectrics, as the name suggests, may "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride compounds are added.Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methylsilsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ / HSQ, a perhydrosilazane (TCPS), a perhydropolysilazane (PSZ), a tetraethylorthosilicate (TEOS), or a silylamine such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multi-function process. After the flowable film is deposited, it is cured and annealed to remove one or more undesirable elements to form silicon oxide. As the undesirable element(s) is / are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and / or phosphorus. In other embodiments, an ALD process is used.

[0045] The insulating layer 30 is first formed in a thick layer such that the entire upper surface of the epitaxial semiconductor layer 25 is covered, and the thick layer is planarized such that the upper surface of the epitaxial semiconductor layer 25 is exposed. In some embodiments, a chemical mechanical polishing (CMP) process is performed as the planarization process. After or before cutting out the insulating layer 30, a thermal process, such as an annealing process, may be performed to improve the quality of the insulating layer 30. In certain embodiments, the thermal process is performed using rapid thermal annealing (RTA) at a temperature in a range of about 900°C to about 1050°C for about 1.5 seconds to about 10 seconds in a protective gas environment, such as an N2, Ar, or He environment.

[0046] As in Fig. 11, in some embodiments, the insulating material for the insulating layer 30 does not completely fill the spaces 100, so air spacers 110 are formed in the space 100. In some embodiments, the air spacers 110 completely surround the insulating material for the insulating layer 30. The thickness of the insulating material at the top, bottom, and lateral ends of the space 100 is not uniform in some embodiments. In other embodiments, a portion of the inner wall of the space 100, which is the semiconductor layer, is exposed in the air spacer 110. In some embodiments, the lateral end of the air spacer 110 opposite the trench 35 comprises a portion of the substrate 10. In other embodiments, the lateral end of the air spacer 110 opposite the trench 35 comprises the impurity-containing layer.In some embodiments, a portion or upper boundary of the air spacer 110 comprises a portion of the epitaxial semiconductor layer 25 and / or comprises a portion of the impurity-containing layer. In other embodiments, a portion of the lower boundary of the air spacer 110 comprises a portion of the substrate 10 and / or comprises a portion of the impurity-containing layer. In some embodiments, the spaces 100 are completely filled by the insulating material, and no air spacer is formed.

[0047] After the insulation layer 30 and the air spacer 110 are formed, a gate structure comprising the gate dielectric layer 42, the gate electrode layer 44, and the gate sidewall spacer 46 is formed over a channel region of the epitaxial semiconductor layer 25, as shown in Fig. 12. Furthermore, the source / drain diffusion regions 50 and the source / drain extension regions 55 are formed as shown in Fig. 12. In some embodiments, a bottom of the source / drain diffusion region 50 is in contact with the insulating material 30 formed in the space 100. In other embodiments, the bottom of the source / drain diffusion region 50 is separated from the insulating material 30 formed in the space 100 by a portion of the epitaxial semiconductor layer 25. The source / drain diffusion regions 50 are formed by one or more ion implantation operations or a thermal or plasma diffusion operation.

[0048] Fig. Figures 13 to 15 show cross-sectional views of the various steps for fabricating a FET device according to an embodiment of this invention. It should be understood that further operations may be performed before, during, and after the methods of Fig. 13 to 15, and that some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanation may be omitted.

[0049] After formation of the trenches 35 similar to Fig. 9, spaces 100 are formed with a triangular or a trapezoidal cross-section, as in Fig. 13. In some embodiments, a wet etching operation is performed using an aqueous solution of TMAH. During the wet etching, etching byproducts fall onto the bottom surface of the etched space, and the etching rate of the bottom surface thus becomes smaller than the etching rate of the top surface of the etched space. Accordingly, the cross-sectional shape has a shape that has a vertical depth that decreases as the distance from the entrance of the space increases, such as a triangular or trapezoidal shape.

[0050] As in Fig. 13, an impurity-containing layer (part of the sacrificial layer 20) having a higher impurity concentration than the substrate 10 and / or the epitaxial semiconductor layer 25 is arranged under the space 100 or around it.

[0051] Then, similar to the operations related to Fig. 11, the trenches 35 and the spaces 100 are formed with the insulation material for the insulation insulation layer 30 and the air spacers 110 are formed as shown in Fig. 14 shown.

[0052] After the insulation layer 30 and the air spacer 110 are formed, a gate structure comprising the gate dielectric layer 42, the gate electrode layer 44, and the gate sidewall spacer 46 is formed over a channel region of the epitaxial semiconductor layer 25, as shown in Fig. 15. Furthermore, the source / drain diffusion regions 50 and the source / drain extension regions 55 are formed as shown in Fig. 15. In some embodiments, a bottom of the source / drain diffusion region 50 is in contact with the insulating material formed in the space 100. In other embodiments, the bottom of the source / drain diffusion region 50 is separated from the insulating material formed in the space 100 by a portion of the epitaxial semiconductor layer 25.

[0053] In some embodiments, at least one surface defining the space 100 has a zigzag shape, as shown in Fig. 16 shown.

[0054] In some embodiments, less etchant reaches or contacts the end of a long distance in the space, and therefore the etch rate becomes lower as the distance from the trench increases. In such a case, as in Fig. 2B, the depth in the Z-direction and / or the width in the X-direction as the distance from the trench increases along the Y-direction, and in some embodiments, two spaces formed from the left side and from the right side do not meet and are separated by a portion of the substrate, as in Fig. 2C shown.

[0055] Fig. 17 shows a plan view of a semiconductor device according to one embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanations may be omitted.

[0056] In some embodiments, as in Fig. 17, a plurality of gate structures are deposited over an active region, including channel regions and source / drain regions formed from a semiconductor and surrounded by the isolation insulating layer. In some embodiments, at least two of the plurality of gate electrodes 44 are connected, and in other embodiments, the plurality of gate electrodes 44 are not connected to each other. For illustrative purposes, various configurations of air spacers are shown in one figure; however, it should be understood that not all configurations are necessarily present in a device. In some embodiments, one or more configurations of the air spacers exist in a device.

[0057] In some embodiments, air spacers are disposed beneath the source / drain diffusion regions 50. In some embodiments, the air spacer 110B disposed beneath the source / drain diffusion region 50 between two gate structures 44 / 46 has different dimensions than the air spacer 110A disposed beneath the source / drain diffusion region 50 along the lines and / or right gate structure. In some embodiments, the width W31 of the air spacer 110A beneath the source / drain diffusion region 50 at the left end or at the right end is greater than the width W32 of the air spacer 110B beneath the source / drain diffusion region 50 between two gate structures.In some embodiments, the length L31 of the air spacer 110A under the source / drain diffusion region 50 at the left end or at the right end is the same as or different from the length L32 of the air spacer 110B under the source / drain diffusion region 50 between two gate structures. In some embodiments, the air spacers 110C and 110D under the source / drain diffusion region have two tapered portions from the edges of the source / drain diffusion region 50 at the isolation insulating layer 30 to the center of the source / drain diffusion region 50 (along the Y direction) in plan view. The tapered portion is caused by insufficient lateral etching of the sacrificial layer 20 under the source / drain diffusion region between two gate structures along the Y direction.In some embodiments, the air spacer 110D under the source / drain diffusion region 50 is discontinuous between two gate structures in the Y direction, while the air spacer 110C under the source / drain diffusion region 50 is continuous at the left end or the right end.

[0058] In some embodiments, the sacrificial layer is formed at a relatively deeper location in the substrate, so that the surface region of the substrate 10 does not include the dopants (e.g., As). In such a case, no epitaxial semiconductor layer 25 is formed, and the surface region is formed as a channel region and source / drain diffusion regions.

[0059] Fig. 18A, Fig. 18B, Fig. 18C and Fig. 18D show various views of semiconductor devices according to another embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanations may be omitted. In this embodiment, a Fin FET (Fin FET) is employed together with the embedded insulation layer.

[0060] Fig. 18A is a plan view, Fig. 18B is a cross-sectional view along Y1-Y1 of Fig. 18A, Fig. 18C is a cross-sectional view along X1-X1 of Fig. 18A and Fig. 18D is a cross-sectional view along Y2-Y2 of Fig. 18A.

[0061] As in Fig. 18A and Fig. 18C, a channel region (fin structure) 225 extends in the X-direction and a metal gate structure 260 extending in the Y-direction is arranged over the fin structure 225. In the source / drain region of the fin structure, as shown in Fig. As shown in Figure 18B, an epitaxial layer is formed around the fin structure 225. Furthermore, a source / drain contact layer 280 is formed. The conductive material of the source / drain contact layer 280 comprises one or more layers of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN, or another suitable material.

[0062] In some embodiments, a silicide layer is formed over the fin structure 225 before the conductive material is formed, as in Fig. 18A and Fig. 18B. The silicide layer comprises one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. When the fin structure 225 comprises Ge, an alloy of Ge and metal (e.g., TiGe, NiGe, or CoGe) is formed, and when the epitaxial layer comprises Si and Ge, an alloy of Si, Ge, and metal (e.g., NiSiGe or TiSiGe) is formed. When the fin structure 225 comprises a Group III-V semiconductor, an alloy such as Ni-InAlAs is formed.

[0063] The gate electrode layer 260 is disposed between gate sidewall spacers 248 and formed on a gate dielectric layer 223. The gate dielectric layer 223 includes one or more layers of dielectric, such as silicon oxide, silicon nitride, or a high-k dielectric, another suitable dielectric, and / or combinations thereof. Examples of high-k dielectrics include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titania, hafnium dioxide-alumina alloy (HfO2-Al2O3 alloy), other suitable high-k dielectrics, and / or combinations thereof. In some embodiments, the gate dielectric layer 223 includes an interface layer formed between the channel layers and the dielectric. The gate dielectric layer 223 may be formed by CVD, ALD, or any suitable method.In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process such as ALD to ensure the formation of a gate dielectric layer with a uniform thickness around each channel layer. The thickness of the gate dielectric layer 223 is in a range of about 1 nm to about 6 nm in one embodiment.

[0064] The gate electrode layer 260 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 260 may be formed by CVD, ALD, electroplating, or another suitable method. The gate dielectric layer and the electrode layer are also deposited over the top surface of an ILD layer 250. The gate dielectric layer and the gate electrode layer formed over the ILD layer 250 are then planarized, for example, using CMP, until the top surface of the ILD layer 250 is exposed.

[0065] In certain embodiments of this disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 223 and a gate electrode layer 260. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or another suitable process.Furthermore, the work function matching layer can be formed separately for the n-channel FET and the p-channel FET, which may use different metal layers.

[0066] As in Fig. 18B and Fig. 18D, an insulating layer 30 (e.g., STI) is formed over the substrate 210. As shown in Fig. As shown in Figures 18B to 18D, the fin structure 225 is insulated from a substrate 210 or a bottom fin structure 220 by an embedded insulation layer 270, which corresponds to the lateral portion of the isolation insulation layer 30 in the above embodiments. In some embodiments, the embedded insulation layer 270 includes an air spacer similar to air spacer 110. In some embodiments, one or more fin liner layers 228 are formed over the bottom fin structures 220. The fin liner layer 228 may be made of SiN or a silicon nitride-based material (e.g., SiON or SiCN). In some embodiments, a doped layer 213 (a portion of the sacrificial layer 212 explained below) is disposed between adjacent fin structures.In some embodiments, a doped layer is disposed between the embedded insulation layer 270 and a bottom of the fin structure 225 and / or a top of the lower fin structure 220. In some embodiments, the embedded insulation layer 270 and the insulation insulation layer 230 are continuously formed from the same insulation material.

[0067] Fig. 19A and Fig. 19B show various views of semiconductor devices according to another embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and detailed explanations may be omitted. In this embodiment, a gate-all-around FET (GAA FET) is employed along with the embedded insulation layer.

[0068] As in Fig. 19A and Fig. 19B, a bottom fin structure 315 is disposed over a substrate 310, and one or more semiconductor wires or sheets 320 are disposed over the bottom fin structure 315. The channel region of each of the wires or sheets 320 is wrapped with a gate structure comprising a gate dielectric layer 342 and a gate electrode layer 340. In some embodiments, the gate electrode layer 340 comprises one or more work function matching layers. As shown in Fig. 19A and Fig. 19B, the gate structure is surrounded by a gate sidewall spacer 348 and an isolation insulating layer 330 is disposed over the substrate 310.

[0069] In some embodiments, an epitaxial source / drain layer 360 is formed on the lateral ends of the wires or sheets 320. In other embodiments, the epitaxial source / drain layer 360 wraps around source / drain regions of the wires or sheets 320.

[0070] As in Fig. 19A and Fig. As shown in Figure 19B, the epitaxial source / drain layer 360 is isolated from a substrate 310 or the bottom fin structure 315 by an embedded insulation layer 300, which corresponds to the lateral portion of the isolation layer 30 in the above embodiments. In some embodiments, the embedded insulation layer 300 includes an air spacer 302 similar to the air spacer 110.

[0071] Fig. 20 to 25 show views of various stages of fabricating a semiconductor device according to an embodiment of this disclosure. It is understood that further operations may be performed before, during, and after the methods of Fig. 20 to 25 may be provided, and some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and a detailed explanation may be omitted. The semiconductor device of Fig. 20 to 25 corresponds to the semiconductor device of Fig. 18A to 18D.

[0072] Similar to Fig. 4, a photoresist pattern is formed as a first mask pattern 18 over a cap layer 204 using one or more lithography operations, as shown in Fig. 20. An alignment key 202 is formed in some embodiments.

[0073] Similar to Fig. 5 and Fig. 6, one or more ion implantation operations are performed to form sacrificial regions 212 containing dopants as in Fig. 21. In some embodiments, after the ion implantation operations and the removal of the mask layer 18, similar to Fig. 6, a thermal process, such as an annealing process, is performed. Further, in some embodiments, well implantation operations are performed to form an n-well 200N for a PFET and a p-well 200P for an NFET.

[0074] Then, similar to Fig. 7, an epitaxial semiconductor layer 225 is formed over the substrate 10, which includes the sacrificial layer 212, as shown in Fig. 22. Since the epitaxial semiconductor layer is subsequently formed in fin structures, a sufficiently thick epitaxial layer 225 is formed.

[0075] Then, as in Fig. 23, fin structures 235 are formed by one or more photolithography and etching operations. The fin structures 235 may be patterned using any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing the creation of structures having, for example, pitches that are smaller than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a dummy layer is formed over a substrate and patterned using a photolithography process.Spacers are formed along the patterned dummy layer using a self-aligned process. The dummy layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a hard mask pattern 229 is used.

[0076] As in Fig. 23, each of the fin structures 235 includes a portion of the epitaxial layer 225, the sacrificial layer 212, and a portion of the substrate as a bottom fin structure 201.

[0077] Then, in some embodiments, a support layer 255 supporting an end portion of the fin structure 235 and exposing the channel region and source / drain regions is formed, as shown in Fig. 24A and Fig. 24B shown. Fig. 24A is a cross-sectional view along the Y direction and Fig. 24B is a cross-sectional view along the X direction, the line Z1-Z1 of Fig. 24A. In some embodiments, the support layer 255 is made of silicon nitride, SiON, or another suitable dielectric formed by CVD, ALD, or another suitable film deposition process. The deposited dielectric is patterned using one or more lithography operations. In some embodiments, the support layer 255 covers about 1-10 nm of the edge portion of the fin structure 235. In some embodiments, one or more support layers 255 are formed over one or more central portions of the fin structure 235.

[0078] During or after forming the fin structure 235, the hard mask structure 229 is removed and then the carrier layer 255 is formed, as in Fig. 24A and Fig. 24B. In other embodiments, after removing the carrier layer 255, the hard mask structure 229 is removed. In such a case, a portion of the hard mask structure 229 remains beneath the carrier layer.

[0079] After forming the carrier layer 255, the sacrificial layer 212 is removed as shown in Fig. 25A to 25C shown. Fig. 25A is a cross-sectional view along the X direction and Fig. Figure 25B is a cross-sectional view along the Y direction. Fig. 25C is a cross-sectional view along the X direction corresponding to the line Z1-Z1 of Fig. 25B. In some embodiments, the sacrificial layer 212 is completely removed. In other embodiments, a portion of the sacrificial layer 212 remains as in Fig. 25D and Fig. 25E shown as a residue 213 under the carrier layer 225. In some embodiments, as in Fig. 25D and Fig. 25E shows a remainder 214 of the sacrificial layer 212 as the bottom of the patterned epitaxial semiconductor layer 225 and / or as the top of the lower fin structure 201.

[0080] Next, as in Fig. 26A to 26C, an insulating insulation layer 230 is formed. The insulating insulation layer 230 comprises one or more layers of insulating material formed over the substrate 200. The insulating material for the first insulating material layer 29 may comprise silicon oxide, silicon nitride, silicon oxynitride (SiON), SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD, or any other suitable film formation process. In some embodiments, the first insulating material layer 230 is made of silicon oxide. An annealing operation may be performed after forming the first insulating material layer 230. In some embodiments, as shown in Fig. 26C, an air spacer 232 similar to air spacer 110 is formed in the first insulation material layer 230 beneath the fin structures. In some embodiments, a portion of the sacrificial layer 212 remains as shown in Fig. 26D and Fig. 26E as a residue 213 under the carrier layer 225. In some embodiments, as shown in Fig. 26D and Fig. 26E, a remainder 214 of the sacrificial layer 212 remains between the first insulating material layer 230 and a bottom of the patterned epitaxial semiconductor layer 225 and / or a top of the lower fin structure 201.

[0081] After forming the isolation insulation layer 230, a dummy gate structure is formed. The dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode layer. The dummy gate dielectric layer includes one or more layers of insulation material, such as silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the dummy gate dielectric layer is in a range of approximately 1 nm to approximately 5 nm in some embodiments.

[0082] After forming the dummy gate structures, a cap layer of an insulating material for sidewall spacers is conformally formed using CVD or other suitable methods. The cap layer is deposited in a conformal manner such that it is formed having substantially equal thicknesses on vertical surfaces, such as the sidewalls, the horizontal surfaces, and the top surface of the dummy gate structures. In some embodiments, the cap layer is deposited with a thickness in a range of about 2 nm to about 20 nm. In one embodiment, the insulating material of the cap layer differs from the materials of the first insulating layer and the second insulating layer and is made of a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. In some embodiments, the cap layer (sidewall spacer 245) is made of SiN.The sidewall spacers 245 are formed by anisotropic etching on opposite sidewalls of the dummy gate structures.

[0083] After forming the sidewall spacers 245, an interlayer dielectric (ILD) layer 250 is formed. Materials for the ILD layer 250 include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 250. After forming the ILD layer 250, a planarization operation, such as CMP, is performed to expose the upper portions of the dummy gate electrode layers of the dummy gate structures.

[0084] In some embodiments, an epitaxial source / drain layer 275 is then formed on the source / drain region of the fin structure 225. In some embodiments, the epitaxial source / drain layer 275 comprises one or more layers of SiP, SiC, SiCP, SiGe, Ge, or other suitable materials.

[0085] Next, the dummy gate structures are replaced with a metal gate structure and a source / drain contact layer 280 is formed, as shown in Fig. 18A to 18D.

[0086] Fig. 27 to 30 show views of various stages of fabricating a semiconductor device according to an embodiment of this disclosure. It is understood that further operations may be performed before, during, and after the methods of Fig. 27 to 30 may be provided, and some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations that are the same as or similar to the above embodiments may be employed in the following embodiments, and a detailed explanation may be omitted. The semiconductor device of Fig. 27 to 30 corresponds to the semiconductor device of Fig. 19A to 19B.

[0087] After forming the sacrificial layer 212 and removing the cap layer 15, epitaxial layers comprising multiple layers of first semiconductor layers 223 and second semiconductor layers 222 are alternately stacked on the substrate 200. In one embodiment, the first semiconductor layers 223 are made of SiGe and the second semiconductor layers 222 are made of Si. The first and second semiconductor layers are as in Fig. 27 are alternately epitaxially formed over the substrate 200. In some embodiments, similar to Fig. 13 to 16, a section of the sacrificial layer 212 in the fin structures.

[0088] Then, similar to Fig. 23, fin structures 235 formed by structuring operations, as in Fig. 28. During or after forming the fin structure 235, the sacrificial layer 225 is removed, as shown in Fig. 29. Next, as shown in Fig. 30 shows an insulation layer 230 similar to that shown in Fig. 25 formed.

[0089] Subsequently, the dummy gate structure is formed, the gate sidewall spacers 348 are formed, the epitaxial source / drain layer 360 is formed, and an ILD layer 380 is formed. In some embodiments, the source / drain region is etched, and then the epitaxial source / drain layer 360 is formed.

[0090] Then, the dummy gate structure is removed to form a gate spacer, and the first semiconductor layers 223 are removed in the gate gap, leaving the second semiconductor layer 222 as the semiconductor wires or sheets 320. Then, as in Fig. 19A and Fig. 19B, the gate dielectric layer 342 and the gate electrode 340 are formed.

[0091] In some embodiments, as in Fig. 31A and Fig. 31B, a portion of the sacrificial layer 212 remains as a residue 213 under the carrier layer 225. In some embodiments, as shown in Fig. 31A and Fig. 31B, a remainder 214 of the sacrificial layer 212 remains between the first insulation material layer 230 and a bottom of the patterned epitaxial semiconductor layer 225 and / or a top of the lower fin structure 201. In some embodiments, the embedded insulation layer 270 includes an air spacer 232 similar to the air spacer 110, as shown in Fig. 31B shown.

[0092] Fig. 32A, Fig. 32B, Fig. 32C, Fig. 32D and Fig. 32E show cross-sectional views of the various stages of a manufacturing operation for a semiconductor device according to an embodiment of this disclosure. In some embodiments, similar to the removal of the sacrificial layer 225 explained above, prior to removing the sacrificial layer 225 by etching, a support layer 255 is formed at both ends of the fin structure 235 to expose the channel region and the source / drain regions. In some embodiments, the support layer 255 is made of silicon nitride.

[0093] After forming the fin structure 235 as in Fig. 32A, is shown as in Fig. 32B, a cover layer for the support structure 255 is formed, and then, as shown in Fig. 32C, a mask layer 256, such as a photoresist pattern, is formed. Then, the cover layer is etched to form Fig. 32D to form the support structure 255. As shown in Fig.32E, after removing the sacrificial layers and the second semiconductor layers 222, the ends of the fin structure are supported by the support structure 255.

[0094] In the embodiments of this invention, an air spacer and / or an embedded insulation layer is disposed under the source and / or drain diffusion regions and / or the gate electrode, and thus the capacitance between the source / drain diffusion region and / or the gate electrode and the substrate can be suppressed or eliminated, which in turn can reduce power consumption and increase the speed of the semiconductor device.

[0095] It should be understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0096] According to one aspect of this invention, in a method of manufacturing a semiconductor device including a field-effect transistor (FET), a sacrificial region is formed in a substrate, and a fin structure is formed by patterning the substrate and the sacrificial region. A space is formed by at least partially etching the sacrificial region. An insulating insulating layer is located over the substrate, and an embedded insulating layer is formed by filling the space with an insulating material, and a gate structure and a source / drain region are formed. In one or more of the preceding and following embodiments, the sacrificial region is formed by an ion implantation operation. In one or more of the preceding and following embodiments, arsenic ions are implanted by the ion implantation operation.In one or more of the preceding and following embodiments, a dose amount in the ion implantation operation is in a range of 5 × 10 . 13 ions / cm 2 up to 5 × 10 15 ions / cm 2. In one or more of the preceding and following embodiments, an acceleration voltage in the ion implantation operation is in a range of 0.5 keV to 10 keV. In one or more of the preceding and following embodiments, at least partially etching the sacrificial region comprises a dry etching operation using chlorine-containing gas. In one or more of the preceding and following embodiments, the embedded insulation layer is located below an upper surface of the insulation layer. In one or more of the preceding and following embodiments, at least partially etching the sacrificial region comprises a wet etching operation using an aqueous solution of tetramethylammonium hydroxide (TMAH). In one or more of the preceding and following embodiments, the embedded insulation layer is connected to the insulation layer.In one or more of the preceding and following embodiments, an air spacer is formed in the embedded insulation layer. In one or more of the preceding and following embodiments, the air spacer is completely enclosed by an insulation material of the embedded insulation layer. In one or more of the preceding and following embodiments, a contaminant-containing region comprising a contaminant in an amount higher than the substrate is disposed between the space and the substrate.

[0097] According to another aspect of this disclosure, in a method of manufacturing a semiconductor device including an FET, a sacrificial region is formed in a substrate, first epitaxial semiconductor layers and second epitaxial semiconductor layers are alternately formed over the substrate to form a stacked layer, and a fin structure is formed by patterning the stacked layer, the sacrificial region, and a portion of the substrate.A space is formed by at least partially etching the sacrificial region, an insulating insulating layer is formed over the substrate, and an embedded insulating layer fills the space with an insulating material, a dummy gate structure and a source / drain region are formed, the dummy gate structure is removed to form a gate space, the first semiconductor layers in the gate space are removed, and a metal gate structure is formed over the second semiconductor layers in the gate space. In one or more of the preceding and following embodiments, the sacrificial region is formed by an ion implantation operation. In one or more of the preceding and following embodiments, an impurity amount of the sacrificial region is in a range of 1 × 10. 19 atoms / cm 3 up to 5 × 10 21 atoms / cm 3. In one or more of the preceding and following embodiments, a thickness of the epitaxial semiconductor layer is in a range from 5 nm to 100 nm. In one or more of the preceding and following embodiments, the embedded insulating layer comprises an air spacer, and a width of the air spacer varies along the first direction in the plan view. In one or more of the preceding and following embodiments, the embedded insulating layer comprises an air spacer, and the air spacer is discontinuous and extends along the first direction of the plan view below the source / drain region.

[0098] According to another aspect of this disclosure, a semiconductor device comprises a FinFET. The FinFET includes a semiconductor fin structure disposed over a bottom fin structure provided over a substrate, an isolation insulating layer disposed over the substrate, a gate dielectric layer disposed over a channel region of the semiconductor fin structures, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulation layer disposed between a bottom of the fin structure and a top of the bottom fin structure, and continuously made of a same material as the isolation insulating layer.In one or more of the preceding and following embodiments, the embedded insulation layer is continuously disposed beneath the channel region and a source / drain region of the fin structure. In one or more of the preceding and following embodiments, an air spacer is formed in the embedded insulation layer. In one or more of the preceding and following embodiments, the air spacer is completely embedded by an insulation material of the insulation layer. In one or more of the preceding and following embodiments, an impurity-containing region comprising an impurity in an amount higher than the lower fin structure is disposed between the embedded insulation layer and the lower fin structure.

[0099] According to another aspect of this disclosure, a semiconductor device includes semiconductor wires arranged over a bottom fin structure provided over a substrate, an isolation insulating layer provided over the substrate, a gate dielectric layer wrapping around a channel region of each of the semiconductor wires, a gate electrode arranged over the gate dielectric layer, a source and a drain arranged adjacent to the channel region, and an embedded insulation layer arranged under the semiconductor wires and continuously made of the same material as the isolation insulating layer. In one or more of the preceding and following embodiments, an air spacer is formed in the embedded insulation layer.An impurity-containing region comprising an impurity with an amount higher than the lower fin structure is disposed between the embedded insulation layer and the lower fin structure.

Claims

[1] A method for manufacturing a semiconductor device comprising a field effect transistor, hereinafter referred to as FET, the method comprising: Forming a sacrificial region (20, 212) in a substrate (10, 200, 210, 310); Forming a fin structure (220, 225, 235, 315) by patterning the substrate (10, 200, 210, 310) and the sacrificial region (20, 212); Forming a space (100) by at least partially etching the sacrificial region (20, 212), wherein an impurity-containing region comprising an impurity in an amount higher than the substrate (10, 200, 210, 310) is arranged between the space (100) and the substrate (10, 200, 210, 310); Forming an insulating layer (30, 230, 330) over the substrate (10, 200, 210, 310) and an embedded insulating layer (270, 300) by filling the space (100) with an insulating material; and Forming a gate structure (44) and a source / drain region. [2] The method of claim 1, wherein the sacrificial region (20, 212) is formed by an ion implantation operation (19). [3] The method of claim 2, wherein ions of arsenic are implanted by the ion implantation operation (19). [4] A method according to claim 2 or 3, wherein a dose amount in the ion implantation operation (19) is in a range of 5 × 10 13 ions / cm 2 up to 5 × 10 15 ions / cm 2 lies. [5] A method according to any one of claims 2 to 4, wherein an acceleration voltage in the ion implantation operation (19) is in a range of 0.5 keV to 10 keV. [6] A method according to any one of the preceding claims, wherein the at least partial etching of the sacrificial region (20, 212) comprises a dry etching operation using chlorine-containing gas. [7] A method according to any one of the preceding claims, wherein the embedded insulation layer (270, 300) is located below an upper surface of the insulation layer (30, 230, 330). [8] The method according to any one of claims 1 to 5 and 7, wherein the at least partial etching of the sacrificial region (20, 212) comprises a wet etching operation using an aqueous solution of tetramethylammonium hydroxide [9] Method according to one of the preceding claims, wherein the embedded insulation layer (270, 300) is connected to the insulation insulation layer (30, 230, 330). [10] A method according to any one of the preceding claims, wherein an air spacer (110, 110A-D, 232, 302) is formed in the embedded insulation layer (270, 300). [11] The method of claim 10, wherein the air spacer (110, 110A-D, 232, 302) is completely enclosed by an insulating material of the embedded insulating layer (270, 300). [12] A semiconductor device comprising a fin-FET comprising: a semiconductor fin structure disposed over a lower fin structure (201, 220, 315) provided over a substrate (10, 200, 210, 310); an insulating layer (30, 230, 330) disposed over the substrate (10, 200, 210, 310); a gate dielectric layer (42, 223, 342) disposed over a channel region (12) of the semiconductor fin structures; a gate electrode (44) disposed over the gate dielectric layer (42, 223, 342); a source and a drain disposed adjacent to the channel region (12); and an embedded insulating layer (270, 300) disposed between a bottom of the semiconductor fin structure (220, 225, 235) and a top of the lower fin structure (201, 220, 315) and continuously made of a same material as the insulating layer (30, 230, 330), wherein an impurity-containing region comprising an impurity in an amount higher than the lower fin structure (201, 220, 315) is disposed between the embedded insulating layer (270, 300) and the lower fin structure (201, 220, 315). [13] The semiconductor device according to claim 12, wherein the embedded insulation layer (270, 300) is continuously disposed under the channel region (12) and a source / drain region of the fin structure (220, 225, 235). [14] The semiconductor device according to claim 12 or 13, wherein an air spacer (110, 110A-D, 232, 302) is formed in the embedded insulation layer (270, 300). [15] The semiconductor device according to claim 14, wherein the air spacer (110, 110A-D, 232, 302) is completely enclosed by an insulating material of the embedded insulating layer (270, 300). [16] A semiconductor device comprising a fin-FET comprising: Semiconductor wires arranged over a lower fin structure (201, 220, 315) provided over a substrate (10, 200, 210, 310); an insulating layer (30, 230, 330) disposed over the substrate (10, 200, 210, 310); a gate dielectric layer (42, 223, 342) wrapping around a channel region (12) of each of the semiconductor wires; a gate electrode (44) disposed over the gate dielectric layer (42, 223, 342); a source and a drain arranged adjacent to the channel region (12); and an embedded insulation layer (270, 300) disposed under the semiconductor wires and continuously made of a same material as the insulation layer (30, 230, 330), wherein an impurity-containing region comprising an impurity in an amount higher than the lower fin structure (201, 220, 315) is disposed between the embedded insulation layer (270, 300) and the lower fin structure (201, 220, 315). [17] The semiconductor device according to claim 16, wherein an air spacer (110, 110A-D, 232, 302) is formed in the embedded insulation layer (270, 300).

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