ULTRA-THIN FIN STRUCTURE AND METHOD FOR ITS MANUFACTURING

Abstract

Exhibiting a semiconductor structure: a substrate (115) which has base structures (110) formed on it; Fin structures (100) formed on the base structures (110) and exhibiting the following: - a downwardly conical section (105) with a lower width (Wb), a middle width (Wm) and an upper width (Wt), wherein the middle width (Wm) is greater than the lower width (Wb) and the upper width (Wt); and - an upper section with a width that is substantially equal to or narrower than the upper width (Wt) of the downwardly conical section (105); and an insulating material (120) arranged between the base structures (110), wherein the mean width (Wm) of the downwardly conical section (105) is formed by a side wall angle (θ1) of the downwardly conical section (105), measured between a side wall surface of the upper section and a side wall surface of the downwardly conical section (105), wherein the side wall angle (θ1) is in a range between about 10° and about 30°.

Description

TECHNICAL BACKGROUND

[0001] Fin field-effect transistors (FinFETs) can feature ultrathin fin structures for improved gate control over the channel region. However, ultrathin fin structures tend to bend or collapse during the formation of isolation regions between the ultrathin fin structures and / or during other manufacturing processes. This is because ultrathin fin structures lack the structural integrity of thicker fin structures. A semiconductor device and a corresponding manufacturing method are already known from document DE 10 2019 131 057 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying FIGS. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of illustration and discussion. Fig. 1A is an isometric view of fin structures with conical bottom profiles made from a silicon epitaxial layer, according to some embodiments. Fig. 1B is an isometric view of fin structures with conical bottom profiles made from a silicon germanium epitaxial layer, according to some embodiments. Fig. 1C is an isometric view of fin structures with conical bottom profiles fabricated from a silicon epitaxial stack, according to some embodiments. Fig. 1D is a germanium concentration plot along a fin structure with a conical bottom profile made from a single silicon germanium epitaxial layer or a silicon germanium epitaxial stack, according to some embodiments. Fig. 2 and Fig. 3 are partial cross-sectional views of fin structures with conical bottom profiles. Fig. 4 is a flow diagram of a manufacturing method for forming fin structures with conical bottom profiles, according to some embodiments. Fig. 5 to 10 are cross-sectional views describing the manufacturing process of fin structures with conical bottom profiles, according to some embodiments. Fig. 11 is a cross-sectional view of a source / drain epitaxial structure grown on fin structures with conical bottom profiles, according to some embodiments. DETAILED DESCRIPTION

[0003] Ultra-thin fin structures—for example, with an average width between about 5 nm and about 15 nm—used in fin field-effect transistors (finFETs) provide improved gate control over the channel region and mitigate problems associated with short-channel effects. For these reasons, ultra-thin fin structures are attractive for finFETs. However, the aforementioned advantages of ultra-thin fin structures are compromised by their limited saturation current—for example, due to their narrower width—and the lack of structural rigidity compared to thicker fin structures (e.g., thicker than about 20 nm). Ultra-thin fin structures can, for example, be susceptible to bending or collapse under mechanical stress from the surrounding layers (e.g.,dielectrics) and / or subsequent manufacturing processes - for example, densification processes that cause stress buildup near the ultra-thin structures.

[0004] To address the above challenges, this disclosure is directed to a method for forming ultrathin fins with a tapered bottom profile for improved structural rigidity while maintaining desired gate control characteristics. In some embodiments, ultrathin fins made of silicon and silicon germanium (SiGe) can be fabricated using the methods described herein. Furthermore, SiGe fins with a variable Ge concentration and a tapered profile can be formed in p-type finFETs for improved gate control over the channel and improved interface quality between the ultrathin fin structure and the gate dielectric stack.

[0005] According to some embodiments, Fig. 1A is a partial isometric view of ultra-thin fin structures 100 (fin structures 100) with a conical bottom profile 105, which significantly improves the structural rigidity of the fin structures 100. In some embodiments, fin structures 100 are deposited on pedestal structures 110 of substrate 115 prior to the formation of a gate stack, in Fig. 1 not shown, formed.

[0006] Fin structures 100 have a top width W between about 5 nm and about 15 nm and a total height H between about 40 nm and about 70 nm. Height H of each fin structure 100 is measured from the interface between fin structure 100 and pedestal structure 110 of substrate 115 and includes height B, which corresponds to the total height of the conical bottom profile 105, and height A - the height of the fin structure 100 above the conical bottom profile 105. In some embodiments, height H is substantially equal to the sum of heights A and B (e.g., H=A+B), as in Fig. 1A. In some embodiments, height A is between about 80% and about 90% of height H (e.g., 80% H ≤ A ≤ 90% H) and height B is between about 10% and about 20% of height H (e.g., 10% H ≤ B ≤ 20% H). For example, when H is between about 40 nm and about 70 nm, height A is between about 32 nm and about 63 nm, and height B (e.g., the height of the conical bottom profile 105) is between about 4 nm and about 14 nm.

[0007] In some embodiments, if height B is less than about 10% of height H, the conical bottom profile 105 may not be thick enough to structurally support fin structure 100. For example, if height B is less than about 10% of height H, fin structure 100 may become prone to bending or collapsing. On the other hand, if height B is greater than about 20% of height H (e.g., if the conical bottom profile 105 occupies a larger portion of the fin structure 100), channel control in the region of the conical bottom profile 105 may be limited. Therefore, the size of the conical bottom profile 105 in fin structure 100 (e.g., height B) must be adjusted so that fin structures 100 have an optimal balance between mechanical stiffness and electrical performance.

[0008] As in Fig. 1A, fin structures 100 are insulated by an insulating material 120 that includes a dielectric material such as silicon oxide, carbonaceous silicon oxide, hydrogen and nitrogen containing silicon oxide, or any other suitable dielectric material or layers.

[0009] Base structures 110 may be formed from substrate 115 and may include one or more doped regions formed in Fig. 1A are not shown. An upper portion of the pedestal structure 110 (e.g., lower conical bottom profile 105) may be doped with, for example, n-type or p-type dopants to prevent leakage current between fin structures 100 and substrate 115 during finFET operation. In some embodiments, substrate 115 is a bulk semiconductor wafer or a top layer of a semiconductor-on-insulator (SOI) wafer, such as silicon on insulator.Substrate 115 may further be made of silicon or another elemental semiconductor, such as (i) germanium (Ge); (ii) a composite semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor including gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) combinations thereof. In some embodiments, substrate 115 has a crystalline microstructure—e.g., it is not amorphous or polycrystalline.

[0010] For exemplary purposes, substrate 115 and pedestal structures 110 are described in the context of crystalline silicon (Si), with their top surface parallel to the (100) crystal plane. Based on the disclosure herein, other materials, as discussed above, or crystalline orientations may also be used. These materials fall within the spirit and scope of this disclosure.

[0011] According to some embodiments, a conical bottom profile 105 of fin structures 100 is formed over the upper surface of the insulation material 120, as shown in Fig. 1A shown.

[0012] In some embodiments, fin structures 100 may include a single epitaxial layer or a stack of epitaxial layers. For example, fin structures 100 may include a single Si epitaxial layer 125, as shown in Fig. 1A, a single SiGe epitaxial layer 130 as shown in Fig. 1B, or a stack of SiGe epitaxial layers 135, 140 and 145 as shown in Fig. 1C. In some embodiments, fin structures 100 are formed with a single silicon epitaxial layer 125, as shown in Fig. 1A, suitable for n-type finFETs (e.g., nFETs). Fin structures 100 with a single SiGe epitaxial layer 130 or a stack of SiGe epitaxial layers 135, 140, and 145, which are Fig. 1B and Fig. 1C are suitable for p-type finFETs (pFETs). In some embodiments, fin structures 100 may be used for both nFETs and pFETs, as shown in Fig. 1A-C, on the same substrate (e.g., substrate 115) using the methods described herein.

[0013] In some embodiments, fin structures 100 are pFET fin structures made from a single SiGe epitaxial layer 130, as in Fig. 1B, and have a Ge atomic concentration (at. %) that varies as a function of height H. With reference to Fig. 1B, the single SiGe epitaxial layer 130 has, for example, a Ge concentration that varies from about 10 atomic percent (at. %) to about 25 at. % along height A of the fin structure 100, and a Ge concentration that varies from about 25 at. % to about 35 at. % along height B of the conical bottom profile 105. In some embodiments, the Ge "peak" concentration is located in a region defined by height A, toward the bottom of height A—for example, within a region of the fin structure 100 defined by a height H G above the conical base profile 105. In some embodiments, the height H G between about 1 / 3 and 2 / 3 of the height H of the fin structure 100. If the total fin height H is about 60 nm, height H G between about 20 nm and about 40 nm.

[0014] In some embodiments, Fig. 1D Ge at. % as a function of the height H of the Fig. 1B. As described above with reference to Fig. 1B, peak Ge at. % is found within the “boundaries” of height A in an area of ​​the fin structure 100 defined by height H G which extends between approximately 1 / 3 and 2 / 3 of the height H of the fin structure 100. In addition, Ge at. % may be even higher in the conical bottom profile 105 (e.g., along height B), as described above and in Fig. 1D. The Fig. The Ge at. % profile shown in Figure 1D can be achieved during the growth of the SiGe epitaxial layer by tuning the deposition process conditions, as will be discussed later.

[0015] In some embodiments, a Fig. 1D shown similar Ge profile for the Fig. 1C, which contains SiGe epitaxial layers 135, 140 and 145. SiGe epitaxial layers 135, 140 and 145 can, for example, be grown with different Ge concentrations that Fig. 1D. By way of example and not limitation, epitaxial layer 145 may be grown with the lowest Ge concentration, epitaxial layer 140 may be grown with a Ge concentration higher than that of epitaxial layer 145 and with a thickness of height H Gis approximately equal, and epitaxial layer 135 can be grown to form conical bottom profile 105 with a higher Ge concentration than that of epitaxial layer 140 and a thickness approximately equal to height B. The above description of SiGe epitaxial layers 135, 140, and 145 is not limiting, and a stack with two layers may be formed instead of three. For example, SiGe epitaxial layers 135 and 140 may be combined into a single SiGe epitaxial layer. Additional SiGe epitaxial layers are also possible and fall within the spirit and scope of this disclosure.

[0016] In some embodiments, Fig. 2 and Fig. 3 enlarged cross-sectional views of the structural elements shown in rectangle 150 in Fig. 1A are included. The Fig. 2 and Fig. 3 The features shown apply equally to Fig. 1B and Fig. 1C. With reference to Fig. 2, the conical bottom profile 105 has a top width Wt between about 5 nm and about 15 nm, a middle width Wm between about 8 nm and about 20 nm, and a bottom width Wb between about 7 nm and about 18 nm. In some embodiments, width Wb is greater than width Wt and width Wm is greater than both widths Wt and Wb. For example: Wm > Wb > Wt. In some embodiments, ratio Wt / Wm is between about 0.25 and about 0.75 (e.g., 0.25 ≤ Wt / Wm ≤ 0.75); and ratio Wb / Wm is between about 0.35 and about 0.90 (e.g., 0.35 ≤ Wb / Wm ≤ 0.90). In some embodiments, ratios Wt / Wm and Wb / Wm less than about 0.25 and 0.35, respectively, may produce exaggeratedly conical profiles with limited channel control in the conical region of the fin structure 100. In some embodiments, ratios Wt / Wm and Wb / Wm greater than about 0.75 and 0.85, respectively, may produce exaggeratedly conical profiles with limited channel control in the conical region of the fin structure 100.0.90 produce conical profiles that are unable to provide adequate structural support for fin structures 100. In some embodiments, width Wt of the conical bottom profile 105 is substantially equal to the top width W of the fin structure 100 shown in FIG. Fig. 1, equal to or greater than this (e.g., Wt ≥ W). It is therefore possible for fin structures 100 to be narrow at the top of the fin structure 100 and increase in width along height A (e.g., W <Wt). In manchen Ausführungsformen ist die Breite der Finnenstrukturen 100 entlang Höhe A konstant (z.B. W=Wt) und nimmt innerhalb der Höhe B des konischen Bodenprofils 105 zu.

[0017] In some embodiments, the width Wm of the conical bottom profile 105 is spaced from the interface between the pedestal structure 110 and the fin structure 100 by a vertical distance C ranging from about 1 nm to about 3 nm. In some embodiments, the vertical distance C is between about 1 / 3 and about 1 / 2 the height B (e.g., the total height of the conical bottom profile 105). In some embodiments, a C / B ratio below about 1 / 3 moves Wm closer to Wb. This creates a difficult geometry for the deposition of gate layers. For example, it would be difficult to conformally deposit the gate layers (e.g., high-k dielectric layer, work function layers, etc.) on portions of the conical bottom profile 105 between Wm and Wb, which may result in undesirable threshold voltage variation between the FETs. On the other hand, a C / B ratio above about 1 / 2 Wm “moves” closer to Wt, which weakens the structural integrity of the fin structure 100.

[0018] In some embodiments, the interface between pedestal structure 110 and fin structure 100 is arranged above the top surface of insulation material 120 by a vertical distance D that is between about 4 nm and about 15 nm.

[0019] As discussed above, fin structures 100 have wide and narrow sections along height H to improve their structural rigidity. However, under the same gate bias conditions, gate control at wider sections of the fin structures 100 (e.g., at the positions of Wt, Wm, and Wb) may prove difficult. According to some embodiments, the Ge concentration may be used to "locally" reduce the Vt over the wider sections of the fin structures 100 and to improve gate control. This is because Ge has a narrower band gap than Si; regions with a higher Ge concentration (e.g., within the region defined by height H Gand conical bottom profile 105) may therefore have a lower Vt compared to regions with a lower Ge concentration (e.g., at the top of the fin structure 100). Consequently, increasing the Ge concentration in wider sections of the fin structures 100 effectively reduces the Vt in the wider sections and improves gate control across the channel. According to some embodiments, adjusting the Ge concentration in the fin structures may be beneficial for the operation of the finFET and provides a substantially constant saturation current along height H of the fin structure 100. In some embodiments, the Ge concentration in the Ge-rich regions of the fin structure 100 may reach about 50%.

[0020] According to some embodiments, width Wm of the Fig. 2 is a critical structural parameter used to adjust the structural stiffness of the fin structure 100. As discussed above, width Wm can range from about 8 nm to about 20 nm. If width Wm is less than about 8 nm, the conical bottom profile 105 is not wide enough to provide adequate structural support for the fin structure 100. Conversely, if width Wm is greater than about 20 nm, channel control in the conical bottom profile 105 becomes difficult, even with a higher Ge concentration.

[0021] In some embodiments, control of the width Wm is achieved via angles θ1 and θ2 on either side of the Fig. 3. In some embodiments, angles θ1 and θ2 between about 10° and about 30° provide a width Wm between about 8 nm and about 20 nm. Therefore, angles θ1 and θ2 less than about 10° result in a width Wm less than about 8 nm, and angles θ1 and θ2 wider than about 30° result in a width Wm greater than about 20 nm. In some embodiments, the average width Wm and angles θ1 and θ2 are controlled via etch and anneal conditions used during and after formation of the fin structures 100. In some embodiments, angle θ3 is between about 120° and about 160°.

[0022] In some embodiments, angles θ1 and θ2 prevent sidewall portions of the conical bottom profile 105 from being coplanar with sidewall portions of the fin structure 100 above and below the conical bottom profile 105. Furthermore, angles θ1 and θ2 prevent sidewall portions of the conical bottom profile 105 from being coplanar with sidewall portions of the pedestal structures 110, as shown in Fig. 3 shown.

[0023] Fig. 4 is a flow diagram of the manufacturing process 400 for forming fin structures 100, which in Fig. 1A. Other manufacturing operations may be performed between various operations of method 400 and are omitted here solely for clarity and simplicity of description. These various operations fall within the spirit and scope of this disclosure. Moreover, not all operations may be required to practice the disclosure provided herein. Some of the operations may be performed concurrently or in a different order than those described in Fig. 4. In some embodiments, one or more other operations may be performed in addition to or instead of the operations described herein. Method 400 is described with reference to Fig. 5 through 10. The FIGS. provided to describe method 400 are for illustrative purposes only and may not be to scale. Furthermore, the FIGS. may not depict the actual geometry of the real structures, features, or movies. Some structures, movies, or geometries may be enlarged or omitted for illustrative purposes.

[0024] With reference to Fig. 4, method 400 begins with operation 405 and the process of depositing a Si epitaxial layer onto a p-type region of a substrate, such as that shown in Fig. 1A. By way of example and without limitation, and according to operation 405 of method 400, Si epitaxial layer 125 may be formed directly on a p-type region 500 of substrate 115, as shown in Fig. 5. P-type region 500 may be formed, for example, with an ion implantation process using a p-type dopant, such as boron (B), and may have a dopant concentration between about 5×10 16 atoms / cm 3 up to about 1×10 19 atoms / cm 3Si epitaxial layer 125 may be grown to a thickness between about 30 nm and about 100 nm using a chemical vapor deposition (CVD) process. Source gases for silicon epitaxial formation may include silane (SiH4), silicon tetrachloride (SiCl4), trichlorosilane (TCS), or dichlorosilane (SiH2Cl2 or DSC). Hydrogen (H2) may be used as a reaction gas that reduces the aforementioned source gases. The deposition temperature during epitaxial layer growth may range from about 700°C to about 1250°C, depending on the gases used. Source gases with fewer chlorine atoms (e.g., DSC), for example, may require lower formation temperatures than source gases with more chlorine atoms, such as SiCl4 or TCS. The aforementioned ranges and gas types are given as examples and are not limiting.

[0025] With reference to Fig. 4, method 400 continues with operation 410 and the process of patterning the Si epitaxial layer 125 and the p-type region 500 to form fin structures on substrate 115. In some embodiments, patterning of the Si epitaxial layer 125 and the p-type region 500 is performed by photolithography and etching processes using Fig. 5. In some embodiments, hard mask structures 505 serve as an etch mask and may include one or more layers, such as silicon oxide and silicon nitride. Fin structures may be patterned by any suitable method. The fin structures may be patterned, for example, using one or more photolithographic processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes may combine photolithography and self-alignment processes, enabling structures to be created that have, for example, smaller pitches than what could otherwise be achieved using a single, direct photolithography process. In some embodiments, a sacrificial layer is formed and patterned over a substrate using a photolithography process.Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures. According to some embodiments, FIG. Fig. 5 shows the final patterning process for forming the fin structures, where hard mask structures 505 may be the remaining spacers arranged on Si epitaxial layer 125.

[0026] According to some embodiments, Fig. 6 shows the resulting fin structures 100 formed according to the process 410 described above. Additional fin structures 100 may be formed on the substrate 115 according to process 410 using additional hard mask structures. In some embodiments, the width and length of the hard mask structures 505 along the Y-axis and the X-axis define the width and length of the Fig. 6. Furthermore, the spacing between hard mask structures 505 defines the spacing between fin structures 100. Therefore, by controlling the dimensions of the hard mask structure 505, the dimensions of the fin structure 100 can be defined. In some embodiments, the width W' of the fin structures 100 after operation 410 is between about 7 nm and about 18 nm, which in Fig. 2 may be similar to or thicker than the Wb shown.

[0027] With reference to Fig. 4, method 400 continues with operation 415 and the process of depositing an insulating material between fin structures 100. Depositing the insulating material includes depositing a liner layer 600 over fin structures 100, as shown in Fig. 6. By way of example and not limitation, liner layer 600 serves as an adhesion layer for the insulating material. By way of example and not limitation, liner layer 600 may be deposited using a conformal deposition process, such as plasma-enhanced atomic layer deposition (PEALD), to a thickness between about 2 nm and 4 nm. By way of example and not limitation, liner layer 600 may be a silicon oxide or a silicon oxide-based dielectric material.

[0028] Subsequently, an insulating material 120 is deposited to surround fin structures 100, as shown in Fig. 6. In some embodiments, insulation material 120 is provided with a thickness of approximately three times the height H of the Fig. 1A. According to some embodiments, insulation material 120 is deposited via a flowable chemical vapor deposition process (e.g., flowable CVD) to ensure that insulation material 120 fills the space between fin structures 100 without forming seams or voids. In some embodiments, insulation material 120 is a silicon oxide-based dielectric material containing, for example, nitrogen or hydrogen. To further improve its dielectric and structural properties, insulation material 120 may be subjected to a wet vapor anneal (e.g., 100% water molecules) at a temperature between approximately 600°C and 1200°C. During the wet vapor anneal, insulation material 120 densifies and its oxygen content increases.

[0029] Subsequently, a chemical mechanical planarization (CMP) process polishes insulation material 120 until upper surfaces of the fin structures 100 are exposed. During the above-mentioned CMP process, the portions of the liner layer 600 on upper surfaces of the fin structures 100 are removed. A dry etching process "pulls back" (e.g., selective etching) the liner layer 600 and insulation material 120 to expose upper portions of the fin structures 100, as shown in Fig. 7. This is because the gas chemistry used in the etching process of the insulation material 120 is also selective towards the liner layer 600. In some embodiments, the etching process includes, but is not limited to, fluorocarbon chemistry. As a result of the aforementioned etching process, the upper portions of the fin structures 100 are exposed, while the lower portions remain embedded in insulation material 120. In some embodiments, insulation material 120 is etched such that the upper surface of the recessed insulation material 120 is spaced from the interface between the pedestal structure 110 and the Si epitaxial layer 125 by a vertical distance R. In some embodiments, vertical distance R is substantially the same as in Fig. 2 (e.g., between about 1 nm and 3 nm). In other words, insulation material 120 is etched to be approximately at the same level as the Fig. 2 shown width Wm to be.

[0030] With reference to Fig. 4, method 400 continues with operation 420 and the process of “trimming” (e.g., etching) the sidewalls of the silicon epitaxial layer 125 of the fin structures 100 that are not covered by insulation material 120—for example, by trimming the exposed portions of the fin structures 100. In some embodiments, trimming (e.g., etching) the sidewalls of the silicon epitaxial layer 125 comprises selectively depositing a silicon-based layer on silicon epitaxial layer 125, reflowing the silicon-based layer such that the silicon-based layer becomes thinner on top of the fin structures 100 and thicker toward the bottom of the fin structures 100, and then etching the silicon-based layer and the silicon epitaxial layer 125 to form an initial or first conical profile.

[0031] In some embodiments, the silicon-based layer is a silicon epitaxial layer that is selectively deposited on top and side surfaces of fin structures 100 in a conformal manner with a thickness between about 1 nm and about 2 nm. As a result, the silicon-based material does not grow on insulation material 120. In some embodiments, the two-step annealing process includes a pre-soak at a temperature between about 600°C and about 700°C for about 10 s to about 30 s, followed by a peak anneal at a temperature between about 800°C and about 1000°C for about 1 ms. The reflow process is configured to redistribute the silicon-based material onto fin structures 100. In some embodiments, about 0.5 nm to about 1 nm of the silicon-based material is redistributed between the top and bottom of fin structures 100.After the reflow process, the thickness of the silicon-based layer may be, for example, about 3 nm at the bottom of the fin structures 100 and about 1 nm at the top of the fin structures 100. . Fig. Figure 7 shows silicon-based layer 700 after the above-mentioned deposition and reflow processes.

[0032] A subsequent etching process, which selectively acts on silicon-based layer 700 and silicon epitaxial layer 125, begins to remove silicon-based layer 700. Due to the non-conformal distribution of the silicon-based layer 700 after the reflow process, the silicon epitaxial layer 125 at the top of the fin structures 100 is exposed to the etching chemistry faster than the silicon epitaxial layer 125 at the bottom of the fin structures 100, where the silicon-based layer 700 is thicker. Consequently, the upper portion of the fin structures 100 is exposed to the etching chemistry for a longer time than the lower portion. This intentional exposure time difference to the etching chemistry is responsible for the formation of an initial conical profile in fin structures 100. The resulting fin structures 100 are in Fig. 8. By way of example and without limitation, fin structures 100 develop rounded upper corners after the etching process, as in Fig. 8. Furthermore, the upper width W'' after the etching process is compared to that shown in Fig. 6 (e.g., W'' < W). In some embodiments, W'' may be the initial upper width W' shown in Fig. 1A shown W be substantially equal to or greater than these (e.g. W'' ≥ W).

[0033] In some embodiments, thicker silicon-based layers (e.g., thicker than about 2 nm) and longer reflow times can be used to create more pronounced conical profiles (e.g., conical bottom profiles with a larger width Wm). However, such conditions can significantly increase the overall processing time and manufacturing costs. On the other hand, thinner silicon-based layers (e.g., thinner than about 2 nm) may not produce the desired conical profile (e.g., the desired difference between the top and bottom widths).

[0034] In some embodiments, the thickness of the silicon-based layer and the reflow conditions (e.g., annealing time and temperature) can be used to adjust the thickness difference between the upper and lower sidewall covering of fin structures 100 and to produce the desired conical profile. In particular, the aforementioned processes can be used to Fig. 3. Furthermore, in some embodiments, operation 420 may be repeated to fine-tune the desired initial conical profile and top width for fin structures 100.

[0035] In some embodiments, the above-mentioned etching process comprises a combination of a wet etch and a dry etch. In some embodiments, the wet etching process is used for the main etch (e.g., to trim the fin structures 100), and the dry etching process is used to remove byproducts formed during the main etch. In some embodiments, the etching process removes between about 10% and 20% of the silicon epitaxial material from the fin structures 100 (e.g., between about 4 nm and about 7 nm). By way of example and without limitation, the wet etch chemistry may include dilute hydrochloric acid (dHF), ammonia hydroxide (NH4OH), and water. The dry etching process may, for example, include ozone (O3) plasma. In some embodiments, the wet etching process is isotropic to ensure etch uniformity from all directions during the main etch.

[0036] With reference to Fig. 4, method 400 continues with operation 425 and depositing an oxide layer on the trimmed fin structures 100. The oxide layer 900 may, for example, and with reference to Fig. 9 to cover top and sidewall surfaces of the trimmed fin structures 100 and top surfaces of the insulation material 120. By way of example and without limitation, oxide layer 900 may be a sacrificial gate oxide layer, such as a silicon oxide layer or a silicon oxynitride layer, having a thickness between about 2 nm and about 5 nm. Oxide layer 900 is replaced in a subsequent process with a gate dielectric stack including a material with a high dielectric constant (e.g., with a dielectric constant greater than about 3.9).

[0037] With reference to Fig. 4, method 400 continues with operation 430 and the process of performing an annealing process to form a second Fig. 10. In particular, the tempering process of operation 430 defines angles θ2 and θ3, which are Fig. 3. The reason for this is that during the annealing process of process 430, fin structures 100 are partially oxidized due to the availability of oxygen from oxide layer 900, lining layer 600 and insulation material 120, as shown in Fig. 9 by short black arrows 905 and long black arrows 910. Because the combined thickness of the liner layer 600 and the insulation material 120 is greater than the thickness of the oxide layer 900, more oxygen is available for oxidation for the portions of the fin structures 100 covered by the liner layer 600 and the insulation material 120 than for the portions of the fin structures 100 covered by the oxide layer 900. Therefore, portions of the fin structures 100 covered by the liner layer 600 and the insulation material 120 are more heavily oxidized than portions of the fin structures 100 covered by the oxide layer 900. Thus, more silicon material is consumed to form thicker oxide on portions of the fin structures 100 covered by liner layer 600 and insulation material 120 than on portions of the fin structures 100 covered by oxide layer 900.At the same time, insulation material 120 shrinks during the above-mentioned annealing process, as indicated by white arrows 915. This reduces the height of insulation material 120 and effectively removes insulation material 120 to accommodate the heat transfer medium. Fig. 10 shown conical bottom profile.

[0038] In some embodiments, the annealing process is similar to that discussed with reference to the reflow of the silicon-based layer 700 in operation 420. However, there are differences. In operation 430, for example, the temperature range for the peak anneal may be larger—for example, between about 700°C and about 1100°C according to some embodiments. Furthermore, the oxygen concentration during the annealing process in operation 430 is higher than in the annealing process described for operation 420. In some embodiments, partial oxidation of the fin structures 100 covered by liner layer 600 and insulation material 120 may also occur during the annealing process, as discussed above with reference to the reflow of the silicon-based layer 700 in operation 420. Similarly, insulation material 120 may also be omitted during the annealing process in operation 430.

[0039] Based on the above-mentioned oxidation process described for operation 430, portions of the oxide layer 900 are deposited on lower portions of the conical bottom profile 105, as indicated by the dashed circles 1000 in Fig. 10, are grown thicker than portions of the oxide layer 900 above the conical bottom profile 105. This is due to the presence of additional oxygen in the vicinity of the lining layer 600 and the insulation material 120, which enhances the oxidation reaction in this region. Simultaneously with the shrinkage of the insulation material 120 and the formation of the recesses relative to fin structures 100, the growth of the oxide layer 900 slows down because the oxygen source is removed by the recessing action of the insulation material 120. Therefore, the conical bottom profile 105 is formed by a combination of the etching and oxidation processes, as explained above.

[0040] According to some embodiments, the Fig. 3 can be modulated by the annealing conditions of process 430. Increasing the annealing temperature (e.g., setting the annealing temperature closer to about 1100°C) and / or the annealing time allows the oxide layer 900, for example, at the bottom of the fin structures 100 to continue to grow, as discussed above. A thicker oxide layer 900 means that there is greater consumption of the Si epitaxial layer 125 by fin structures 100, resulting in a larger θ2 and a larger width Wm and a narrower θ3. Conversely, an annealing temperature closer to about 700°C and / or shorter annealing times produce a thinner oxide layer and less consumption of the Si epitaxial layer 125, resulting in a smaller θ2 and a smaller width Wm and a wider θ3. Oxide layer 900 and lining layer 600 are Fig. 1A-1C, 2 and 3 not shown for ease of description.

[0041] In some embodiments, after operation 430, a sacrificial gate electrode 1005 is deposited on fin structures 100, as shown in Fig. 10. In some embodiments, the sacrificial gate electrode 1005 does not cover the entire length of the fin structures 100 along the X-direction. For example, the sacrificial gate electrode 1005 covers a central region of the fin structures 1005, leaving the rest of the fin structures 100 exposed. Furthermore, the width W of the fin structures 100 does not change significantly after operation 430. In some embodiments, the height of the fin structures 100 is successively reduced in operations 420 and 425 starting from operation 410 due to the etching and annealing processes described above.

[0042] In some embodiments, exposed areas of the fin structures 100 (e.g., portions of the fin structures 100 that are not covered by the sacrificial gate electrode 1005) are removed from the oxide layer 900 (e.g., via an etching process that is preferably selective toward the oxide layer 900) and, as shown in Fig. 11, a source / drain epitaxial structure 1100 is grown. In some embodiments, the source / drain epitaxial structure 1100 is a fused source / drain epitaxial structure formed by two or more epitaxial layers grown from each fin structure 100. During the final growth phases, the two or more epitaxial layers are allowed to fuse and the Fig. 11. In some embodiments, the source / drain epitaxial structure 1100 includes SiGe for p-type finFETs and carbon-doped Si (Si:C) for n-type finFETs.

[0043] Method 400 may also be used to form the Fig. 1B and Fig. 1C may be used. In operation 405, for example, a single SiGe epitaxial layer or SiGe epitaxial stack may be formed on n-type regions of the substrate 115 to form the SiGe fin structures shown in Fig. 1B and Fig.1C—which, as discussed above, are suitable for p-type finFETs. In some embodiments, SiGe epitaxial layer(s) is / are grown using a heteroepitaxial process using, for example, a CVD process. By way of example and without limitation, precursor gases used for growing the single SiGe epitaxial layer or epitaxial stack may include a combination of (i) SiH4, disaline (Si2H6), SiH2Cl2, germane (GeH4), or hydrochloric acid (HCl), and (ii) hydrogen (H2), nitrogen (N2), or argon (Ar). In some embodiments, a buffer layer (not shown) may be deposited prior to growing the SiGe epitaxial layer(s) to suppress growth defects due to lattice mismatch between the SiGe growth and underlying substrate 115.Furthermore, substrate 115 may be pretreated prior to growth of the SiGe epitaxial layer(s) to remove native oxide layers that have formed thereon.

[0044] By way of example and without limitation, the Ge concentration during growth can be modulated by the partial pressure of GeH4 and the partial pressure of other gases such as SiH4, Si2H6, and SiH2Cl2 during growth. For example, a higher partial pressure of GeH4 or a lower partial pressure of SiH4, Si2H6, or SiH2Cl2 during growth favors SiGe layers with a higher Ge concentration. A lower partial pressure of GeH4 or a higher partial pressure of SiH4, Si2H6, or SiH2Cl2 favors SiGe layers with a lower Ge concentration.

[0045] Various embodiments according to this disclosure describe a method for forming ultra-thin fins with a conical bottom profile for improved structural rigidity and desirable gate control properties. In some embodiments, ultra-thin Si and SiGe fins can be fabricated using the methods described herein. Furthermore, SiGe fins with a variable Ge concentration and a conical bottom profile can be formed in p-type finFETs for improved gate control over the channel. In some embodiments, the variable Ge concentration of the SiGe fin structures ranges from about 10% to about 35%, with higher Ge concentration toward the bottom of the fin structures. In some embodiments, the top width of the ultra-thin fin structures ranges between about 5 nm and about 15 nm, and the width of the conical bottom profile ranges between about 8 nm and about 20 nm.In some embodiments, a first conical profile is achieved by depositing and reflowing a silicon-based layer on the patterned fin structure, followed by trimming the fin structure using a combination of wet etching and dry etching processes. In some embodiments, the second conical profile is formed by depositing an oxide layer on the trimmed portions of the fin and subjecting the fin structure to an annealing process that oxidizes the lower portion of the fin structure more than the upper portion of the fin structure.

[0046] The invention relates to a semiconductor structure comprising a substrate comprising pedestal structures formed thereon and fin structures formed on the pedestal structures. The fin structure further includes a downwardly tapered portion having a lower width, a middle width, and an upper width, wherein the middle width is greater than the lower width and the upper width. The fin structure also includes an upper portion having a width substantially equal to or narrower than the upper width of the downwardly tapered portion. The semiconductor structure further includes an insulating material disposed between the pedestal structures.The mean width of the downwardly tapered section is formed by a sidewall angle of the downwardly tapered section, measured between a sidewall surface of the upper section and a sidewall surface of the downwardly tapered section, wherein the sidewall angle is in a range between about 10° and about 30°.

[0047] The invention further relates to a semiconductor structure comprising a substrate including pedestal structures formed thereon and fin structures formed on the pedestal structures. The fin structures further include a top portion and a downwardly tapered portion wider than the top portion, wherein each sidewall of the downwardly tapered portion is non-coplanar with sidewall surfaces of the top portion of the fin structure and sidewall surfaces of the pedestal structures. The semiconductor structure further includes an insulating material disposed between the pedestal structures.

[0048] Furthermore, the invention relates to a method comprising: depositing an epitaxial layer on a doped region of a substrate; patterning the epitaxial layer and the doped region to form a fin structure including an epitaxial layer portion and a doped region portion. The method further comprises forming an isolation region on the substrate such that an upper portion of the epitaxial layer portion overlies the isolation region; depositing a silicon-based layer on the upper portion of the epitaxial layer over the isolation region; annealing the silicon-based layer to reflow the silicon-based layer; and etching the silicon-based layer and the fin structure over the isolation region to form a first conical bottom profile in the fin structure over the isolation region.The method further comprises annealing the fin structure to form a second conical bottom profile below the first conical bottom profile and above the isolation region such that the first and second conical bottom profiles collectively form a bottom profile having a top width, a middle width, and a bottom width, the middle width being greater than each of the top and bottom widths.

Claims

[1] Semiconductor structure having: a substrate (115) having socket structures (110) formed thereon; Fin structures (100) formed on the base structures (110) and comprising: - a downwardly tapered portion (105) having a lower width (Wb), a middle width (Wm) and an upper width (Wt), the middle width (Wm) being greater than the lower width (Wb) and the upper width (Wt); and - an upper portion having a width substantially equal to or narrower than the upper width (Wt) of the downwardly tapered portion (105); and an insulating material (120) arranged between the base structures (110), wherein the mean width (Wm) of the downwardly tapered portion (105) is formed by a sidewall angle (θ1) of the downwardly tapered portion (105), measured between a sidewall surface of the upper portion and a sidewall surface of the downwardly tapered portion (105), the sidewall angle (θ1) being in a range between about 10° and about 30°. [2] The semiconductor structure of claim 1, wherein the fin structures (100) comprise a silicon epitaxial layer (125). [3] The semiconductor structure of claim 1, wherein the fin structures (100) comprise a silicon germanium epitaxial layer with varying germanium concentration between the top portion and the conical bottom portion (105). [4] The semiconductor structure of claim 3, wherein the upper portion has a germanium concentration gradient with a peak germanium concentration in a lower region of the upper portion. [5] A semiconductor structure according to claim 3 or 4, wherein the downwardly tapered portion (105) has a higher germanium concentration than the upper portion. [6] A semiconductor structure according to any one of the preceding claims, wherein the fin structures (100) comprise a stack of silicon germanium epitaxial layers (135, 140, 145), and wherein each silicon germanium epitaxial layer has a different germanium concentration. [7] A semiconductor structure according to any preceding claim, wherein the top width (Wt) is between about 5 nm and about 15 nm and the average width (Wm) is between about 8 nm and about 20 nm. [8] Semiconductor structure having: a substrate (115) having socket structures (110) formed thereon; Fin structures (100) formed on the pedestal structures (110) and comprising an upper portion and a downwardly tapered portion (105) wider than the upper portion, each sidewall of the downwardly tapered portion being non-coplanar with sidewall surfaces of the upper portion of the fin structure (100) and sidewall surfaces of the pedestal structures (110); and an insulating material (120) arranged between the base structures (110). [9] The semiconductor structure of claim 8, wherein a conical angle (θ1, θ2) between a sidewall of the downwardly tapered portion (105) and a sidewall surface of the upper portion is in a range between about 10° and 30°. [10] A semiconductor structure according to claim 8 or 9, wherein adjacent side walls of the downwardly conical bottom portion (15) form an angle (θ3) which is between about 120° and about 160°. [11] A semiconductor structure according to any one of the preceding claims 9 to 11, wherein the downwardly tapered portion (105) comprises: a height (B); an upper width (Wt); a mean width (Wm); and a lower width (Wb), where the middle width (Wm) is greater than each of the upper width (Wt) and the lower width (Wb). [12] The semiconductor structure of claim 11, wherein the average width (Wm) is in a range between about 8 nm and 20 nm. [13] A semiconductor structure according to claim 11 or 12, wherein the middle width (Wm) is greater than the upper width (Wt) and the lower width (Wb), wherein the lower width (Wb) is greater than the upper width (Wt). [14] A semiconductor structure according to any one of the preceding claims 11 to 13, wherein the average width (Wm) is arranged between about 1 nm and about 3 nm over the pedestal structures (110). [15] Semiconductor structure according to one of the preceding claims 11 to 14, wherein the height (B) of the downwardly conical portion (105) is between about 10% and about 20% of a height of the fin structures (100) [16] Procedure comprising: Depositing an epitaxial layer (135) on a doped region (500) of a substrate (115); Forming a fin structure (100) by patterning the epitaxial layer (135) and the doped region (500), the fin structure (100) having an epitaxial layer portion and a doped region portion; Forming an isolation region (120) on the substrate (115) such that an upper region of the epitaxial layer portion lies above the isolation region (120); Depositing a silicon-based layer (140) on the upper region of the epitaxial layer section above the isolation region (120); Annealing the silicon-based layer (140) to reflow the silicon-based layer (140); Forming a first downwardly conical profile in the fin structure (100) above the isolation region (120) by etching the silicon-based layer (140) and the fin structure (100) above the isolation region (120); and Forming a second downwardly conical profile below the first downwardly conical profile and above the insulation region (120) by annealing the fin structure (100), wherein the first downwardly tapered profile and the second downwardly tapered profile collectively form a lower profile (105) having an upper width (Wt), a middle width (Wm) and a lower width (Wb), and where the middle width (Wm) is greater than each of the upper width (Wt) and the lower width (Wb). [17] The method of claim 16, wherein annealing the silicon-based layer (140) comprises reflowing the silicon-based layer (140) such that a top cover of the silicon-based layer (140) on the fin structure (100) is thinner than a bottom cover of the silicon-based layer (140) on the fin structure (100). [18] The method of claim 16 or 17, wherein annealing the fin structure (100) comprises oxidizing the fin structure (100) covered by the isolation region (120) to form the second downwardly tapered profile.

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