Semiconductor components and semiconductor housings

Abstract

Semiconductor component comprising: a chip (2) having a mounting surface (5), a non-mounting surface (6) and a side wall (7a to 7D) connecting the mounting surface (5) and the non-mounting surface (6) and having an overhang section (10A to 10D) which extends further outwards on the side wall (7A to 7D) than the mounting surface (5);and a metal layer (21) covering the mounting surface (5), wherein the overhang section (10A to 10D) has an inner end section (12) arranged in a direction (Z) perpendicular to the mounting surface (5) on the side of the mounting surface (5), an outer end section (13) arranged in the direction (Z) on the side of the non-mounting surface (6), and a connecting section (14) connecting the inner end section (12) and the outer end section (13), and wherein the connecting section (14) has an inclined surface forming an obtuse angle with the side wall (7A to 7D) at the inner end section (12) and the outer end section (13).

Description

BACKGROUND OF THE INVENTION 1. Field of the invention The present invention relates to a semiconductor component. 2. Description of the state of the art Figure 9 of document JP 2011-249257A discloses a semiconductor package comprising a semiconductor device, a main package body, a die or chip pad, a terminal, and a conductive bonding material. The semiconductor device includes a chip and a back-surface electrode covering one rear surface of the chip. The semiconductor device is arranged on the die pad in an orientation such that the back-surface electrode faces the die pad. The conductive bonding material is positioned between the die pad and the back-surface electrode and bonds the semiconductor device to the die pad. Further semiconductor components are known from documents US 2015 / 0 249 133 A1, US 2018 / 0 204 786 A1 and DE 10 2013 112 797 A1. OVERVIEW OF THE INVENTION The present invention provides a semiconductor component according to claim 1, comprising a chip that includes a mounting surface, a non-mounting surface and a side wall connecting the mounting surface and the non-mounting surface, and which has an overhang portion that projects further outwards on the side wall than the mounting surface, and which has a metal layer covering the mounting surface. The present invention further provides a semiconductor component according to claim 11, comprising a chip having a laminated structure, including a semiconductor substrate and an epitaxial or epitaxial layer, having a mounting surface on the side of the semiconductor substrate, having a non-mounting surface on the side of the epitaxial layer, having a side wall formed by the semiconductor substrate and the epitaxial layer, having an overhang section that projects further outwards than the mounting surface on a section of the side wall formed by the semiconductor substrate, and having a metal layer covering the mounting surface. The aforementioned and further tasks, features and effects of the present invention will become clearer from the following description of the preferred embodiments, which is given below, with reference to the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a perspective view of a semiconductor device according to a preferred embodiment of the present invention. Fig. 2 is a perspective view showing the semiconductor device shown in Fig. 1 from a different direction. Fig. 3 is a perspective view of a chip shown in Fig. 1. Fig. 4 is a sectional view of the semiconductor device shown in Fig. 1. Fig. 5 is an enlarged view of region V shown in Fig. 4. Fig. 6 is an enlarged view of region VI shown in Fig. 4. Fig. 7 is a top view of a structure on one side of a non-mounting area of ​​the semiconductor device shown in Fig. 1. Fig. 8 is a diagram of an electrical configuration of the semiconductor device shown in Fig. 1. Fig. 9 is a top view of a structure of a power MISFET shown in Fig. 8.Figure 10 is a sectional view along a line XX shown in Figure 9. Figure 11 is a perspective view of a semiconductor package containing the semiconductor device shown in Figure 1, through the main body of the package. Figure 12 is a sectional view of a bonded state of the semiconductor device shown in Figure 11. Figures 13A to 13L are sectional views illustrating an example of a method for fabricating the semiconductor device shown in Figure 1. Figures 14A to 14G are sectional views of steps according to Figure 13G and are sectional views illustrating the method for fabricating the semiconductor device shown in Figure 1 in greater detail. Figures 15A and 15B are sectional views of steps according to Figure 14F and are sectional views to describe a further method for cutting or separating a wafer. Figure 16 corresponds to Figure 14F.4 and is a sectional view of the semiconductor component produced by the steps of Fig. 15A and Fig. 15B. DETAILED DESCRIPTION OF PREFERRED EXECUTION FORMS A preferred embodiment of the present invention provides a semiconductor component capable of suppressing the flowing around of a conductive bonding material from a mounting surface to a non-mounting surface. A preferred embodiment of the present invention provides a semiconductor device comprising a chip that includes a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface, and which includes an overhang portion that projects further outward from the side wall than the mounting surface and which contains a metal layer covering the mounting surface. According to the present semiconductor device, the overhang portion can suppress the flow of a conductive bonding material from the mounting surface to the non-mounting surface. A preferred embodiment of the present invention provides a semiconductor device comprising a chip having a laminated structure, including a semiconductor substrate and an epitaxial layer, a mounting surface on the side of the semiconductor substrate, a non-mounting surface on the side of the epitaxial layer, a side wall formed by the semiconductor substrate and the epitaxial layer, and an overhang section that projects further outward from a portion of the side wall formed by the semiconductor substrate than the mounting surface, and a metal layer covering the mounting surface. According to the present semiconductor device, the overhang section can suppress the flow of a conductive bonding material from the mounting surface to the non-mounting surface. Preferred embodiments of the present invention are described in detail below with reference to the accompanying drawing. Fig. 1 is a perspective view of a semiconductor device 1 according to a preferred embodiment of the present invention. Fig. 2 is a perspective view in which the semiconductor device 1 shown in Fig. 1 is viewed from a different direction. Fig. 3 is a perspective view of a chip 2 shown in Fig. 1. Fig. 4 is a sectional view of the semiconductor device 1 shown in Fig. 1. Fig. 5 is an enlarged view of region V shown in Fig. 4. Fig. 6 is an enlarged view of region VI shown in Fig. 4. With reference to Figures 1, 2, 3, 4, 5 to 6, the semiconductor device 1 includes a silicon chip 2. In Figures 1, 2, 3, 4, 5 to 6, the chip 2 is shown with dimensions that differ from its actual dimensions in order to clarify the structure of the chip 2 (the same applies to the subsequent figures and drawings). In this embodiment, the chip 2 has a laminated structure comprising a substrate 3 and an epitaxial layer 4. In this embodiment, one conductivity type of the substrate 3 and one conductivity type of the epitaxial layer 4 are both of the n type. The n-type impurity concentration of substrate 3 may be no less than 1 × 10¹⁸ cm⁻³ and no greater than 1 × 10²¹ cm⁻³. Epitaxial layer 4 has an n-type impurity concentration that is lower than the n-type impurity concentration of substrate 3. The n-type impurity concentration of epitaxial layer 4 may be no less than 1 × 10¹⁵ cm⁻³ and no greater than 1 × 10¹⁸ cm⁻³. The thickness of substrate 3 may be no less than 50 µm and no greater than 450 µm. Alternatively, the thickness of substrate 3 may be no less than 50 µm and no greater than 150 µm, no less than 150 µm and no greater than 250 µm, no less than 250 µm and no greater than 350 µm, or no less than 350 µm and no greater than 450 µm. By making substrate 3 thinner, the resistance of chip 2 can be reduced. The thickness of substrate 3 is adjusted by looping. The epitaxial layer 4 has a thickness that is less than that of the substrate 3. The thickness of the epitaxial layer 4 is optionally not less than 5 µm and optionally not greater than 50 µm. The thickness of the epitaxial layer 4 is optionally not less than 5 µm and not greater than 10 µm, optionally not less than 10 µm and not greater than 20 µm, optionally not less than 20 µm and not greater than 30 µm, optionally not less than 30 µm and not greater than 40 µm, or optionally not less than 40 µm and not greater than 50 µm. The thickness of the epitaxial layer 4 is preferably not less than 10 µm and preferably not greater than 30 µm. The chip 2 has a mounting surface 5 on one side, a non-mounting surface 6 on the other side, and four side walls 7A to 7D that connect the mounting surface 5 and the non-mounting surface 6. The mounting surface 5 is an outer surface (facing a connection object) that faces the semiconductor component 1 when it is to be connected to the connection object. The mounting surface 5 is formed by the substrate 3. The non-mounting surface 6 is formed by the epitaxial layer 4. The side walls 7A to 7D are each formed by the substrate 3 and the epitaxial layer 4. The mounting surface 5 is formed in a four-sided shape when viewed from a normal direction Z to the mounting surface 5 (hereinafter simply referred to as the "top view"). In this embodiment, the mounting surface 5 is formed in a square shape. The mounting surface 5 can also be formed in a rectangular shape. The mounting surface 5 has a first area S1. The non-mounting surface 6 is formed in a four-sided shape in plan view. In this embodiment, the non-mounting surface 6 is formed in a square shape. The non-mounting surface 6 can also be formed in a rectangular shape. The non-mounting surface 6 has a second area S2, which is larger than the first area S1 of the mounting surface 5 (S1 < S2). The non-mounting surface 6 preferably has a planar shape, similar to the planar shape of the mounting surface 5. The non-mounting surface 6 projects further outwards along the plane directions (tangential directions) of the mounting surface 5 than the mounting surface 5. In this embodiment, the non-mounting surface 6 projects further outwards than the mounting surface 5 over its entire circumference. The non-mounting surface 6 is a component surface on which a functional component is formed. The side walls 7A to 7D comprise, more precisely, the first side wall 7A, the second side wall 7B, the third side wall 7C, and the fourth side wall 7D. The first side wall 7A and the second side wall 7B extend along a first direction X and each point in a second direction Y that intersects the first direction X. The third side wall 7C and the fourth side wall 7D each extend along the second direction Y and each point in the first direction X. More precisely, the second direction Y is orthogonal to the first direction X. The length of each side wall 7A to 7D is not less than 0.5 mm and not greater than 2 mm. The side walls 7A to 7D each have overhang sections 10A to 10D in regions between the mounting surface 5 and the non-mounting surface 6. These overhang sections project further outwards along the plane directions (tangential directions) of the mounting surface 5 than the mounting surface 5 itself. The overhang sections 10A to 10D face the non-mounting surface 6, are opposite it, or are adjacent to it in the normal direction Z. The overhang sections 10A to 10D are formed by cut-out or notched sections 11, in which circumferential edge sections of the mounting surface 5 are cut or notched in the direction towards the non-mounting surface 6. More precisely, overhang sections 10A to 10D include a first overhang section 10A, a second overhang section 10B, a third overhang section 10C and a fourth overhang section 10D. The first overhang section 10A is formed in the first side wall 7A. The first overhang section 10A is formed as a band that extends in the first side wall 7A along the first direction X. The first overhang section 10A extends in a direction parallel to the mounting surface 5 (the non-mounting surface 6). The first overhang section 10A extends in the first side wall 7A from a corner portion on the side of the third side wall 7C to an edge portion on the side of the fourth side wall 7D. The second overhang section 10B is formed in the second side wall 7B. The second overhang section 10B is formed as a band extending along the first direction X in the second side wall 7B. The second overhang section 10B extends in a direction parallel to the mounting surface 5 (the non-mounting surface 6). The second overhang section 10B extends in the second side wall 7B from an edge section on the side of the third side wall 7C to an edge section on the side of the fourth side wall 7D. The third overhang section 10C is formed in the third side wall 7C. The third overhang section 10C is formed as a band extending along the second direction Y in the third side wall 7C. The third overhang section 10C extends in a direction parallel to the mounting surface 5 (the non-mounting surface 6). The third overhang section 10C extends in the third side wall 7C from an edge section on the side of the first side wall 7A to an edge section on the side of the second side wall 7B. The third overhang section 10C transitions continuously into the first overhang section 10A at the edge section on the side of the first side wall 7A. The third overhang section 10C transitions continuously into the second overhang section 10B at the edge section on the side of the second side wall 7B. The fourth overhang section 10D is formed in the fourth side wall 7D. The fourth overhang section 10D is formed as a band extending along the second direction Y in the fourth side wall 7D. The fourth overhang section 10D extends in a direction parallel to the mounting surface 5 (the non-mounting surface 6). The fourth overhang section 10D extends in the fourth side wall 7D from an edge section on the side of the first side wall 7A to an edge section on the side of the second side wall 7B. The fourth overhang section 10D transitions continuously into the first overhang section 10A at the edge section on the side of the first side wall 7A. The fourth overhang section 10D transitions continuously into the second overhang section 10B at the edge section on the side of the second side wall 7B. The overhang sections 10A to 10D thus extend over the entire circumference of the chip 2. Furthermore, the overhang sections 10A to 10D form a single overhang section that extends in a ring shape in a top view (a four-sided ring shape in this embodiment). The overhang sections 10A to 10D each extend from the non-mounting surface 6 at intervals towards the side of the mounting surface 5. Preferably, the overhang sections 10A to 10D are each formed on the substrate 3. It is particularly preferred if the overhang sections 10A to 10D are each formed on the substrate 3 at intervals from the epitaxial layer 4. This allows variations in the physical and electrical properties of the epitaxial layer 4 due to the overhang sections 10A to 10D to be suppressed, and consequently, variations in the electrical characteristics of the functional component formed in the epitaxial layer 4 can be suitably suppressed. The overhang sections 10A to 10D do not necessarily have to be formed at the same depth. At least one of the overhang sections 10A to 10D can be offset or displaced in the normal direction Z relative to the other overhang sections 10A to 10D. Referring to Figures 3 and 4, each of the overhang sections 10A to 10D has an inner end section 12 on the side of the mounting surface 5, an outer end section 13 on the side of the non-mounting surface 6, and a connecting section 14 that joins the inner end section 12 and the outer end section 13, as shown in a top view. In this embodiment, the outer end section 13 is positioned perpendicular to the inner end section 12 in the direction Z on the side of the non-mounting surface 6. As a result, the connecting section 14 has an inclined surface that slopes from the inner end section 12 towards the outer end section 13. The connecting section 14 can extend flat, planar, or in a straight line between the inner end section 12 and the outer end section 13.The connecting section 14 can be formed in a curved shape, which is excluded or set back between the inner end section 12 and the outer end section 13 towards the side of the non-mounting surface 6. The outer end section 13 can be positioned on the same plane as the inner end section 12. The connecting section 14 can extend in a direction parallel to the mounting surface 5 and the non-mounting surface 6. The side walls 7A to 7D each have first connecting walls 15A to 15D, which connect the mounting surface 5 and the inner end sections 12 of the overhang sections 10A to 10D, and second connecting walls 16A to 16D, which connect the non-mounting surface 6 and the outer end sections 13 of the overhang sections 10A to 10D. The cut-out sections 11 mentioned above are formed by the overhang sections 10A to 10D and the first connecting walls 15A to 15D and are recessed or cut away from the mounting surface 5 in the direction of the non-mounting surface 6. The first connecting walls 15A to 15D are formed by the substrate 3. The first connecting walls 15A to 15D are formed at an angle that differs from that of the overhang sections 10A to 10D. The first connecting walls 15A to 15D can extend along a direction perpendicular to the mounting surface 5, in regions between the circumferential edges of the mounting surface 5 and the inner end sections 12 of the overhang sections 10A to 10D. If the inner end sections 12 of the overhang sections 10A to 10D are positioned further outwards than the perimeter edges of the mounting surface 5, the first connecting walls 15A to 15D can be inclined upwards from the perimeter edges of the mounting surface 5 towards the inner end sections 12 of the overhang sections 10A to 10D. If the inner end sections 12 of the overhang sections 10A to 10D are positioned further inwards than the perimeter edges of the mounting surface 5, the first connecting walls 15A to 15D can be inclined downwards from the inner end sections 12 of the overhang sections 10A to 10D towards the perimeter edges of the mounting surface 5. The second connecting walls 16A to 16D are formed by the substrate 3 and the epitaxial layer 4. The second connecting walls 16A to 16D are formed at an angle that differs from that of the overhang sections 10A to 10D. The second connecting walls 16A to 16D can extend along a direction perpendicular to the non-mounting surface 6, in regions between the circumferential edges of the non-mounting surface 6 and the outer end sections 13 of the overhang sections 10A to 10D. The second connecting walls 16A to 16D can be formed by ground surfaces (separated or cut surfaces) that have grinding marks. If the outer end sections 13 of the overhang sections 10A to 10D are positioned further outwards than the perimeter edges of the non-mounting surface 6, the second connecting walls 16A to 16D can be inclined downwards from the perimeter edges of the non-mounting surface 6 towards the outer end sections 13 of the overhang sections 10A to 10D. If the outer end sections 13 of the overhang sections 10A to 10D are positioned further inwards than the perimeter edges of the non-mounting surface 6, the second connecting walls 16A to 16D can be inclined upwards from the outer end sections 13 of the overhang sections 10A to 10D towards the perimeter edges of the non-mounting surface 6. The thickness T of the second connecting walls 16A to 16D may, under the condition that it exceeds the thickness of the epitaxial layer 4, be no less than 10 µm and no greater than 200 µm. The thickness T may be no less than 10 µm and no greater than 50 µm, no less than 50 µm and no greater than 100 µm, no less than 100 µm and no greater than 150 µm, or no less than 150 µm and no greater or thicker than 200 µm. The width WE of the overhang sections 10A to 10D may be not less than 10 µm and not greater than 100 µm. The width WE is a width in a direction orthogonal to the direction in which the overhang sections 10A to 10D extend in a plan view. The width WE may be not less than 10 µm and not greater than 20 µm, not less than 20 µm and not greater than 40 µm, not less than 40 µm and not greater than 60 µm, not less than 60 µm and not greater than 80 µm, or not less than 80 µm and not greater than 100 µm. Preferably, the width WE is not less than 20 µm and not greater than 60 µm. The chip 2 thus has a hammerhead structure, with a body section 17 and a head section 18. In Fig. 1 and Fig. 2, the head section 18 is represented by hatching. The body section 17 includes the mounting surface 5 and the first connecting walls 15A to 15D. The head section 18 includes the non-mounting surface 6, the overhang sections 10A to 10D, and the second connecting walls 16A to 16D. The overhang sections 10A to 10D suppress the flow of a conductive bonding material 104 (see Fig. 11 and Fig. 12, which are described below), which is composed of a solder or metal paste, from the side of the mounting surface 5 to the side of the non-mounting surface 6 when the semiconductor component 1 is bonded to a connection object. The semiconductor component 1 includes a first metal layer 21 that covers the mounting surface 5. The first metal layer 21 covers the entire mounting surface 5. The first metal layer 21 is formed as a bond layer, which is bonded to the interconnect via the conductive bonding material 104. The first metal layer 21 can have a laminated structure in which a plurality of metal layers are laminated on top of each other, or it can have a single-layer structure that is built up or produced from a single metal layer. The first metal layer 21 preferably has an outer surface formed by a metal with an affinity (wetting property) with respect to the conductive bonding material 104 that is higher than that of the chip 2 (silicon). The first metal layer 21 preferably has an outer surface that includes a noble metal. In this embodiment, the first metal layer 21 has a laminated structure comprising a Ti layer 22, a Ni layer 23, an Au layer 24, a Pd layer 25, and an Ag layer 26, which are laminated in that order starting from the side of the mounting surface 5. The Ti layer 22 is formed as an ohmic electrode with respect to the chip 2 (substrate 3). The first metal layer 21 does not necessarily have to include all layers of the Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26. The first metal layer 21 can have a laminated structure that includes the Ti layer 22, the Ni layer 23, the Au layer 24, and the Ag layer 26. The first metal layer 21 can have a laminated structure that includes the Ti layer 22, the Ni layer 23, and the Au layer 24. The first metal layer 21 can have a single-layer structure that is formed from the Ti layer 22 or from the Au layer 24. The semiconductor device 1 includes a second metal layer 27 (sidewall metal layer) that covers the sidewalls 7A to 7D, extending from the non-mounting surface 6 towards the side of the mounting surface 5. More precisely, the second metal layer 27 on sidewalls 7A to 7D covers a region between the mounting surface 5 and the second interconnection walls 16A to 16D, such that the second interconnection walls 16A to 16D are exposed. That is, the second metal layer 27 exposes the epitaxial layer 4. Variations in the electrical properties of the epitaxial layer 4 due to the second metal layer 27 can thus be suppressed, and consequently, variations in the electrical properties or characteristics of the functional component formed in the epitaxial layer 4 can be suppressed. The second metal layer 27 is formed as a film along the first connecting walls 15A to 15D and the overhang sections 10A to 10D. The second metal layer 27 forms overhang sections that correspond to the overhang sections 10A to 10D on the side walls 7A to 7D of the chip 2. More precisely, the second metal layer 27 includes a first covering section 28, which covers the first connecting walls 15A to 15D, and a second covering section 29, which covers the overhang sections 10A to 10D. The first connecting walls 15A to 15D transition continuously into the first metal layer 21 on the side of the mounting surface 5. The second covering section 29 transitions continuously into the first covering section 28 on the sides of the first connecting walls 15A to 15D. The second covering section 29 includes an exposed section 30, which is exposed opposite the second connecting walls 16A to 16D. In Fig. 1 and Fig. 2, the exposed section 30 is shown by hatching. The exposed section 30 transitions continuously into the second connecting walls 16A to 16D. More precisely, the exposed section 30 is flush with the second connecting walls 16A to 16D. Even more precisely, the exposed section 30 of the second covering section 29 forms a single ground surface (cut or separated surface) together with the second connecting walls 16A to 16D. The second metal layer 27 acts as a heat sink, absorbing heat generated at the chip 2 from the sides of the sidewalls 7A to 7D, and simultaneously acts as a bond layer, bonded to the interconnect via the conductive bonding material 104. The second metal layer 27 can have a laminated structure, in which multiple metal layers are laminated on top of each other, or it can have a single-layer structure, consisting of a single metal layer. The second metal layer 27 preferably has an outer surface formed by a metal with an affinity (wetting property) with respect to the conductive bonding material 104 that is higher than that of the chip 2 (silicon). The second metal layer 27 preferably has an outer surface comprising a noble metal. In this embodiment, the second metal layer 27 has the same structure as the first metal layer 21 and is integrally formed with the first metal layer 21. That is, the second metal layer 27 has the laminated structure comprising the Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26, which are laminated in that order starting from the sides of the sidewalls 7A to 7D. The second metal layer 27 need not necessarily include all layers of the Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26. If the first metal layer 21 has the laminated structure that includes the Ti layer 22, the Ni layer 23, the Au layer 24, and the Ag layer 26, the second metal layer 27 preferably has the laminated structure that includes the Ti layer 22, the Ni layer 23, the Au layer 24, and the Ag layer 26. If the first metal layer 21 has the laminated structure comprising the Ti layer 22, the Ni layer 23, and the Au layer 24, the second metal layer 27 preferably has the laminated structure comprising the Ti layer 22, the Ni layer 23, and the Au layer 24. If the first metal layer 21 has the single-layer structure formed from the Ti layer 22 or from the Au layer 24, the second metal layer 27 preferably has the single-layer structure formed from the Ti layer 22 or from the Au layer 24. The mounting surface 5, the overhang sections 10A to 10D, and the first connecting walls 15A to 15D are preferably formed from rough surfaces having a predetermined arithmetic mean roughness Ra. The mounting surface 5, the overhang sections 10A to 10D, and the first connecting walls 15A to 15D may be roughened by a roughening etching process. The arithmetic mean roughness (Ra) may exceed 0 nm and may not exceed 1000 nm. The arithmetic mean roughness (Ra) may exceed 0 nm and not exceed 200 nm, or may not exceed 200 nm and not exceed 400 nm, or may not exceed 400 nm and not exceed 600 nm, or may not exceed 600 nm and not exceed 800 nm, or may not exceed 800 nm and not exceed 1000 nm. In this case, the first metal layer 21 covers the roughened mounting surface 5. This increases the adhesive force of the first metal layer 21 on the mounting surface 5 and thus effectively prevents peeling or detachment of the first metal layer 21 from the mounting surface 5. Similarly, the second metal layer 27 covers the roughened overhang sections 10A to 10D and the first connecting walls 15A to 15D. This also increases the adhesive force of the second metal layer 27 on the overhang sections 10A to 10D and the first connecting walls 15A to 15D, thus effectively preventing peeling or detachment of the second metal layer 27 from the overhang sections 10A to 10D and the first connecting walls 15A to 15D. On the other hand, the second connecting walls 16A to 16D preferably differ in their appearance from the overhang sections 10A to 10D and the first connecting walls 15A to 15D. In this case, the second connecting walls 16A to 16D are preferably produced from ground surfaces (separated or cut surfaces) that have grinding marks. The semiconductor component 1 includes an interlayer insulating layer 31 that covers the non-mounting area 6. In Figures 1 and 2, the interlayer insulating layer 31 is represented by hatching. The circumferential edges of the interlayer insulating layer 31 are exposed relative to the second connecting walls 16A to 16D. In this embodiment, the circumferential edges of the interlayer insulating layer 31 transition continuously into the second connecting walls 16A to 16D. More precisely, the circumferential edges of the interlayer insulating layer 31 are flush with the second connecting walls 16A to 16D. Even more precisely, the circumferential edges of the interlayer insulating layer 31 together with the second connecting walls 16A to 16D form a single ground surface (cut or separated surface). The intermediate insulating layer 31 covers substantially the entire non-mounting area 6. The intermediate insulating layer 31 can contain at least one of the following materials: undoped silicon dioxide glass (USG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG), with silicon dioxide being an example. The intermediate insulating layer 31 has a single-layer structure formed from a USG layer. The intermediate insulating layer 31 can have a flattened main surface. The main surface of the intermediate insulating layer 31 can be formed from a ground surface with grinding marks or grinding traces. The semiconductor component 1 includes a plurality of electrodes 32 (five in this embodiment) formed on the non-mounting surface 6. Each of the plurality of electrodes 32 is formed on the intermediate insulating layer 31. Each of the plurality of electrodes 32 is formed as a terminal electrode, which is externally connected by lead wires (for example, bond wires), etc. The number, configuration, and plane shapes of the plurality of electrodes 32 are arbitrary and are not limited to those shown in Fig. 1, etc. The plurality of electrodes 32 can each include at least one type of layer consisting of a Ti layer, a TiN layer, an Al layer, a Cu layer, an AlSi layer, an AlCu layer, an AlSiCu layer, a Ni layer, an Au layer, a Pd layer and an Ag layer. The semiconductor device 1 includes an upper insulating layer 33 that covers the intermediate insulating layer 31. The upper insulating layer 33 has a plurality of pad openings 34, each exposing a plurality of electrodes 32. The plane shapes of the plurality of pad openings 34 are arbitrary. The circumferential edges of the upper insulating layer 33 can be formed with inwardly directed or offset distances from the first connecting walls 15A to 15D, as seen in a top view. The circumferential edges of the upper insulating layer 33 can be positioned in regions between the first connecting walls 15A to 15D and the second connecting walls 16A to 16D, as seen in a top view. The circumferential edges of the upper insulating layer 33 are formed with gaps or intervals in plan view, and are directed inwards with respect to the second connecting walls 16A to 16D. The circumferential edges of the upper insulating layer 33, together with the second connecting walls 16A to 16D, demarcate or delimit a dicing street 35. The dicing street 35 is formed as a band extending along the second connecting walls 16A to 16D. More precisely, the dicing street 35 is formed in a ring shape (a four-sided ring shape in this embodiment) that surrounds the upper insulating layer 33. The width WD of the separating section 35 is not less than 1 µm and not greater than 100 µm. The width WD is a width in a direction orthogonal to the direction in which the separating section 35 extends. The width WD is not less than 1 µm and not greater than 25 µm, not less than 25 µm and not greater than 50 µm, not less than 50 µm and not greater than 75 µm, or not less than 75 µm and not greater than 100 µm. The separation line 35 eliminates the need to physically cut or separate the upper insulating layer 33 when separating or singulating the semiconductor component 1 from a wafer 111 (see Figures 13A to 13L, described below). This allows the semiconductor component 1 to be easily separated or singulated from the wafer 111. Furthermore, the occurrence of fractures in the chip 2 (especially of the second interconnect walls 16A to 16D) due to peeling or deterioration of the upper insulating layer 33 can be suppressed. The chip 2, which has the overhang sections 10A to 10D, can thus be formed appropriately. Referring to Fig. 4, the upper insulating layer 33 in this embodiment has a laminated structure comprising a passivation layer 36 and a resin layer 37, which are laminated in this order starting from the side of the non-mounting surface 6. The passivation layer 36 preferably comprises an insulating material that differs from that of the intermediate insulating layer 31. In this embodiment, the passivation layer 36 is formed from a silicon nitride layer. The passivation layer 36 is formed as a film along the intermediate insulating layer 31 and the plurality of electrodes 32. The passivation layer 36 has a plurality of first openings 38 that expose respective sections of the plurality of electrodes 32. The plane shapes of the plurality of first openings 38 are arbitrary. The thickness of the passivation layer 36 may be no less than 0.1 µm and no greater than 20 µm. The thickness of the passivation layer 36 may be no less than 0.1 µm and no greater than 1 µm, no less than 1 µm and no greater than 5 µm, no less than 5 µm and no greater than 10 µm, no less than 10 µm and no greater than 15 µm, or no less than 15 µm and no greater than 20 µm. The resin layer 37 is formed as a film along a major surface of the passivation layer 36. The resin layer 37 can contain a photosensitive resin. The photosensitive resin can be of a negative or a positive type. The resin layer 37 can contain at least one polyimide, one polyamide, and one polybenzoxazole. In this embodiment, the resin layer 37 contains polybenzoxazole. In this embodiment, the circumferential edges of the resin layer 37 expose the circumferential edges of the passivation layer 36. The circumferential edges of the upper insulating layer 33 are formed by the resin layer 37 and by the passivation layer 36. Optionally, the resin layer 37 can cover the circumferential edges of the passivation layer 36. The resin layer 37 has a plurality of secondary openings 39 that expose respective sections of the plurality of electrodes 32. The plane configurations of the plurality of secondary openings 39 are arbitrary. Each secondary opening 39 communicates with a corresponding primary opening 38 and, together with the corresponding primary opening 38, forms a single pad opening 34. The inner walls of the respective second openings 39 can be flush with the inner walls of the respective first openings 38. The inner walls of the respective second openings 39 can be positioned on the outer sides of the respective first openings 38. That is, the resin layer 37 may, if necessary, expose the inner walls of the respective first openings 38. The inner walls of the respective second openings 39 may, if necessary, be positioned on the inner sides of the respective first openings 38. That is, the resin layer 37 may, if necessary, cover the inner walls of the respective first openings 38. The thickness of the resin layer 37 may be no less than 1 µm and no greater than 50 µm. The thickness of the resin layer 37 may be no less than 1 µm and no greater than 10 µm, no less than 10 µm and no greater than 20 µm, no less than 20 µm and no greater than 30 µm, no less than 30 µm and no greater than 40 µm, or no less than 40 µm and no greater than 50 µm. Fig. 7 is a top view of the structure of the non-mounting surface 6 of the semiconductor device 1 shown in Fig. 1. Fig. 7 is a schematic view and the upper insulating layer 33 is omitted. Referring to Fig. 7, the non-mounting surface 6 includes an output region 41 and an input region 42. The output region 41 and the input region 42 are formed in a region on the side of the third side wall 7C. The input region 42 and the output region 41 are formed in a region on the side of the fourth side wall 7D. The area of ​​the output region 41 is preferably not smaller than the area of ​​the input region 42. The planar shape of the input region 42 and the planar shape of the output region 41 are arbitrary and are not limited to specific shapes. The output region 41 includes a power MISFET (metal insulator-semiconductor field-effect transistor) 43 as an example of a functional component. The power MISFET 43 includes a gate, a drain, and a source. This means that the substrate 3 is formed as a drain region 44 of the power MISFET 43. Furthermore, the epitaxial layer 4 is formed as a drift region 45 of the power MISFET 43. Additionally, the first metal layer 21 and the second metal layer 27 are formed as a drain electrode 46 of the power MISFET 43. The input region 42 includes a control circuit 47 as an example of a functional component. The control circuit 47 comprises a variety of functional circuit types that implement different functions. Among these functional circuit types is a circuit that generates a gate signal which drives and controls the power MISFET 43 based on an external electrical signal. The control circuit 47, together with the power MISFET 43, forms an intelligent power device (IPD). The IPD is also referred to as an intelligent power module (IPM). The semiconductor device 1 includes a region separation structure 48 that electrically separates the output region 41 and the input region 42. In Fig. 7, the region separation structure 48 is indicated by hatching. Although a specific description is omitted, the region separation structure 48 can have a trench insulation structure in which an insulator is embedded in a trench. The region separation structure 48 can include a conductor embedded in the trench via the insulator. In this case, the conductor is preferably source-grounded. The exit region 41, the entry region 42, and the region separation structure 48 are formed within a region that, in plan view, is surrounded by the overhang sections 10A to 10D (first connecting walls 15A to 15D). That is, the functional components are formed within the region that, in plan view, is surrounded by the overhang sections 10A to 10D (first connecting walls 15A to 15D). In this embodiment, the plurality of electrodes 32 includes a source electrode 49, an input electrode 50, a reference voltage electrode 51, an enable electrode 52, and a sense electrode 53. The source electrode 49 is formed on the output region 41. The input electrode 50, the reference voltage electrode 51, the enable electrode 52, and the sense electrode 53 are each formed on the input region 42. The source electrode 49 transmits a source voltage to the source of the power MISFET 43. The input electrode 50 transmits an input voltage to drive the control circuit 47. The reference voltage electrode 51 transmits a reference voltage (for example, a ground voltage) to the power MISFET 43 and the control circuit 47. The enable electrode 52 transmits an electrical signal to enable or disable a section or all of the functions of the control circuit 47. The detect electrode 53 transmits an electrical signal to detect an abnormality of the control circuit 47. The semiconductor device 1 includes a gate wiring 54 formed on the interlayer insulating layer 31. The gate wiring 54 is selectively routed to the output region 41 and to the input region 42. The gate wiring 54 is electrically connected to the gate of the power MISFET 43 in the output region 41 and to the control circuit 47 in the input region 42. The gate wiring 54 transmits a gate signal generated by the control circuit 47 to the gate of the power MISFET 43. Fig. 8 is a diagram of an electrical configuration of the semiconductor device 1 shown in Fig. 1. Although an embodiment example is described below in which the semiconductor device 1 is a high-side switching device, the semiconductor device 1 is not limited to a high-side switching device. The semiconductor device 1 can also be provided as a low-side switching device by adjusting an electrical connection configuration and functions of the control circuit 47. Referring to Fig. 8, the drain electrode 46 is connected to a power supply. The drain electrode 46 provides a power supply voltage VB for the power MISFET 43 and the control circuit 47. The power supply voltage VB is not less than 10 V and not greater than 20 V. The source electrode 49 is connected to a load. The input electrode 50 can be connected to an MCU (microcontroller unit), a DC / DC converter, an LDO (low dropout), etc. The input electrode 50 provides the input voltage for the control circuit 47. The input voltage may be no less than 1 V and no greater than 10 V. The reference voltage electrode 51 is connected to a reference voltage wiring. The reference voltage electrode 51 provides the reference voltage for the power MISFET 43 and the control circuit 47. The enable electrode 52 can be connected to the MCU. The detect electrode 53 can be connected to a resistor. The gate of the power MISFET 43 is connected via the gate wiring 54 to the control circuit 47 (a gate control circuit 59, which is described below). The drain of the power MISFET 43 is connected to the drain electrode 46. The source of the power MISFET 43 is connected to the control circuit 47 (a current sensing circuit 61, which is described below) and to the source electrode 49. The control circuit 47 includes a sensor MISFET 55, an input circuit 56, a current / voltage control circuit 57, a protection circuit 58, the gate control circuit 59, an "active-clamp" circuit 60, the current sensing circuit 61, a power supply reverse connection protection circuit or power supply reverse polarity protection circuit 62 and an abnormality detection circuit 63. One gate of the sensor MISFET 55 is connected to the gate control circuit 59. One drain of the sensor MISFET 55 is connected to the drain electrode 46. One source of the sensor MISFET 55 is connected to the current sensing circuit 61. The input circuit 56 is connected to the input electrode 50 and to the current / voltage control circuit 57. The input circuit 56 can include a Schmitt trigger circuit. The input circuit 56 shapes a waveform or signal waveform of an electrical signal applied to the input electrode 50. A signal generated by the input circuit 56 is fed into the current / voltage control circuit 57. The current / voltage control circuit 57 is connected to the protection circuit 58, the gate control circuit 59, the power supply reverse connection protection circuit 62, and the abnormality detection circuit 63. The current / voltage control circuit 57 may include a logic circuit. The current / voltage control circuit 57 generates different voltages according to the electrical signal from the input circuit 56 and an electrical signal from the protection circuit 58. In this embodiment, the current / voltage control circuit 57 includes a control or driver voltage generation circuit 64, a first constant voltage generation circuit 65, a second constant voltage generation circuit 66, and a reference voltage / reference current generation circuit 67. The drive voltage generation circuit 64 generates a drive voltage to control the gate control circuit 59. The drive voltage can be set to a value at which a predetermined value is subtracted from the power supply voltage VB. The drive voltage generation circuit 64 can generate a drive voltage of at least 5 V and at most 15 V, where 5 V is subtracted from the power supply voltage VB. The drive voltage is input to the gate control circuit 59. The first constant voltage generation circuit 65 generates an initial constant voltage to drive the protection circuit 58. The first constant voltage generation circuit 65 can include a Zener diode or a regulator circuit (here, a Zener diode). The initial constant voltage may be no less than 1 V and may be no greater than 5 V. The initial constant voltage is fed into the protection circuit 58 (more precisely, a load-open detection circuit 69, etc., which is described below). The second constant voltage generation circuit 66 generates a second constant voltage to drive the protection circuit 58. The second constant voltage generation circuit 66 can include a Zener diode or a regulator circuit. The second constant voltage may be no less than 1 V and no greater than 5 V. The second constant voltage is fed into the protection circuit 58 (more precisely, into an overheating protection circuit 70 and an undervoltage malfunction suppression circuit 71, which is described below). The reference voltage / reference current generating circuit 67 generates a reference voltage and reference current for various circuits. The reference voltage may be no less than 1 V and no greater than 5 V. The reference current may be no less than 1 mA and no greater than 1 A. The reference voltage and reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and reference current can be input to the comparator. The protection circuit 58 is connected to the current / voltage control circuit 57, the gate control circuit 59, the abnormality detection circuit 63, the source of the power MISFET 43, and the source of the sensor MISFET 55. The protection circuit 58 includes an overcurrent protection circuit 68, a load-open detection circuit 69, the overheat protection circuit 70, and the low-voltage malfunction suppression circuit 71. The overcurrent protection circuit 68 protects the power MISFET 43 against overcurrent. The overcurrent protection circuit 68 is connected to the gate control circuit 59 and to the source of the sensor MISFET 55. The overcurrent protection circuit 68 may include a current monitoring circuit. A signal generated by the overcurrent protection circuit 68 is fed into the gate control circuit 59 (more precisely, a drive signal output circuit 74, which is described below). The load-open detection circuit 69 detects a short-circuit state or an open / unloaded state of the load. The load-open detection circuit 69 is connected to the current / voltage control circuit 57 and to the source of the power MISFET 43. A signal generated by the load-open detection circuit 69 is fed into the current / voltage control circuit 57. The overheating protection circuit 70 monitors the temperature of the power MISFET 43 and protects it against excessive temperature rise. The overheating protection circuit 70 is connected to the current / voltage control circuit 57. The overheating protection circuit 70 includes a temperature sensing component. This component preferably comprises a temperature sensing diode, which includes a pn junction diode. A signal generated by the overheating protection circuit 70 is fed into the current / voltage control circuit 57. The low-voltage malfunction suppression circuit 71 suppresses a malfunction of the power MISFET 43 when the power supply voltage VB is less than a predetermined value. The low-voltage malfunction suppression circuit 71 is connected to the current / voltage control circuit 57. A signal generated by the low-voltage malfunction suppression circuit 71 is fed into the current / voltage control circuit 57. The gate control circuit 59 controls an on state and an off state of the power MISFET 43 and an on state and an off state of the sensor MISFET 55. The gate control circuit 59 is connected to the current / voltage control circuit 57, the protection circuit 58, the gate of the power MISFET 43 and the gate of the sensor MISFET 55. The gate control circuit 59 generates a gate signal according to the number of gate wires 54, based on an electrical signal from the current / voltage control circuit 57 and an electrical signal from the protection circuit 58. The gate signal is fed via the gate wiring 54 into the gate of the power MISFET 43 or into the gate of the sensor MISFET 55. More precisely, the gate control circuit 59 comprises an oscillation circuit 72, a charge pump circuit 73, and the control signal output circuit 74. The oscillation circuit 72 oscillates according to the electrical signal from the current / voltage control circuit 57 and generates a predetermined electrical signal. The electrical signal generated by the oscillation circuit 72 is fed into the charge pump circuit 73. The charge pump circuit 73 amplifies ("boosts") the electrical signal from the oscillation circuit 72. The electrical signal amplified by the charge pump circuit 73 is fed into the control signal output circuit 74. The control signal output circuit 74 generates the gate signal according to the electrical signal from the charge pump circuit 73 and the electrical signal from the protection circuit 58 (more precisely, the overcurrent protection circuit 68). The gate signal is fed via the gate wiring 54 into the gate of the power MISFET 43 and the gate of the sensor MISFET 55. The sensor MISFET 55 and the power MISFET 43 are controlled simultaneously by the gate control circuit 59. The active-clamp circuit 60 protects the power MISFET 43 against back electromotive force. The active-clamp circuit 60 is connected to the drain electrode 46, the gate of the power MISFET 43, and the gate of the sensor MISFET 55. The active-clamp circuit 60 can include a variety of diodes. The "Active-Clamp" circuit 60 can include a variety of diodes that are biased together. The "Active-Clamp" circuit 60 can also include a variety of diodes that are reverse biased together. The "Active-Clamp" circuit 60 can include a variety of diodes that are biased together, and a variety of diodes that are reverse biased together. The variety of diodes can include a pn junction diode, a Zener diode, or both a pn junction diode and a Zener diode. The current sensing circuit 61 detects a current flowing through the power MISFET 43 or the sensor MISFET 55. The current sensing circuit 61 is connected to the protection circuit 58, the abnormality detection circuit 63, the source of the power MISFET 43, and the source of the sensor MISFET 55. The current sensing circuit 61 generates a current sensing signal based on an electrical signal generated by the power MISFET 43 and an electrical signal generated by the sensor MISFET 55. This current sensing signal is fed into the abnormality detection circuit 63. The power supply reverse connection protection circuit 62 protects the current / voltage control circuit 57, the power MISFET 43, etc., against a reverse voltage if a power supply is connected with reversed polarity. The power supply reverse connection protection circuit 62 is connected to the reference voltage electrode 51 and the current / voltage control circuit 57. The abnormality detection circuit 63 monitors a voltage of the protection circuit 58. The abnormality detection circuit 63 is connected to the current / voltage control circuit 57, the protection circuit 58, and the current sensing circuit 61. If an abnormality (variation in voltage, etc.) occurs in any of the circuits of the overcurrent protection circuit 68, the open-load detection circuit 69, the overheat protection circuit 70, and the low-voltage malfunction suppression circuit 71, the abnormality detection circuit 63 generates an abnormality detection signal, corresponding to the voltage of the protection circuit 58, and outputs it externally. More precisely, the abnormality detection circuit 63 comprises a first multiplexer circuit 75 and a second multiplexer circuit 76. The first multiplexer circuit 75 includes two input sections, one output section, and a selection control input section. The protection circuit 58 and the current detection circuit 61 are connected to the respective input sections of the first multiplexer circuit 75. The second multiplexer circuit 76 is connected to the output section of the first multiplexer circuit 75. The current / voltage control circuit 57 is connected to the selection control input section of the first multiplexer circuit 75. The first multiplexer circuit 75 generates an abnormality detection signal according to the electrical signal from the current / voltage control circuit 57, the voltage detection signal from the protection circuit 58, and the current detection signal from the current detection circuit 61. The abnormality detection signal generated by the first multiplexer circuit 75 is fed into the second multiplexer circuit 76. The second multiplexer circuit 76 comprises two input sections and one output section. The output section of the second multiplexer circuit 76 and the enable electrode 52 are each connected to the input sections of the second multiplexer circuit 76. The detect electrode 53 is connected to the output section of the second multiplexer circuit 76. When the MCU is connected to the enable electrode 52 and the resistor is connected to the detect electrode 53, an on signal is input from the MCU to the enable electrode 52, and the abnormal detection signal is taken from the detect electrode 53. The abnormal detection signal is converted into an electrical signal by the resistor connected to the detect electrode 53. A state abnormality of the semiconductor device 1 is detected based on this electrical signal. Fig. 9 is a top view of the structure of the power MISFET 43 shown in Fig. 8. Fig. 10 is a sectional view along a line XX shown in Fig. 9. Referring to Figures 9 and 10, the semiconductor device 1 includes a p-type body region 81 formed in a surface layer section of the non-mounting area 6 in the starting region 41. The p-type impurity concentration of the body region 81 is not less than 1 × 10¹⁶ cm⁻³ and not greater than 1 × 10¹⁸ cm⁻³. Body region 81 is formed in drift region 45. A base section of body region 81 is formed in relation to a base section of drift region 45 in a region on the side of the non-mounting surface 6. The thickness of body region 81 may be not less than 0.5 µm and not greater than 2 µm. The thickness of body region 81 may be not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 1.5 µm, or not less than 1.5 µm and not greater than 2 µm. The semiconductor device 1 incorporates a plurality of trench-gate structures 82 formed in the non-mounting area 6 in the exit region 41. In plan view, the plurality of trench-gate structures 82 extend as bands along the first direction X and are spaced apart in the second direction Y. In plan view, the plurality of trench-gate structures 82 are collectively arranged in strips. A distance (“pitch”) PS between the plurality of trench-gate structures 82 is optionally not less than 0.1 µm and not greater than 2 µm. The distance PS is preferably not less than 0.3 µm and not greater than 1.5 µm. A distance (“pitch”) PC between central sections of the plurality of trench-gate structures 82 is optionally not less than 1 µm and not greater than 8 µm. The distance PC is preferably not less than 1 µm and not greater than 3 µm. Each trench-gate structure 82 includes a gate trench 83, an insulating layer 84, and an embedded electrode 85. The gate trench 83 is formed by trenching starting from the non-mounting surface 6 and extending towards the side of the mounting surface 5. The gate trench 83 penetrates the body region 81. The gate trench 83 comprises a side wall and a bottom wall. The side wall of the gate trench 83 exposes the drift region 45 and the body region 81. The side wall of the gate trench 83 extends along the normal direction Z. The side wall of the gate trench 83 can be formed perpendicular to the non-mounting surface 6. The absolute value of the angle formed by the side wall with the non-mounting surface 6 within the chip 2 can exceed 90° and may not exceed 95° (for example, approximately 91°). This means that the gate trench 83 can be formed in a conical shape, narrowing in terms of opening width from the side of the non-mounting surface 6 towards the side of the bottom wall. The bottom wall of the gate trench 83 is formed extending from the bottom section of the drift region 45 at a distance from the side of the non-mounting surface 6. The bottom wall of the gate trench 83 exposes the drift region 45. The bottom wall of the gate trench 83 is formed in a curved shape (U-shape) that points towards the bottom section of the drift region 45. The bottom wall of the gate trench 83 is preferably formed at a distance of not less than 1 µm and not more than 5 µm from the bottom section of the drift region 45. The width of the gate trench 83 is optionally not less than 0.5 µm and not greater than 2 µm. The width of the gate trench 83 is preferably not less than 0.8 µm and not greater than 1.2 µm. The depth of the gate trench 83 is optionally not less than 1 µm and not greater than 10 µm. The depth of the gate trench 83 is preferably not less than 2 µm and not greater than 6 µm. The insulating layer 84 is formed as a film along the inner wall of the gate trench 83. The insulating layer 84 delineates a recessed space inside the gate trench 83. A section of the insulating layer 84 covering the bottom wall of the gate trench 83 is formed in accordance with the bottom wall of the gate trench 83. The insulating layer 84 thereby delineates a U-shaped space that is recessed into a U-shape within the gate trench 83. The insulating layer 84 comprises at least one material of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. In this embodiment, the insulating layer 84 has a single-layer structure formed from a silicon oxide layer. The insulating layer 84 has a bottom-side insulating layer 86 and an opening-side insulating layer 87, which extend from the side of the bottom wall towards the side of the non-mounting surface 6 of the gate trench 83. The bottom-side insulating layer 86 covers the inner wall on the side of the bottom wall of the gate trench 83. More precisely, the bottom-side insulating layer 86 covers the inner wall on the side of the bottom wall of the gate trench 83, starting from the bottom section of the body region 81. The bottom-side insulating layer 86 delineates the U-shaped space on the side of the bottom wall of the gate trench 83. A section of the bottom-side insulating layer 86 can contact the body region 81. The opening-side insulating layer 87 covers the inner wall on the opening side of the gate trench 83. More precisely, the opening-side insulating layer 87 covers the side wall of the gate trench 83 in a region on the opening side of the gate trench 83, specifically in relation to the bottom section of the body region 81. The opening-side insulating layer 87 is in contact with the body region 81. A section of the opening-side insulating layer 87 may contact the drift region 45. The bottom-side insulating layer 86 has a first thickness T1. The opening-side insulating layer 87 has a second thickness T2, which is less than the first thickness T1. The first thickness T1 is a thickness along a normal direction to the inner wall of the gate trench 83, specifically at the bottom-side insulating layer 86. The second thickness T2 is a thickness along the normal direction to the inner wall of the gate trench 83, specifically at the opening-side insulating layer 87. The embedded electrode 85 is embedded in the gate groove 83 via the insulating layer 84. In this embodiment, the embedded electrode 85 has an electrode structure of the dielectric insulation type, comprising a bottom-side electrode 88, an opening-side electrode 89, and an intermediate insulating layer 90. The bottom electrode 88 is embedded via the insulating layer 84 on the side of the bottom wall of the gate trench 83. More precisely, the bottom electrode 88 is embedded on the side of the bottom wall of the gate trench 83 via the bottom insulating layer 86. The bottom electrode 88 points towards the drift region 45 via the bottom insulating layer 86. A section of the bottom electrode 88 can point via the bottom insulating layer 86 towards the body region 81. The bottom electrode 88 includes an extended section that leads out towards the opening of the gate trench 83 in a region not shown. This extended section of the bottom electrode 88 is electrically connected to the gate wiring 54 or to the source electrode 49 in the region not shown. The bottom electrode 88 can comprise at least one material of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the bottom electrode 88 comprises conductive polysilicon. The conductive polysilicon can contain an n-type or a p-type impurity. The conductive polysilicon preferably comprises an n-type impurity. The opening-side electrode 89 is embedded via the insulating layer 84 at the opening side of the gate trench 83. More precisely, the opening-side electrode 89 is embedded via the opening-side insulating layer 87 in the recess space delimited at the opening side of the gate trench 83. The opening-side electrode 89 points via the opening-side insulating layer 87 towards the body region 81. A section of the opening-side electrode 89 may point via the opening-side insulating layer 87 towards the drift region 45. The opening-side electrode 89 is electrically connected to the gate wiring 54 in a region not shown. The opening-side electrode 89 can comprise at least one material of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the opening-side electrode 89 comprises conductive polysilicon. The conductive polysilicon can contain an n-type or a p-type impurity. The conductive polysilicon preferably contains an n-type impurity. The intermediate insulating layer 90 is arranged between the bottom-side electrode 88 and the opening-side electrode 89 and provides electrical insulation between the bottom-side electrode 88 and the opening-side electrode 89. More precisely, the intermediate insulating layer 90 covers an outer surface of the bottom-side electrode 88 that is exposed by the bottom-side insulating layer 86 in a region between the bottom-side electrode 88 and the opening-side electrode 89. The intermediate insulating layer 90 transitions continuously into the insulating layer 84 (bottom-side insulating layer 86). The intermediate insulating layer 90 has a third thickness T3. The third thickness T3 is less than the first thickness T1 of the bottom electrode 88. The intermediate insulating layer 90 comprises at least one material of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. In this embodiment, the intermediate insulating layer 90 has a single-layer structure formed from a silicon oxide layer. When the power MISFET 43 is driven (i.e., during gate turn-on), a gate voltage can be applied to the ground electrode 88 and a gate voltage can be applied to the open electrode 89. In this case, the ground electrode 88 and the open electrode 89 function as gate electrodes. This suppresses a voltage drop between the ground electrode 88 and the open electrode 89, and therefore a decrease in withstand voltage due to an electric field concentration between the ground electrode 88 and the open electrode 89 can be suppressed. Furthermore, the ON resistance of chip 2 can be reduced, thus achieving a reduction in power consumption. When the power MISFET 43 is driven (i.e., during the gate's turn-on phase), the reference voltage can be applied to the ground electrode 88, and the gate voltage can be applied to the open electrode 89. In this case, the open electrode 89 functions as a gate electrode, while the ground electrode 88 functions as a field electrode. This reduces parasitic capacitance and improves switching speed. The semiconductor device 1 contains a multitude of n+-type source regions 91 formed in a surface layer section of body region 81. The n-type impurity concentration of the source regions 91 exceeds the n-type impurity concentration of the drift region 45. The n-type impurity concentration of the source regions 91 may be no less than 1 × 10¹⁹ cm⁻³ and may not be greater than 1 × 10²¹ cm⁻³. The multitude of source regions 91 are formed in the surface layer section of body region 81 along the side walls of the gate trenches 83. Bottom sections of the multitude of source regions 91 are positioned relative to the bottom section of body region 81 in a region on the side of the non-mounting surface 6 or the mounting surface 5. The multitude of source regions 91 point via the insulating layers 84 (opening-side insulating layers 87) towards the embedded electrodes 85 (opening-side electrodes 89). The multitude of source regions 91 are formed in regions between the multitude of mutually adjacent gate trenches 83 with spacing in the second direction Y. Each source region 91 defines a channel of the power MISFET 43 inside the body region 81, together with the drift region 45. The semiconductor device 1 includes a multitude of p+-type contact regions 92 formed in the surface layer section of body region 81. The p-type impurity concentration of the contact regions 92 exceeds the p-type impurity concentration of the body region 81. The p-type impurity concentration of the contact regions 92 may be no less than 1 × 10¹⁹ cm⁻³ and may not be greater than 1 × 10²¹ cm⁻³. The multitude of contact regions 92 are formed in the surface layer section of body region 81 in regions between the multitude of source regions 91. The multitude of contact regions 92 are therefore formed in the surface layer section of body region 81 in a mode in which they are alternately arranged in an array-like manner with respect to the multitude of source regions 91. The semiconductor device 1 comprises a plurality of plug electrodes 93 embedded in the intermediate insulating layer 31 in the source region 41. The plurality of plug electrodes 93 may contain tungsten. The plurality of plug electrodes 93 includes a plurality of plug electrodes 93 electrically connected to corresponding source regions 91 and contact regions 92. Furthermore, the plurality of plug electrodes 93 includes a plurality of plug electrodes 93 electrically connected to corresponding bottom-side electrodes 88. The plurality of plug electrodes 93 also includes plug electrodes 93 electrically connected to corresponding opening-side electrodes 89. The source electrode 49 is electrically connected to the source regions 91 and the contact regions 92 via a corresponding plurality of plug electrodes 93. The source electrode 49 can also be electrically connected to the opening-side electrodes 89 via a corresponding plurality of plug electrodes 93. The gate wiring 54 is electrically connected to the bottom-side electrodes 88 and / or the opening-side electrodes 89 via a corresponding plurality of plug electrodes 93. Fig. 11 is a perspective view of a semiconductor package 101 that accommodates the semiconductor device 1 shown in Fig. 1, as seen through a main body of the package 102. Fig. 12 is a sectional view of a bonded state of the semiconductor device 1 shown in Fig. 11. Referring to Figures 11 and 12, the semiconductor package 101 in this embodiment is a so-called SOP (small outline package). The semiconductor package 101 includes the main body 102, a die pad 103, the semiconductor component 1, the conductive bonding material 104, a plurality (eight in this embodiment) of connection terminals 105, and a plurality (eight in this embodiment) of connecting wires 106. The main housing body 102 is produced or formed from casting resin. The main housing body 102 can contain an epoxy resin as an example of the casting resin. The main housing body 102 is formed in a rectangular parallelepiped shape. The main housing body 102 includes a first main surface 107 on one side, a second main surface 108 on the other side, and four side surfaces 109A, 109B, 109C, and 109D that connect the first main surface 107 and the second main surface 108. More precisely, the four face surfaces 109A to 109D comprise the first face surface 109A, the second face surface 109B, the third face surface 109C, and the fourth face surface 109D. The first face surface 109A and the second face surface 109B face each other. The third face surface 109C and the fourth face surface 109D face each other. The die pad 103 is arranged within the main body of the housing 102. The die pad 103 may optionally be exposed opposite the second main surface 108. The die pad 103 is formed from a metal plate shaped into a rectangular parallelepiped form. The die pad 103 may contain at least one material of Fe, Au, Ag, Cu, and Al. The die pad 103 may optionally have an outer surface on which at least one film of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The multiple connection terminals 105 include a first connection terminal 105A, a second connection terminal 105B, a third connection terminal 105C, a fourth connection terminal 105D, a fifth connection terminal 105E, a sixth connection terminal 105F, a seventh connection terminal 105G, and an eighth connection terminal 105H. The number of connection terminals 105 is set according to the functions of the semiconductor device 1 and is not limited to the number shown in Fig. 11 and Fig. 12. The four connection terminals 105A to 105D are arranged on the side of the first side surface 109A of the main body of the housing 102. The four connection terminals 105A to 105D are spaced apart from the die pad 103. The four connection terminals 105A to 105D are aligned or lined up in a direction in which the first side surface 109A extends, spaced apart from one another. The four connection terminals 105A to 105D cross or intersect the first side surface 109A, starting from the inside of the main body of the housing 102, and extend outwards to the outside of the main body of the housing 102. The four connection terminals 105E to 105H are arranged on the side of the second side surface 109B of the main body of the housing 102. The four connection terminals 105E to 105H are spaced apart from the die pad 103. The four connection terminals 105E to 105H are aligned or lined up in the direction in which the second side surface 109B extends, spaced apart or at intervals. The four connection terminals 105E to 105H cross or intersect the second side surface 109B from the inside of the main body of the housing 102 and extend outwards from the main body of the housing 102. The plurality of connection terminals 105 can contain at least one material of Fe, Au, Ag, Cu and Al. The plurality of connection terminals 105 can each have an outer surface on which at least one film of a Ni plating film, an Au plating film, an Ag plating film and a Cu plating film is formed. The semiconductor component 1 is arranged on the die pad 103 in an orientation where the mounting surface 5 faces the die pad 103. The conductive bonding material 104 is positioned between the semiconductor component 1 and the die pad 103 and bonds the drain electrode 46 of the semiconductor component 1 to the die pad 103. More precisely, the conductive bonding material 104 is positioned between the first metal layer 21 and the die pad 103 and covers the second metal layer 27. The conductive bonding material 104 covers the mounting surface 5 over the first metal layer 21. The conductive bonding material 104 covers the entire mounting surface 5 over the first metal layer 21. The conductive bonding material 104 covers the second metal layer 27 over a distance from the side of the mounting surface 5 to the non-mounting surface 6. The conductive bonding material 104 covers the first bonding walls 15A to 15D and the overhang sections 10A to 10D over the second metal layer 27. The conductive bonding material 104 exposes the second interconnection walls 16A to 16D. That is, the conductive bonding material 104 exposes the epitaxial layer 4. The affinity (wetting property) of the conductive bonding material 104 with respect to the chip 2 is lower than the affinity (wetting property) of the conductive bonding material 104 with respect to the second metal layer 27. Therefore, wet spreading of the conductive bonding material 104 towards the second interconnection walls 16A to 16D can be suppressed. Variations in the electrical properties of the epitaxial layer 4 due to the conductive bonding material 104 can therefore be suppressed, and consequently, variations in the electrical characteristics of the functional components formed in the epitaxial layer 4 can be suitably suppressed. The conductive bonding material 104 is produced from a solder or a conductive paste. The solder can be lead-free. The solder can contain at least one of the following materials: SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal paste can contain at least one of the following materials: Au, Ag, and Cu. The conductive bonding material 104 is preferably produced from a silver paste. The silver paste is particularly preferably produced from a sintered silver paste. The sintered silver paste is produced from a paste in which silver particles of nano or micro size are dispersed in an organic solvent. The heat generated by the semiconductor device 1 is transferred via the first metal layer 21 and the second metal layer 27 to the conductive bonding material 104. The heat transferred to the conductive bonding material 104 is then transferred to the die pad 103. A temperature increase of the semiconductor device 1 can therefore be suppressed. If the die pad 103 is exposed relative to the second main surface 108 of the main body of the package 102, the heat from the die pad 103 can be efficiently dissipated from the main body of the package 102. The temperature increase of the semiconductor device 1 can therefore be effectively suppressed. The multiple connecting wires 106 include a first connecting wire 106A, a second connecting wire 106B, a third connecting wire 106C, a fourth connecting wire 106D, a fifth connecting wire 106E, a sixth connecting wire 106F, a seventh connecting wire 106G, and an eighth connecting wire 106H. The number of connecting wires 106 is set according to the functions of the semiconductor device 1 and is not limited to the number shown in Fig. 11 and Fig. 12. The first connecting wire 106A is electrically connected to an end section of the first connecting terminal 105A and the source electrode 49. In this embodiment, the first connecting wire 106A is made of aluminum wire, as an example of a bond wire. The first connecting wire 106A can be made of gold wire or copper wire instead of aluminum wire. The second connecting wire 106B is electrically connected to an end section of the second connecting terminal 105B and the reference voltage electrode 51. The third connecting wire 106C is electrically connected to an end section of the third connecting terminal 105C and the RELEASE electrode 52. The fourth connecting wire 106D is electrically connected to an end section of the fourth connecting terminal 105D and the DETECTION electrode 53. The fifth connecting wire 106E is electrically connected to an end section of the fifth connecting terminal 105E and the die pad 103. The sixth connecting wire 106F is electrically connected to an end section of the sixth connecting terminal 105F and the die pad 103. The seventh connecting wire 106G is electrically connected to an end section of the seventh connecting terminal 105G and the input electrode 50. The eighth connecting wire 106H is electrically connected to an end section of the eighth connecting terminal 105H and the die pad 103. In this embodiment, the second to eighth connecting wires 106B to 106H are each made of a gold wire or a copper wire, as an example of a bond wire. In this embodiment, the second to eighth connecting wires 106B to 106H can each be made of an aluminum wire. The connection configuration of the plurality of connecting wires 106 with respect to the die pad 103, the semiconductor component 1, and the plurality of connection terminals 105A to 105H is arbitrary and is not limited to the connection configuration shown in Figures 11 and 12. With regard to the shape of the semiconductor package 101, a shape other than SOP can also be used. The semiconductor package 101 can have the shape of a TO (transistor outline), a QFN (quad for non-lead package), a DFP (dual flat package), a DIP (dual inline package), a QFP (quad flat package), a SIP (single inline package), a SOJ (small outline J-leaded package), or any of the various shapes related to these. As described above, the semiconductor device 1 has sidewalls 7A to 7D, which contain overhang sections 10A to 10D. Consequently, the overhang sections 10A to 10D prevent the conductive bonding material 104 from flowing towards the non-mounting surface 6. Likewise, in addition to the first metal layer 21, which covers the mounting surface 5, the semiconductor device 1 includes a second metal layer 27, which covers sidewalls 7A to 7D. The second metal layer 27 covers sidewalls 7A to 7D at intervals from the non-mounting surface 6, towards the side of the mounting surface 5. This can suitably improve heat dissipation. The heat dissipation of the semiconductor component 1 can be further improved by forming the conductive bonding material 104, which covers the second metal layer 27 within the semiconductor housing 101. Figures 13A to 13L are sectional views illustrating an example of a method for fabricating the semiconductor device 1 shown in Figure 1. The steps for forming the functional components are omitted below. Referring to Fig. 13A, a wafer 111 made of silicon is prepared. The wafer 111 includes a first wafer main surface 112 on one side and a second wafer main surface 113 on the other side. The first wafer main surface 112 and the second wafer main surface 113 correspond to the mounting area 5 and the non-mounting area 6 of the chip 2, respectively. Wafer 111 has a laminated structure comprising substrate 3 and epitaxial layer 4. Epitaxial layer 4 is formed by an epitaxial growth process, whereby silicon is epitaxially grown from a major surface of substrate 3. Referring to Fig. 13B, the interlayer insulating layer 31 is formed on the first wafer main surface 112. The interlayer insulating layer 31 can be formed by a thermal oxidation treatment process and / or a CVD process (CVD, "chemical vapor deposition"). Referring to Fig. 13C, a base electrode 114, which is intended to serve as a base for the plurality of electrodes 32, is formed on the intermediate insulating layer 31. The base electrode 114 can be formed by a sputtering process and / or a plating process. Referring to Fig. 13D, a resist mask 115 with a predetermined pattern is formed on the base electrode 114. Next, unnecessary sections of the base electrode 114 are removed by means of an etching process over the resist mask 115. The etching process can be a wet etching process and / or a dry etching process. The base electrode 114 is thereby subdivided into the plurality of electrodes 32. The resist mask 115 is then removed. Referring to Fig. 13E, a base insulating layer 116, which is intended to form a base for the upper insulating layers 33, is formed on the intermediate insulating layer 31. The base insulating layer 116 has a laminated structure that includes the passivation layer 36 and the resin layer 37. The passivation layer 36 contains silicon nitride. The passivation layer 36 can be formed by a CVD process. The resin layer 37 contains a photosensitive resin (polybenzoxazole in this embodiment). The resin layer 37 can be formed by coating the photosensitive resin onto the passivation layer 36. Referring to Fig. 13F, the resin layer 37 is selectively exposed and subsequently developed. This creates the second openings 39 and a dicing street 117 in the resin layer 37. Referring to Fig. 13G, sections of the passivation layer 36 that are exposed relative to the resin layer 37 are removed by an etching process via the resin layer 37. The etching process can be a wet etching process and / or a dry etching process. The first openings 38 and the separation line 117 are thereby formed in the passivation layer 36. Thus, the plurality of pad openings 34 and the separation path 117 are formed in the base insulating layer 116, and at the same time the base insulating layer 116 is subdivided into a plurality of upper insulating layers 33. The plurality of pad openings 34 are each formed by a first opening 38 and a second opening 39. The plurality of pad openings 34 each expose a corresponding electrode 32. The separation path 117 is delimited by the circumferential edges of the plurality of upper insulating layers 33 and is formed in a grid shape in plan view. The width WD2 of the separating section 117 may be no less than 2 µm and no greater than 200 µm. The width WD2 is a width in a direction orthogonal to the direction in which the separating section 117 extends. The width WD2 may be no less than 2 µm and no greater than 50 µm, no less than 50 µm and no greater than 100 µm, no less than 100 µm and no greater than 150 µm, or no less than 150 µm and no greater than 200 µm. Referring to Fig. 13H, the second wafer main surface 113 is ground. The second wafer main surface 113 can be ground using a CMP process (CMP, "chemical mechanical polishing"). This reduces the wafer 111 (substrate 3) to a desired thickness. Referring to Fig. 13I, a recess 118 is formed in the second wafer main surface 113. The recess or groove 118 is formed in a lattice shape that, in plan view, is oriented along the separation line 117. The recess 118 delineates regions of the wafer 111, which are to be semiconductor components 1, from the side of the second wafer main surface 113. In this step, the groove 118 is formed by a grinding process using a first cutting edge 119, which has a first cutting edge width WB1. The first cutting edge width WB1 is preferably smaller than the width WD2 of the separation line 117. The depression 118 can be formed by an etching process instead of or in addition to the grinding process. If the depression 118 is formed by an etching process, a resist mask (not shown) with an opening exposing a region in which the depression 118 is to be formed is first created on the second wafer main face 113. Next, an unnecessary section of the second wafer main face 113 is removed by the etching process over the resist mask (not shown). The etching process can be a wet etching process and / or a dry etching process. Preferably, a dry etching process is used (for example, a reactive ion etching process). This creates the recess 118 in the second main wafer surface 113. The resist mask (not shown) is then removed. Referring to Fig. 13J, the second wafer main surface 113 and an inner wall of the depression 118 can be roughened by a roughening etching process. The roughening etching process can be a wet etching process and / or a dry etching process. The roughening etching process is preferably a wet etching process. Referring to Fig. 13K, a base metal layer 120, which is intended to form a base for the first metal layer 21 and the second metal layer 27, is formed on the second wafer main surface 113. The base metal layer 120 is formed as a film along the second wafer main surface 113 and the inner wall of the depression 118. The base metal layer 120 thus delineates a depression or recess space inside the depression 118. In this embodiment, the base metal layer 120 has a laminated structure comprising the Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26. The Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26 can each be formed by a sputtering process, a vapor deposition process, and / or a plating process. The base metal layer 120 covers the second wafer main surface 113 and the inner wall of the well 118, which have been roughened. This increases the adhesive force of the base metal layer 120 on the second wafer main surface 113 and the inner wall of the well 118, and thus effectively suppresses detachment or peeling of the base metal layer 120 from the second wafer main surface 113 and the inner wall of the well 118. Referring to Fig. 13L, the wafer 111 is separated along the separation line 117 and divided or singulated into a plurality of semiconductor components 1. In this step, the wafer 111 is cut or separated by a grinding process using a second cutting edge 121, which has a second cutting edge width WB2 that is smaller than the first cutting edge width WB1. The wafer 111 is separated by the second cutting edge 121 starting from the side of the first wafer face 112. The semiconductor component 1 is manufactured by steps that include the steps described above. Steps starting from Fig. 13G are now described in detail with reference to Figs. 14A to 14G. Figs. 14A to 14G are sectional views of steps starting from Fig. 13G and are sectional views to describe the method for manufacturing the semiconductor device 1 shown in Fig. 1 in greater detail. Referring to Fig. 14A, a first carrier tape 122 is tacked ("stuck") to the side of the first wafer main surface 112 after the passivation layer 36 has been removed in the step of Fig. 13G. The first carrier tape 122 is preferably made of a one-sided tacky tape that is ultraviolet curable. The first carrier tape 122 can, for example, be a back grinding tape comprising a base film with an ultraviolet-transmitting resin and a tacky agent layer provided on one surface side of the base film, which also comprises an ultraviolet-curable resin. Referring to Fig. 14B, the second wafer face 113 is ground in a state where the wafer 111 is supported or held by the first support tape 122. The second wafer face 113 can be ground using a CMP process. This reduces the thickness of the wafer 111 (substrate 3) to a desired thickness. Referring to Fig. 14C, the depression 118 in the second wafer face 113 is formed in a state where the wafer 111 is supported by the first support tape 122. The depression 118 is formed in a lattice configuration, or grid, oriented along the parting line 117. The depression 118 delineates the regions of the wafer 111 that are to be the semiconductor devices 1 from the side of the second wafer face 113. In this step, the depression 118 is formed by grinding, using the first cutting edge or blade 119, which has the first cutting edge width WB1. The first cutting width WB1 is preferably smaller than the width WD2 of the cutting line 117. After the recess 118 has been formed, ultraviolet rays are directed onto the first carrier tape 122, and the first carrier tape 122 is lifted or peeled off. It is understood that the depression 118 can be formed by an etching process instead of or in addition to the grinding process. In this case, for example, the resist mask (not shown), which has the opening that exposes the region in which the depression 118 is to be formed, is formed on the second wafer main surface 113 in a state where the wafer 111 is supported or held by the first support tape 122. Next, the unnecessary or non-essential section of the second wafer main surface 113 is removed by the etching process over the resist mask (not shown). The etching process can be a wet etching process and / or a dry etching process. Preferably, the etching process is a dry etching process (for example, a reactive ion etching process). This creates the depression 118 in the second wafer main surface 113. After the depression 118 has been created, the first carrier tape 122 and the resist mask (not shown) are removed. Referring to Fig. 14D, the second wafer main surface 113 and the inner wall of the depression 118 can be roughened by a roughening etching process. The roughening etching process can be a wet etching process and / or a dry etching process. The roughening etching process is preferably a wet etching process. Referring to Fig. 14E, the base metal layer 120, which is to form the basis of the first metal layer 21 and the second metal layer 27, is formed on the second wafer main surface 113. The base metal layer 120 is formed as a film along the second wafer main surface 113 and the inner wall of the well 118. The base metal layer 120 is bounded here by the recessed area inside the well 118. In this embodiment, the base metal layer 120 has a laminated structure comprising the Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26. The Ti layer 22, the Ni layer 23, the Au layer 24, the Pd layer 25, and the Ag layer 26 can each be formed by a sputtering process, a vapor deposition process, and / or a plating process. The base metal layer 120 covers the second wafer main surface 113 and the inner wall of the well 118, which have been roughened. This increases the adhesive force of the base metal layer 120 on the second wafer main surface 113 and the inner wall of the well 118, and thus effectively suppresses detachment of the base metal layer 120 from the second wafer main surface 113 and the inner wall of the well 118. Referring to Fig. 14F, a second carrier tape 123 is affixed to the side of the second wafer main surface 113 (more precisely, the base metal layer 120). The second carrier tape 123 is preferably made of a single-sided adhesive tape that is ultraviolet curable. The second carrier tape 123 can, for example, be a separating tape or dicing tape comprising a base film including an ultraviolet-transmitting resin and an adhesive layer provided on one surface side of the base film, which contains an ultraviolet-curable resin. Referring to Fig. 14G, in a state where the wafer 111 is supported by the second support tape 123, the wafer 111 is cut or singulated along the separation line 117, starting from the side of the first wafer face 112, and is divided into the plurality of semiconductor components 1. In this step, the wafer 111 is cut by the grinding process using the second cutting edge 121, which has a second cutting edge width WB2 that is smaller than the first cutting edge width WB1. After the wafer 111 is cut, ultraviolet rays are directed onto the second carrier tape 123, reducing its adhesive strength. Subsequently, the numerous semiconductor components 1 are picked up from the second carrier tape 123. During this process, the first metal layer 21 and the second metal layer 27 cover the second wafer surface 113 and the roughened inner wall of the well 118. This prevents the first metal layer 21 and the second metal layer 27 from peeling off, which would otherwise result in the semiconductor components 1 detaching. Apart from the separation method using the second cutting edge 121, the wafer 111 can also be separated or cut by a separation method shown in Fig. 15A and Fig. 15B. Fig. 15A and Fig. 15B are sectional views of steps starting from Fig. 14F and are sectional views to describe a further method for separating the wafer 111. Referring to Fig. 15A, after attachment to the second carrier tape 123, laser light from a laser light source (not shown) is directed into the interior of the wafer 111 via the separation line 117. The laser light is preferably directed into the interior of the wafer 111 in pulses, originating from the side of the first main wafer face 112 that does not include the base metal layer 120. A light-converging section (focal point) of the laser light is positioned in the interior (a section central in the thickness direction) of the wafer 111, and the laser light irradiation position is moved along the separation line 117. A modified layer 124, extending along the separation line 117 and the depression 118 in plan view, is thereby formed in the interior of the wafer 111. The modified layer 124 is generated from a laser light irradiation marking and is produced from a region where a crystal structure of the wafer 111 has been modified to exhibit an altered property. That is, the modified layer 124 is produced from a region where a density, refractive index, mechanical strength (crystal strength), or another physical characteristic has been modified to a property that differs from that of the crystal structure of the wafer 111. The modified layer 124 can include at least one layer of an amorphous layer, a melt rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The amorphous layer is a layer in which a section of the wafer 111 has been made amorphous. The melt rehardened layer is a layer in which a section of the wafer 111 has been rehardened after being melted. The defect layer is a layer containing a hole, fracture, etc., formed in the wafer 111. The dielectric breakdown layer is a layer in which a section of the wafer 111 has undergone dielectric breakdown. The refractive index change layer is a layer in which a section of the wafer 111 has been modified to have a refractive index different from that of the wafer 111. The modified layer 124 has a planar shape that corresponds to or is identical with the planar shapes of the separating line 117 and the depression 118 in plan view. That is, the modified layer 124 is formed in a grid or lattice shape in plan view. The modified layer 124 is formed in a region of the interior of the wafer 111 that faces the separating line 117 and the depression 118. The modified layer 124 is preferably formed in a region that faces a central section of the depression 118 in plan view. The width of the modified layer 124 is preferably smaller than the width WD2 of the separating line 117. Furthermore, the width of the modified layer 124 is particularly preferably smaller than the width of the depression 118 (equivalent to the width of the first cutting edge WB1). The modified layer 124 is preferably formed at intervals between the first wafer main surface 112 and the depression 118 in the interior of the wafer 111. In this case, the modified layer 124 is preferably formed in a section of the interior of the wafer 111 that is formed from the substrate 3 (drain region 44). The modified layer 124 is particularly preferably formed in a section of the interior of the wafer 111 that is formed from the substrate 3 at a distance from the epitaxial layer 4 (drift region 45). It is most preferred if the modified layer 124 is not formed in the epitaxial layer 4 in the interior of the wafer 111. Referring to Fig. 15B, an external force is applied to the wafer 111, and the wafer 111 is cleaved, with the modified layer 124 serving as a starting point. The intermediate insulating layer 31 and the base metal layer 120 are cleaved simultaneously with the cleavage of the wafer 111. The upper insulating layers 33 delimit the cleavage path 117 and are not positioned on a cleavage line, thus preventing them from being cleaved. If the upper insulating layers 33, which contain the resin layers 37, are positioned on the cleavage line, cleavage is prevented by the elasticity of the resin layers 37. Therefore, in the cleavage step according to this embodiment, the cleavage of the wafer 111 can be carried out without difficulty. Furthermore, in this embodiment, a pressing member 125 applies the external force to the wafer 111 from the side of the second main wafer surface 113 via the second carrier tape 123. This method allows the plurality of semiconductor components 1 to be tilted in the directions of separation during the slitting of the wafer 111, with the pressing member 125 serving as a starting point. This prevents collisions between the plurality of semiconductor components 1 during the slitting process and also prevents breakage of the semiconductor components 1. After the wafer 111 is cleaved, ultraviolet rays are directed onto the second carrier tape 123, reducing its adhesive strength. Subsequently, the numerous semiconductor devices 1 are removed from the second carrier tape 123. During this process, the first metal layer 21 and the second metal layer 27 cover the second wafer surface 113 and the roughened inner wall of the well 118. This prevents the first metal layer 21 and the second metal layer 27 from separating and lifting off the semiconductor devices 1. Fig. 16 corresponds to Fig. 4 and is a sectional view of the semiconductor device 1, which was fabricated via the steps of Fig. 15A and Fig. 15B. Structures already mentioned below are designated with the same reference numerals, and a description of them is omitted. Referring to Fig. 16, in the semiconductor component 1, the sidewalls 7A to 7D have gaps in regions between the non-mounting surface 6 and the overhang sections 10A to 10D. That is, the sidewalls 7A to 7D have notched or cut-out sections 11 on the side of the mounting surface 5 and split sections 126 on the side of the non-mounting surface 6. The notched sections 11 include the overhang sections 10A to 10D and the first connecting walls 15A to 15D and are recessed or cut out from the mounting surface 5 towards the non-mounting surface 6. The split sections 126 include the second connecting walls 16A to 16D and are formed in regions between the non-mounting surface 6 and the notched sections 11. In this structure, the semiconductor component 1 includes the modified layers 124, which are formed in the split sections 126 of the sidewalls 7A to 7D. That is, the modified layers 124 are formed in the head section 18 of the chip 2. The modified layers 124 are preferably formed in the sidewalls 7A to 7D at distances from the non-mounting area 6 and the cut sections 11 (overhang sections 10A to 10D). The modified layers 124 are preferably formed in sections of the sidewalls 7A to 7D that are formed or generated from the substrate 3 (drain region 44). In this case, the modified layers 124 are particularly preferably formed in sections of the side walls 7A to 7D, which are formed from the substrate 3, at a distance from the epitaxial layer 4 (drift region 45). It is preferred that the modified layers 124 are not formed in the epitaxial layer 4 in the side walls 7A to 7D. The width of the modified layers 124 is preferably smaller than the width WE of the overhang sections 10A to 10D. In this embodiment, the exposed section 30 of the second covering section 29 in the second metal layer 27 is formed from the split surfaces. The exposed section 30 of the second covering section 29 forms a single split surface (split section) with the split sections 126 of the respective side walls 7A to 7D. Furthermore, in this embodiment, the circumferential edges of the intermediate insulating layer 31 are formed from split surfaces. The circumferential edges of the intermediate insulating layer 31 form a single split surface (split section) with the split sections 126 of the side walls 7A to 7D. As described above, according to this manufacturing process, the modified layer 124 is formed in the section of the interior of wafer 111 that has been thinned by the depression 118, and the wafer 111 is cleaved with the modified layer 124 as the starting point. The section of wafer 111 to be cleaved is thereby made small, thus reducing the risk of fractures occurring during the cleavage process. This suppresses an appearance defect of the semiconductor device 1. Furthermore, the slitting step of the wafer 111 eliminates the need for the second cutting edge 121. This prevents wear on the second cutting edge 121. Additionally, the process tolerance or process margin of the second cutting edge 121 can be eliminated, and the loss of a section of the wafer 111 due to grinding (i.e., due to a parting line or cutting tolerance) can be eliminated. This increases the number of semiconductor devices 1 that can be obtained from a single wafer 111. Furthermore, according to this manufacturing process, the irradiation area of ​​the laser light relative to wafer 111 can be narrowed by the depression 118, thus shortening the laser irradiation time. This allows the wafer 111 to be easily slit. From the above, it can be concluded that the wafer 111 with the depression 118 has an extremely high affinity for the slitting step. The modified layer 124 is preferably formed at a distance from the well 118 (cut sections 11) towards the side of the first wafer main face 112 (non-mounting face 6). In this way, fractures of the well 118 (cut sections 11) due to the modified layer 124 can be suppressed during slitting. The modified layer 124 is also preferably formed at a distance from the first wafer main face 112 (non-mounting face 6) towards the side of the well 118 (cut sections 11). In this case, fractures at corner or edge sections of the chip 2, viewed in cross-section, can be suppressed during slitting. The width of the modified layer 124 formed in the wafer 111 is preferably smaller than the width of the well 118 (equivalent to the width of the first cutting edge WB1).In this case, damage to wafer 111 can be reduced and consequently the risk of fractures occurring at the depression 118 (cut section 11) can be reduced. The epitaxial layer 4 has the component surface (non-mounting surface 6) on which the functional components are formed, and when the modified layer 124 is formed in the epitaxial layer 4, a section of the epitaxial layer is changed due to the modified layer 124, and this cannot be considered preferable with regard to the physical and electrical properties of the epitaxial layer 4. Therefore, the light-converging section (focal point) of the laser light is preferably directed onto a section of the wafer 111 that is formed or generated from the substrate 3 (drain region 44). That is, the modified layer 124 is preferably formed in the section of the wafer 111 that is formed from the substrate 3 (drain region 44). Variations in the physical and electrical characteristics of the epitaxial layer 4 due to the modified layer 124 can consequently be suppressed. As a result, variations in the electrical characteristics of the functional components formed in the epitaxial layer 4 can also be suppressed. In this case, the modified layer 124 is particularly preferably formed in a section of the interior of the wafer 111, which is formed from the substrate 3, at a distance from the epitaxial layer 4 (drift region 45). It is most preferred that the modified layer 124 is not formed in the epitaxial layer 4 in the interior of the wafer 111. It is understood that this disclosure does not prevent or exclude a structure in which the modified layer 124 is formed in the epitaxial layer 4, and the modified layer 124 can be formed in the epitaxial layer 4 as necessary. The preferred embodiment of the present invention can also be implemented in further embodiments. In the preferred embodiment described above, an example was described in which the side walls 7A to 7D each have overhang sections 10A to 10D. However, a structure can be used in which one, two, or three of the side walls 7A to 7D have, or do not have, the overhang sections 10A to 10D. Such a structure is formed by omitting a section of the step of forming the recess 118. However, with regard to symmetry, heat dissipation, etc., of the chip 2, it is preferred if all side walls 7A to 7D have the overhang sections 10A to 10D. In the preferred embodiment described above, an example was presented in which the mounting surface 5, the overhang sections 10A to 10D, and the first connecting walls 15A to 15D are formed by rough surfaces. However, the mounting surface 5, the overhang sections 10A to 10D, and the first connecting walls 15A to 15D need not be roughened. In this case, the step of Fig. 13J is omitted. If the step of Fig. 13J is omitted, at least the mounting surface 5 is formed from a ground surface with grinding marks. If the recess 118 in the step of Fig. 13I is formed by the first cutting edge 119, the overhang sections 10A to 10D and the first connecting walls 15A to 15D are formed from ground surfaces with grinding marks. In the preferred embodiment described above, an example was described in which the upper insulating layer 33 has a laminated structure comprising the passivation layer 36 and the resin layer 37. However, the upper insulating layer 33 can have a single-layer structure formed from either the passivation layer 36 or the resin layer 37. In the preferred embodiment described above, an example was described in which the embedded electrode 85 has a dielectric insulating electrode structure comprising the bottom-side electrode 88, the opening-side electrode 89, and the intermediate insulating layer 90. However, the embedded electrode 85 can be embedded as a single piece over the insulating layer 84 in the gate groove 83. In this case, the insulating layer 84 can have a uniform thickness. In the preferred embodiment described above, a structure can be used in which the conductivity types of the respective semiconductor sections are inverted. That is, a p-type section can be made into an n-type, and an n-type section can be made into a p-type. In the preferred embodiment described above, an example was given in which the chip 2, made of silicon, is used. However, in the preferred embodiment described above, the chip 2 made of a semiconductor material with a wide bandgap can also be used. In this case, the chip 2 made of silicon carbide can be used. The preferred embodiment described above also allows the chip 2 made of a composite semiconductor material to be used. In this case, the chip 2 made of gallium nitride or gallium oxide can be used. In the preferred embodiment described above, an example was described in which the functional components, which include the vertical-type component (power MISFET 43), are formed in the chip 2, which has overhang sections 10A to 10D. However, a functional component that includes a lateral-type component can also be formed in the chip 2, which has overhang sections 10A to 10D. Likewise, only a functional component that is generated from a lateral-type component can be formed in the chip 2, which has overhang sections 10A to 10D. In the preferred embodiment described above, an example was described in which the functional components are an integrated phase device (IPD). However, the functional components are not limited to an IPD. The chip 2, which has overhang sections 10A to 10D, can be applied to various electronic components (semiconductor devices) that are equipped with functional components other than an IPD. For example, the chip 2, which has overhang sections 10A to 10D, can be applied to an electronic component (semiconductor device), etc., that is equipped with at least one passive component, one passive semiconductor component, one rectifying semiconductor component, one light-emitting semiconductor component, and one switching semiconductor component. The passive component (passive semiconductor component) can include at least one element consisting of a resistor, a capacitor, and an inductor. The rectifying semiconductor component can include at least one diode consisting of a pn junction diode, a Zener diode, a Schottky barrier diode, and a first recovery diode. The light-emitting semiconductor component can include at least one element consisting of a light-emitting diode, a semiconductor laser, and an organic electroluminescent component. The switching semiconductor component can contain at least one component of a JFET (junction field-effect transistor), a BJT (bipolar junction transistor), a MISFET (metal insulator field-effect transistor) and an IGBT (bipolar junction transistor with insulated gate). The functional component can include a circuit network in which at least two elements from the passive component (passive semiconductor component), the rectifying semiconductor component, and the switching semiconductor component are combined. The circuit network can form a section of an integrated circuit or can form the entire integrated circuit. The integrated circuit can include or be of the following type: SSI (small-scale integration), LSI (large-scale integration), MSI (medium-scale integration), VLSI (very-large-scale integration), or ULSI (ultra-very-large-scale integration). Examples of features that can be extracted from the present description and figures are given below. The heat dissipation of a semiconductor device can be improved by forming a metal layer on a sidewall of the chip. However, in this case, it is likely that undesirable short circuits will occur as a result of conductive bonding material flowing across the metal layer to a non-mounting area of ​​the chip. Consequently, the heat dissipation cannot be adequately improved. Therefore, paragraphs [A1] to [A19] below provide a semiconductor device in which the heat dissipation can be adequately improved.[A1] Semiconductor device comprising: a chip having a mounting surface, a non-mounting surface projecting further outward than the mounting surface, and a side wall comprising an overhang section projecting further outward than the mounting surface and connecting the mounting surface and the non-mounting surface; a first metal layer covering the mounting surface; and a second metal layer covering the side wall at a distance from the non-mounting surface towards the side of the mounting surface. According to this semiconductor device, the overhang section can suppress or prevent a conductive bonding material from flowing around the non-mounting surface. Consequently, a semiconductor device with suitably improved heat dissipation can be provided. [A2] Semiconductor device according to A1, wherein the overhang section is formed at a distance from the non-mounting surface towards the side of the mounting surface.[A3] Semiconductor device according to A1 or A2, wherein the second metal layer covers a region in the side wall between the mounting surface and the overhang section. [A4] Semiconductor device according to any one of A1 to A3, wherein the second metal layer covers the overhang section. [A5] Semiconductor device according to any one of A1 to A4, wherein the overhang section has an inner end section on the side of the mounting surface, an outer end section on the side of the non-mounting surface, and a connecting section that joins the inner end section and the outer end section. [A6] Semiconductor device according to A5, wherein the connecting section is formed or constructed from an inclined section. [A7] Semiconductor device according to any one of A1 to A6, wherein the side wall has a connecting wall that joins the non-mounting surface and the overhang section, and wherein the second metal layer exposes the connecting wall.[A8] Semiconductor device according to any one of A1 to A7, wherein the chip has a laminated structure comprising a substrate forming the mounting surface and an epitaxial layer forming the non-mounting surface, the overhang section being formed on the substrate. [A9] Semiconductor device according to A8, wherein the overhang section is formed in the substrate at a distance from the epitaxial layer. [A10] Semiconductor device according to A8 or A9, wherein the second metal layer exposes the epitaxial layer. [A11] Semiconductor device according to any one of A1 to A10, wherein the overhang section is formed by a notched section in which a circumferential edge section of the mounting surface is notched or cut out in the direction of the non-mounting surface. [A12] Semiconductor device according to any one of A1 to A11, wherein the first metal layer comprises a noble metal.[A13] Semiconductor device according to any one of A1 to A12, wherein the second metal layer comprises a noble metal. [A14] Semiconductor package comprising: a die pad; a terminal arranged at a distance from the die pad; the semiconductor device according to any one of A1 to A13, arranged on the die pad in an orientation such that the mounting surface faces the die pad; and a conductive bonding material arranged between the first metal layer and the die pad, covering the second metal layer and bonding the semiconductor device to the die pad. [A15] Semiconductor package according to A14, wherein the conductive bonding material covers the second metal layer with a distance from the non-mounting surface towards the side of the mounting surface. [A16] Semiconductor package according to A14 or A15, wherein the conductive bonding material covers the overhang section.[A17] Semiconductor package according to any one of A14 to A16, wherein the conductive bonding material is formed from a solder or a conductive paste. [A18] Semiconductor package according to A17, wherein the conductive bonding material is formed from a silver paste. [A19] Semiconductor package according to any one of A14 to A18, further comprising: a package main body formed from a resin; and wherein the die pad, the terminal, the semiconductor device and the conductive bonding material are arranged inside the package main body. The following paragraphs [B1] to [B20] provide a semiconductor device in which the flow of a conductive bonding material can be suppressed. [B1] Semiconductor device (1) comprising: a semiconductor chip (2) having a first surface (5), a second surface (6) and a side wall (7A to 7D) connecting the first surface (5) and the second surface (6) and having a cut-out section (11) extending from the first surface (5) towards the second surface (6) in the side wall (7A to 7D), with a split section (16A to 16D, 126) being formed between the second surface (6) and the cut-out section (11) in the side wall (7A to 7D); and a modified layer (124) formed in the split section (16A to 16D, 126) on the side wall (7A to 7D) which is modified to have a property,which differs from that of a crystal structure of the semiconductor chip (2). According to this semiconductor device (1), the flow of a conductive bonding material to the second surface (6) can be suppressed by means of the incised section (11). [B2] Semiconductor device (1) according to B1, wherein the modified layer (124) is formed at a distance from the second surface (6) towards the side of the incised section (11). [B3] Semiconductor device (1) according to B1 or B2, wherein the modified layer (124) is formed at a distance from the incised section (11) towards the side of the second surface (6). [B4] Semiconductor device (1) according to any one from B1 to B3, wherein the modified layer (124), when viewed in a plane direction along the first surface (5), has a width that is less than a width (WE) of the incised section (11). [B5] Semiconductor device (1) according to any one from B1 to B4,further comprising: a metal layer (21) covering the first surface (5).[B6] Semiconductor device (1) according to any one of B1 to B5, further comprising: a sidewall metal layer (22) covering the cut section (11).[B7] Semiconductor device (1) according to B6, wherein the sidewall metal layer (22) exposes the split section (16A to 16D, 126).[B8] Semiconductor device (1) according to any one of B1 to B7, wherein the first surface (5) is a mounting surface (5) and wherein the second surface (6) is a non-mounting surface (6).[B9] Semiconductor device (1) comprising: a semiconductor chip (2) having a laminated structure with a semiconductor substrate (3) and an epitaxial layer (4), having a first surface (5) on the side of the semiconductor substrate (3), and a second surface (6) on the side of the epitaxial layer. (4) has and has a side wall (7A to 7D) formed by the semiconductor substrate (3) and the epitaxial layer (4),and which has a cut-out section (11) in the side wall (7A to 7D) extending from the first surface (5) towards the second surface (6), and a split section (16A to 16D, 126) formed on the side wall (7A to 7D) between the second surface (6) and the cut-out section (11); and a modified layer (124) formed in the split section (16A to 16D, 126) on the side wall (7A to 7D) which is modified to have a property that differs from that of a crystal structure of the semiconductor chip (2). According to this semiconductor device (1), the cut-out section (11) can suppress the flow of a conductive bonding material towards the second surface (6). [B10] Semiconductor device (1) according to B9,wherein the incised section (11) is formed starting from the first surface (5) in the direction towards the second surface (6) and up to a section of the semiconductor substrate (3) that is mid-thickness, and wherein the split section (16A to 16D, 126) is formed by the semiconductor substrate (3) and the epitaxial layer (4). [B11] Semiconductor device (1) according to B9 or B10, wherein the modified layer (124) is formed at a distance from the second surface (6) towards the side of the incised section (11). [B12] Semiconductor device (1) according to any one of B9 to B11, wherein the modified layer (124) is formed at a distance from the incised section (11) towards the side of the second surface (6). [B13] Semiconductor device (1) according to any one of B9 to B12, wherein the modified layer (124) is formed in a section of the side wall (7A to 7D) is formed,which is formed from the semiconductor substrate (3).[B14] Semiconductor device (1) according to any one of B9 to B13, wherein the modified layer (124) is formed in a section of the sidewall (7A to 7D) formed from the semiconductor substrate (3), with a distance from the epitaxial layer (4) towards the side of the cut section (11).[B15] Semiconductor device (1) according to any one of B9 to B14, wherein the modified layer (124), when viewed in a plane direction along the first surface (5), has a width which is less than a width (WE) of the cut section (11).[B16] Semiconductor device (1) according to any one of B9 to B15, further comprising: a metal layer (21) covering the first surface (5).[B17] Semiconductor device (1) according to any one of B9 to B16, further comprising: a sidewall metal layer (22), which covers the side wall (7A to 7D).[B18] Semiconductor component (1) according to B17,wherein the sidewall metal layer (22) covers the cut section (11) and exposes the split section (16A to 16D, 126).[B19] Semiconductor device (1) according to B17 or B18, wherein the sidewall metal layer (22) covers a section of the sidewall (7A to 7D) formed from the semiconductor substrate (3), with a distance from the epitaxial layer (4) towards the side of the cut section (11).[B20] Semiconductor device (1) according to any one of B9 to B19, wherein the first surface (5) is a mounting surface (5) and wherein the second surface (6) is a non-mounting surface (6).

Claims

Semiconductor component comprising: a chip (2) having a mounting surface (5), a non-mounting surface (6) and a side wall (7a to 7D) connecting the mounting surface (5) and the non-mounting surface (6) and having an overhang section (10A to 10D) which extends further outwards on the side wall (7A to 7D) than the mounting surface (5);and a metal layer (21) covering the mounting surface (5), wherein the overhang section (10A to 10D) has an inner end section (12) arranged in a direction (Z) perpendicular to the mounting surface (5) on the side of the mounting surface (5), an outer end section (13) arranged in the direction (Z) on the side of the non-mounting surface (6), and a connecting section (14) connecting the inner end section (12) and the outer end section (13), and wherein the connecting section (14) has an inclined surface forming an obtuse angle with the side wall (7A to 7D) at the inner end section (12) and the outer end section (13). Semiconductor component according to claim 1, wherein the non-mounting surface (6) projects further outwards than the mounting surface (5) and wherein the overhang section (10A to 10D) points in a thickness direction of the chip towards the non-mounting surface (6). Semiconductor component according to claim 1, further comprising: a sidewall metal layer covering the sidewall (7a to 7D). Semiconductor component according to claim 3, wherein the side wall metal layer (27) is formed at a distance from the non-mounting surface (6) towards the side of the mounting surface (5). Semiconductor component according to claim 3, wherein the side wall metal layer (27) covers a region of the side wall (7a to 7D) between the mounting surface (5) and the overhang section (10A to 10D). Semiconductor component according to claim 3, wherein the sidewall metal layer (27) points in a thickness direction of the chip towards the non-mounting surface (6). Semiconductor component according to claim 3, wherein the side wall metal layer (27) covers the overhang section (10A to 10D). Semiconductor component according to claim 3, wherein the side wall (7a to 7D) has a connecting wall that connects the non-mounting surface (6) and the overhang section (10A to 10D), and wherein the side wall metal layer (27) exposes the connecting wall. Semiconductor component according to claim 3, wherein the sidewall metal layer (27) contains a precious metal. Semiconductor component according to claim 1, wherein the metal layer (21) contains a precious metal. Semiconductor component comprising: a chip (2) having a laminated structure including a semiconductor substrate (3) and an epitaxial layer (4), a mounting surface (5) on the side of the semiconductor substrate, a non-mounting surface (6) on the side of the epitaxial layer (4), and a side wall (7a to 7D) formed by the semiconductor substrate and the epitaxial layer (4), and an overhang section (10A to 10D) which extends further outwards from a section of the side wall (7a to 7D) formed by the semiconductor substrate than the mounting surface (5);and a metal layer (21) covering the mounting surface (5), wherein the overhang section (10A to 10D) has an inner end section (12) arranged in a direction (Z) perpendicular to the mounting surface (5) on the side of the mounting surface (5), an outer end section (13) arranged in the direction (Z) on the side of the non-mounting surface (6), and a connecting section (14) connecting the inner end section (12) and the outer end section (13), and wherein the connecting section (14) has an inclined surface forming an obtuse angle with the side wall (7A to 7D) at the inner end section (12) and the outer end section (13). Semiconductor component according to claim 11, wherein the non-mounting surface (6) projects further outwards than the mounting surface (5) and wherein the overhang section (10A to 10D) points in a thickness direction of the chip towards the non-mounting surface (6). Semiconductor component according to claim 11, wherein the overhang section (10A to 10D) is formed on a section of the side wall (7A to 7D) formed from the semiconductor substrate (3), with a distance from the epitaxial layer (4) towards the side of the mounting surface (5). Semiconductor component according to claim 11, further comprising: a sidewall metal layer (27) covering the sidewall (7a to 7D). Semiconductor component according to claim 11, wherein the side wall metal layer (27) is formed at a distance from the non-mounting surface (6) towards the side of the mounting surface (5). Semiconductor component according to claim 14, wherein the sidewall metal layer (27) covers a section of the sidewall (7a to 7D) formed from the semiconductor substrate, at a distance from the epitaxial layer (4) towards the side of the mounting surface (5). Semiconductor component according to claim 14, wherein the sidewall metal layer (27) exposes the epitaxial layer (4). Semiconductor component according to claim 14, further comprising: a functional component formed in the epitaxial layer (4). Semiconductor package comprising: a die pad (103); a connection terminal (105) arranged at a distance from the die pad (103); the semiconductor component according to claim 1, arranged on the die pad (103) in an orientation in which the mounting surface (5) faces the die pad (103); and a conductive bonding material (104) arranged between the metal layer (21) and the die pad (103), bonding the semiconductor component to the die pad (103) at a distance from the non-mounting surface (6) towards the side of the mounting surface (5). Semiconductor package according to claim 19, wherein the conductive bonding material (104) covers the overhang section (10A to 10D).

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