METHOD FOR INSPECTING SEMICONDUCTOR WAFERS AND SYSTEM THEREFOR

Abstract

A method for inspecting semiconductor wafers, comprising: Scanning a semiconductor wafer (40) to acquire a scanned map (300), wherein the semiconductor wafer (40) is structured according to a design map (200) having a programmed defect (201, 301, 401, 401A, 401B); and Transforming the design map (200) and the scanned map (300) into a transformed inspection map (500) according to the position of the programmed defect (201, 301, 401, 401A, 401B) on the design map (200) and the position of the programmed defect (201, 301, 401, 401A, 401B) on the scanned map (300); wherein the method further comprises self-monitoring a transformation accuracy by comparing the position of the programmed defect (201, 301, 401, 401A, 401B) on the transformed inspection map (500) and the position of a pair of machining area markers on the transformed inspection map (500).

Description

CROSS REFERENCE TO RELATED APPLICATIONThis application claims priority to previously filed U.S. Provisional Application Serial No. 62 / 893,665, filed August 29, 2019.REGIONThe present disclosure relates to a method of inspecting semiconductor wafers and a system thereof, and more particularly to a system and method that uses programmed defects to align design layouts and scanned images prior to normal defect inspection.BACKGROUNDThe fabrication of semiconductor devices such as logic and memory devices typically involves processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. Lithography is, for example, a semiconductor manufacturing process in which a pattern is transferred from a reticle to a resist disposed on a semiconductor wafer. In some other examples, the fabrication processes may include operations such as chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an array on a single semiconductor wafer and then separated into individual semiconductor devices.Inspection processes are used at various stages during a semiconductor manufacturing process to detect defects on wafers to aid in higher yield in the manufacturing process. Inspection has always been an important component in the manufacture of semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes increasingly important for successful manufacture of acceptable semiconductor devices because minor defects can result in device failure. US 2011 / 0 116 085 A1 discloses a method for inspecting wafers.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common practice in the industry, various structures are not drawn to scale. Rather, the dimensions of the various structure may be increased or decreased as needed in the interest of clarity of discussion. FIG. 1 illustrates a flow diagram of a method for inspecting semiconductor wafers in accordance with some embodiments of the present disclosure. FIG. 2A illustrates a top view of a design card, in accordance with some embodiments of the present disclosure. FIG. 2B illustrates a top view of a design card, in accordance with some embodiments of the present disclosure. FIG. 2C illustrates a top view of a mask layer, in accordance with some embodiments of the present disclosure. FIG. 3 illustrates a top view of a scanned map, in accordance with some embodiments of the present disclosure. FIG. 4A illustrates a top view of a design card in accordance with some embodiments of the present disclosure. FIG. 4B illustrates a top view of a scanned map, in accordance with some embodiments of the present disclosure. FIG. 5 illustrates a top view of a portion of a semiconductor wafer in accordance with some embodiments of the present disclosure. FIG. 6 illustrates a top view of a transformed inspection map, in accordance with some embodiments of the present disclosure. FIG. 7 illustrates a top view of a design card in accordance with some embodiments of the present disclosure. FIG. 8A illustrates a top view of a transformed inspection map, in accordance with some embodiments of the present disclosure. FIG. 8B illustrates a top view of a transformed inspection map, in accordance with some embodiments of the present disclosure. FIG. 9 illustrates the system for inspecting semiconductor wafers according to some embodiments of the present disclosure.DETAILED DESCRIPTIONImproved methods and a system for inspecting semiconductor wafers are provided according to independent claims 1, 8 and 15. The following disclosure provides many different embodiments or examples for implementing different features of the subject matter discussed herein. Concrete examples of elements and arrangements will be described below in order to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not necessarily in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not automatically provide a relationship between the various embodiments and / or configurations discussed.Furthermore, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees, or other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections. These elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish a single element, component, region, layer, or section from each other. Terms such as "first," "second," and "third," when used herein, do not imply a sequence or order unless the context requires such meaning in a non-limiting manner.A "hotspot" is a device structure that has relatively large critical dimensions and patterning feature errors with respect to targets on wafers. To increase process yield, hot spot inspection has been developed to locate specific local structures on the cell or die surface that have excessive manufacturing anomalies. In general, a hot-spot inspection is carried out using particularly sensitive detection on exactly the local image region which corresponds to the hot-spots in the layout of the wafer. Therefore, the inspection areas of the hot spots provided during the wafer scanning must be accurately placed on the captured images.Some of the inspection tools perform the scanning using a patch design alignment (PDA) method, which first renders a layer of the design layout image into synthetic images and then aligns the rendered synthetic images with scanned images. However, this patch design alignment method presents many challenges. For example, it requires considerable computing power for rendering a synthetic image based on the design layout, because a complex image processing operation depending on dozen parameters needs to be performed. For example, when using such a patch design alignment method in a recipe inspection process, a user first selects layers of a design to be rendered. Then, a system searches the parameter space for the optimal rendering parameters that can yield the best matching images. Such complex and time-consuming operations must be repeated for each scan test of the recipe inspection.As the process is varied, the scanned images are likely to also change, such that the previously optimized rendered synthetic images may no longer match the scanned images. For example, in certain circumstances, although the design layout of the semiconductor wafer is the same, the subsequent semiconductor wafer may have a different thickness than the previous one, so that such an alignment method is not reliable because the optical images of the semiconductor wafers may be different.Accordingly, the present disclosure provides a system and method for optical inspection tools for automatically and accurately registering design images to scanned images using programmed defects (PDs) during image registration or alignment.FIG. 1 illustrates a flow diagram for inspecting a semiconductor wafer in accordance with some embodiments of the present disclosure. In some embodiments, the inspection includes an operation 101: scanning the semiconductor wafer to detect a scanned map, the semiconductor wafer being patterned according to a design map having a programmed defect; and an operation 102: transforming the design map and the scanned map into a transformed inspection map according to the position of the programmed defect on the design map and the position of the programmed defect on the scanned map.In performing operation 101, the programmed defect is designed to be formed on the semiconductor wafer. Generally, the programmed defects are defects defined as a particular structure that are not particles or other foreign material and that can be observed on the wafer using a suitable inspection tool. For example, the programmed defects are intentionally embedded in the design of the semiconductor wafer, and are intentionally created by, for example, adding or removing a portion of the structures on the design card. Such programmed defects are transferred to the semiconductor wafer through a mask having such a programmed defect pattern. As shown in FIG. 2A, which shows the design card 200 without programmed defects, the layout of the semiconductor wafer seems to have multiple stripes. In contrast, as shown in FIGS. 2B and 2C, the design card 200 having a programmed defect 201 and a mask layer 20 formed according to the design card 200 having a programmed defect 201, respectively. An opening 21 is formed on the mask layer 20 according to the programmed defect 201 of the design card 200. By a photolithography operation, the programmed defect 201 can be transferred to the semiconductor wafer.Turning to FIG. 3, a scanned image of a portion of the patterned semiconductor wafer is shown. The semiconductor wafer with the programmed defect 301 may be scanned by optical devices such as optical, laser-assisted, electron beam, or similar types of inspection tools, thereby correspondingly capturing a scanned map 300. In some embodiments, the scanned map 300 need only show a portion of the semiconductor wafer, for example a chip region on the semiconductor wafer.After the scanned card 300 is detected, the design card 200 and the scanned card 300 may be converted into a transformed inspection card according to the position of the programmed defect 201 on the design card 200 and the position of the programmed defect 301 on the scanned card 300. In some embodiments, the size, scale, and / or angle of the scanned map and the design map may be different, such that an imaging function may be introduced prior to the transformation operation to align the coordinate of the design map 200 and the coordinate of the scanned map 300. For sophisticated inspection tools with a high precision stage, the mapping function should be a linear function that involves only scaling and shifting. The scaling may be attributed to imperfect pixel size and the shift may be attributed to imperfect wafer orientation. As a result, the parameters of the linear mapping function can be determined with two anchor points per strip height. However, in less sophisticated inspection tools that have non-linear image distortion, the mapping function may be non-linear. As a result, the parameters of the nonlinear mapping function can be determined with more than two anchor points per strip height.In some embodiments, the mapping function correlates the design map coordinate and the scanned map coordinate. Referring to FIG. 4A, in some embodiments, the design map 200 may include a first coordinate plane 202, and referring to FIG. 4B, the scanned map 300 may include a second coordinate plane 302. In some embodiments, the first coordinate plane 202 and the second coordinate plane 302 may be correlated with the linear mapping function.In some embodiments, for a sophisticated inspection tool with a high precision table, the second coordinate plane 302 may be registered to the first coordinate plane 202 according to the linear mapping function. For example, the second coordinate plane 302 may be aligned with the first coordinate plane 202 by following an imaging function f(D x, D y) = ( S x, S y) where (D x, D y) is the coordinate of the design map 200 and (S x, S y) is the coordinate of the scanned map 300. Moreover, in such an example, the mapping function may be a linear function having a scaling constant and a shift constant. In some embodiments, the scaling constant is due to imperfect pixel size and the shift constant is due to imperfect wafer orientation.In some other embodiments, the first coordinate plane 202 may be registered to the second coordinate plane 302 according to the linear mapping function. In such embodiments, the coordinates of the points in the design map 200 (i.e., the programmed errors) may be transformed into new coordinates according to the linear function, and the transformed inspection map formed by registering the first coordinate plane 202 and the second coordinate plane 302 may follow either the coordination of the first coordinate plane 202 or the second coordinate plane 302. In some embodiments, both the first coordinate plane 202 and the second coordinate plane 302 are transformed into a different aligned coordinate plane than the first coordinate plane 202 and the second coordinate plane 302 to form the transformed inspection map by registering the transformed coordinate planes.In some other embodiments, the linear mapping function may be independently calculated for each strip. A strip and its follower strips may be formed in a serpentine shape, for example. Each stripe covers a stripe height which is a defined stripe area on the semiconductor wafer. In other words, the registration between the design card 200 and the scanned card 300 is performed independently for each stripe. The scaling constant and the shift constant of the linear mapping function can be determined with two anchor points per strip height. Accordingly, in some embodiments, there may be two programmed defects per stripe height on the design card and thus on the semiconductor wafer.As discussed above, the amount of programmed defects per strip may be related to the shape or quality of the optical inspection tools. In some embodiments, the optical inspection tools may perform a three-dimensional (3D) inspection and provide the scanned map in a three-dimensional image when the optical inspection tools may provide the parameters regarding depths. For example, the focus of the optical inspection tool may be adjustable, and the microstructure or nanostructure on different depth planes near the surface of the semiconductor wafer may be observed. As a result, the mapping function can be represented as f(D x, D y, D z) = ( S x, S y, S z) where the z coordinate is included and at least three programmed defects per stripe height on the semiconductor wafer are designed accordingly. In some other embodiments, in a less sophisticated optical inspection tool, the scanned card may have non-linear image distortion, and therefore it is desirable to generate or add more than two programmed defects per stripe on the semiconductor wafer in order to register the design card 200 and the scanned card 300 with such non-linear distortion.In some embodiments, after registering the design map 200 and the scanned map 300, the positions of the hot spots identified in the design map 200 in advance may be inspected on a transformed inspection map. In some embodiments, after the coordinate registration, the transformed inspection map may be a superposition of the scanned map 300 and the design map 200. As a result, the hot spots on the wafer or on a particular chip region of the wafer can be inspected by routing the inspection tool to the previously known positions of the hot spots.Refer to FIG. 5, which is a portion of the semiconductor wafer from a plan view perspective. In some embodiments, the semiconductor wafer 40 may include a plurality of chip regions 41, 42. In some embodiments, the sizes of the individual chip regions 41, 42 may not be identical to each other. For example, the chip regions 41 arranged along a direction A may have a different size than the chip regions 42 arranged along a direction B. In some embodiments, each of the chip regions 41, 42 may have a side length at least equal to a stripe height H S. In some embodiments, the programmed defects 401, which are the physical defects of the chip regions, are configured to form near two opposing boundaries of each of the chip regions 41, 42. As shown in FIG. 5, in some embodiments, the chip regions 41, 42 may be scanned from one boundary to another boundary with the stripe height H S in a single stripe, and thus at least two programmed defects 401 per stripe may be covered when the scanning of a particular chip region 41 or 42 of a semiconductor wafer is performed.In some embodiments, only different chip regions 41, 42 need to have programmed defects so that inspection can be performed on the chips of interest rather than on the entire chip. In some embodiments, for each strip and prior to the actual defect detection, cell-to-cell (C2C) detection may be performed on local areas in the captured scanned image where the programmed defects are located.FIG. 6 is a transformed inspection map 500 according to some embodiments of the present disclosure. For reasons of clarity, only the programmed fault structure is shown on the transformed inspection card 500. As shown in FIG. 6, the transformed inspection map 500 includes the information regarding the expected location 502 of the programmed defect on the design map and the actual location 503 of the programmed defect on the scanned map, both of which are represented under the transformed inspection map coordinate based on the linear or non-linear mapping function discussed above. Accordingly, an offset 504 between the expected position 502 and the actual position 503 of the programmed defect may be determined, and if such an offset 504 is not zero, in some embodiments, the offset 504 is considered in the imaging calculation of the next strip to obtain a more accurate imaging result. Alternatively, the offset identification performed in situ may feedback the mapping accuracy in the previous swath instantaneously to optimize the mapping result in the subsequent swath.In some embodiments, the method of inspecting semiconductor wafers of the present disclosure further includes an operation of self-monitoring the transformation accuracy by comparing the position of the programmed defect on the transformed inspection map and the positions of a pair of processing area marks on the transformed inspection map. As shown in FIG. 7, the pair of machining area marks 203, 204 may be included in the design map 200, with the pair of machining area marks 203, 204 being symmetrically disposed with respect to the expected position of the programmed defect 201. For example, in some embodiments, the programmed defect 201 is located at the origin of the first coordinate plane 202, and a first machining area marker 203 is located in the first quadrant of the first coordinate plane 202, while the second machining area marker 204 is located in the third quadrant of the first coordinate plane 202. In some embodiments, the first processing area mark 203 and the second processing area mark 204 are symmetrically located on two sides of the x coordinate. In some embodiments, the first processing area mark 203 and the second processing area mark 204 are symmetrically located on two sides of the y coordinate. In some embodiments, a bottom 203LO of the first machining area mark 203, the expected position of the programmed defect 201, and a top 204U of the second machining area mark 204 are collinear. In some embodiments, a left side 203LFof the first machining area marker 203, the expected position of the programmed defect 201, and a right side 204R of the second machining area marker 204 are collinear. In some embodiments, the expected position of the programmed defect 201 is between opposing corners of the first processing area mark 203 and the second processing area mark 204.Although the position coordinate of the programmed defect in the design map 200 may be known in advance, it is not readily observed on the transformed inspection map. In some embodiments, after transforming the design map 200 and the scanned map 300 into a transformed inspection map using the pair of processing area marks as references, in-place image accuracy feedback may be referred to the pair of processing area marks and the nearby programmed defect. Referring to FIG. 8A, FIG. 8A illustrates a top view of a transformed inspection map obtained from the design map of FIG. 7. The expected position 502 and the actual position 503 of the programmed defect 201 in the transformed inspection map 500 may be considered to overlap, meaning that the registration between the scanned map and the design map based on the previous stripe is accurate. In contrast, FIG. 8B shows an example that the detected programmed defect does not overlap with the expected programmed defect. There is an offset 504 between the expected position 502 and the actual position 503 of the programmed defect 201. In such circumstances, the first processing area marker 203 and the second processing area marker 204 may be used to return the transformed result of the design map and the scanned map in place, since the intersection of the processing area markers 203 and 204 indicates the expected location 502 of the programmed defect. In some embodiments, an image processing algorithm may be implemented to define the intersections of the processing area markers 203 and 204 to identify the expected position 502 of the programmed defect. The self-monitoring of the transformation accuracy may be performed by comparing the position of the detected or scanned programmed defect 201 on the transformed inspection map 500 and the position of the pair of machining area marks 203 and 204 on the transformed inspection map 500.For example, after the actual position 503 of the programmed defect 201 is detected according to the transformed inspection map 500, the system described later may use an image processing algorithm to find the corners 203A, 204A of the first machining area mark 203 and the second machining area mark 204 in the transformed inspection map 500 in the vicinity of the programmed defect 201. The center between the two opposing corners 203A, 204A is the expected position 502 of the programmed defect 201. Thus, the offset between the actual position 503 and the expected position 502 of the programmed defect 201 may be measured to determine the imaging accuracy. Moreover, the imaging accuracy can be fed back and taken into account in the imaging calculation of the subsequent strip.In some embodiments, the pair of processing area markers 203, 204 may be replaced with a reticle as a reference to indicate the expected position of the programmed defect on the transformed inspection map, as previously shown in FIG. 6.To perform the above-mentioned method for inspecting semiconductor wafers as shown in FIG. 9, the system 60 for inspecting semiconductor wafers of the present disclosure includes at least a computing device 601, a patterning device 602, and an inspection device 603 in some embodiments. In some embodiments, both the structuring device 602 and the inspection device 603 are coupled to the computing device 601.In some embodiments, computing device 601 is configured to provide design map 200 having a first programmed defect at the expected position, as shown in FIG. 2B previously shown. In some embodiments, computing device 601 is further configured to generate transformed inspection map 500 to determine the offset between the expected position and the actual position, as shown in FIG. 8B previously shown.In some embodiments, the patterning device 602 is configured to form the first programmed defect on the semiconductor wafer 40 according to the design map. Generally, lithography techniques may be used to transfer the programmed defect pattern of the mask to the semiconductor wafer 40. Lithography techniques can generally include X-ray, ion, electron beam or optical techniques. These methods are known in the industry under various trade names of their tools. In some embodiments, the lithography techniques may use dry or wet processing.In some embodiments, the inspection device 603 is configured to scan the semiconductor wafer 40 to detect the scanned map. In some implementations, the inspection device 603 may be an optical device, such as an optical, laser-assisted, electron beam, or similar type of inspection tool. In some embodiments, the inspection device 603 may be a scanning electron microscope (SEM) used to determine the size and positions of the programmed nano- or micro-sized defects. In some embodiments, after registering the scanned map and the design map, the hot spots of the semiconductor wafer may be inspected by the inspection device 603 by locating the inspection device 603 at the previously known locations of the hot spots.In some embodiments, the inspection device 603 may include a light source. The light source may be any suitable light source known in the art, such as a broadband plasma light source. In some embodiments, the inspection device 603 may further include a beam splitter and a refractive optical element (ROE), wherein light from the light source may be reflected by the beam splitter to the refractive optical element. Accordingly, the light from the light source can be directed at the semiconductor wafer at any suitable angle of incidence. In some embodiments, the inspection device 603 may further include some other suitable optical elements such as filters or polarizers. Moreover, the light reflected from the semiconductor wafer 40 can be collected by the inspection device 603 through the above-mentioned refractive optical element and the beam splitter. In some embodiments, the optical detector may be any suitable optical detector, such as a charge coupled device (CCD). The optical detector may provide the output with respect to the scanned map as mentioned above. In some embodiments, the form of output may include signals, signal data, images, image data, and any other suitable output.In addition to the first programmed defect, in some embodiments, the design card may further include a second programmed defect, and the second programmed defect is formed on the semiconductor wafer 40 by the patterning device 602 and then scanned by the inspection device 603. Moreover, as previously shown in FIG. 5, in some embodiments, the first programmed defect 401A and the second programmed defect 401B are within a scan stripe height H S of the inspection device 603. In other words, the first programmed defect 401A and the second programmed defect 401B are the two anchor points in determining the scaling constant and the displacement constant of the linear mapping function in some embodiments.In accordance with the present disclosure, the method of inspecting semiconductor wafers using programmed defects is disclosed. The programmed defects may be inserted at multiple strategic locations during the layout design of the die. Next, the programmed defects may be detected in the scanned images during the inspection process and used as anchors to register the design layout on the scanned image. Moreover, during registering the design layout and the scanned image with programmed defects, a field-implemented mechanism for monitoring imaging accuracy may be implemented by identifying an offset between the actual and expected positions of the programmed defects on the transformed inspection map. In some embodiments, using a pair of processing area markers in the transformed inspection map allows in-place imaging accuracy feedback to be achieved in a simpler and more efficient manner.In an exemplary aspect, a method for inspecting semiconductor wafers is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed into a transformed inspection map according to the position of the programmed defect on the design map and the position of the programmed defect on the scanned map. The method further includes self-monitoring transformation accuracy by comparing the position of the programmed defect on the transformed inspection map and the position of a pair of machining area marks on the transformed inspection map.In another exemplary aspect, a method of inspecting semiconductor wafers is provided. The method includes the following operations. A programmed defect is formed on the semiconductor wafer according to an expected position on a design map. A semiconductor wafer is scanned to acquire a scanned map. An actual position of the programmed defect on the scanned map is detected. Based on the design map and the scanned map, a transformed inspection map is obtained to determine an offset between the expected position and the actual position. The design map includes a first coordinate plane and the scanned map includes a second coordinate plane, wherein the first coordinate plane and the second coordinate plane are correlated with a linear mapping function.In another exemplary aspect, a system for inspecting semiconductor wafers is provided. The system includes a computing device, a structuring device, and an inspection device. The computing device is configured to provide a design map having a first programmed defect at an expected location. The patterning device is coupled to the computing device and is configured to form the first programmed defect at an actual position of the semiconductor wafer according to the design map. The inspection device is coupled to the computing device and is configured to scan the semiconductor wafer to detect a scanned map. The computing device is further configured to generate a transformed inspection map to determine an offset between the expected position and the actual position. Self-monitoring of transformation accuracy is performed by comparing the position of the programmed defect on the transformed inspection map and the position of a pair of machining area marks on the transformed inspection map.

Claims

A method for inspecting semiconductor wafers, comprising: scanning a semiconductor wafer (40) to acquire a scanned card (300), wherein the semiconductor wafer (40) is structured according to a design card (200) having a programmed defect (201, 301, 401, 401A, 401B); and transforming the design card (200) and the scanned card (300) into a transformed inspection card (500) according to the position of the programmed defect (201, 301, 401, 401A, 401B) on the design card (200) and the position of the programmed defect (201, 301, 401, 401A, 401B) on the scanned card (300); wherein the method further comprises self-monitoring transformation accuracy by comparing the position of the programmed defect (201, 301, 401, 401A, 401B) on the transformed inspection map (500) and the position of a pair of machining area marks on the transformed inspection map (500).The method according to claim 1, wherein the pair of machining area marks are arranged symmetrically with respect to the programmed defect (201, 301, 401, 401A, 401B) on the design card (200) and indicate an expected position (502) of the programmed defect (201, 301, 401, 401A, 401B).The method of claim 2, wherein comparing the position of the programmed defect (201, 301, 401, 401A, 401B) on the transformed inspection map (500) and the positions of the pair of machining area marks comprises obtaining an offset between the expected position (502) of the programmed defect (201, 301, 401, 401A, 401B) and the position of the programmed defect (201, 301, 401, 401A, 401B) on the transformed inspection map (500).The method of claim 3, further comprising updating the transformed inspection map (500) according to the offset (504).The method of any preceding claim, wherein scanning the semiconductor wafer (40) comprises scanning through at least two programmed defects (201, 301, 401, 401A, 401B) per stripe height.The method according to any one of the preceding claims 1 to 5, wherein the programmed defects (201, 301, 401, 401A, 401B) are located at a boundary of a chip region (41, 42) on the design card (200).The method of any one of the preceding claims 1 to 5, wherein the programmed defects (201, 301, 401, 401A, 401B) are in repeating structures of the design card (200).A method for inspecting semiconductor wafers, comprising: forming a programmed defect (201, 301, 401, 401A, 401B) on a semiconductor wafer (40) according to an expected position (502) on a design map (200); scanning the semiconductor wafer (40) to detect a scanned map (300); detecting an actual position (503) of the programmed defect (201, 301, 401, 401A, 401B) on the scanned map (300); Obtaining a transformed inspection map (500) based on the design map (200) and the scanned map (300) to determine an offset (504) between the expected location and the actual location, wherein the design map (200) comprises a first coordinate plane (202) and the scanned map (300) comprises a second coordinate plane (302), wherein the first coordinate plane (202) and the second coordinate plane (302) are correlated with a linear mapping function.The method of claim 8, wherein forming the programmed defect (201, 301, 401, 401A, 401B) comprises: forming an opening (21) in a mask layer (20); and patterning the semiconductor wafer (40) through the mask layer (20).The method according to claim 8 or 9, wherein the design map (200) further comprises two machining area marks arranged symmetrically with respect to the expected position (502) of the programmed defect (201, 301, 401, 401A, 401B).The method of claim 10, wherein the expected position (502) of the programmed defect (201, 301, 401, 401A, 401B) is between opposing corners of the two machining area marks.The method of claim 10 or 11, wherein the scanned map (300) comprises at least two programmed defects (201, 301, 401, 401A, 401B) per swath.The method of claim 12, wherein obtaining the transformed inspection map (500) comprises: resolving the linear mapping function based on the expected position (502) and the actual position (503) of the programmed defect (201, 301, 401, 401A, 401B); and transforming the scanned map (300) into the transformed inspection map (500) according to the linear mapping function.The method of claim 13, wherein transforming the scanned map (300) into the transformed inspection map (500) comprises: scaling and translating the second coordinate plane (302).A system for inspecting semiconductor wafers, comprising: a computing device (601) configured to provide a design map (200) having a first programmed defect (201, 301, 401, 401A, 401B) at an expected position (502); a patterning device (602) coupled to the computing device (601) and configured to form the first programmed defect (201, 301, 401, 401A, 401B) at an actual position (503) of a semiconductor wafer (40) according to the design map (200); and an inspection device (603) coupled to the computing device (601) and configured to scan the semiconductor wafer (40) to detect a scanned map (300); wherein the computing device (601) is further configured to generate a transformed inspection map (500) to determine an offset (504) between the expected position (502) and the actual position (503); and wherein self-monitoring of a transformation accuracy is performed by comparing the position of the programmed defect (201, 301, 401, 401A, 401B) on the transformed inspection map (500) and the position of a pair of machining area marks on the transformed inspection map (500).The system of claim 15, wherein the design card (200) further comprises a second programmed defect (201, 301, 401, 401A, 401B), and the second programmed defect (201, 301, 401, 401A, 401B) is formed on the semiconductor wafer (40) by the patterning device (602) and scanned by the inspection device (603).The system of claim 16, wherein the first programmed defect (201, 301, 401, 401A, 401B) and the second programmed defect (201, 301, 401, 401A, 401B) are within a scan stripe height of the inspection device (603).The system according to any one of the preceding claims 15 to 17, wherein the inspection device (603) is further configured to detect a hot spot of the semiconductor wafer (40), wherein the actual position (503) of the first programmed defect (201, 301, 401, 401A, 401B) is not overlapped within the hot spot of the semiconductor wafer (40).

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