Selective hybrid capping layer for metal gates of transistors and manufacturing processes

Abstract

Procedure with the following steps: Creating a gate electrode (74) over a semiconductor area (20); Recessing the gate electrode (74) to create a recess (80); Performing a first deposition process to produce a first metal layer (84A) on the gate electrode (74) and in the recess (80), wherein the first deposition process is carried out using a first precursor; Performing a passivation process using N2; Performing a second deposition process to produce a second metal layer (84B) on top of the first metal layer (84A) using a second precursor that is different from the first precursor, wherein the first metal layer (84A) and the second metal layer (84B) are of the same metal; Producing a dielectric hard mask (88) over the second metal layer (84B); and Producing a gate contact pin (90) such that it penetrates the dielectric hard mask (88), wherein the gate contact pin (90) contacts a top surface of the second metal layer (84B).

Description

background

[0001] Metal oxide semiconductor (MOS) devices are fundamental building blocks in integrated circuits. A conventional MOS device typically features a gate electrode made of polysilicon doped with p- or n-type dopants via doping processes such as ion implantation or thermal diffusion. The work function of the gate electrode can be matched to the silicon band edge. In an n-type metal oxide semiconductor (NMOS) device, the work function can be closely matched to the silicon conduction band. In a p-type metal oxide semiconductor (PMOS) device, the work function can be closely matched to the silicon valence band. Matching the work function of the polysilicon gate electrode can be achieved by selecting appropriate dopants.

[0002] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as the polysilicon depletion effect. This effect occurs when applied electric fields remove carriers from gate regions near the gate dielectric, resulting in depletion layers. In an n-doped polysilicon layer, the depletion layer contains ionized, non-mobile donor sites, while in a p-doped polysilicon layer, the depletion layer contains ionized, non-mobile acceptor sites. The depletion effect leads to an increase in the effective gate dielectric thickness, which hinders the formation of an inversion layer on the semiconductor surface.

[0003] The problem of polysilicon depletion can be solved by manufacturing metal-gate electrodes, whereby the metal gates used in NMOS and PMOS devices can also have strip-edge exit work. Accordingly, the resulting metal gates have multiple layers to meet the requirements of the NMOS and PMOS devices.

[0004] US 2014 / 0353734 A1 describes semiconductor structures with reduced gate and / or contact resistances and methods for their fabrication. US 2019 / 0096679 A1 describes gate stack structures. US 2017 / 0077256 A1 describes metal cap protective layers for gate and contact metallization. US 2018 / 0175201 A1 describes FinFET structures and methods for their fabrication. Brief description of the drawings

[0005] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. The Fig. Figures 1 to 6, 7A, 7B, 8A, 8B, 9 to 19, 20A and 20B show sectional views and perspective representations of intermediate stages in the manufacture of a fin field-effect transistor (FinFET) according to some embodiments. Fig. Figure 21 shows a top view of a FinFET according to some embodiments. Fig. Figure 22 shows a distribution of some elements according to some embodiments. Fig. Figure 23 shows a flowchart of a process flow for manufacturing a FinFET according to some embodiments. Detailed description

[0006] The present disclosure solves the problem underlying the application through the subject matter of the claims. The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples. For instance, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0008] According to some embodiments, transistors with hybrid encapsulation layers and methods for their fabrication are provided. A first low-resistance conductive layer is fabricated over and in contact with a recessed metal gate. This first low-resistance conductive layer serves as a seed layer, allowing for the selective fabrication of a second low-resistance conductive layer to achieve a desired thickness. The low-resistance conductive layers have resistance values ​​lower than those of at least some layers in the metal gate, thus reducing the overall gate resistance of the metal gate. The intermediate stages of transistor fabrication are described in some embodiments, and some variations of certain embodiments are discussed.In all illustrations and explanatory embodiments, similar reference numerals are used to designate similar elements. Furthermore, some embodiments may be discussed as those carried out in a specific sequence, while other embodiments may be carried out in any logical order. In some embodiments, the fabrication of FinFETs is used as an example to illustrate the principle of the present invention. The principle of the present invention can also be applied to other types of transistors, such as planar transistors. In some embodiments of the present invention, a metal (substitute) gate for a FinFET is fabricated. The metal gate is then etched and recessed, creating a cavity.

[0009] The Fig. Figures 1 to 6, 7A, 7B, 8A, 8B, 9 to 19, 20A and 20B show sectional views and perspective representations of intermediate steps in the fabrication of FinFETs according to some embodiments of the present invention. The steps shown in these figures are also schematically indicated in the process flow 200, which is described in Fig. 23 is shown.

[0010] In Fig. 1. A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The semiconductor substrate 20 can be part of a wafer 10, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise: silicon; germanium; a compound semiconductor, such as carbon-doped silicon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0011] Let's stay with Fig. 1. A trough area 22 is produced in the substrate 20. The corresponding step is specified as step 202 in the process flow 200, which is described in Fig. Figure 23 shows that in some embodiments of the present invention, the well region 22 is a p-well region produced by implanting a p-doping agent, such as boron, indium, or the like, into the substrate 20. In other embodiments of the present invention, the well region 22 is an n-well region produced by implanting an n-doping agent, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. The resulting well region 22 may extend from a top surface of the substrate 20. The n- or p-doping concentration may be equal to or less than 10 18 cm -3 be and can be about 10 17 cm -3 up to about 10 18 cm -3 be.

[0012] In Fig. 2 Insulation zones 24 are produced such that they extend from the top of the substrate 20 into the substrate 20. The insulation zones 24 are subsequently referred to alternatively as STI zones (STI: shallow trench insulation). The corresponding step is specified as step 204 in the process flow 200, which is described in Fig. Figure 23 shows the portions of the substrate 20 between adjacent STI regions 24, which are referred to as semiconductor strips 26. To fabricate the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are produced on the semiconductor substrate 20 and subsequently patterned. The pad oxide layer 28 can be a thin layer made of silicon oxide. In some embodiments of the present invention, the pad oxide layer 28 is produced in a thermal oxidation process in which a surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesive layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also act as an etch stop layer for etching the hard mask layer 30.In some embodiments of the present invention, the hard mask layer 30 is produced from silicon nitride, for example, by low-pressure gravure chemical vapor deposition (LPCVD). In other embodiments of the present invention, the hard mask layer 30 is produced by thermal nitriding of silicon or by plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is produced on the hard mask layer 30 and subsequently patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to produce patterned hard masks 30, as shown in [reference]. Fig. 2 is shown.

[0013] The structured hard mask layer 30 is then used as an etching mask for etching the pad oxide layer 28 and the substrate 20. Subsequently, the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a mechanical grinding process, is then performed to remove excess dielectric materials, and the remaining dielectric materials are the STI regions 24. The STI regions 24 may have a dielectric coating (not shown), which may be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20.The dielectric coating can also be a deposited silicon oxide layer, silicon nitride layer, or the like, produced, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or chemical vapor deposition (CVD). The STI areas 24 can also have a dielectric material over the oxide coating, wherein the dielectric material can be deposited by flowable chemical vapor deposition (FCVD), spin coating, or the like. In some embodiments, the dielectric material over the dielectric coating can be silicon oxide.

[0014] The top surfaces of the hard masks 30 and the top surfaces of the STI regions 24 can be essentially at the same level. Semiconductor strips 26 are located between adjacent STI regions 24. In some embodiments of the present invention, the semiconductor strips 26 are parts of the original substrate 20, and therefore the material of the semiconductor strips 26 is the same as that of the substrate 20. In alternative embodiments of the present invention, the semiconductor strips 26 are substitute strips produced by etching the parts of the substrate 20 between the STI regions 24 to create recesses and performing an epitaxial process to grow further semiconductor material in the recesses. Accordingly, the semiconductor strips 26 are produced from a semiconductor material different from that of the substrate 20.In some embodiments, the semiconductor strips 26 are made of silicon germanium, silicon-carbon, or a III-V compound semiconductor material. Then the hard masks 30 are removed.

[0015] In Fig. 3. The STI areas 24 are left out so that upper parts of the semiconductor strips 26 protrude over top surfaces 24A of the remaining parts of the STI areas 24, forming protruding fins 36. The corresponding step is specified as step 206 in the process sequence 200, which is described in Fig. Figure 23 shows that the pad oxides 28 are also removed. The etching can be carried out using a dry etching process, in which, for example, NF3 and NH3 are used as etching gases. A plasma can be generated during the etching process. Argon can also be used. In alternative embodiments of the present invention, the removal of the STI areas 24 can be carried out using a wet etching process. For example, HF can be used as the etching chemical.

[0016] In the embodiments described above, the fins can be structured using any suitable method. For example, the fins can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers, or thorns, can then be used to structure the fins.

[0017] In Fig. 4. Dummy gate stacks 38 are manufactured such that they extend onto the surfaces and sidewalls of the (protruding) fins 36. The corresponding step is specified as step 208 in the process flow 200, which is described in Fig. Figure 23 shows that the dummy gate stacks 38 can comprise dummy gate dielectrics 40 and dummy gate electrodes 42 over the dummy gate dielectrics 40. The dummy gate dielectrics 40 can be made of silicon oxide or similar materials. The dummy gate electrodes 42 can be made, for example, using polysilicon, but other materials can also be used. The dummy gate stacks 38 can each comprise one or more hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 can be made of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stacks 38 can extend over one or more of the projecting fins 36 and / or STI areas 24. The dummy gate stacks 38 can also have longitudinal directions that are perpendicular to longitudinal directions of the projecting fins 36.

[0018] Then, gate spacers 46 are manufactured on the side walls of the dummy gate stacks 38. The corresponding step is also specified as step 208 in process flow 200, which is described in Fig. Figure 23 shows that in some embodiments of the present invention, the gate spacers 46 are made of one or more dielectric materials, such as porous silicon oxide nitride, porous silicon carbonitride, porous silicon nitride, or the like, and they can have a single-layer structure or a multi-layer structure with a plurality of dielectric layers. The dielectric constant (k-value) of the gate spacers 46 is lower than 3.8 and can be lower than about 3.0, and can be, for example, about 2.5 to about 3.0.

[0019] Then an etching process is carried out to etch the parts of the protruding fins 36 that are not covered by the dummy gate stacks 38 and the gate spacers 46, so that the in Fig. The structure shown in section 5 is created. The corresponding step is indicated as step 210 in process flow 200, which is in Fig. Figure 23 shows that the recess can be anisotropic, and therefore portions of the fins 36 directly beneath the dummy gate stacks 38 and the gate spacers 46 are protected and not etched. In some embodiments, the top surfaces of the recessed semiconductor strips 26 can be lower than the top surfaces 24A of the STI areas 24, creating recesses 50. The recesses 50 include portions located on opposite sides of the dummy gate stacks 38 and portions between remaining portions of the projecting fins 36.

[0020] Then, epitaxial regions (source / drain regions) 54 are produced by selective growth (by epitaxy) of a semiconductor material in the recesses 50, so that the in Fig. The structure shown in Figure 6 is created. The corresponding step is indicated as step 212 in process flow 200, which is in Fig. Figure 23 shows that, depending on whether the resulting FinFET is a p- or an n-FinFET, a p- or an n-type dopant can be grown in situ during epitaxy. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. Conversely, if the resulting FinFET is an n-FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. In alternative embodiments of the present invention, the epitaxial regions comprise 54 III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the recesses 50 have been filled with the epitaxial areas 54, the further epitaxial growth of the epitaxial areas 54 causes them to expand horizontally, and bevels may be formed.Furthermore, as the epitaxial areas 54 continue to grow, adjacent epitaxial areas 54 can fuse together. This can create cavities (air gaps) 56. In some embodiments of the present invention, the production of the epitaxial areas 54 can be stopped when the upper surface of the epitaxial areas 54 is still wavy, or when the upper surface of the fused epitaxial areas 54 has become planar, which is achieved by further growth of the epitaxial areas 54, as shown in [reference]. Fig. 6 is shown.

[0021] Following the epitaxy process, the epitaxy regions 54 can be further doped with a p- or n-type dopant to create source and drain regions, which are also designated by the reference number 54. In alternative embodiments of the present invention, the implantation step is omitted if the epitaxy regions 54 are doped in situ with the p- or n-type dopant during epitaxy.

[0022] Fig. Figure 7A shows a perspective view of the structure after the fabrication of a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. The corresponding step is indicated as step 214 in the process flow 200, which is described in Fig. Figure 23 shows that the CESL 58 can be fabricated from silicon nitride, silicon oxide, silicon carbon nitride, or the like by CVD, ALD, or the like. The ILD 60 can be a dielectric material deposited, for example, by FCVD, spin coating, CVD, or another deposition process. The ILD 60 can be fabricated from an oxygen-containing dielectric material, which can be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, can be performed to bring the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacer 46 to the same height. Fig. 7B shows the reference cross-section 7B - 7B of Fig. 7A according to some embodiments, wherein only one of the dummy gate stacks 38 is shown.

[0023] After the in the Fig. 7A and Fig. The structures shown in Figure 7B have been manufactured, and the dummy gate stacks 38 can be replaced by metal gates and replacement gate dielectrics, as shown in the Fig. Figures 8A, 8B and 9 to 12 are shown. In later figures, the top surfaces 24A of the STI regions 24 are shown to indicate the position of the semiconductor fin 36, which projects beyond the top surfaces 24A of the STI regions 24.

[0024] To manufacture the replacement gates, the hard mask layer 44, the dummy gate electrode 42 and the dummy gate dielectric 40, which are in Fig. shown in 7B, removed, creating openings 59 which are located in the Fig. 8A and Fig. 8B are shown. The corresponding step is indicated as step 216 in process flow 200, which is shown in Fig. 23 is shown. The top and side walls of the projecting fin 36 are exposed to the openings 59.

[0025] Then in Fig. 9 a gate dielectric 61 is produced which extends into the openings 59. The corresponding step is specified as step 218 in the process flow 200, which is described in Fig. Figure 23 shows that in some embodiments of the present invention, the gate dielectric 61 has an interface layer (IL) 62 produced on the exposed top and sidewall surfaces of the projecting fin 36. The IL 62 can be an oxide layer, such as a silicon oxide layer, produced by thermal oxidation of the projecting fin 36, a chemical oxidation process, or a deposition process. The gate dielectric 61 can also have a high-k dielectric layer 64 over the IL 62. The high-k dielectric layer 64 can be made of a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, a combination thereof, multiple layers thereof, or the like. The dielectric constant (k-value) of the high-k dielectric material is greater than 3.9 and can be greater than about 7.0, and can occasionally even be 21.0 or more.The dielectric high-k layer 64 is arranged above the IL 62 and can contact it. The dielectric high-k layer 64 is produced as a conformal layer and extends onto the side walls of the projecting fin 36 and the top and side walls of the gate spacers 46. In some embodiments of the present invention, the dielectric high-k layer 64 is produced by ALD, CVD, or the like.

[0026] In some embodiments, an adhesive layer 65 (which is also a diffusion barrier layer) is produced over the dielectric high-k layer 64. The corresponding step is specified as step 220 in the process sequence 200, which is described in Fig. Figure 23 shows that the adhesive layer 65 can be made of TiN or titanium silicon nitride (TSN). The TiN layer can be produced by ALD or CVD, and the TSN layer can comprise alternating deposited TiN and SiN layers, produced, for example, by ALD. Because the TiN and SiN layers are very thin, these layers may not be distinguishable from one another, and therefore they are referred to as a single TSN layer. In alternative embodiments, the adhesive layer 65 is not produced, and the exit work layer produced subsequently is in contact with the dielectric high-k layer 64. Step 220 in Fig. Figure 23 is represented by a dashed box to indicate that this step can be performed or omitted. In later figures, the adhesive layer 65 is not shown, although it may or may not be produced.

[0027] In the Fig. 10 and Fig. 11. An exit working layer 66 is produced by deposition. The corresponding step is specified as step 222 in process flow 200, which is in Fig. 23 is shown. The exit working layer 66 has at least one homogeneous layer (such as a sublayer 66A in Fig. 10) which is made entirely of one and the same material, or it may comprise multiple sublayers made of different materials. The materials for the one or more layers in the output work layer 66 can be chosen depending on whether the FinFET being fabricated is an n- or a p-FinFET. For example, if the FinFET is an n-FinFET, the output work layer 66 may be an n-type output work layer, which may be an Al-based layer made of, for example, TiAl, TiAlN, TiAlC, TaAlN, TaAl, TaAlC, or the like, or multiple layers thereof. If the adhesive layer 65 is not fabricated, a titanium nitride (TiN) layer (not shown) may (or may not) be fabricated between (and in contact with) the n-type output work layer and the dielectric high-k layer 64 to adjust the output work.If the FinFET is a p-FinFET, the corresponding exit function layer 66 can be a p-exit function layer, such as a TiN layer, a tungsten carbon nitride (WCN) layer, or the like.

[0028] In some embodiments, the exit working layer 66 can comprise sublayer 66A and sublayer 66B, as shown in Fig. Figure 11 shows. For example, an output work layer 66 of an n-FinFET can comprise an n-output work layer (shown as 66A) and a p-output work layer (shown as 66B) above the n-output work layer, the n-output work layer determining the output work of the respective FinFET and being fabricated concurrently with the p-output work layer for a p-FinFET.

[0029] As in Fig. As shown in Figure 11, in alternative embodiments, the output work layer of a p-FinFET can also comprise a p-output work layer (shown as 66A) and an n-output work layer (shown as 66B) above the p-output work layer, wherein the p-output work layer determines the output work of the respective FinFET and is fabricated simultaneously with the n-output work layer for an n-FinFET. In subsequent exemplary figures, output work layers 66A and 66B are both shown, but in some embodiments, only one output work layer may be used.

[0030] In some embodiments of the present invention, a blocking layer 70 (which is an adhesive layer) is produced above the exit working layer 66. The corresponding step is specified as step 224 in the process sequence 200, which is described in Fig. Figure 23 shows that the blocking layer 70 can be a metal-containing layer, which in some embodiments can be made of TiN. Other materials, such as TaN, can also be used. In some embodiments, the blocking layer 70 is produced by ALD, CVD, or the like. In some embodiments, the blocking layer 70 completely fills the remaining opening 59 ( Fig. 8B). In alternative embodiments, a gap-filling process is carried out to fill the remaining opening 59 with a filler metal, which may be tungsten, cobalt or the like.

[0031] After the opening 59 has been completely filled, a planarization process, such as a CMP process or a mechanical polishing process, is carried out to remove excess parts of the deposited layers, as in Fig. 11 is shown, so that a gate stack 76 is created, which is in Fig. 12 is shown. The corresponding step is indicated as step 226 in process flow 200, which is shown in Fig. Figure 23 shows the gate stack 76 comprising the gate dielectric 61 and a gate electrode 74.

[0032] The Fig. 13 and Fig. Figure 14 shows the processes for omitting the gate stack 76. The corresponding step is indicated as step 228 in the process flow 200, which is in Fig. 23 is shown. Fig. Figure 13 shows a first back-etching process 78 performed on the gate stack 76 and the gate spacers 46, the etching being indicated by arrows. This creates a recess 80. The first back-etching process can comprise a dry etching process and / or a wet etching process. Furthermore, the etching can be isotropic or anisotropic. In some embodiments of the present invention, the first back-etching process is performed using an etchant that etches the gate spacers 46 and the gate stack 76, but not the CESL 58 and the ILD 60. In some embodiments, when a dry etching process is used, the etching gases can contain fluorine-based etchants, such as CF4, C2F6, or NF3, or the like, or a combination thereof. In some embodiments, when a wet etching process is used, the etching chemical may be diluted HF solution, NH4OH (aqueous ammonia solution) or a combination thereof.In some embodiments, after the first etching process, the gate stacks 76 have a height H1 that can range from approximately 10 nm to approximately 40 nm. A vertical distance from the top of a projecting fin 136 (or 236) to the top of the ILD 60 is shown as H2. The ratio H1 / H2 can be approximately 1 / 3 to approximately 1 / 2. A recess depth D1 can range from approximately 50 nm to approximately 80 nm. It is understood that the value of the recess depth D1 must not be too high or too low. If the value is too high, some parts (such as the parts directly above the projecting fin 36) of the gate stack 76 may be adversely removed, leading to fixture failure. If the value is too low, the recess will not be large enough to accommodate the self-aligned hard mask in subsequent processes.

[0033] As in Fig. As shown in Figure 13, in some embodiments the gate spacers 46 are recessed by the first etching process 78. In alternative embodiments, the gate spacers 46 are not recessed by the first etching process 78, with dashed lines 46' being used to show the upper parts of the gate spacers 46 that remain after the first etching process 78.

[0034] After the in Fig. In the first etching process 78 shown in 13, a second etching process 78' can be carried out, which in Fig. Figure 14 shows that this creates a recess 81 between opposing parts of the corresponding dielectric high-k layer 64. The second etching process 78' is carried out using an etching gas or etching chemical solution different from those used in the first etching process 78. The second etching process 78' can comprise a dry etching process and / or a wet etching process. Furthermore, the etching can be isotropic or anisotropic. In some embodiments of the present invention, the second etching process is carried out using an etchant that etches the gate electrode 74 but not the gate spacers 46, the dielectric high-k layer 64, the CESL 58, and the ILD 60. In some embodiments, when a dry etching process is used, the etching gases can be BCl3, Cl2, or WF6, or a combination thereof.In some embodiments, if a wet etching process is used, the etching chemical may be NH4OH or the like. In some embodiments, the recess depth D2 is approximately 4 nm to approximately 8 nm. It is understood that the value of the recess depth D2 must not be too high or too low. If the value is too high, some parts of the gate electrode 74 may be adversely removed, leading to device failure. If the value is too low, the recess is not large enough to allow for subsequent filling with conductive layers of low resistivity. In some embodiments, the height H3 of the gate stack 76 after the second back-etching process 78' is approximately 5 nm to approximately 30 nm.

[0035] Due to the selectivity of the etching agent for different materials, a top surface 46TS of the gate spacers 46 can be at the same height as, or higher or lower than, top surfaces 64TS of the dielectric high-k layer 64.

[0036] Fig. Figure 15 shows a passivation process 82, which is carried out in some embodiments. The corresponding step is specified as step 230 in the process sequence 200, which is described in Fig. Figure 23 shows that in some embodiments, if dry etching is used in the back-etch processes 78 and 78', the material for the gate electrode 74 can be re-dusted onto the dielectric high-k layer 64, the gate spacers 46, the CESL 58, and the ILD 60. However, this can lead to problems. For example, the re-dusted materials become a seed layer for low-resistance layers 84A and 84B ( Fig. 18), which are subsequently selectively deposited so that the layers 84A and 84B with low resistivity are grown in undesired locations. In addition, these materials can prevent an electrical short circuit between the gate electrode 74 and other conductive structural elements, such as contact pins 94 ( Fig. 20A). Therefore, a passivation process is carried out to improve the selectivity in the subsequent deposition processes and to convert the re-dusted materials (if any) into dielectric materials. In other embodiments, the passivation process 82 can be omitted if the re-dusting is not so severe as to impair the selectivity in the deposition. Accordingly, the passivation process 230 in Fig. 23 is represented by a dashed box.

[0037] In some embodiments, the passivation process 82 is carried out by annealing the wafer 10 in an oxygen (O2)-containing environment or by plasma treatment of the wafer 10 using O2 as a process gas. In some embodiments, the annealing with oxygen is carried out at a temperature of approximately 200 °C to approximately 350 °C for a duration of, for example, approximately 10 s to approximately 60 s. This oxidizes a surface layer of the gate electrode 74 and the re-dusted material to an oxide. In alternative embodiments, the passivation process 82 is carried out by treating the wafer 10 in a nitrogen (N2) and hydrogen (H2)-containing environment. This converts the surface layer of the gate electrode 74 and the re-dusted material into a nitride.It is understood that the gate electrode 74 may already contain a metal nitride, and the nitriding further improves the selectivity because the damaged SiN sidewall is passivated, and any metal residue is also passivated, thus improving the selectivity. In further embodiments, the passivation process 82 is carried out by thermal immersion of the wafer 10 in an NF3-containing environment or by performing plasma treatment on the wafer 10 using NF3 as a process gas. In some embodiments, the thermal immersion takes place at a temperature of approximately 250 °C to approximately 400 °C for a duration of, for example, 1 min to approximately 10 min.

[0038] In Fig. 16. A first conductive layer 84A with low resistivity, which may be a metal layer, is produced by a selective deposition process. The low resistivity layer 84A is also referred to below as the lower (metallic) sublayer 84A. The corresponding step is specified as step 232 in process flow 200, which is described in Fig. Figure 23 is shown. Throughout the entire description, the lower sublayer 84A can also be considered part of the respective gate electrodes. In some embodiments of the present invention, the lower sublayer 84A is made of tungsten (W). The resistivity of the lower sublayer 84A can be lower than the resistivity of the layers (comprising layers 66 and 70) in the gate electrode 74. The lower sublayer 84A is deposited on the gate electrode 74, but not on the exposed surfaces of the dielectric materials comprising the gate spacers 46, the high-k dielectric layer 64, the CESL 58, and the ILD 60. In some embodiments, deposition is carried out by ALD. A precursor may comprise WCl5 and a reducing agent such as H2. The deposition process comprises multiple ALD cycles, each involving the introduction of WCl5, the removal of WCl5, the introduction of H2, and the removal of H2.The deposition process can be carried out at an elevated temperature, for example at about 400 °C to about 500 °C.

[0039] It is understood that WCl5 has the function of etching metal oxides. When the first passivation process 82 is carried out using oxygen, the resulting metal oxide, which is formed by the oxidation of the surface layer of the gate electrode 74, and the re-dusted material of the gate electrode 74 are etched before the lower sublayer 84A is grown.

[0040] In Fig. 17. After the deposition of the lower sublayer 84A, a passivation process 86 is carried out using N2. The corresponding step is specified as step 234 in the process flow 200, which is described in Fig. 23 is shown. Step 234 in Fig. 23 is represented by a dashed box. The passivation process 86, which is carried out using N2, can be carried out using a method from the same group of eligible methods as for passivation process 82 ( Fig. 15) can be selected. Therefore, the details are not repeated here. Furthermore, the passivation process 86 can be carried out using the same method and the same process gases or with other methods and process gases.

[0041] In Fig. 18. After the production of the lower sublayer 84A and the passivation process 86, a metal layer 84B (hereinafter referred to as the upper sublayer 84B) is selectively deposited onto the lower sublayer 84A. The corresponding step is specified as step 236 in the process sequence 200, which is described in Fig. Figure 23 shows that the resistivity of the upper sublayer 84B is also lower than the resistivity of the layers (comprising layers 66 and 70) in the gate electrode 74. The upper sublayer 84B is produced using the lower sublayer 84A as a seed layer and is therefore not deposited on the exposed surfaces of dielectric materials such as the gate spacers 46, the dielectric high-k layer 64, the CESL 58, and the ILD 60. In some embodiments, the upper sublayer 84B is deposited by ALD. The precursor is different from the precursor used to deposit the lower sublayer 84A. For example, the precursor for producing the upper sublayer 84B may contain WF6 and a reducing agent such as H2.The deposition process can comprise multiple ALD cycles, each involving the introduction of WF6, the removal of WF6, the introduction of H2, and the removal of H2. The deposition process can be a thermal process carried out at an elevated temperature, for example, at approximately 250 °C to approximately 400 °C.

[0042] The sublayers 84A and 84B have different functions. The lower sublayer 84A (which can be fabricated using WCl5) can be selectively grown on the gate electrode 74 (such as TiN) without being deposited on the exposed dielectric layers. However, the lower sublayer 84A must not be deposited too thickly, as it will eventually be deposited on the exposed dielectric layers if deposition continues. Therefore, the deposition of the lower sublayer 84A is stopped before it is deposited on the exposed dielectric layers. In some embodiments, the thickness of the lower sublayer 84A is less than about 3 nm to ensure that it is not deposited on the exposed dielectric layers.On the other hand, the lower sublayer 84A is used as a seed layer for the selective growth of the upper sublayer 84B, which is not grown on the gate electrode 74. The lower sublayer 84A thus has sufficient thickness to ensure that it completely covers the exposed gate electrode 74, and therefore its thickness is greater than approximately 1 nm. Accordingly, the thickness T1 of the lower sublayer 84A can range from approximately 1 nm to approximately 3 nm.

[0043] The upper sublayer 84B (which can be fabricated using WF6) is deposited on a metal, such as the lower sublayer 84A, but it is not deposited on the exposed dielectric layer, even if the deposition of the upper sublayer 84B takes a long time. Accordingly, the upper sublayer 84B is selectively deposited on the lower sublayer 84A if the lower sublayer 84A has been fabricated as the seed layer. If the thickness T2 of the upper sublayer 84B is large, it still will not grow on the exposed dielectric layers. Therefore, the thickness T2 of the upper sublayer 84B can be increased without the risk of it growing on the exposed dielectric layers. The thickness T2 of the upper sublayer 84B can be greater than approximately 1 nm, greater than approximately 3 nm, greater than approximately 5 nm, or even greater.In some embodiments, the thickness T2 is approximately 1 nm to approximately 5 nm. The top surface of the upper sublayer 84B can be at the same level as, or slightly lower than, the top surfaces of the high-k dielectric layer 64. The sublayers 84A and 84B are collectively referred to as the low-resistance conductive layer 84. Throughout this description, the low-resistance conductive layer 84 is considered part of the gate electrode, designated 74'. The low-resistance conductive layers 84A and 84B can together achieve a sufficiently large thickness, and therefore the overall resistivity of the gate electrode 74 (which includes the low-resistance conductive layer 84) can be reduced.

[0044] Due to the selective deposition, sublayers 84A and 84B can be conformal layers. Furthermore, sublayers 84A and 84B can be substantially planar if the top surface of the underlying portion of the gate electrode 74' is planar. Alternatively, sublayers 84A and 84B can be convex and have a topology that follows the top surface profile of the respective underlying portions of the gate electrode 74'.

[0045] In Fig. 19. The remaining recesses 80 and 81 (if present) are then filled with a dielectric material to produce a self-aligning hard mask 88. The corresponding step is specified as step 238 in the process flow 200, which is described in Fig. Figure 23 shows that the self-aligned hard mask 88 can be made of a non-low-k dielectric material, such as silicon nitride, silicon oxide nitride, silicon oxide carbide, or the like. The self-aligned hard mask 88 can also be made of a homogeneous low-k dielectric material, such as porous silicon nitride, porous silicon oxide nitride, porous silicon oxide carbide, or the like. The self-aligned hard mask 88 is also planarized so that its top surface is coplanar with the top surface of the ILD 60. In some embodiments, side walls of the self-aligned hard mask 88 are in contact with side walls of the CESL 58. In other embodiments, where the gate spacers 46 are not recessed, the side walls of the hard mask 88 are in contact with the side walls of the upper parts (shown with dashed lines 46') of the gate spacers 46.

[0046] Fig. Figure 20A shows the fabrication of a gate contact pin 90, source / drain silicide areas 92, and source / drain contact pins 94. The corresponding step is indicated as step 240 in process flow 200, which is described in Fig. Figure 23 shows the fabrication of the source / drain contact pins 94. This involves creating contact openings by etching the ILD 60 to expose the underlying portions of the CESL 58, and subsequently etching the exposed portions of the CESL 58 to reveal source / drain regions 54. In a subsequent process, a metal layer (such as a titanium layer) is deposited to extend into the contact openings. A metal nitride blocking layer (such as a TiN layer) can then be fabricated. A tempering process is then carried out to react the metal layer with an upper portion of the source / drain regions 54 to form the silicide regions 92. The previously fabricated metal nitride layer is then either left in place or removed, followed by the deposition of another metal nitride layer (such as a titanium nitride layer).A metallic filler material, such as tungsten, cobalt, or the like, is then inserted into the contact orifices, followed by a planarization process to remove excess material, resulting in the source / drain contact pins 94. Fabrication of the gate contact pin 90 may involve etching the self-aligned hard mask 88 to expose the upper sublayer 84B and fabricating the gate contact pin 90 in the corresponding orifices. The gate contact pin 90 may also include a diffusion barrier layer (such as titanium nitride) and a metal (such as copper, tungsten, cobalt, or the like) over the diffusion barrier layer. This results in a FinFET 100. Fig. Figure 20B shows a perspective view of the FinFET 100.

[0047] In Fig. 20A is designed with a thickness ratio T2 / T1 that is neither too large nor too small. If the thickness ratio T2 / T1 is too large, either the thickness T1 is too small, and / or the thickness T2 is too large. If the thickness T1 is too small, the lower sublayer 84A cannot completely cover a gate electrode 66 and cannot function as an effective seed layer. If the thickness T2 is too large, the top surface of the upper sublayer 84B may be higher than the top edges of the dielectric high-k layer 64, causing problems in the subsequent fabrication of the self-aligned hard mask 88. Conversely, if the thickness ratio T2 / T1 is too small, either the thickness T1 is too large, and / or the thickness T2 is too small.If the thickness T1 is too large, the lower sublayer 84A can be grown on dielectric materials such as ILD 60, and the deposition of the lower sublayer 84A and the upper sublayer 84B will be non-selective. If the thickness T2 is too small, the resistance of the sublayer 84B (and thus the total resistance of layers 84A and 84B) will be high, which is contrary to the purpose of producing layers 84A and 84B with low resistivity. In some embodiments, the thickness ratio T2 / T1 is 1 to about 5.

[0048] To ensure that the upper sublayer 84B is not grown on the dielectric high-k layer 64 and the gate spacers 46, in some embodiments the top surface of the upper sublayer 84B can be at the same level as the top edges of the dielectric high-k layer 64 and / or the top edges of the gate spacers 46. In alternative embodiments, the top surface of the upper sublayer 84B is lower than the top edges of the dielectric high-k layer 64 and / or the top edges of the gate spacers 46 by a difference to provide a process margin. The difference can be less than about 1 nm.

[0049] As in Fig. As shown in Figure 20A, the underside of the gate contact pin 90 can extend from the left edge shown to the right edge shown of the upper sublayer 84B. Alternatively, the underside of the gate contact pin 90 can be laterally recessed from the left and / or right edge of the upper sublayer 84B, as shown in Figure 20A. Fig. Figure 20A shows this. In further embodiments, the underside of the gate contact pin 90 can extend onto and contact the upper ends of the dielectric high-k layer 64, and it can (or may not) extend onto and contact the upper ends of the gate spacers 46.

[0050] Fig. Figure 21 shows a top view of some parts of the FinFET 100, namely the gate electrode 74' and the conductive layers 84A and 84B located above it. The vertical portions of the high-k dielectric layer 64 can form rings that enclose the corresponding gate electrode 74' (which includes the corresponding low-resistance conductive layer 84 located above it). The gate contact pin 90, the projecting fins 36, and the source / drain regions 54 are also shown.

[0051] As in Fig. As shown in Figure 21, the low-resistance conductive layers 84A and 84B can completely cover the exit working layer 66, and the edges of the conductive layers 84A and 84B can be flush with the corresponding edges of the exit working layer 66. The high-k dielectric layer 64 can form a ring that contacts the sidewalls of the low-resistance conductive layers 84A and 84B and the exit working layer 66. The hard mask 88 can be completely enclosed by the vertical portions of the CESL 58. The gate contact pin 90 can contact part (but not all) of the upper sublayer 84B, with the low-resistance conductive layers 84A and 84B extending beyond a left sidewall 90C and a right sidewall 90D of the gate contact pin 90.Although the side walls 90A and 90B of the gate contact pin 90 are shown to be located directly on the upper sublayer 84B, it is understood that the side walls 90A and 90B can also extend in the direction of the arrows 95 and can be located at a position on the paths of the arrows 95.

[0052] Fig. Figure 22 shows a schematic distribution of some elements, where atomic fractions of the elements F, Cl and N are shown as a function of the height in the gate electrode 74, with the height in the direction of an arrow 108 from Fig.20A is measured. Curves 102, 104, and 106 show exemplary atomic fractions of chlorine, fluorine, and nitrogen, respectively. If the lower sublayer 84A is produced using WCl5 as a process gas, curve 102 indicates that the peak atomic fraction of Cl is found in the lower sublayer 84A, and the Cl atomic fraction decreases stepwise in the upper sublayer 84B (and in the dielectric hard mask 88) and the exit working layer 66. If the upper sublayer 84B is produced using WF6 as a process gas, curve 104 indicates that the peak atomic fraction of F is found in the upper sublayer 84B, and the F atomic fraction decreases stepwise in the lower sublayer 84A, the dielectric hard mask 88, and the gate contact pin 90. The distribution of curves 102 and 104 can be determined by X-ray photoelectron spectroscopy (XPS).In some embodiments, the peak atomic fraction of F in the upper sublayer 84B is higher than about 12%, and can range from about 5% to about 20%. The peak atomic fraction of Cl in the lower sublayer 84A is higher than about 10% and can also range from about 5% to about 20%.

[0053] Curve 106 shows an embodiment in which the passivation process 86 using N₂ is carried out after the deposition of sublayer 84A and before the deposition of sublayer 84B. According to the invention, the peak nitrogen atomic fraction is found at the interface between layers 84A and 84B, and the nitrogen atomic fraction decreases in both sublayers 84A and 84B. The distribution of curve 106 can be determined by energy-dispersive X-ray spectroscopy (EDS or EDX). Furthermore, the two layers 84A and 84B can be distinguished from each other by EDX. Experiments have also shown that sublayers 84A and 84B can be distinguished from each other by transmission electron microscopy (TEM) based on their difference in degree of crystallinity.

[0054] The embodiments of the present invention can offer several advantages. By producing a first conductive layer with low resistivity, selective deposition of this layer is possible only on the gate electrode, but not on the exposed dielectric layers. The loss of selectivity due to the longer deposition time of the first conductive layer with low resistivity is overcome by stopping the deposition of this layer and selectively depositing a second conductive layer with low resistivity on a metal. The selectivity of the deposition is not lost if the thickness of the second conductive layer with low resistivity is increased.

[0055] According to some embodiments of the present invention, a method comprises the following steps: fabricating a gate electrode on a semiconductor region; recessing the gate electrode to create a recess; performing a first deposition process to fabricate a first metal layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor; performing a passivation process using N2; performing a second deposition process to fabricate a second metal layer on the first metal layer using a second precursor that is different from the first precursor, wherein the first metal layer and the second metal layer comprise the same metal; fabricating a dielectric hard mask over the second metal layer; and fabricating a gate contact pin such that it penetrates the dielectric hard mask.wherein the gate contact pin contacts a top surface of the second metal layer. In one embodiment, the first precursor comprises tungsten chloride (WCl5), and the second precursor comprises tungsten fluoride (WF6). In one embodiment, in the first deposition process, surfaces of dielectric materials adjacent to the gate electrode are exposed, and the first deposition process is terminated before the first metal layer begins to grow on the exposed dielectric materials adjacent to the gate electrode. In one embodiment, the first and second deposition processes each comprise an atomic layer deposition process. In some embodiments, the gate electrode recession comprises a first recession process to recess the gate electrode, a gate dielectric, and gate spacers.wherein the gate dielectric comprises first sidewall portions on sidewalls of the gate electrode and the gate electrode and the gate dielectric are arranged between the gate spacers; and a second recession process to recess the gate electrode so that it is lower than the upper edges of the gate dielectric. In one embodiment, the first metal layer has a first thickness of less than about 3 nm. In another embodiment, the second metal layer has a second thickness of greater than about 3 nm.

[0056] According to some embodiments of the present invention, a device comprises: a semiconductor region; a gate dielectric above the semiconductor region; a gate electrode comprising a first part with a working layer located therein and a second part above and in contact with the first part, wherein the second part contains fluorine and chlorine and has a lower sublayer having a first peak atomic fraction of chlorine, and an upper sublayer above and in contact with the lower sublayer, wherein the upper sublayer has a second peak atomic fraction of fluorine and the lower sublayer and the upper sublayer comprise the same metal, wherein the lower and the upper sublayers both contain nitrogen, wherein an atomic fraction of nitrogen has a peak at an interface between the first sublayer and the second sublayer; and a gate contact pin above and in contact with the upper sublayer.In one embodiment, the first part comprises titanium, and the second part comprises tungsten. In another embodiment, the lower and upper sublayers are distinguishable by transmission electron microscopy (TEM). In yet another embodiment, the gate dielectric has sidewall parts and a lower part that is arranged beneath and connected to the sidewall parts, with the first and second parts of the gate electrode positioned between the sidewall parts. In yet another embodiment, an upper surface of the upper sublayer is at the same level as, or lower than, the upper edges of the sidewall parts of the gate dielectric.In one embodiment, the device further comprises: gate spacers on opposite sides of the gate dielectric and the gate electrode; and an interlayer dielectric in which the gate spacers are arranged, wherein a first top surface of the gate dielectric is recessed deeper than a second top surface of the interlayer dielectric. In one embodiment, the gate spacers are recessed such that they have a third top surface that is lower than the second top surface.

[0057] According to some embodiments of the present invention, a device comprises: a semiconductor substrate; insulating regions extending into the semiconductor substrate; a semiconductor fin projecting over portions of the insulating regions on opposite sides of the semiconductor fin; and a gate stack comprising: a high-k gate dielectric on the semiconductor fin, a leakage working layer on the high-k gate dielectric, a capping layer, a first tungsten layer above and in contact with the leakage working layer and the capping layer, and a second tungsten layer above and in contact with the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other, and wherein the first and the second tungsten layers both contain nitrogen.wherein an atomic fraction of nitrogen in the gate stack has a peak at an interface between the first tungsten layer and the second tungsten layer. In one embodiment, the first and second tungsten layers both contain fluorine and chlorine, wherein the first tungsten layer has a first peak atomic fraction of chlorine. In another embodiment, the second tungsten layer has a second peak atomic fraction of fluorine. In another embodiment, the high-k gate dielectric has sidewall parts on opposite sides of the first and second tungsten layers, wherein an upper surface of the second tungsten layer is located between upper edges of the sidewall parts of the high-k gate dielectric and is at the same level as, or lower than, the upper edges of the sidewall parts of the high-k gate dielectric. In another embodiment, the capping layer comprises titanium nitride.

Claims

[1] Procedure with the following steps: Creating a gate electrode (74) over a semiconductor area (20); Recessing the gate electrode (74) to create a recess (80); Performing a first deposition process to produce a first metal layer (84A) on the gate electrode (74) and in the recess (80), wherein the first deposition process is carried out using a first precursor; Performing a passivation process using N2; Performing a second deposition process to produce a second metal layer (84B) on top of the first metal layer (84A) using a second precursor that is different from the first precursor, wherein the first metal layer (84A) and the second metal layer (84B) are of the same metal; Producing a dielectric hard mask (88) over the second metal layer (84B); and Producing a gate contact pin (90) such that it penetrates the dielectric hard mask (88), wherein the gate contact pin (90) contacts a top surface of the second metal layer (84B). [2] The method of claim 1, wherein the first precursor comprises tungsten chloride and the second precursor comprises tungsten fluoride [3] Method according to claim 1 or 2, wherein in the first deposition process surfaces of dielectric materials adjacent to the gate electrode (74) are exposed and the first deposition process is terminated before the first metal layer (84A) begins to grow on the exposed dielectric materials adjacent to the gate electrode (74). [4] Method according to any of the preceding claims, wherein the first and second deposition processes each comprise an atomic layer deposition process. [5] Method according to any of the preceding claims, wherein the recession of the gate electrode (74) comprises: a first recession process for recessing the gate electrode (74), a gate dielectric (61) and gate spacers (46), wherein the gate dielectric (61) comprises first sidewall parts on sidewalls of the gate electrode (74) and the gate electrode (74) and the gate dielectric (61) are arranged between the gate spacers (46); and a second recession process to recess the gate electrode (74) so ​​that it is lower than the upper edges of the gate dielectric (61). [6] Method according to any of the preceding claims, wherein the first metal layer (84A) has a first thickness that is less than about 3 nm. [7] Method according to any of the preceding claims, wherein the second metal layer (84B) has a second thickness greater than about 3 nm. [8] Device with: a semiconductor area (20); a gate dielectric (61) over the semiconductor area; a gate electrode (74) which has the following features: a first part containing an exit work shift (66), and a second part above and in contact with the first part, the second part containing fluorine and chlorine and having the following features: a lower sublayer (84A) which has a first peak atomic fraction of chlorine, and an upper sublayer (84B) above and in contact with the lower sublayer (84A), wherein the upper sublayer (84B) has a second peak atomic fraction of fluorine and the lower sublayer (84A) and the upper sublayer (84B) have the same metal, where the lower and upper sublayers (84A, 84B) both contain nitrogen, where an atomic fraction of nitrogen forms a peak at an interface between the first sublayer and second sublayer; and a gate contact pin (90) above and in contact with the upper sublayer (84B). [9] Device according to claim 8, wherein the first part comprises titanium and the second part comprises tungsten. [10] Device according to claim 8 or 9, wherein the lower sublayer (84A) and the upper sublayer (84B) are distinguishable by transmission electron microscopy. [11] Device according to one of claims 8 to 10, wherein the gate dielectric (61) has side wall parts and a lower part which is arranged below and connected to the side wall parts, wherein the first part and the second part of the gate electrode (74) are arranged between the side wall parts. [12] Device according to claim 11, wherein an upper surface of the upper sublayer (84B) is at the same level as or lower than the upper edges of the sidewall parts of the gate dielectric (61). [13] Device according to any one of claims 8 to 12, further comprising: Gate spacers (46) on opposite sides of the gate dielectric (61) and the gate electrode (74); and an interlayer dielectric in which the gate spacers (46) are arranged, wherein a first top surface of the gate dielectric (61) is recessed deeper than a second top surface of the interlayer dielectric. [14] Device according to claim 13, wherein the gate spacers (46) are recessed such that they have a third top surface which is lower than the second top surface. [15] Device with: a semiconductor substrate (20); Insulation areas (24) extending into the semiconductor substrate (20); a semiconductor fin (36) that extends over parts of the insulating areas (24) on opposite sides of the semiconductor fin; and a gate stack (76) comprising the following: a high-k gated dielectric (61, 64) on the semiconductor fin (36), an exit working layer (66) on the high-k gated dielectric (61), a capping layer (70), a first tungsten layer (84A) over and in contact with the exit working layer (66) and the capping layer (70), and a second tungsten layer (84B) over and in contact with the first tungsten layer (84A), wherein the first tungsten layer and the second tungsten layer are distinguishable from each other, and wherein the first and second tungsten layers (84A, 84B) both contain nitrogen, wherein an atomic fraction of nitrogen in the gate stack (76) has a peak at an interface between the first tungsten layer and the second tungsten layer. [16] Device according to claim 15, wherein the first and second tungsten layers (84A, 84B) both contain fluorine and chlorine, wherein the first tungsten layer (84A) contains a first peak atomic fraction of chlorine. [17] Device according to claim 16, wherein the second tungsten layer (84B) has a second peak atomic fraction of fluorine. [18] Device according to any one of claims 15 to 17, wherein the high-k gated dielectric (61) has sidewall parts on opposite sides of the first tungsten layer (84A) and the second tungsten layer (84B), wherein a top side of the second tungsten layer (84B) is located between the upper edges of the sidewall parts of the high-k gated dielectric (61, 64) and is at the same level as or lower than the upper edges of the sidewall parts of the high-k gated dielectric (61, 64). [19] Device according to any one of claims 15 to 18, wherein the capping layer (70) comprises titanium niride.

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