Device with magnetic tunnel transition and method for manufacturing the same

Abstract

Device comprising: a magnetoresistive random access memory array (52), MRAM array comprising MRAM cells (58) arranged in rows and columns, a first column of the columns comprising: - first lower electrodes (132) arranged along the first column; - first magnetic tunnel junction stack (134), MTJ stack, over the first lower electrodes (132); - a first shared electrode (160) over each of the first MTJ stacks (134); - second lower electrodes (132) arranged along the first column; - second MTJ stacks (134) above the second lower electrodes (132); - a second shared electrode (160) over each of the second MTJ stacks (134); and - a bit line (176L, BL) electrically connected to the first shared electrode (160) and the second shared electrode (160); - first upper electrodes (136) arranged between the first MTJ stacks (134) and the first shared electrode (160); - second upper electrodes (136) arranged between the second MTJ stacks (134) and the second shared electrode (160); - a first conductive via (176V) physically and electrically connecting the bit line (176L, BL) to the first shared electrode (160); and - a second conductive via (176V) physically and electrically connecting the bit line (176L, BL) to the second shared electrode (160), wherein widths of the first conductive via (176V) and the second conductive via (176V) are greater than widths of each of the first upper electrodes (136) and each of the second upper electrodes (136); and wherein widths of the first shared electrode (160) and the second shared electrode (160) are greater than the widths of the first upper electrodes (136), the second upper electrodes (136), the first conductive via (176V) and the second conductive via (176V).

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications such as radios, televisions, mobile phones, and personal computing devices. One type of semiconductor device is magneto-resistive random access memory (MRAM), which incorporates spintronics, combining semiconductor technology with magnetic materials and devices. The spins of electrons are used to display bit values ​​through their magnetic moments. An MRAM cell typically has a magnetic tunnel junction (MTJ) stack, which includes two ferromagnets separated by a thin insulator.

[0002] US 2016 / 0 225 817 A1 describes a semiconductor device comprising a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device and the second MTJ device contain a barrier layer. The top electrode is connected to the first MTJ device and the second MTJ device.

[0003] Document WO 2020 / 192207 A1 describes an MRAM memory array with an array of storage units, each storage unit comprising an MTJ unit, and a magnetization direction of the MTJ unit being a growth direction along an MTJ thin film. For pairs of adjacent storage units, the top surfaces of the MTJ units are provided with a common magnetic electrode. The magnetic electrodes in the array are arranged in the same direction and are used to provide a magnetic moment for respective MTJ units, thereby assisting free layers of the MTJ units in implementing flipping.

[0004] Further prior art is known from the document DE 10 2018 124 716 A1 and the document DE 10 2016 114 870 A1.

[0005] The task is to improve corresponding MRAM devices.

[0006] The object is achieved by the device according to patent claim 1 and the methods according to patent claims 9 and 13. Further embodiments emerge from the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood by reference to the following detailed description when considered in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as necessary for clarity of explanation. Fig. 1 is a cross-sectional view of an MRAM device according to some embodiments. Fig. 2 is a block diagram of an MRAM device according to some embodiments. Fig. 3 to 23 are various views of intermediate stages in the fabrication of an interconnect structure for an MRAM device according to some embodiments. Fig. 24 and Fig. 25 are various views of an MRAM device according to some embodiments. Fig. 26 to 40 are cross-sectional views of intermediate stages in the fabrication of an interconnect structure for an MRAM device according to some other embodiments. Fig. 41 is a cross-sectional view of an MRAM device according to some other embodiments. Fig. 42 is a cross-sectional view of an MRAM device according to some other embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the drawings. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the drawings. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] According to some embodiments, an MRAM array is formed in an interconnect structure, wherein the MRAM array includes shared electrodes for the MTJ stacks in the MRAM array. More specifically, electrodes are shared by multiple MTJ stacks along columns of the MRAM array and are electrically connected to the same bitline. Forming shared electrodes for the MTJ stacks contributes to reducing contact resistance to the MTJ stacks and reduces the risk of damage to the MTJ stacks during the subsequent formation of overlying metallization layers. According to some other embodiments, dielectric protection structures are formed around the MRAM cells prior to the formation of overlying metallization layers. The protection structures prevent etching of the MTJ stacks during the subsequent formation of overlying metallization layers.By forming the shared electrodes and / or protection structures, damage to the MRAM cells during processing can be avoided, especially when the MRAM array is formed in a higher level of the interconnect structure.

[0011] Fig. 1 is a block diagram of an MRAM device 50 according to some embodiments. The MRAM device 50 includes an MRAM array 52, a row decoder 54, and a column decoder 56. The MRAM array 52 includes MRAM cells 58 arranged in rows and columns. The row decoder 54 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like. During operation, the row decoder 54 selects desired MRAM cells 58 in a row of the MRAM array 52 by activating the respective word line WL for the row. The column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like, and may include writer drivers, sense amplifiers, combinations thereof, or the like.During operation, the column decoder 56 selects bit lines BL for the desired MRAM cells 58 from columns of the MRAM array 52 in the selected row and uses the bit lines BL to read data from or write data to the selected MRAM cells 58.

[0012] Fig. 2 is a cross-sectional view of the MRAM device 50 according to some embodiments. Fig. Figure 2 is a simplified view, and some features (discussed below) have been omitted for clarity. The MRAM device 50 includes a logic region 50L and a memory region 50M. Memory devices (e.g., MRAMs) are formed in the memory region 50M, and logic devices (e.g., logic circuits) are formed in the logic region 50L. For example, the MRAM array 52 (see Fig. 1) in the memory region 50M, and the row decoder 54 and the column decoder 56 (see Fig. 1) may be formed in the logic region 50L. The logic region 50L may occupy most of the area of ​​the MRAM device 50. For example, the logic region 50L may occupy from 95% to 99% of the area of ​​the MRAM device 50, while the memory region 50M occupies the remaining area of ​​the MRAM device 50. The memory region 50M may be arranged at an edge of the logic region 50L, or the logic region 50L may surround the memory region 50M.

[0013] The logic region 50L and the memory region 50M are formed on the same semiconductor substrate 60. The semiconductor substrate 60 may be doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 60 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0014] Devices 62 are formed on the active area of ​​the semiconductor substrate 60. The devices 62 may be active or passive devices. The electrical devices may be, for example, transistors, diodes, capacitors, resistors, or the like, formed by any suitable formation method. The devices 62 are connected together to form the memory devices and logic devices of the MRAM device 50. For example, some of the devices 62 may be access transistors.

[0015] One or more inter-layer dielectric (ILD) layers 64 are formed on the semiconductor substrate 60, and electrically conductive features, such as contact plugs 66, are formed that are electrically connected to the devices 62. The one or more ILD layers 64 may be formed from any suitable dielectric material, for example, a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The one or more ILD layers may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof.The electrically conductive features in the one or more ILD layers may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, double damascene, etc.), the like, or combinations thereof.

[0016] An interconnect structure 68 is formed over the semiconductor substrate 60. The interconnect structure 68 connects the devices 62 to form integrated circuits in each of the logic region 50L and the memory region 50M. The interconnect structure 68 includes multiple metallization layers M1-M6. Although six metallization layers are illustrated, it should be understood that more or fewer metallization layers may be present. Each of the metallization layers M1-M6 includes metallization structures in dielectric layers. The metallization structures are electrically coupled to the devices 62 of the semiconductor substrate 60 and include metal lines L1-L6 and metal vias V1-V6, respectively, formed in one or more inter-metal dielectric (IMD) layers.The interconnect structure 68 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, the contact plugs 66 are also part of the metallization structures, such as part of the lower layer of metal vias V1. Fig. 2 is also labeled with some reference numbers, which will be described further below.

[0017] The MRAM cells 58 are formed in the interconnect structure 68. The MRAM cells 58 can be formed in any of the metallization layers M1-M6 and are illustrated as being formed in an intermediate metallization layer M5. Each MRAM cell 58 includes a conductive via 72, a bottom electrode 74 on the conductive via 72, an MTJ stack 76 on the bottom electrode 74, and a top electrode 78 on the MTJ stack 76. An additional IMD layer 80 can be formed around the MRAM cells 58, with the conductive via 72 extending through the IMD layer 80. Spacers 82 can also be formed around the MRAM cells 58. The IMD layer 80 and / or the spacers 82 surround and protect the components of the MRAM cells 58. The resistance of an MTJ stack 76 is programmable and can be set between a high resistance (R ap), which can represent a value such as a logical “1”, and a low resistance (R p ), which may represent a value such as a logic "0." Thus, a value may be written to an MRAM cell 58 by programming the resistance of the MTJ stack 76 with its respective access transistor, and the value may be read from the MRAM cell 58 by measuring the resistance of the MTJ stack 76 with the access transistor.

[0018] The MRAM cells 58 are electrically connected to the devices 62. The conductive via 72 is physically and electrically coupled to an underlying metallization structure, such as metal lines L4 in the illustrated example. The top electrode 78 is physically and electrically coupled to an overlying metallization structure, such as metal vias V6 in the illustrated example. The MRAM cells 58 are arranged in an MRAM array having rows and columns of memory. The metallization structures include access lines (e.g., word lines and bit lines) for the MRAM array. For example, the underlying metallization structures may include word lines arranged along the rows of the MRAM array, and the overlying metallization structures may include bit lines arranged along the columns of the MRAM array.

[0019] Fig. 3 to 23 are various views of intermediate stages in the fabrication of an interconnect structure for MRAM device 50 according to some embodiments. The interconnect structure includes an MRAM array of memory cells. As discussed further below, groups of memory cells along the columns of the MRAM array share electrodes, which may reduce contact resistance to the memory cells.

[0020] In Fig. 3 a metallization layer (for example M4, see Fig. 2) of the interconnect structure. The metallization layer comprises an IMD layer 102 and conductive features 104 (which may correspond to the metal lines L4, see Fig. 2). The IMD layer 102 is formed over the one or more ILD layers 64. The IMD layer 102 may be formed from any suitable dielectric material, for example, a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The IMD layer 102 may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. The IMD layer 102 may be a layer formed from a low-k dielectric material having a k value of less than about 3.0. The IMD layer 102 may be a layer formed from an extra-low-k (ELK) dielectric material having a k value of less than about 2.5.

[0021] Conductive features 104 are formed in the IMD layer 102 and are electrically connected to the devices 62. According to some embodiments, the conductive features 104 include diffusion barrier layers and conductive material over the conductive barrier layers 114. Openings are formed in the IMD layer 102, for example, using an etching process. The openings expose underlying conductive features, such as underlying metal vias. The diffusion barrier layers may be formed from TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the openings by a deposition process such as atomic layer deposition (ALD) or the like.The conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, or the like, and may be formed over the diffusion barrier layers in the openings by an electrochemical plating process, CVD, ALD, PVD, or the like, or a combination thereof. In one embodiment, the conductive material is copper, and the diffusion barrier layers are thin barrier layers that prevent the copper from diffusing into the IMD layer 102. After the formation of the diffusion barrier layers and the conductive material, the excess of the diffusion barrier layers and the conductive material may be removed, for example, by a planarization process, such as a chemical mechanical polishing (CMP) process. In some embodiments, the conductive features 104 are metal lines.

[0022] One or more etch stop layers 106 are formed on the conductive features 104 and the IMD layer 102. The one or more etch stop layers 106 may be formed from a dielectric material such as aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, a combination thereof, or the like. The one or more etch stop layers 106 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, a spin-on dielectric process, the like, or a combination thereof. The one or more etch stop layers 106 may also be a composite layer formed from multiple dielectric layers. In this embodiment, the one or more etch stop layers 106 include a first etch stop layer 106A and a second etch stop layer 106B over the first etch stop layer 106A.The first etch stop layer 106A may be formed from a first dielectric material, such as silicon carbide, and the second etch stop layer 106B may be formed from a second dielectric material, such as aluminum oxide. The silicon carbide layer is used as a glue layer to improve adhesion between the aluminum oxide layer and the IMD layer 102. The one or more etch stop layers 106 may be formed to a combined thickness in the range of about 3 nm to about 15 nm.

[0023] An IMD layer 108 is formed on the one or more etch stop layers 106. In some implementations, the IMD layer 108 is formed from a tetraethylorthosilicate oxide (TEOS oxide) (e.g., silicon oxide deposited, for example, by a chemical vapor deposition (CVD) process with TEOS as a precursor). In some embodiments, the IMD layer 108 may be formed using PSG, BSG, BPSG, undoped silicate glass (USG), fluorosilicate glass (FSG), SiOCH, flowable oxide, a porous oxide, or the like, or combinations thereof. The IMD layer 108 may also be formed from a low-k dielectric material, for example, having a k value of less than about 3.0. The IMD layer 108 may be formed to a thickness in the range of about 35 nm to about 55 nm.

[0024] Conductive vias 110 are formed, extending through the IMD layer 108 and the one or more etch stop layers 106. The conductive vias 110 may also be referred to as bottom vias. In some embodiments, the conductive vias 110 include conductive regions 112 and conductive barrier layers 114 lining sidewalls and bottom surfaces of the conductive regions 112. The conductive barrier layers 114 may be formed from titanium, titanium nitride, tantalum, tantalum nitride, cobalt, a combination thereof, or the like. The conductive regions 112 may be formed from metals such as copper, aluminum, tungsten, cobalt, their alloys, or the like.Forming the conductive vias 110 may include etching the IMD layer 108 and the one or more etch stop layers 106 to form via openings, forming a blanket-deposited conductive barrier layer extending into the via openings, depositing a metallic material over the blanket-deposited conductive barrier layer, and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the blanket-deposited conductive barrier layer and the metallic material.

[0025] One or more bottom electrode layers 116 are formed on the conductive vias 110 and the IMD layer 108. In some implementations, the one or more bottom electrode layers 116 are formed as capping layers and may be formed using CVD, physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, or the like. The one or more bottom electrode layers 116 may be formed from conductive materials such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, multilayers thereof, or the like. For example, the one or more bottom electrode layers 116 may include a first bottom electrode layer 116A and a second bottom electrode layer 116B over the first bottom electrode layer 116A.The first bottom electrode layer 116A may be formed from a first conductive material, such as TaN, and the second bottom electrode layer 116B may be formed from a second conductive material, such as TiN. The one or more bottom electrode layers 116 may be formed to a combined thickness in the range of about 2 nm to about 15 nm.

[0026] In Fig. 4, an MTJ film stack 118 is formed on the one or more bottom electrode layers 116. The MTJ film stack 118 is a multilayer comprising an anti-ferromagnetic layer 118A, a pinned layer 118B over the anti-ferromagnetic layer 118A, a tunnel barrier layer 118C over the pinned layer 118B, and a free layer 118D over the tunnel barrier layer 118C. The MTJ film stack 118 has a total thickness in the range of about 20 nm to about 40 nm. Each layer of the MTJ film stack 118 can be deposited using one or more deposition techniques, such as CVD, PVD, ALD, a combination thereof, or the like.

[0027] The anti-ferromagnetic layer 118A may be formed from a metal alloy containing manganese (Mn) and one or more other metals, such as platinum (Pt), iridium (Ir), rhodium (Rh), nickel (Ni), palladium (Pd), iron (Fe), osmium (Os), or the like. For example, the anti-ferromagnetic layer 118A may be formed from PtMn, IrMn, RhMn, NiMn, PdPtMn, FeMn, OsMn, or the like. The anti-ferromagnetic layer 118A may have a thickness in the range of about 5 nm to about 20 nm.

[0028] The pinned layer 118B may be formed from a ferromagnetic material with a larger coercive field than the free layer 118D, such as cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), a combination thereof, or the like. The pinned layer 118B may have a thickness ranging from about 5 nm to about 10 nm. In some embodiments, the pinned layer 118B has a synthetic ferromagnetic (SFM) structure in which the coupling between magnetic layers is a ferromagnetic coupling. The pinned layer 118B may also adopt a synthetic anti-ferromagnetic (SAF) structure comprising multiple magnetic metal layers separated by multiple non-magnetic spacer layers. The magnetic metal layers may be formed from Co, Fe, Ni, or the like. The non-magnetic spacer layers may be formed of Cu, Ru, Ir, Pt, W, Ta, Mg or the like.For example, the pinned layer 118B may be a Co layer and repeated (Pt / Co). x layers above the Co layer, where x represents a repeating number that can be any integer of at least 1, such as 20.

[0029] The tunnel barrier layer 118C may be formed from a dielectric material, such as MgO, AlO, AlN, a combination thereof, or the like. The tunnel barrier layer 118C may have a thickness in the range of about 0.5 nm to about 3 nm. The tunnel barrier layer 118C is thicker than the other layers of the MTJ film stack 118.

[0030] The free layer 118D may be formed from a ferromagnetic material such as CoFe, NiFe, CoFeB, CoFeBW, a combination thereof, or the like. The free layer 118D may also adopt a synthetic ferromagnetic structure similar to a SAF structure, wherein the thickness of the non-magnetic spacer layers is adjusted to achieve ferromagnetic coupling between the separated magnetic metals, for example, by causing the magnetic moment to couple in the same direction. The magnetic moment of the free layer 118D is programmable, and the resistances of the resulting MTJ stacks are programmable accordingly. More specifically, the resistances of the resulting MTJ stacks may range between a high resistance (R ap ) and a low resistance (R p) based on the programmed magnetic moment of the free layer 118D. Therefore, the resulting MTJ stacks can also be referred to as programmable resistance elements or programmable resistors. The thickness of the tunnel junction layer 118C contributes to the R ap and the R p the resulting MTJ stack.

[0031] It is understood that the materials and structure of the MTJ film stack 118 may have many variations, which also fall within the scope of this disclosure. For example, layers 118A, 118B, 118C, and 118D may be formed in an order that is reversed from that described above. Accordingly, the free layer 118D may be the bottom layer of the MTJ film stack 118, and the anti-ferromagnetic layer 118A may be the top layer of the MTJ film stack 118.

[0032] A top electrode layer 120 is formed on the MTJ film stack 118. In some implementations, the top electrode layer 120 is formed as a cap layer and may be formed using CVD, PVD, ECP, electroless plating, or the like. The material of the top electrode layer 120 may include metals such as titanium, tantalum, tungsten, aluminum, copper, their alloys, or the like. For example, the top electrode layer 120 may be formed from TiN, Ta, TaN, Ti, Ru, W, WC, Ru, multilayers thereof, or the like. In some implementations, the top electrode layer 120 is formed from titanium nitride. In some implementations, the top electrode layer 120 has a thickness in the range of about 40 nm to about 150 nm. In some implementations, the thickness of the top electrode layer 120 is greater than the combined thickness of the one or more bottom electrode layers 116.The top electrode layer 120 is used as a hard mask during the subsequent patterning of the MTJ film stack 118.

[0033] In Fig. 5, one or more masks are formed over the top electrode layer 120. The masks are used to simultaneously pattern the various layers and form MRAM cells. In some embodiments, the one or more masks may include one or more hard masks, a three-layer mask, a combination thereof, or the like. For example, a hard mask layer 126 may be formed over the top electrode layer 120, and a photosensitive mask 128 may be formed over the hard mask layer 126. In some embodiments, the hard mask layer 126 is formed from an oxide such as titanium oxide, silicon oxide, a combination thereof, or the like. The photosensitive mask 128 may be a photoresist such as a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like.The photosensitive mask 128 is formed in the memory region 50M, wherein the structure of the photosensitive mask 128 corresponds to the structure of the subsequently formed MRAM cells.

[0034] In Fig. 6, the photosensitive mask 128 is used as an etch mask to etch and pattern the hard mask layer 126. The patterned hard mask layer 126 is then used as an etch mask to etch and pattern the top electrode layer 120, the MTJ film stack 118, and the one or more bottom electrode layers 116. Patterning may include one or more etching processes and may form recesses 130 in the IMD layer 108. The etching process may include a plasma etching process, such as ion beam etching (IBE). IBE provides a high degree of precision (e.g., high anisotropy), which can help control the profile of the resulting MRAM cells. Etching can be implemented using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), or the like.The photosensitive mask 128 and the hard mask layer 126 may be consumed in the etching process or may be removed after the etching process.

[0035] The etching process forms bottom electrodes 132, MTJ stacks 134, and top electrodes 136, which together form MRAM cells 58. Each MRAM cell 58 includes a bottom electrode 132, an MTJ stack 134, and a top electrode 136. The bottom electrodes 132 are formed from the remaining portions of the one or more bottom electrode layers 116. The MTJ stacks 134 comprise remaining portions of the MTJ film stack 118. The top electrodes 136 comprise remaining portions of the top electrode layer 120. In some embodiments, the etching process partially etches the IMD layer 108 and conductive vias 110. In such embodiments, the remaining portions of the IMD layer 108 have sloped sidewalls and, in the illustrated cross-section, have trapezoidal shapes. After the etching process, the remaining portions of the IMD layer 108 in the logic region 50L may have a thickness in the range of about 3 nm to about 30 nm.The MTJ stacks 134 and the bottom electrodes 132 also have sloped sidewalls and have trapezoidal shapes in the illustrated cross-section.

[0036] In Fig. 7, spacers 140 are formed on the sidewalls of the MRAM cells 58. The spacers 140 surround and protect the components of the MRAM cells 58. The spacers 140 may be formed from an oxide (e.g., silicon oxide, aluminum oxide, etc.), a nitride (e.g., silicon nitride, aluminum nitride, etc.), a carbide (e.g., silicon carbide), combinations thereof (e.g., silicon oxynitride, silicon carbonitride, etc.), multilayers thereof, or the like.

[0037] In an embodiment in which the spacers 140 comprise a multi-layer, the spacers 140 comprise passivation layers 142 and 144 and an oxide layer 146. As an example of forming the spacers 140, the passivation layer 142 may be formed overlying the MRAM cells 58 and in the recesses 130 (see Fig. 7). In some embodiments, the passivation layer 142 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, plasma-enhanced atomic layer deposition (PEALD), PVD, a combination thereof, or the like. In some embodiments, the passivation layer 142 may reduce or prevent the diffusion of moisture (e.g., H2O) into the MRAM cells 58 during subsequent processing. The passivation layer 142 is then patterned to expose portions of the top electrodes 136. In some embodiments, the patterning is a dry etching process, such as an anisotropic etching process. During patterning, horizontal portions of the passivation layer 142 are removed.Subsequently, another passivation layer 144 is formed over the passivation layer 142. In some embodiments, the passivation layer 144 is formed from one of the candidate materials and methods for the passivation layer 142, but is formed from a different material than the passivation layer 142. For example, the passivation layer 142 may be formed from an oxide, for example, silicon oxide, and the passivation layer 144 may be formed from a nitride, for example, silicon nitride. The oxide layer 146 is then formed over the passivation layer 144. In some embodiments, the oxide layer 146 may comprise silicon oxide or the like and may be formed using CVD, PECVD, ALD, PEALD, a combination thereof, or the like.Subsequently, one or more dry etching processes are performed to etch the passivation layer 144 and the oxide layer 146 and expose portions of the top electrodes 136. In some embodiments, the one or more dry etching processes are anisotropic etching processes and remove horizontal portions of the oxide layer 146. The remaining portions of the passivation layer 142, the passivation layer 144, and the oxide layer 146 form the spacers 140. The IMD layer 108 in the logic region 50L is exposed after patterning the spacers 140.

[0038] In Fig. 8, an etch stop layer 148 is formed over exposed portions of the spacers 140, the top electrodes 136, and the IMD layer 108. Then, an IMD layer 150 is formed on the etch stop layer 148. The etch stop layer 148 may be formed from a dielectric material such as aluminum nitride, aluminum oxide, silicon carbide, silicon carbonitride, a combination thereof, multilayers thereof, or the like. In some embodiments, the IMD layer 150 is formed using similar materials and methods as the IMD layer 108. In some embodiments, the etch stop layer 148 is formed from aluminum nitride, and the IMD layer 150 is formed from silicon oxide. Aluminum nitride and silicon oxide have high selectivity relative to an etch process used to pattern the IMD layer 150 (which will be discussed further below).The IMD layer 150 is formed to a thickness ranging from about 120 nm to about 160 nm. Due to structural loading, portions of the IMD layer 150 in the memory region 50M may extend over portions of the IMD layer 150 in the logic region 50L. The IMD layer 150 is formed to a sufficient thickness such that the portions of the IMD layer 150 in the logic region 50L have a greater thickness than the MRAM cells 58.

[0039] In Fig. 9, a planarization process is performed to planarize the IMD layer 150. The planarization process may be a CMP process, a mechanical grinding process, or the like. The MRAM cells 58 remain buried after the planarization process, and portions of the IMD layer 150 in the logic region 50L and the memory region 50M share a planar top surface after the planarization process.

[0040] In Fig. 10, a hard mask 152 is formed on the planar top surface of the IMD layer 150. The hard mask 152 may comprise a dielectric material such as silicon oxide, silicon nitride, titanium oxide, BSG, BPSG, USG, FSG, SiOCH, flowable oxide, a porous oxide, or the like; a conductive material such as titanium, tantalum, tungsten, alloys thereof, or the like; multilayers thereof, or the like. For example, the hard mask 152 may include a silicon carbide layer and a titanium nitride layer formed on the silicon carbide layer, wherein the titanium nitride layer has a thickness in the range of about 20 nm to about 40 nm and the silicon carbide layer has a thickness in the range of about 5 nm to about 15 nm. The silicon carbide layer is used as a glue layer to improve the adhesion between the titanium nitride layer and the IMD layer 150.After the masking material of the hard mask 152 has been formed, a patterning process is performed, with remaining portions of the masking material forming the hard mask 152. The patterning may be a dry etching process, such as an anisotropic etching process using a photoresist as an etch mask. The photoresist may be a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like. The resulting hard mask 152 has openings 154 that expose the underlying portions of the IMD layer 150.

[0041] Fig. Figure 11 is a top view of the MRAM device 50 after forming the hard mask 152. As will be discussed further below, the hard mask 152 is used to form the openings 156 (see Fig. 12) in the IMD layer 150 and expose the underlying MRAM cells 58. The openings 154 in the hard mask 152 are each arranged over several MRAM cells 58 along columns of the MRAM array 52 (see Fig. 1). Thus, each opening 156 (see Fig. 12), which is subsequently formed in the IMD layer 150, exposes a plurality of MRAM cells 58 along columns of the resulting MRAM array 52.

[0042] Each opening 154 is used to expose the same number of MRAM cells 58 in the memory region 50M. The openings 154 in the hard mask 152 have uniform dimensions, for example, uniform widths W1 and uniform lengths L1. The widths W1 of the openings 154 may range from about 25 nm to about 45 nm and are larger than diameters D1 of the MRAM cells 58, such as the diameters of the top electrodes 136. The diameter D1 may range from about 30 nm to about 40 nm. The lengths L1 may range from about 140 nm to about 50 µm and are large enough to bridge multiple MRAM cells 58. In the illustrated embodiment, the openings 154 fully expose the MRAM cells 58 in the middle region of the openings 154 and partially expose the MRAM cells 58 at the end regions of the openings 154.More specifically, the openings 154 may overlap with MRAM cells 58 at the end regions of the openings 154 by a distance D2 that may be less than about 10 nm.

[0043] Fig. Figure 11 further illustrates the reference cross sections used in later drawings. Cross section AA runs along one column of the MRAM array 52 (see Fig. 1) and in a direction of, for example, a bit line for the MRAM array 52. ​​The cross section BB is perpendicular to the cross section AA and runs along a row of the MRAM array 52 and in a direction of, for example, a word line for the MRAM array 52. ​​The subsequent drawings refer to these reference cross sections for clarity. More specifically, Fig. 12A, Fig. 13A and Fig. 14A along the cross section AA, and Fig. 12B, Fig. 13B and Fig. 14B are illustrated along the cross section BB.

[0044] In Fig. 12A and Fig. 12B, the hard mask 152 is used as an etch mask to pattern the IMD layer 150 and the etch stop layer 148. The patterning may include one or more etching processes and forms openings 156 in the IMD layer 150 and the etch stop layer 148. As shown, the openings 156 have substantially the same shape and dimensions (e.g., the same width W1 and the same length L1) as the openings 154 in the hard mask 152 (see Fig. 11). More specifically, a first etch process may be performed to form the openings 156 in the IMD layer 150, and a second etch process may be performed to extend the openings 156 through the etch stop layer 148. In some embodiments, the patterning is one or more dry etch processes, such as one or more anisotropic etch processes. The etch stop layer 148 helps protect the top electrodes 136, and thus the MTJ stacks 134, from overetch damage during the etching of the IMD layer 150. Because the width W1 of the openings 156 is greater than the diameter D1 of the MRAM cells 58 (see Fig. 11), the openings 156 define side walls of the upper electrodes 136 in the Fig. 12B. In some embodiments, remaining portions 148R of the etch stop layer 148R may remain between adjacent top electrodes 136. Although the remaining portions 148R of the etch stop layer 148R may remain, top surfaces of the top electrodes 136 are exposed.

[0045] The openings 156 have various depths, measured from the planar top surface of the IMD layer 150. The openings 156 have a depth D3 above the top electrodes 136, which may range from about 10 nm to about 30 nm. The openings 156 have a depth D4 above the remaining portions 148R of the etch stop layer 148, which may range from about 30 nm to about 40 nm. In this embodiment, the openings 156 do not completely expose the top surfaces of all of the top electrodes 136. Rather, some of the top surfaces of the top electrodes 136 are only partially exposed. In other embodiments (discussed further below), the openings 156 completely expose the top surfaces of all of the top electrodes 136.

[0046] In Fig. 13A and Fig. 13B, a shared electrode layer 158 is formed on the hard mask 152 and in the openings 156 (see Fig. 12A and Fig. 12B). The shared electrode layer 158 may be formed from a conductive material. In some embodiments, the shared electrode layer 158 is formed using similar materials and methods as the top electrode layer 120 (see Fig. 4) and / or the hard mask 152 in embodiments where the hard mask 152 is formed from a conductive material. The shared electrode layer 158 may be formed to a thickness in the range of about 50 nm to about 80 nm.

[0047] In Fig. 14A and Fig. 14B, a planarization process is performed to planarize the shared electrode layer 158 and the IMD layer 150. The planarization process may be a CMP process, a mechanical grinding process, or the like. The hard mask 152 and excess portions of the shared electrode layer 158 outside the openings 156 (see Fig. 13A and Fig. 13B) are removed by the planarization process. The planarization process forms shared electrodes 160, which comprise remaining portions of the shared electrode layer 158.

[0048] Fig. 15 is a top view of the MRAM device 50 after forming the shared electrodes 160. As shown, the shared electrodes 160 have substantially the same shape and dimensions (e.g., the same width W1 and the same length L1) as the openings 154 in the hard mask 152 (see Fig. 11). In this embodiment, the shared electrodes 160 completely overlap with the MRAM cells 58 in the middle regions of the shared electrodes 160, but only partially overlap with the MRAM cells 58 at the end regions of the shared electrodes 160.

[0049] In Fig. 16, the IMD layer 150, the etch stop layer 148, and the IMD layer 108 are patterned to expose the one or more etch stop layers 106 in the logic region 50L. In some embodiments, the patterning process may include suitable photolithography and etching processes. Portions of the IMD layer 150, the etch stop layer 148, and the IMD layer 108 in the memory region 50M remain after the patterning process.

[0050] In Fig. 17, a portion of the one or more etch stop layers 106 may optionally be removed, such as in embodiments where the one or more etch stop layers 106 comprise a multilayer. For example, if the one or more etch stop layers 106 comprise a first etch stop layer 106A and a second etch stop layer 106B, portions of the second etch stop layer 106B in the logic region 50L may be removed to expose the underlying first etch stop layer 106A. The second etch stop layer 106B may be removed using an isotropic wet cleaning process that is selective to the material of the second etch stop layer 106B.The etch process used to remove the second etch stop layer 106B may be different from the one or more etch processes used to pattern the IMD layer 150, the etch stop layer 148, and the IMD layer 108 (e.g., different etchants and / or different etch process parameters may be used). Using one or more multi-layered etch stop layers 106 may be advantageous in some embodiments. For example, the second etch stop layer 106B may be removed by the one or more etch processes used to etch the IMD layer 150, the etch stop layer 148, and the IMD layer 108 (see FIG. Fig. 16), may be etched more slowly than the first etch stop layer 106A. Likewise, the first etch stop layer 106A may be etched by one or more etch processes that are subsequently used to pattern openings for conductive features in the logic region 50L (see Fig. 21), are etched more slowly than the second etch stop layer 106B.

[0051] In Fig. 18, an IMD layer 162 is formed on the shared electrodes 160, the IMD layer 150, and the first etch stop layer 106A. In some embodiments, the IMD layer 162 is formed using similar materials and methods as the IMD layer 108. The IMD layer 162 may be formed to a thickness in the range of about 110 nm to about 165 nm. An anti-reflective layer 164 is then formed on the IMD layer 162. The anti-reflective layer 164 may be a nitrogen-free anti-reflective layer (NFARL) and may be formed from a nitrogen-free dielectric material such as silicon oxycarbide. The anti-reflective layer 164 may be formed to a thickness in the range of about 15 nm to about 40 nm. The anti-reflection layer 164 is used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0052] In Fig. 19, openings 166 are formed in the logic region 50L, exposing the conductive features 104 in the logic region 50L. More specifically, the openings 166 are formed through the anti-reflective layer 164, the IMD layer 162, and the first etch stop layer 106A. The openings 166 may be patterned using suitable photolithography and etching processes. Each of the openings 166 has an upper portion (e.g., trench portion) in which a line is formed, and a lower portion (e.g., via portion) in which a conductive via is formed. In some embodiments, the openings 166 are formed using a via-first process. In other embodiments, the openings 166 are formed using a trench-first process.As discussed further below, an optional etch-back process may be performed to remove portions of the IMD layer 162 and the anti-reflective layer 164 over the MRAM cells 58 before the openings 166 are formed.

[0053] In Fig. 20, a conductive material 168 is formed in the openings 166. The conductive material 168 may overfill the openings 166 and may also be formed over the IMD layer 162 and the anti-reflective layer 164. The conductive material 168 may be copper, aluminum, tungsten, gold, combinations thereof, or the like, and may be formed in the openings 166 by an electrochemical plating process, CVD, ALD, PVD, or the like, or a combination thereof.

[0054] In Fig. 21, a planarization process is performed to remove the excess of the conductive material 168 outside the openings 166. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization process may remove the anti-reflective layer 164 and expose the uppermost surfaces of the IMD layer 150 and the shared electrodes 160. The planarization process forms conductive features 170 that include remaining portions of the conductive material 168 in the openings 166. The conductive features 170 include conductive vias 170V formed in the lower portions (e.g., via portions) of the openings 166 and lines 170L formed in the upper portions (e.g., trench portions) of the openings 166. The memory region 50M can be free of the conductive vias 170V and the lines 170L.Although each conductive via 170V and corresponding line 170L are illustrated as a separate element, it should be understood that they may be a continuous conductive feature, such as in embodiments where they are formed using a double damascene process. After the planarization process, the top surfaces of the conductive features 170, the IMD layer 162, the IMD layer 150, and the shared electrodes 160 are planar.

[0055] After the planarization process, the shared electrodes 160 have different heights, measured from the planar top surface of the IMD layer 150. The shared electrodes 160 have a height H1 above the top electrodes 136, which may range from about 15 nm to about 25 nm. The shared electrodes 160 have a height H2 above the remaining portions 148R (see Fig. 12A) of the etch stop layer 148, which may be in the range of about 23 nm to about 35 nm.

[0056] In Fig. 22, another metallization layer (for example M6, see Fig. 2) of the interconnect structure. The metallization layer comprises one or more etch stop layers 172, an IMD layer 174, and the conductive features 176. The conductive features include conductive vias 176V (which may correspond to the metal vias V6, see Fig. 2) and lines 176L (which can correspond to the metal lines L6, see Fig. 2) and are formed in both the logic region 50L and the memory region 50M. In some embodiments, the one or more etch stop layers 172 may be formed using similar materials and methods as the one or more etch stop layers 106. In some embodiments, the IMD layer 174 is formed using similar materials and methods as the IMD layer 162. In some embodiments, the conductive vias 176V and the lines 176L are formed using similar materials and methods as the conductive vias 176V and the lines 176L, respectively. Although each conductive via 176V and corresponding line 176L is illustrated as a separate element, it should be understood that they may be a continuous conductive feature, such as in embodiments where they are formed using a double damascene process.Notably, the conductive vias 176V and the lines 176L may be formed from a different conductive material than the shared electrodes 160. By selecting different conductive materials, the contact resistance of the shared electrodes 160 can be tuned. The conductive features 176 are electrically connected to the memory devices (e.g., MRAMs) formed in the memory region 50M and the logic devices (e.g., logic circuits) formed in the logic region 50L. More specifically, some of the conductive vias 176V are physically and electrically connected to the shared electrodes 160. In some embodiments, the conductive vias 176V and the lines 176L electrically connect the memory devices in the memory region 50M to the logic devices in the logic region 50L.In some embodiments, the conductive features 176 in the logic region 50L and the memory region 50M are formed in the same process. In some embodiments, the conductive features 176 in the logic region 50L and the conductive features 176 in the memory region 50M are formed in different processes. For example, because the shared electrodes 160 provide an increased contact area, the conductive features 176 in the memory region 50M may be formed larger (e.g., wider) than the conductive features 176 in the logic region 50L, which may help reduce the contact resistance to the MRAM cells 58.

[0057] Fig. Figure 23 is an open plan view of the MRAM device 50 after forming the conductive vias 176V and the lines 176L. As shown, the lines 176L comprise bit lines BL for the MRAM array 52 (see Fig. 1). Each bit line BL is electrically connected to a plurality of shared electrodes 160 through the conductive vias 176V. Each of the shared electrodes 160 is in turn electrically connected to a plurality of MRAM cells 58 (see Fig. 15). The conductive vias 176V have a width W2 that may range from about 45 nm to about 65 nm. The widths W1 of the shared electrodes 160 are greater than the widths W2 of the conductive vias 176V.

[0058] Embodiments can realize advantages. The diameters D1 of the MRAM cells 58 (see Fig. 11) may be small. More specifically, the diameters D1 of the MRAM cells 58 are smaller than the widths W2 of the conductive vias 176V, especially when the MRAM cells 58 are arranged in a higher level (for example, M5 in Fig. 2) an interconnect structure. However, the widths W1 of the shared electrodes 160 are larger than the widths W2 of the conductive vias 176V. Advantageously, the shared electrodes 160 thus provide sufficiently large contact areas for the conductive vias 176V, which may prevent strike-through to the underlying layers during the formation of the conductive vias 176V. For example, the top electrodes 136 and the MTJ stacks 134 may be protected from overetch damage during the etching of the openings for the conductive vias 176V. Furthermore, by providing a larger contact area, the contact resistance of the conductive vias 176V may be reduced.Finally, as mentioned above, the conductive material chosen for the shared electrodes 160 may be different from that of the overlying conductive features 176, thereby allowing the contact resistance of the shared electrodes 160 to be tuned.

[0059] Fig. 24 and Fig. 25 are various views of an MRAM device 50 according to some embodiments. Fig. 24 is illustrated at a similar stage of production as Fig. 15, and Fig. 25 is illustrated at a similar stage of production as Fig. 22. In this embodiment, the shared electrodes 160 are formed to a longer length L1 than in the previous embodiment. For example, in this embodiment, the lengths L1 may range from about 150 nm to about 50 µm. Due to their longer length L1, the shared electrodes 160 do not partially overlap with the MRAM cells 58 at the end regions of the shared electrodes 160. Rather, in this embodiment, the shared electrodes 160 completely overlap with all MRAM cells 58 with which the shared electrodes 160 are in contact. By increasing the contact area, the contact resistance to the MRAM cells 58 can be further reduced.

[0060] Fig. 26 to 40 are cross-sectional views of intermediate stages in the fabrication of an interconnect structure for the MRAM device 50 according to some other embodiments. The interconnect structure also includes an MRAM array of memory cells. As discussed further below, protection structures are formed around the memory cells of the MRAM array to help protect the memory cells during the subsequent formation of overlying metallization layers. Some of the Fig. The features shown in figures 26 to 40 are similar to those shown in Fig. 3 to 23, and their descriptions will not be repeated. Such features are shown using similar reference numerals.

[0061] In Fig. 26 an intermediate structure similar to that in relation to Fig. 6. A passivation layer 202 is then formed over the MRAM cells 58 and in the recesses 130 (see Fig. 6). In some embodiments, the passivation layer 202 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, plasma-enhanced atomic layer deposition (PEALD), PVD, a combination thereof, or the like. In some embodiments, the passivation layer 202 is a nitride, such as silicon nitride. The passivation layer 202 may reduce or prevent the diffusion of moisture (e.g., H2O) into the MRAM cells 58 during subsequent processing. The passivation layer 202 is formed to a thickness ranging from about 50 nm to about 1500 nm. More specifically, the passivation layer 202 is formed to a thickness sufficient to fill the recesses 130 and bury the MRAM cells 58.

[0062] A dielectric layer 204 is then formed over the passivation layer 202. In some embodiments, the dielectric layer 204 is formed using similar materials and methods as the IMD layer 108. For example, the dielectric layer 204 may be formed from an oxide, such as silicon oxide. The dielectric layer 204 may be formed to a thickness in the range of about 10 nm to about 30 nm.

[0063] Subsequently, a planarization stop layer 206 is formed on the dielectric layer 204. The planarization stop layer 206 may be a nitrogen-free layer and may be formed from a nitrogen-free dielectric material. For example, the planarization stop layer 206 may be formed from a doped or undoped oxide, such as silicon oxycarbide. The planarization stop layer 206 may be formed to a thickness in the range of about 8 nm to about 15 nm. The planarization stop layer 206 is used to protect the logic region 50L during subsequent processing (discussed further below).

[0064] A dielectric layer 208 is then formed over the planarization stop layer 206. In some embodiments, the dielectric layer 208 is formed using similar materials and methods as the IMD layer 108 and the dielectric layer 204. For example, the dielectric layer 208 may be formed from silicon oxide. The dielectric layer 208 may be formed to a thickness in the range of about 20 nm to about 40 nm.

[0065] A coating layer 210 is then formed over the dielectric layer 208. The coating layer 210 acts as a buffer layer to reduce topography variations during a subsequent etch-back process. The coating layer 210 may be formed using a coating process, for example, a spin-coating process. The coating layer 210 may be formed from a material that is ashable and liquid, such as a bottom layer of photoresist. After the spin-coating process, the material may be cured. Curing the material hardens the coating layer 210. In some embodiments, curing the material includes exposing the material to an elevated temperature.

[0066] In Fig. 27, an etch-back process is performed to remove portions of the overlay layer 210, the dielectric layer 208, and the planarization stop layer 206. More specifically, the etch-back process removes portions of the planarization stop layer 206 in the memory region 50M to expose portions of the dielectric layer 204 over the MRAM cells 58. The logic region 50L is covered by the remaining portions of the planarization stop layer 206. The etch-back process may be a dry etch process using an etchant such as CH x F y, CF4, He, O2, N2, Ar, NF3, SF6, combinations thereof, or the like is used as an etching gas. The overcoat layer 210 may be consumed by the etchback process, or the overcoat layer 210 may be removed after the etchback process, for example, by a suitable ashing or stripping process. In some embodiments, some portions of the overcoat layer 210 remain in the logic region 50L after the etchback process, and those portions are removed after the etchback process.

[0067] In Fig. 28, a planarization process is performed to expose the top electrodes 136 of the MRAM cells 58. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization process removes remaining portions of the dielectric layer 208 and also removes portions of the dielectric layer 204 above the MRAM cells 58. The planarization stop layer 206 has a lower removal rate relative to the planarization process than the dielectric layers 204 and 208. Therefore, the planarization process may be performed until the planarization stop layer 206 (and thus the top electrodes 136) is exposed.In some embodiments, the uppermost surface of the planarization stop layer 206 is formed to a thickness such that it extends above the uppermost surfaces of the upper electrodes 136, and the upper electrodes 136 are exposed, for example, by dishing, which may occur during the planarization process. The exposed portions of the planarization stop layer 206 cover the logic region 50L and may cover a portion of the memory region 50M. Although the planarization process does not remove the planarization stop layer 206, it may reduce the thickness of the planarization stop layer 206. After the planarization process, the planarization stop layer 206 may have a thickness T1 in the range of about 5 nm to about 10 nm.

[0068] In Fig. 29, an etch-back process 212 is performed to remove the passivation layer 202 and form recesses 214 around the top electrodes 136 of the MRAM cells 58. The recesses 214 are formed to a depth D5, which may range from about 5 nm to about 20 nm. The recesses 214 expose the sidewalls of the top electrodes 136 but do not expose the sidewalls of the MTJ stacks 134. The sidewalls of the MTJ stacks 134 remain covered and protected by the passivation layer 202 after the etch-back process 212.

[0069] The etch-back process 212 is selective for the material of the passivation layer 202. As mentioned above, in some embodiments, the passivation layer 202 is a nitride, and the dielectric layer 204 and the planarization stop layer 206 are oxides. In such embodiments, the etch-back process 212 may etch the material of the passivation layer 202 (e.g., nitrides) at a higher rate than the one or more materials of the dielectric layer 204 and the planarization stop layer 206 (e.g., oxides). For example, the ratio of the etch rate of the passivation layer 202 to the etch rates of the dielectric layer 204 and the planarization stop layer 206, relative to the etch-back process 212, may range from about 3:1 to about 10:1.As an example of the etch-back process 212, a dry etching process such as IBE, reactive ion etching (RIE) or the like using an etchant such as HBr, CF4, He, O2, N2, CH may be used. x F y, combinations thereof, or the like as an etching gas. Carrier gases for the etching gas may include N2, Ar, He, combinations thereof, or the like. The etching may be implemented using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), or the like. The etching may be performed with a source power ranging from about 100 watts to about 1500 watts and may be performed with a bias voltage of up to about 1000 volts. The etching may be performed for a duration ranging from about 7 seconds to about 300 seconds.Performing the etch-back process 212 with such parameters enables high etch selectivity between the material of the passivation layer 202 (e.g., nitrides) and the one or more materials of the dielectric layer 204 and the planarization stop layer 206 (e.g., oxides).

[0070] Although the etch-back process 212 is selective for the material of the passivation layer 202, some etching of the planarization stop layer 206 may still occur. For example, the etch-back process 212 may reduce the thickness of the planarization stop layer 206 to a thickness T2 in the range of about 1 nm to about 5 nm. The new thickness T2 of the planarization stop layer 206 is less than the original thickness T1 of the planarization stop layer 206, but still sufficiently thick to withstand subsequent processing. In some embodiments, the new thickness T2 of the planarization stop layer 206 is at least half of the original thickness T1 of the planarization stop layer 206.

[0071] In Fig. 30, a protective layer 216 is formed in the recesses 214 and on exposed surfaces of the MRAM cells 58, the dielectric layer 204, and the planarization stop layer 206. The protective layer 216 is formed on a dielectric material such as aluminum nitride, aluminum oxide, silicon carbide, silicon carbonitride, a combination thereof, multilayers thereof, or the like, and is formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), ALD, combinations thereof, or the like. The protective layer 216 is formed from a material that has high selectivity with respect to an etch process used to pattern subsequently formed metallization layers of the interconnect structure (as discussed further below).For example, the protective layer 216 may be a silicon carbide layer, an aluminum oxide layer, or a multilayer comprising a silicon carbide sublayer and an aluminum oxide sublayer on the silicon carbide sublayer. Once formed, the protective layer 216 surrounds the top electrodes 136 of the MRAM cells 58. Forming the protective layer 216 in the recesses 214 advantageously enables self-alignment of the protective layer 216 to the top electrodes 136 of the MRAM cells 58.

[0072] In Fig. 31, a planarization process is performed to expose the top electrodes 136 of the MRAM cells 58. The planarization process removes portions of the protective layer 216 outside the recesses 214 (see Fig. 29), for example, portions of the protective layer 216 over the MRAM cells 58, the dielectric layer 204, and the planarization stop layer 206. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization stop layer 206 has a lower removal rate than the protective layer 216 relative to the planarization process. Therefore, the planarization process may be performed until the planarization stop layer 206 is exposed. The top electrodes 136 are exposed after the planarization process. The planarization process forms protective structures 218 that include the portions of the protective layer 216 that remain in the recesses 214 after the planarization process.

[0073] Several planarization processes are performed using the planarization stop layer 206. More specifically, the planarization processes are performed by Fig. 28 and Fig. 31, both are performed, and both are stopped on the planarization stop layer 206. Performing multiple planarization processes helps reduce non-uniform topography that may be caused by variations in feature density between the logic region 50L and the memory region 50M, and helps ensure that the features in the logic region 50L and the memory region 50M share a planar surface.

[0074] After the planarization process, the protection structures 218 have a thickness T3, which may range from about 8 nm to about 20 nm, and the top electrodes 136 have a thickness T4, which may range from about 15 nm to about 30 nm. The thickness T3 is smaller than the thickness T4. More specifically, the thickness T3 of the protection structures 218 is sufficient to ensure that the MRAM cells 58 are protected during subsequent processing, but small enough to ensure that the sidewalls of the MTJ stacks 134 are free of unwanted materials (thereby maintaining their desired high resistance values ​​(R ap ) and low resistance values ​​(R p ) such as residues from a subsequent contact etching process (discussed below).

[0075] In Fig. 32, an anti-reflection layer 220 is formed on the planarized surface of the intermediate structure. More specifically, the anti-reflection layer 220 is formed on planarized surfaces of the protective structures 218, the upper electrodes 136, the planarization stop layer 206, and the dielectric layer 204. The anti-reflection layer 220 may be a nitrogen-free anti-reflection layer (NFARL) and may be made of a nitrogen-free dielectric material such as, for example, Silicon oxycarbide may be formed. In some embodiments, the anti-reflection layer 220 is formed from a different material than the protection structures 218. The anti-reflection layer 220 may be formed to a thickness in the range of about 10 nm to about 35 nm. The anti-reflection layer 220 is used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0076] In Fig. 33, the intermediate structure is patterned to expose the one or more etch stop layers 106 in the logic region 50L. The patterning may include suitable photolithography and etching processes. For example, one or more dry etch processes may be performed using an etch mask 222 to etch the anti-reflection layer 220, the planarization stop layer 206, the dielectric layer 204, the passivation layer 202, and the IMD layer 108. The etch mask 222 may be a photoresist, such as a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like. In some embodiments, the remaining portions of the planarization stop layer 206 are removed by the etch process(es). In some embodiments (discussed below), portions of the planarization stop layer 206 may remain after the one or more etch processes.Some portions of the dielectric layer 204 may remain in the storage region 50M after the one or more etch processes. The one or more etch processes form one or more openings 224 exposing the one or more etch stop layers 106, such as the second etch stop layer 106B in embodiments where the one or more etch stop layers 106 comprise a multilayer. The etch mask 222 may be consumed by the one or more etch processes, or the etch mask 222 may be removed after the one or more etch processes, for example, by a suitable ashing or stripping process.

[0077] In Fig. 34, a portion of the one or more etch stop layers 106 may optionally be removed, such as in embodiments where the one or more etch stop layers 106 comprise a multilayer. For example, if the one or more etch stop layers 106 comprise a first etch stop layer 106A and a second etch stop layer 106B, portions of the second etch stop layer 106B in the one or more openings 224 may be removed to expose the underlying first etch stop layer 106A. The second etch stop layer 106B may be removed using an isotropic wet cleaning process that is selective to the material of the second etch stop layer 106B.The etch process used to remove the second etch stop layer 106B may be different from the one or more etch processes used to initially form the openings 224 (e.g., different etchants and / or different etch process parameters may be used). The use of one or more multi-layer etch stop layers 106 may be advantageous in some embodiments. For example, the second etch stop layer 106B may be formed by the one or more etch processes used to etch the anti-reflective layer 220, the planarization stop layer 206, the dielectric layer 204, the passivation layer 202, and the IMD layer 108 (see FIG. Fig. 32), may be etched more slowly than the first etch stop layer 106A. Likewise, the first etch stop layer 106A may be etched by one or more etch processes that are subsequently used to pattern openings for conductive features in the logic region 50L (see Fig. 39), are etched more slowly than the second etch stop layer 106B.

[0078] In Fig. 35, the IMD layer 162 is formed in the one or more openings 224 and over the MRAM cells 58 and protection structures 218, such as on the anti-reflective layer 220. The anti-reflective layer 164 is then formed on the IMD layer 162. The anti-reflective layer 164 is used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0079] In Fig. 36, an etch-back process may optionally be performed to remove portions of the IMD layer 162 and the anti-reflective layer 164 over the MRAM cells 58, thereby exposing the anti-reflective layer 220. Portions of the logic region 50L, such as portions over the conductive features 104, may be covered by an etch mask 226 during the etch-back process. The etch-back process may be a dry etch process using an etchant such as CH x F y, CF4, He, O2, N2, Ar, NF3, SF6, combinations thereof, or the like is used as an etch gas. The etch mask 226 may be consumed by the etch-back process, or the etch mask 226 may be removed after the etch-back process, for example, by a suitable ashing or stripping process. After the etch-back process, the remaining portions of the anti-reflective layer 164 are disposed in the logic region 50L and do not extend into the memory region 50M. In some embodiments, the etch-back process is omitted, and the portions of the IMD layer 162 and the anti-reflective layer 164 over the MRAM cells 58 may be removed during a subsequent planarization process (as discussed further below).

[0080] In Fig. 37, the openings 166 are formed in the logic region 50L, exposing the conductive features 104 in the logic region 50L. More specifically, the openings 166 are formed through the anti-reflective layer 164, the IMD layer 162, and the one or more etch stop layers 106 (e.g., the first etch stop layer 106A) remaining in the logic region 50L. The openings 166 may be formed using similar processes and materials as those described above with respect to Fig. 19 discussed above.

[0081] In Fig. 38, the conductive material 168 is formed in the openings 166. The conductive material 168 may overfill the openings 166 and may also be formed over the IMD layer 162 and the anti-reflective layers 164 and 220. The conductive material 168 may be formed using similar processes and materials as those described above with respect to Fig. 20 discussed will be formed.

[0082] In Fig. 39, a planarization process is performed to remove the excess of the conductive material 168 outside the openings 166. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization process may remove the anti-reflective layers 164 and 220 and expose the top electrodes 136 and protective structures 218. The planarization process forms the conductive features 170. After the planarization process, the top surfaces of the conductive features 170, the IMD layer 162, the protective structures 218, the dielectric layer 204, and the top electrodes 136 are planar.

[0083] As mentioned above, the Fig. 36 is optional. The etch-back process may help reduce uneven topography that may be caused by variations in the structure density between the logic region 50L and the memory region 50M. In some embodiments, the etch-back process shown in Fig. 36 is omitted, and the portions of the IMD layer 162 and the anti-reflective layer 164 over the MRAM cells 58 may instead be removed during the etching process shown in Fig. 39 shown planarization process.

[0084] In Fig. 40, the one or more etch stop layers 172, the IMD layer 174, and the conductive features 176 are formed. In the illustrated embodiment, the one or more etch stop layers 172 comprise a single etch stop layer 172, such as a layer of silicon nitride. The conductive vias 176V in the memory region 50M are physically and electrically connected to the top electrodes 136. The MRAM cells 58 may be small, particularly when high-density memory is desired. For example, the diameters D1 of the top electrodes 136 may be smaller than the width W2 of the overlying conductive vias 176V, particularly when the MRAM cells 58 are formed in a higher level (for example, M5 in Fig. 2) an interconnect structure. Thus, the conductive vias 176V can contact the upper electrodes 136 and portions of the protective structures 218.

[0085] In some embodiments, the conductive features 176 are formed using similar materials and methods as the conductive features 170. For example, openings are formed exposing the conductive features 170 and the top electrodes 136. The openings are filled with a conductive material, and then a planarization process is performed to form the conductive features 176, including remaining portions of the conductive material in the openings. Once the openings for the conductive features 176 are formed, the IMD layer 174 is patterned using a first etch process, and the etch stop layer 172 is used to stop the first etch process. The first etch process may include suitable photolithography and etch steps. The etch stop layer 172 is then opened using a second etch process to expose the conductive features 170 and the top electrodes 136.The second etching process may include suitable photolithography and etching steps. The protective structures 218 surround and protect the MRAM cells 58 during the second etching process. Protection can be achieved in various ways. The protective structures 218 prevent the second etching process from etching the MTJ stacks 134 of the MRAM cells 58. Damage to the MRAM cells 58 can thus be avoided.

[0086] In some embodiments, the protection structures 218 are formed from a similar etch stop material as the etch stop layer 172. This increases the amount of etch stop material protecting the MRAM cells 58, thereby increasing the process window for the second etch process. The likelihood of etching the MTJ stacks 134 is thereby reduced.

[0087] In some embodiments, the protective structures 218 are formed from a different etch stop material than the etch stop layer 172. More specifically, the second etch process may be selective for the material of the etch stop layer 172. For example, in some embodiments, the protective structures 218 are silicon carbide and / or aluminum oxide, and the etch stop layer 172 is silicon nitride. In such embodiments, the second etch process may etch the material of the etch stop layer 172 (e.g., silicon nitride) at a higher rate than the material of the protective structures 218 (e.g., silicon carbide and / or aluminum oxide). For example, the ratio of the etch rate of the etch stop layer 172 to the etch rate of the protective structures 218, relative to the second etch process, may range from about 1 to about 5. As an example of the second etch process, an isotropic wet cleaning process may be performed that is selective for the material of the etch stop layer 172.The etching may be performed with a solution containing water, such as deionized water, carbonated deionized water, or the like. The etching may be performed for a duration ranging from about 5 seconds to about 600 seconds. Performing the second etch process with such parameters enables high etch selectivity between the material of the etch stop layer 172 (e.g., silicon nitride) and the material of the protective structures 218 (e.g., silicon carbide and / or aluminum oxide). The likelihood of etching the MTJ stacks 134 is thereby further reduced.

[0088] Fig. 41 is a cross-sectional view of the MRAM device 50 according to some other embodiments. Fig. 41 shows an embodiment where some etching of the protection structures 218 occurs during the formation of a conductive feature 176. As shown, the protection structures 218 contribute to the protection of the MTJ stacks 134 even if partial breakdown of the protection structures 218 occurs.

[0089] Fig. 42 is a cross-sectional view of the MRAM device 50 according to some other embodiments. In this embodiment, portions of the planarization stop layer 206 remain after the one or more etch processes of Fig. 33. Such remaining portions of the planarization stop layer 206 are disposed between the etch stop layer 172 and the remaining portions of the dielectric layer 204.

[0090] Embodiments may realize advantages. Forming the protection structures 218 around the top electrodes 136 contributes to protecting the MRAM cells 58 during formation of the overlying metallization layer. More specifically, etching of the MTJ stacks 134 during formation of the conductive features 176 may be avoided. The protection structures 218 may protect the top electrodes 136 by either increasing the process window for forming the conductive features 176 or serving as an etch stop layer to prevent etching of the MTJ stacks 134. Damage to the MRAM cells 58 may thus be avoided, increasing the production yield of the resulting devices.

[0091] Although embodiments have been described in the context of MRAM cells, it should be understood that similar techniques can be used to form other types of memory cells with programmable resistive elements. For example, similar techniques can be used in forming PCRAM (Phase-Change Memory) cells, RRAM (Resistive Random Access Memory) cells, and the like.

[0092] In one embodiment, a device comprises: a magnetoresistive random access memory (MRAM) array comprising MRAM cells arranged in rows and columns, wherein a first column of the columns comprises: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; a bit line electrically connected to the first shared electrode and the second shared electrode; first top electrodes arranged between the first MTJ stacks and the first shared electrode;second top electrodes disposed between the second MTJ stacks and the second shared electrode; a first conductive via physically and electrically connecting the bit line to the first shared electrode; and a second conductive via physically and electrically connecting the bit line to the second shared electrode, wherein widths of the first conductive via and the second conductive via are greater than widths of each of the first top electrodes and each of the second top electrodes; and wherein widths of the first shared electrode and the second shared electrode are greater than the widths of the first top electrodes, the second top electrodes, the first conductive via, and the second conductive via.

[0093] In some embodiments of the device, the first bottom electrodes, the second bottom electrodes, the first shared electrode, and the second shared electrode each include titanium nitride, and the bit line includes copper. In some embodiments of the device, the first shared electrode completely overlaps with each of the first top electrodes. In some embodiments of the device, the first shared electrode completely overlaps with a first subset of the first top electrodes and partially overlaps with a second subset of the first top electrodes. In some embodiments of the device, the first shared electrode and the second shared electrode have the same length along the first column.In some embodiments of the device, each row of the rows has a word line electrically connected to one of the first bottom electrodes or the second bottom electrodes, and further comprises: a row decoder electrically connected to the word line of each of the rows; and a column decoder electrically connected to the bit line. In some embodiments of the device, the first column further comprises: a first spacer laterally surrounding the first bottom electrodes and the first MTJ stacks; an etch stop layer extending along top surfaces and sidewalls of the first spacer; and a first intermetal dielectric (IMD) layer on the etch stop layer, wherein the first shared electrode extends through the first IMD layer and the etch stop layer. In some embodiments of the device, the etch stop layer includes aluminum nitride.

[0094] In one embodiment, a method comprises: forming a first intermetal dielectric (IMD) layer over a substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a top electrode layer over the MTJ film stack; patterning the top electrode layer, the MTJ film stack, and the bottom electrode layer to form a first magnetoresistive random access memory (MRAM) cell and a second MRAM cell; forming a spacer around sidewalls of the first MRAM cell and the second MRAM cell; depositing an etch stop layer over the spacer and exposed portions of the first IMD layer; depositing a second IMD layer over the etch stop layer; exposing portions of the first MRAM cell and the second MRAM cell;and forming a shared electrode on the exposed portions of the first MRAM cell and the second MRAM cell. Exposing the portions of the first MRAM cell and the second MRAM cell comprises etching an opening in the second IMD layer and the etch stop layer, the opening fully exposing a first upper surface of the first MRAM cell and partially exposing a second upper surface of the second MRAM cell.

[0095] In some embodiments of the method, exposing the portions of the first MRAM cell and the second MRAM cell comprises etching an opening in the second IMD layer, and forming the shared electrode comprises: depositing a conductive material in the opening; and planarizing the conductive material to remove portions of the conductive material outside the opening, wherein the shared electrode has remaining portions of the conductive material after planarization. In some embodiments, the method further comprises: depositing a third IMD layer over the shared electrode and the second IMD layer; planarizing the third IMD layer such that the surfaces of the third IMD layer, the second IMD layer, and the shared electrode are planar; and forming conductive features in the third IMD layer.In some embodiments, the method further comprises: depositing a fourth IMD layer over the third IMD layer, the second IMD layer, and the shared electrode; forming a conductive via in the fourth IMD layer; and forming a bitline in the fourth IMD layer, wherein the conductive via electrically and physically connects the bitline to the shared electrode.

[0096] In one embodiment, a method comprises: forming a magnetoresistive random access memory (MRAM) cell over a substrate, the MRAM cell comprising: a first bottom electrode over the substrate; a first magnetic tunnel junction (MTJ) stack over the first bottom electrode; a first top electrode over the first MTJ stack; forming a first dielectric layer laterally surrounding the first bottom electrode, the first MTJ stack, and the first top electrode; recessing the first dielectric layer to expose portions of sidewalls of the first top electrode; forming a protective structure contacting the exposed portions of the sidewalls of the first top electrode; depositing a first intermetal dielectric (IMD) layer over the MRAM cell;and forming a conductive feature extending through the first IMD layer, wherein the conductive feature contacts the first top electrode and the protective structure. The method further comprises forming an etch stop layer over the protective structure, wherein the first IMD layer is deposited over the etch stop layer, wherein the etch stop layer includes silicon nitride, and wherein the protective structure includes silicon carbide or aluminum oxide.

[0097] In some embodiments of the method, recessing the first dielectric layer forms a recess, and forming the protective structure comprises: depositing a second dielectric layer in the recess; and planarizing the second dielectric layer to form the protective structure, wherein the surfaces of the protective structure and the first top electrode are planar.

Claims

[1] Device comprising: a magnetoresistive random access memory array (52), MRAM array comprising MRAM cells (58) arranged in rows and columns, a first column of the columns comprising: - first lower electrodes (132) arranged along the first column; - first magnetic tunnel junction stack (134), MTJ stack, over the first lower electrodes (132); - a first shared electrode (160) over each of the first MTJ stacks (134); - second lower electrodes (132) arranged along the first column; - second MTJ stacks (134) above the second lower electrodes (132); - a second shared electrode (160) over each of the second MTJ stacks (134); and - a bit line (176L, BL) electrically connected to the first shared electrode (160) and the second shared electrode (160); - first upper electrodes (136) arranged between the first MTJ stacks (134) and the first shared electrode (160); - second upper electrodes (136) arranged between the second MTJ stacks (134) and the second shared electrode (160); - a first conductive via (176V) physically and electrically connecting the bit line (176L, BL) to the first shared electrode (160); and - a second conductive via (176V) physically and electrically connecting the bit line (176L, BL) to the second shared electrode (160), wherein widths of the first conductive via (176V) and the second conductive via (176V) are greater than widths of each of the first upper electrodes (136) and each of the second upper electrodes (136); and wherein widths of the first shared electrode (160) and the second shared electrode (160) are greater than the widths of the first upper electrodes (136), the second upper electrodes (136), the first conductive via (176V) and the second conductive via (176V). [2] The device of claim 1, wherein the first lower electrodes (132), the second lower electrodes (132), the first shared electrode (160) and the second shared electrode (160) each comprise titanium nitride, and wherein the bit line (176L, BL) comprises copper. [3] The device of claim 1 or 2, wherein the first shared electrode (160) completely overlaps with each of the first upper electrodes (136). [4] The device of claim 1 or 2, wherein the first shared electrode (160) completely overlaps with a first subset of the first upper electrodes (136) and partially overlaps with a second subset of the first upper electrodes (136). [5] The device of any preceding claim, wherein the first shared electrode (160) and the second shared electrode (160) have the same lengths along the first column. [6] A device according to any one of the preceding claims, wherein each of the rows comprises a word line electrically connected to one of the first lower electrodes (132) or the second lower electrodes (132), and further comprising: a row decoder (54) electrically connected to the word line of each of the rows; and a column decoder (56) electrically connected to the bit line (176L, BL). [7] Apparatus according to any one of the preceding claims, wherein the first column further comprises: a first spacer (140) laterally surrounding the first lower electrodes (132) and the first MTJ stacks (134); an etch stop layer (148) extending along upper surfaces and sidewalls of the first spacer (140); and a first intermetal dielectric layer (150), IMD layer, on the etch stop layer (148), wherein the first shared electrode (160) extends through the first IMD layer (150) and the etch stop layer (148). [8] The device of claim 7, wherein the etch stop layer (148) comprises aluminum nitride. [9] Procedure comprising: Forming a first intermetal dielectric layer (108), IMD layer, over a substrate (60); Forming a lower electrode layer (116) over the first IMD layer (108); Forming a magnetic tunnel junction film stack (118), MTJ film stack, over the bottom electrode layer (116); Forming a top electrode layer (120) over the MTJ film stack (118); Patterning the top electrode layer (120), the MTJ film stack (118), and the bottom electrode layer (116) to form a first MRAM cell (58) and a second MRAM cell (58); Forming a spacer (140) around sidewalls of the first MRAM cell (58) and the second MRAM cell (58); Depositing an etch stop layer (148) over the spacer (140) and exposed portions of the first IMD layer (108); Depositing a second IMD layer (150) over the etch stop layer (148); Exposing portions of the first MRAM cell (58) and the second MRAM cell (58); and Forming a shared electrode (160) on the exposed portions of the first MRAM cell (58) and the second MRAM cell (58); wherein exposing the portions of the first MRAM cell (58) and the second MRAM cell (58) comprises etching an opening into the second IMD layer (150) and the etch stop layer (148), the opening fully exposing a first upper surface of the first MRAM cell and partially exposing a second upper surface of the second MRAM cell. [10] The method of claim 9, wherein exposing the portions of the first MRAM cell (58) and the second MRAM cell (58) comprises etching an opening (156) in the second IMD layer (150), and wherein forming the shared electrode (160) comprises: depositing a conductive material in the opening (156); and Planarizing the conductive material to remove portions of the conductive material outside the opening, wherein the shared electrode (160) comprises remaining portions of the conductive material after planarizing. [11] The method of claim 9 or 10, further comprising: depositing a third IMD layer (162) over the shared electrode (160) and the second IMD layer (150); Planarizing the third IMD layer (162) such that the surfaces of the third IMD layer (162), the second IMD layer (150) and the shared electrode (160) are planar; and Forming conductive features (170) in the third IMD layer (162). [12] The method of claim 11, further comprising: depositing a fourth IMD layer (174) over the third IMD layer (162), the second IMD layer (150) and the shared electrode (160); Forming a conductive via (176V) in the fourth IMD layer (174); and Forming a bit line (176L, BL) in the fourth IMD layer (174), wherein the conductive via (176V) electrically and physically connects the bit line to the shared electrode (160). [13] Procedure comprising: Forming an MRAM cell (58) over a substrate (60), the MRAM cell comprising: - a first lower electrode (132) above the substrate (60); - a first magnetic tunnel junction stack (134), MTJ stack, over the first lower electrode (132); - a first upper electrode (136) above the first MTJ stack (134); Forming a first dielectric layer (202) laterally surrounding the first lower electrode (132), the first MTJ stack (134), and the first upper electrode (136); recessing the first dielectric layer (202) to expose portions of sidewalls of the first top electrode (136); Forming a protective structure (218) that contacts the exposed portions of the sidewalls of the first upper electrode (136); Depositing a first intermetal dielectric layer (174), IMD layer, over the MRAM cell (58); and Forming a conductive feature (176) extending through the first IMD layer (174), the conductive feature contacting the first top electrode (136) and the protective structure (218); the method further comprising: Forming an etch stop layer (172) over the protective structure (218), wherein the first IMD layer (174) is deposited over the etch stop layer (172), wherein the etch stop layer (172) contains silicon nitride, and wherein the protective structure (218) contains silicon carbide or aluminum oxide. [14] The method of claim 13, wherein the recessing of the first dielectric layer (202) forms a recess (214), and wherein the forming of the protective structure (218) comprises: Depositing a second dielectric layer (216) in the recess (214); and Planarizing the protective structure (218) silicon carbide to form the protective structure (218), wherein surfaces of the protective structure (218) and the first upper electrode (136) are planar.

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