ON-CHIP HARMONIC FILTERING FOR HIGH FREQUENCY (RF) COMMUNICATIONS

Abstract

An integrated circuit (202) comprising: a circuit (212) coupled between a first node (208) and a connection pad (132) for the integrated circuit (202), the circuit (212) comprising: a first inductance (122) coupled between the first node (208) and a second node (210); a first capacitance (204) coupled between the first node (208) and the second node (210) in parallel with the first inductance (122); a variable second capacitance (206) coupled between the second node (210) and a ground (130); and a second inductance (124) coupled between the second node (210) and the terminal pad (132); and a controller (220) coupled to control a capacitance amount for the variable second capacitance (206), to determine filtering with respect to a high-frequency signal, RF signal, passing through the circuit (212), and to determine impedance matching with respect to a load (105) coupled to the terminal pad (132), wherein the variable second capacitance (206) comprises: a first variable capacitor circuit (602) having a coarse tuning control signal (222A) as an input from the controller (220); and a second variable capacitor circuit (612) having a fine tuning control signal (222B) as an input from the controller (220), and wherein the coarse tuning control signal (222A) adjusts an impedance match for the circuit (212), and wherein the fine tuning control signal (222B) adjusts a filtering for the circuit (212).

Description

Technical FieldThe art relates to radio frequency (RF) wireless communications and, more particularly, to harmonic filtering of RF communications.BackgroundRadio frequency (RF) wireless devices often include integrated circuits (ICs) that are used to receive RF input signals, to transmit RF output signals, or to both receive and transmit RF signals. Where receiving functionality is included, RF communication ICs typically receive analog signals from antennas and convert the analog signals to digital data. Where transmit functionality is included, RF communication ICs typically convert digital data to analog output signals and transmit these analog output signals to antennas via power amplifiers. To increase or maximize power transfer from antennas during receive modes, matching circuits may be used such that the input impedance matches the impedance of the antenna during reception. To increase or maximize power transfer to antennas during transmit modes, matching circuits may also be used so that the output impedance matches the impedance of the antenna during transmission. Configurable matching circuits have been drawn in on-chip to provide this impedance matching.FIG. 1 (prior art) is a circuit diagram of an example embodiment 100 that includes an on-chip matching network 120 configurable based on a variable capacitance 126. Integrated circuit 102 includes a receiving mixer 108, a low noise amplifier 116, a frequency synthesizer 110 including a controlled oscillator 112, a transmitting mixer 109, a power amplifier 118, and a matching network 120. A harmonic suppression filter 106 is coupled off-chip between the pad 132 and an input / output node 103. Note also that in some prior solutions the matching network 120 is also included off-chip and an off-chip circuit block may be used to provide both a matching function and a harmonic suppression function. The input / output node 103 is coupled to an antenna represented by a load 105. A common impedance for an antenna is 50 ohms, although other antenna impedances may be used. The integrated circuit 102 includes a receive path and a transmit path.For the receive path, an RF input signal is received at the antenna or load 105 and provided to the pad 132 via the off-chip harmonic suppression filter 106. The receive signal then passes through matching network 120 and low noise amplifier 116 before being downconverted to a lower frequency by receive mixer 108. The receiving mixer 108 receives a local oscillator mixing signal from the on-chip frequency synthesizer 110 including the controlled oscillator 112. The downconverted RF input signal 114 is then processed further by a circuit within the integrated circuit 102. For example, the downconverted RF input signal 114 may be converted to digital values by an analog-to-digital converter and then processed by a digital processing circuit within the integrated circuit 102.For the transmit path, an analog output signal 115 is received by the power amplifier 118 via the transmit mixer 109. This analog output signal 115 may be, for example, an output from a digital-to-analog converter that receives a digital signal generated by a digital processing circuit within the integrated circuit 102. The transmit mixer 109 receives a local oscillator mixed signal from the on-chip frequency synthesizer 110 including the controlled oscillator 112. The transmit mixer 109 upconverts the analog output signal 115 to an RF output signal having a desired transmit frequency. This upconverted RF output signal is provided to power amplifier 118, which may be programmed to generate a transmit output signal at a desired power level. Note also that direct modulation may also be used, where the local oscillator signal from the frequency synthesizer 110 is modulated with the transmit data and then directly input to the power amplifier 118. The transmit output signal is routed via matching network 120 and pad 132 to harmonic suppression filter 106 before being transmitted through antenna or load 105.The configurable matching network 120 may be implemented using a first inductor 122, a second inductor 124, and a variable capacitance 126. The variable capacitance 126 is controlled to allow matching for the input and / or output impedances. In the illustrated embodiment, the first inductor (L 1) 122 is coupled between node 134 and node 136, and the second inductor (L 2) 124 is coupled between node 136 and pad 132. Variable capacitance (C) 126 is coupled between node 136 and ground 130, and may be controlled with, for example, on-chip control. During operation, configurable matching network 120 is controlled to enable impedance matching. Note that US 10 141 971 B1 describes embodiments that provide on-chip configurable matching networks. U.S. Pat. No. 10,141,971 B1 is hereby incorporated by reference in its entirety.It should be noted that active or passive techniques may be used in the filtering. For transmit modes, active techniques are based on a combination of outputs of multiple power amplifiers running with different phases or on a calibration of a conduction angle for the power amplifier. These active techniques may also use switched capacitor circuits that generate notches at frequencies that are multiples or harmonics of the transmit clock frequency. However, active techniques are very sensitive to clock inaccuracies and normally consume relatively high power. Passive techniques use inductors and capacitors to ensure harmonic filtering, and often use switched techniques. While passive techniques consume less power, passive techniques are not easily tunable because switched passive circuits normally have low quality factors (Q) that reduce maximum achievable filtering. Thus, previous solutions have not used on-chip tunable passive techniques to implement harmonic filtering. Rather, off-chip filtering has been used for RF communication devices, such as harmonic suppression filter 106 shown in FIG. 1 (prior art). While the off-chip harmonic suppression filter 106 improves the performance of the RF communications, the external components required to implement the harmonic suppression filter 106 increase the cost and size requirements for RF communication devices.US 2013 / 0187712 A1 describes an impedance matching circuit having at least one tunable notch filter for a power amplifier. The power amplifier amplifies an input radio frequency signal and provides an amplified RF signal. The impedance matching circuit performs output impedance matching for the power amplifier and includes at least one tunable notch filter. Each tunable notch filter has a notch whose frequency can be varied to achieve better attenuation of an unwanted signal. The at least one tunable notch filter attenuates at least one unwanted signal in the amplified RF signal. The at least one tunable notch filter may include a first tunable notch filter for attenuating a first undesired signal at a second harmonic of the amplified RF signal and / or a second tunable notch filter for attenuating a second undesired signal at a third harmonic of the amplified RF signal.US 2012 / 0075033 A1 describes a matching network. The matching network includes an input terminal connected to a multi-frequency input and an output terminal connected to the plasma load. Between the input terminal and the output terminal, a capacitor and an inductor are provided, which are connected in series to each other to form a branch.SUMMARY OF THE INVENTIONThe present invention relates to an integrated circuit according to claim 1, a circuit according to claim 6 and a method according to claim 10. Claims 2 to 5 describe particularly advantageous implementations of the integrated circuit according to claim 1. Claims 7 to 9 describe particularly advantageous implementations of the circuit according to claim 6. Claims 11 to 14 describe particularly advantageous implementations of the method according to claim 10.Systems and methods for on-chip harmonic filtering for radio frequency (RF) communications are disclosed. A filter and matching circuit is coupled to an integrated circuit pad. The circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductances. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the pad. In an embodiment, the variable second capacitance includes a coarse tuning variable capacitor circuit and a fine tuning variable capacitor circuit. The coarse tuning is for controlling impedance matching, and the fine tuning is for controlling a notch for filtering. The load may be an antenna for the RF communications. The integrated circuit may also include a receive path, a transmit path, or both. Other features and variations may also be implemented, and related systems and methods may also be used.For one embodiment, an integrated circuit is disclosed that includes a circuit coupled between a first node and a pad for the integrated circuit and a controller. The circuit includes a first inductor coupled between the first node and a second node, a first capacitor coupled between the first node and the second node in parallel with the first inductor, a variable second capacitor coupled between the second node and a ground, and a second inductor coupled between the second node and the pad. The controller is coupled to control a capacitance amount for the variable second capacitance, to determine filtering with respect to a radio frequency (RF) signal passing through the circuit, and to determine impedance matching with respect to a load coupled to the pad.In further embodiments, two separate inductor structures are used to provide the first inductor and the second inductor, or a tapped inductor structure is used to provide the first inductor and the second inductor. In further embodiments, the controller is coupled to provide one or more control signals to the variable second capacitance based on calibration data stored within the integrated circuit. In still further embodiments, the integrated circuit further includes a low noise amplifier coupled to the first node and configured to receive an RF input signal from the load via the circuit, and a power amplifier coupled to the first node and configured to transmit an RF output signal to the load via the circuit.The variable second capacitance includes a first variable capacitor circuit having a coarse tuning control signal as an input from the controller and a second variable capacitor circuit having a fine tuning control signal as an input from the controller. The coarse tuning control signal adjusts impedance matching for the circuit, and the fine tuning control signal adjusts filtering for the circuit. In further embodiments, the fine tuning control signal is adjusted to filter a third harmonic of the RF signal.For one embodiment, a circuit within an integrated circuit is disclosed that includes a first inductor coupled between a first node and a second node within the integrated circuit, a first capacitor coupled between the first node and the second node within the integrated circuit in parallel with the first inductor, a variable second capacitor coupled between the second node and a ground, and a second inductor coupled between the second node and the integrated circuit connection pad. The capacitance amount for the variable second capacitance determines filtering with respect to a radio frequency (RF) signal passing through the circuit and determines impedance matching with respect to a load coupled to the pad.In further embodiments, two separate inductor structures are used to provide the first inductor and the second inductor, or a tapped inductor structure is used to provide the first inductor and the second inductor.The variable second capacitance includes a first variable capacitor circuit having a coarse tuning control signal as an input and a second variable capacitor circuit having a fine tuning control signal as an input. The coarse tuning control signal adjusts impedance matching for the circuit, and the fine tuning control signal adjusts filtering for the circuit. In further embodiments, the fine tuning control signal is adjusted to filter a third harmonic of the RF signal.In further embodiments, a value for the first capacitance and a nominal value for the variable second capacitance are selected to determine an impedance match for the circuit, and the variable second capacitance is adjusted to determine a notch frequency for the filtering.For one embodiment, a method of operating an integrated circuit is disclosed that includes passing a radio frequency (RF) signal through a circuit within an integrated circuit and controlling a capacitance amount for the variable second capacitance. The circuit includes a first inductor coupled between a first node and a second node, a first capacitor coupled between the first node and the second node in parallel with the first inductor, a variable second capacitor coupled between the second node and a ground, and a second inductor coupled between the second node and a pad for the integrated circuit. The controller determines filtering with respect to the radio frequency (RF) signal and determines impedance matching with respect to a load coupled to the pad.In further embodiments, two separate inductor structures are used to provide the first inductor and the second inductor, or a tapped inductor structure is used to provide the first inductor and the second inductor. In further embodiments, the method includes receiving, with a low noise amplifier, an RF input signal from the load via the circuit, and transmitting, with a power amplifier, an RF output signal to the load via the circuit.The variable second capacitance includes a first variable capacitor circuit and a second variable capacitor circuit, and the controlling includes adjusting the first variable capacitor circuit with a coarse tuning control signal and adjusting the second variable capacitor circuit with a fine tuning control signal. The method includes using the coarse tuning control signal to adjust impedance matching for the circuit and using the fine tuning control signal to adjust filtering for the circuit. In further embodiments, the fine tuning control signal is adjusted to filter a third harmonic of the RF signal.In further embodiments, the method includes adjusting a value for the first capacitance and a nominal value for the variable second capacitance to determine an impedance match for the circuit, and adjusting the variable second capacitance to determine a notch frequency for the filtering.Other or additional features, variations, and embodiments may also be implemented, and related systems and methods may also be used.DESCRIPTION OF THE DRAWINGSIt should be understood that the appended drawings illustrate only exemplary embodiments of the invention and are therefore not to be considered as limiting the scope thereof, for the invention may permit other equally effective embodiments. FIG. 1 (prior art) is a circuit diagram of an example embodiment that includes an on-chip matching network configurable based on variable capacitance. FIG. 2 is a circuit diagram of an exemplary embodiment in which capacitance has been added to a reconfigurable matching network to achieve both suppression filtering and impedance matching within a common on-chip filter and matching circuit. FIG. 3A is a circuit diagram of an example embodiment indicating magnetic coupling between inductors within the filter and matching circuit. FIG. 3B is a circuit diagram of an example embodiment for the equivalent circuit having an equivalent inductance in series with the variable capacitance in FIG. 3A. FIG. 4 is a diagram of an example embodiment illustrating a frequency response for the circuit in FIG. 3A as represented by the equivalent circuit in FIG. 3B. FIG. 5A is a diagram of an example embodiment in which the circuit is implemented using two inductor structures formed within an integrated circuit. FIG. 5B is a diagram of an example embodiment in which the circuit is implemented using a single tapped inductor structure formed within an integrated circuit. FIG. 6 is a circuit diagram of an exemplary embodiment in which coarse tuning of the variable capacitance is used for impedance matching and fine tuning of the variable capacitance is used for filtering. FIG. 7A is a diagram of an example embodiment of transmit power levels with respect to selected capacitance values for the filter and matching circuit. FIG. 7B is a diagram of an exemplary embodiment for third harmonic power levels with respect to selected capacitance values for the filter and matching circuit.DETAILED DESCRIPTION OF THE INVENTIONSystems and methods for on-chip harmonic filtering for radio frequency (RF) communications are disclosed. For disclosed embodiments, a filter and matching circuit is included within an integrated circuit to eliminate the need for an external harmonic suppression filter. The circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance, and a variable second capacitance. The variable second capacitance is controlled to provide both on-chip filtering and impedance matching. Other features and variations may be implemented for the embodiments described herein, and related systems and methods may also be used.In contrast to previous solutions, the embodiments described herein use additional on-chip capacitances to achieve tunable on-chip filtering in combination with a reconfigurable on-chip matching network. This tunable on-chip filtering may be used to ensure harmonic suppression filtering for RF communications, for example filtering third harmonics of transmit frequencies. Using the disclosed embodiments, off-chip filtering may be removed, particularly for low power applications. For high performance applications, additional off-chip filtering may be provided due to the limited on-chip quality factors (Q). Other variants may also be implemented. Further, it should be appreciated that the RF communications may include communications within one or more frequency bands or channels associated therewith at frequencies from about 3 kilohertz (kHz) to 3 GHz or more. For one embodiment, the RF communications are performed using multiple channels within a 2.4 gigahertz (GHz) frequency band.FIG. 2 is a circuit diagram of an example embodiment 200 in which a capacitance 204 has been added to a reconfigurable matching network to achieve both suppression filtering and impedance matching within a common filter and matching circuit 212 for an integrated circuit 202. Example embodiment 200 is similar to example embodiment 100 of FIG. 1 (prior art), except that external harmonic suppression filter 106 has been removed as indicated by bracket 214, and on-chip capacitance 204 has been added in parallel with inductor (L 1) 122. With the addition of capacitance 204, adjustments to a variable second capacitance (C2) 206 ensure tuning for both filtering and impedance matching. Thus, the additional first on-chip capacitance 204 provides cancellation filtering without requiring the off-chip circuitry used in previous solutions. However, it should be appreciated that additional off-chip filter circuits could be added while still taking advantage of the tunable on-chip filtering techniques described herein.The filtering and matching circuit 212 is configurable based on a selection of the amount of capacitance for the first capacitance (C 1) 204 and a control of the variable second capacitance (C 2) 206. Similar to the integrated circuit 102 of FIG. 1 (prior art), the integrated circuit 202 of FIG. 2 also includes a receiving mixer 108, a low noise amplifier 116, a frequency synthesizer 110 including a controlled oscillator 112, a transmitting mixer 109, and a power amplifier 118. The pad 132 is coupled to an input / output node 103. Although not shown, a blocking capacitor may also be included between the pad 132 and the input / output node 103. The input / output node 103 is coupled to an antenna represented by a load 105. A common impedance for an antenna is 50 ohms, although other antenna impedances may be used. The integrated circuit 202 includes a receive path and a transmit path. It should also be appreciated that other or additional circuitry may be included within integrated circuit 202.For the receive path, an RF input signal is received at the antenna or load 105 and provided to the pad 132. The received signal then passes through the filtering and matching circuit 212. The impedance matching provided by circuit 212 improves receive signal levels. The filtering provided by the circuit 212 typically does not affect signal reception, as this filtering is typically tuned to the filtering of transmit harmonics, such as third harmonics of the transmit frequency. After passing through circuit 212, the receive signal then passes through low noise amplifier 116 before being downconverted to a lower frequency by mixer 108. The mixer 108 receives a local oscillator mixing signal from the on-chip frequency synthesizer 110 including the controlled oscillator 112. The downconverted RF input signal 114 is then further processed by circuitry within the integrated circuit 202. For example, the downconverted RF input signal 114 may be converted to digital values by an analog-to-digital converter and then processed by a digital processing circuit within the integrated circuit 202. Note that additional or different receive path circuitry could also be used while still exploiting the advantages of the tunable on-chip filtering techniques described herein.For the transmit path, an analog output signal 115 is received by the power amplifier 118 via the transmit mixer 109. This analog output signal 115 may be, for example, an output of a digital-to-analog converter that receives a digital signal generated by a digital processing circuit within the integrated circuit 202. The transmit mixer 109 receives a local oscillator mixed signal from the on-chip frequency synthesizer 110 including the controlled oscillator 112. The transmit mixer 109 upconverts the analog output signal 115 to an RF output signal having a desired transmit frequency. This upconverted RF output signal is provided to power amplifier 118, which may be programmed to generate a transmit output signal at a desired power level. Note also that direct modulation may also be used, where the local oscillator signal from the frequency synthesizer 110 is modulated with digital or analog transmit data and then fed directly to the power amplifier 118. The transmit output signal is then passed through the filter and matching circuit 212. As described herein, circuit 212 not only provides for impedance matching, but also operates to filter frequencies within the RF output signal, such as third harmonics of that transmit frequency, based on the addition of capacitance (C1) 204. The transmit output signal then passes through the pad 132 before being transmitted through the antenna or load 105. Note that additional or different transmit path circuitry could also be used while still exploiting the advantages of the tunable on-chip filtering techniques described herein.For the illustrated embodiment, the filtering and matching circuit 212 is implemented using a first inductor 122, a second inductor 124, a first capacitor 204, and a variable second capacitor 206. The first inductor (L 1) 122 is coupled between node 208 and node 210, and the second inductor (L 2) 124 is coupled between node 210 and pad 132. The first capacitance (C 1) 204 is coupled in parallel with the first inductance (L 1) 122 between nodes 208 and 210. The second variable capacitance (C 2) 206 is coupled between node 210 and ground 130, and is controlled by the controller 220 by one or more control signals 222. The controller 220 may also provide control signals 224 to other circuits within the integrated circuit 202 and / or to external circuits.According to the embodiments described herein, the filtering is provided by adding the fixed first capacitance (C 1) 204. In particular, adding capacitance (C 1) 204 in parallel with inductor (L 1) 122 generates a parallel resonant circuit that can be used to block undesired frequencies, such as the third harmonics of the frequency for the RF transmit signal. For example, if third harmonics are suppressed for the output signal 115, these third harmonics only circulate within the power amplifier 118 and do not flow to the off-chip antenna or load 105. Circuit 212 may also filter higher order harmonics. This on-chip filtering, provided by adding capacitance (C 1) 204 in parallel with inductance (L 1) 122 between nodes 208 and 210, generates on-chip filtering that allows removal of off-chip external harmonic suppression filter 106 of FIG. 1 (prior art). In this way, the two to three discrete components typically used off-chip to implement the harmonic suppression filter 106 may be removed, thereby reducing the cost and size of the resulting RF communication device.In addition to this filtering, circuit 212 also provides configurable impedance matching by controlling variable second capacitance (C2) 206. This impedance matching translates the input and / or output impedance to a desired impedance so that the power amplifier 118 can provide an increased or maximized output power to the antenna or target load 105. Note that the impedance matching provided by inductors 122 / 124 and variable capacitance 206 is similar to the impedance matching described in U.S. Pat. No. 10,141,971 B1, which is hereby incorporated by reference in its entirety.Unlike previous solutions, adjustments to the variable second capacitance (C2) 206 in FIG. 2 may be made to configure both filter and adjustment functions for the integrated circuit 202. For an embodiment as described in more detail below with reference to FIG. 6, coarse tuning adjustments are made to the variable capacitance (C 2) 206 to configure the impedance matching provided by the circuit 212 and fine tuning adjustments are made to the variable capacitance (C 2) 206 to configure the filtering provided by the circuit 212. Other variations may also be implemented.It should also be appreciated that values for the first capacitance (C 1) 204, the first inductance (L 1) 122, the second inductance (L 2) 124, and the variable second capacitance (C 2) 206 may be selected based on frequencies to be filtered and impedances to be matched for any particular solution. The magnetic coupling between inductors 122 / 124 is a parameter that can be taken into account in determining these values.FIG. 3A is a circuit diagram of an example embodiment indicating magnetic coupling (M) 302 between inductors 122 and 124 within filter and matching circuit 212. This magnetic coupling may be modeled as an equivalent inductance in series with the variable capacitance (C 2) 206 as shown in FIG. 3B. Note that inductors 122 and 124 may be implemented using a variety of techniques. For example, inductors 122 and 124 may be separate inductors or two portions of a single inductor structure tapped by variable capacitance (C 2) 206. Other implementations may also be used.FIG. 3B is a circuit diagram of an example embodiment for the equivalent circuit 350 having an equivalent inductance (-M) 304 in series with the variable capacitance (C 2) 206. Due to the magnetic coupling represented by this equivalent inductance (-M) 304, an estimate for the resonant frequency involves inductance (L1) 122, capacitance (C1) 204, equivalent inductance (-M), and variable capacitance (C2) 206. Assuming that no current flows from the inductor (L2) 124 at the resonant frequency (f 0) the following equation can be used to estimate the resonant frequency (f 0) and select inductor and capacitance values.FIG. 4 is a diagram of an example embodiment 400 illustrating a frequency response 406 for circuit 212 in FIG. 3A as represented by equivalent circuit 350. The vertical axis 402 represents signal level and the horizontal axis 404 represents frequency. The resonant frequency (f 0) 408 creates a notch within the frequency response 406 and this notch represents the center frequency for filtering provided by the filtering and matching circuit 212. Note that the notch at the resonant frequency (f 0) is preferably narrow to achieve a high quality factor (Q) for the filtering provided by the filtering and matching circuit 212.Because the variable capacitance (C2) 206 is part of the resonance, it can be used to tune the center frequency for the on-chip filtering provided by adding the capacitance (C1) 204. For example, the variable capacitance (C 2) 206 may be adjusted to suppress a target harmonic frequency of the RF output signal. In addition to the tunable impedance matching provided by the variable capacitance (C) 126 in FIG. 1 (prior art), the second variable capacitance (C 2) 206 in combination with the additional first capacitance (C 1) 204 therefore enables tuning of the center frequency for on-chip filtering provided by the circuit 212 as well as its impedance matching.Note that the first fixed capacitance (C 1) 204 could also be implemented as a variable capacitor and used to tune the on-chip filter. However, using only variable capacitance (C2) 206 to tune the center frequency or notch frequency for filtering offers a significant advantage. Although conceptually the capacitance (C1) 204 could be implemented as a variable capacitor and used to tune the notch frequency, this solution is not preferable. Adding switches in series with capacitors to implement capacitance (C1) 204 as a variable capacitance would result in a significantly degraded quality factor (Q), and a narrow notch for filtering at a selected frequency or harmonic would not be achieved. In contrast, adding switches in series with capacitors to implement capacitance (C2) 206 as a variable capacitance does not result in significant degradation of the overall quality factor (Q). With the selection of component values for inductors (L 1, L 2) 122, and 124, first capacitance (C 1) 204, and second variable capacitance (C 2) 206, harmonic filtering on-chip along with impedance matching may be achieved.Note further that characterization data may be collected and used to calibrate the variable capacity (C2) tuning 206. For example, a calibration may be performed at various process, temperature, and / or other operating parameters. The resulting calibration data and associated filter settings may then be stored in the integrated circuit 202. For example, the calibration data may be stored in an on-chip memory coupled to the controller 220. This stored calibration data may then be used to adjust the control signals 222 provided to the circuit 212. Other variants could also be implemented.FIG. 5A is a diagram of an example embodiment in which circuit 212 is implemented using two inductor structures 502 and 504 formed within integrated circuit 202. The inductor structure 502 provides the inductor (L 1) 122, and the inductor structure 504 provides the inductor (L 2) 124. Capacitance (C 1) 204 is coupled between nodes 208 and 210 in parallel with inductance structure 502 for inductance (L 1) 122. Variable capacitance (C 2) 206 is coupled to node 210 between the two inductor structures 502 and 504. Note that the physical distance between the two inductors 122 and 124 is a parameter that affects the equivalent inductance (-M) 404 and therefore affects the resonant frequency for the circuit 212.FIG. 5B is a diagram of an example embodiment in which circuit 212 is implemented using a single tapped inductor structure 510 formed within integrated circuit 202. The inductor structure 510 is tapped by the variable capacitance (C2) 206 at the tap point 512 to form two inductor sections. A first coil portion leading back to node 208 provides inductance (L 1) 122. A second coil portion leading in the other direction provides the inductance (L 2) 124. Capacitance (C1) 204 is coupled in parallel with inductance (L1) 122 between nodes 208 and 210. Variable capacitance (C 2) 206 is coupled between node 210 and ground, and node 210 is coupled to tap point 512 within inductance structure 510.FIG. 6 is a circuit diagram of an example embodiment for the variable capacitance 206, where coarse tuning of the variable capacitance (C2) 206 is used to ensure impedance matching and fine tuning of the variable capacitance (C2) 206 is used to ensure filtering. For the illustrated exemplary embodiment, a first variable capacitor circuit 602 provides coarse tuning and a second variable capacitor circuit 612 provides fine tuning. The first variable capacitor circuit 602 includes a plurality of capacitors (C C1, C C2... C CN) 604, which is connected to a plurality of switches (S C1, S C2... S CN) 606. The switches (S C1, S C2... S CN) 606 are controlled by a coarse tuning control signal 222A comprising a plurality of control bits (B C1, B C2... B includes CN). The second variable capacitor circuit 612 includes a plurality of capacitors (C F1, C F2... C FN) 614, which is connected to a plurality of switches (S F1, S F2... S FN) 616. The switches (S F1, S F2... S FN) 616 are controlled by a fine tuning control signal 222B comprising a plurality of control bits (B F1, B F2... B includes FN). As noted above, coarse tuning control signal 222A may be used to provide impedance matching and fine tuning control signal 222B may be used to provide harmonic filtering. The coarse tuning control signal 222A and the fine tuning control signal 222B may be output from a controller 220. Other variants may also be implemented.FIG. 7A is a diagram of an example embodiment 700 for transmit power levels with respect to values for capacitance (C 1) 204 and varied capacitances for capacitance (C 2) 206 within filter and matching circuit 212. The vertical axis 702 represents the power level in decibels relative to one milliwatt (dBm), and the horizontal axis 704 represents the capacitance in picofarads (pF). The values 708, 710, 712, 714, 716, 718, 720, and 722 were selected for the capacitance (C1) 204 and are represented in femtofarads (fF). The capacity for capacity (C2) 206 was then varied to produce the corresponding power level response curves shown in embodiment 700. Preferably, a power level response curve is selected such that the power levels are above zero dBm so that circuit 212 does not reduce the output power levels. This zero dBm level is represented by dashed line 706. Note that the zero dBm power amplifier represented by FIG. 7A is provided as an exemplary embodiment. Other power amplifier implementations could also be used while still exploiting the advantages of the tunable on-chip filtering techniques described herein.FIG. 7B is a diagram of an example embodiment 750 for third harmonic power levels with respect to values for capacitance (C1) 204 and varied capacitances for capacitance (C2) 206 within filter and matching circuit 212. The vertical axis 752 represents the third harmonic power level in decibels relative to one milliwatt (dBm), and the horizontal axis 754 represents the capacitance in picofarads (pF). Values 708, 710, 712, 714, 716, 718, 720, and 722 have been selected for capacitance (C1) 204 and correspond to those in FIG. 7A. The capacity for the capacity (C2) 206 was then varied to generate the corresponding power levels shown in embodiment 750. Preferably, the capacitances are selected to achieve a deep and narrow notch for circuit 212. As shown in point 756, a deep and narrow notch of negative 51 dBm is achieved with the value 714. Referring to FIG. 7A, the value 714 also reaches a power level response curve above the zero dBm level, which is represented by dashed line 702. Thus, for an exemplary embodiment, a value of about 520 fF for capacitance (C 1) 204 and a nominal value of about 550 fF for capacitance (C 2) 206 may be selected. When the example embodiment of FIG. 6 is used, the nominal value for capacitance (C 2) 206 may represent a coarse tuning selection to provide tunable impedance matching, and capacitance (C 2) 206 may then be further adjusted using a fine tuning selection to provide tunable filtering.Note that the functional blocks, devices, and / or circuits described herein may be implemented using hardware, software, or a combination of hardware and software. In addition, one or more processing devices (e.g., central processing units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, processors, programmable integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and / or other processing devices) that execute software, firmware, and / or other program instructions may be used to implement the disclosed embodiments. Further, it is to be understood that one or more of the operations, tasks, functions, or methods described herein may be implemented, for example, as software, firmware, and / or other program instructions embodied in one or more non-transitory, tangible computer readable media (e.g., data storage devices, flash memory, random access memory, read only memory, programmable memory devices, re-programmable memory devices, hard disks, floppy disks, DVDs, CD-ROMs, and / or other tangible data storage media) for programming the one or more processing devices (e.g., central processing units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, processors, programmable integrated circuits, field programmable gate arrays (FPGAs), ASICs (application specific integrated circuits) and / or other processing devices) may be used to perform the operations, tasks, functions, or methods described herein.Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. It will therefore be appreciated that the present invention is not limited by these exemplary arrangements. Accordingly, this description is to be taken by way of illustration only and is for the purpose of teaching one skilled in the art the manner of practicing the invention. It is to be understood that the forms of the invention shown and described herein are to be considered the presently preferred embodiments. Various changes may be made in the implementations and architectures. For example, equivalent elements may be substituted for those illustrated and described herein, and certain features of the invention may be used regardless of the use of other features, all of which would be apparent to one skilled in the art having the benefit of this description of the invention.

Claims

An integrated circuit (202) comprising: a circuit (212) coupled between a first node (208) and a pad (132) for the integrated circuit (202), the circuit (212) comprising: a first inductor (122) coupled between the first node (208) and a second node (210); a first capacitor (204) coupled between the first node (208) and the second node (210) in parallel with the first inductor (122); a variable second capacitor (206) coupled between the second node (210) and a ground (130); and a second inductor (124) coupled between the second node (210) and the pad (132); and a controller (220) coupled to control an amount of capacitance for the variable second capacitance (206), to determine filtering with respect to a radio frequency, RF, signal passing through the circuit (212), and to determine impedance matching with respect to a load (105) coupled to the pad (132), the variable second capacitance (206) comprising: a first variable capacitor circuit (602) having a coarse tuning control signal (222A) as an input from the controller (220); and; and a second variable capacitor circuit (612) having a fine tuning control signal (222B) as an input from the controller (220), and wherein the coarse tuning control signal (222A) adjusts impedance matching for the circuit (212), and wherein the fine tuning control signal (222B) adjusts filtering for the circuit (212).The integrated circuit (202) of claim 1, wherein two separate inductance structures are used to provide the first inductance (122) and the second inductance (124), or wherein a tapped inductance structure (510) is used to provide the first inductance (122) and the second inductance (124).The integrated circuit (202) of claim 1 or 2, wherein the controller (220) is coupled to provide one or more control signals to the variable second capacitance (206) based on calibration data stored in the integrated circuit (202).The integrated circuit (202) of any preceding claim, further comprising: a low noise amplifier (116) coupled to the first node (208) and configured to receive an RF input signal (114) from the load (105) via the circuit (212); and a power amplifier (118) coupled to the first node (208) and configured to transmit an RF output signal to the load (105) via the circuit (212).The integrated circuit (202) of any of claims 1 to 4, wherein the fine tuning control signal (222B) is adjusted to filter a third harmonic of the RF signal.A circuit (212) within an integrated circuit (202), comprising: a first inductor (122) coupled between a first node (208) and a second node (210) within the integrated circuit (202); a first capacitor (204) coupled between the first node (208) and the second node (210) within the integrated circuit (202) in parallel with the first inductor (122); a variable second capacitor (206) coupled between the second node (210) and a ground (130); and a second inductor (124) coupled between the second node (210) and a pad (132) for the integrated circuit (202); wherein a capacitance amount for the variable second capacitance (206) determines filtering with respect to a radio frequency, RF, signal passing through the circuit (212) and determines impedance matching with respect to a load (105) coupled to the pad (132), wherein the variable second capacitance (206) comprises: a first variable capacitor circuit (602) having a coarse tuning control signal (222A) as an input; and a second variable capacitor circuit (612) having a fine tuning control signal (222B) as an input, and wherein the coarse tuning control signal (222A) adjusts impedance matching for the circuit (212), and wherein the fine tuning control signal (222B) adjusts filtering for the circuit (212).The circuit (212) of claim 6, wherein two separate inductance structures are used to provide the first inductance (122) and the second inductance (124), or wherein a tapped inductance structure (510) is used to provide the first inductance (122) and the second inductance (124).The circuit (212) of claim 6 or 7, wherein the fine tuning control signal (222B) is adjusted to filter a third harmonic of the RF signal.The circuit (212) of any of claims 6 to 8, wherein a value for the first capacitance (204) and a nominal value for the variable second capacitance (206) are selected to determine an impedance match for the circuit (212), and wherein the variable second capacitance (206) is adjusted to determine a notch frequency for the filtering.A method of operating an integrated circuit (202), comprising: passing a radio frequency, RF, signal through a circuit (212) within an integrated circuit (202), the circuit (212) comprising: a first inductor (122) coupled between a first node (208) and a second node (210); a first capacitor (204) coupled between the first node (208) and the second node (210) in parallel with the first inductor (122); a variable second capacitor (206) coupled between the second node (210) and a ground (130); and a second inductor (124) coupled between the second node (210) and a connection pad (132) for the integrated circuit (202); and controlling a capacitance amount for the variable second capacitance (206) to determine filtering with respect to the RF signal and to determine impedance matching with respect to a load (105) coupled to the connection pad (132), wherein the variable second capacitance (206) comprises a first variable capacitor circuit (602) and a second variable capacitor circuit (612), and wherein the controlling comprises: matching the first variable capacitor circuit with a coarse tuning control signal (222A); and adjusting the second variable capacitor circuit with a fine tuning control signal (222B), and wherein the method further comprises: using the coarse tuning control signal (222A) to adjust impedance matching for the circuit (212); and using the fine tuning control signal (222B) to adjust filtering for the circuit (212).The method of claim 10, wherein two separate inductance structures are used to provide the first inductance (122) and the second inductance (124), or wherein one tapped inductance structure (510) is used to provide the first inductance (122) and the second inductance (124).The method of claim 10 or 11, further comprising: receiving, with a low noise amplifier (116), an RF input signal (114) from the load (105) via the circuit (212); and transmitting, with a power amplifier (118), an RF output signal via the circuit (212) to the load (105).The method of any of claims 10 to 12, wherein the fine tuning control signal (222B) is adjusted to filter a third harmonic of the RF signal.The method of any of claims 10 to 13, further comprising: setting a value for the first capacitance (204) and a nominal value for the variable second capacitance (206) to determine an impedance match for the circuit (212), and adjusting the variable second capacitance to determine a notch frequency for the filtering.

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