METHOD FOR POLYSILICIUM REMOVAL IN THE WORD CONDITION CONTACT REGION OF STORAGE DEVICES

Abstract

Demonstrating procedures: Forming, on a substrate (230), a first polysilicon conductor (110A) with a first width and a second polysilicon conductor (110B) with a second width, wherein the first polysilicon conductor (110A) and the second polysilicon conductor (110B) are spaced apart from each other by a polysilicon layer (200) and the first polysilicon conductor (110A) and the second polysilicon conductor (110B) each have a contact region (120) which is wider than the first width and the second width; Deposition of a mask layer (400, 410) on the first polysilicon conductor (110A), the contact region (120) of the second polysilicon conductor (110B) and the polysilicon layer (200), wherein the deposition of the mask layer (400, 410) has: Deposition of an oxide layer (400) on the first polysilicon conductor (110A), the contact region (120) of the second polysilicon conductor (110B) and the polysilicon layer (200); and Deposition of a nitride layer (410) on the oxide layer (400); Etching of the mask layer (400, 410) from the polysilicon layer (200) by a dry etching process to remove a section of the mask layer (400, 410) and to expose a first section of the polysilicon layer (200), wherein the etching of the mask layer (400, 410) results in unremoved sections of the oxide layer (400) which have a section that is arranged parallel to the substrate (230) on the polysilicon layer (200); Etching the unremoved portions of the oxide layer (400) from the polysilicon layer (200) by a wet etching process to expose a second portion of the polysilicon layer (200) that is larger than the first portion, wherein the second portion is narrower than the polysilicon layer (200) that is inserted between the contact region (120) of the second polysilicon conductor (110B) and the first polysilicon conductor (110A); and Removing the exposed second section of the polysilicon layer (200) to form a separation between the contact region (120) of the second polysilicon conductor (110B) and the first polysilicon conductor (110A).

Description

BACKGROUND

[0001] Non-volatile memory devices such as flash memory are used in a wide range of electronic devices and instruments (e.g., computers, mobile phones, tablets, digital cameras, scientific instruments, etc.) to store data and / or programming instructions that can subsequently be read, erased, programmed, and saved when the power supply is disconnected. Non-volatile memory cells (NVM cells) are therefore an important component of modern chips. A method for manufacturing a non-volatile memory device is known from German patent application DE 10 2019 101 676 A1. A semiconductor device with a non-volatile memory cell and a corresponding method for manufacturing it are known from US patent application 2020 / 0 161 317 A1. Other devices and methods are also known from publications US 2015 / 0 255 473 A1, US 2020 / 0 105 346 A1, US 2015 / 0 076 669 A1 and US 2020 / 0 075404 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present revelation can best be understood by referring to the following detailed description in conjunction with the accompanying drawings. Fig. 1A and Fig. 1B are top views of polysilicon conductors in a belt region of a storage cell according to some embodiments. Fig. Figure 2A is a cross-sectional view of polysilicon conductors in a belt region of a memory cell according to some embodiments. Fig. 2B is a cross-sectional view of polysilicon conductors in a region of a memory cell outside a belt region according to some embodiments. Fig. 2C is a cross-sectional view of polysilicon conductors in a belt region of a memory cell according to some embodiments. Fig. Figure 3 is a flowchart of a structuring process for removing polysilicon material in a belt region of a memory cell according to some embodiments. Fig. Figure 4 is a cross-sectional view of an intermediate structure during a structuring process for removing polysilicon material in a belt region of a memory cell according to some embodiments. Fig. 5A, Fig. 5B and Fig. Figure 5C shows cross-sectional views of intermediate structures during a structuring process for the removal of polysilicon material, in a belt region of a memory cell, in a region of the memory cell outside the belt region, and in a region outside the memory cell according to some embodiments. Fig. 6A and Fig. Figure 6B shows cross-sectional views of intermediate structures during a structuring process for the removal of polysilicon material, both in a belt region of a memory cell and in a region of the memory cell outside the belt region according to some embodiments. Fig. 7A and Fig. Figure 7B shows cross-sectional views of intermediate structures during a structuring process for the removal of polysilicon material, both in a belt region of a memory cell and in a region of the memory cell outside the belt region according to some embodiments. Fig. 8A, Fig. 8B and Fig. Figure 8C shows cross-sectional views of intermediate structures during a structuring process for the removal of polysilicon material, in a belt region of a memory cell, in a region of the memory cell outside the belt region, and in a region outside the memory cell according to some embodiments. Fig. 9A, Fig. 9B and Fig. Figure 9C shows cross-sectional views of intermediate structures during a structuring process for the removal of polysilicon material, in a belt region of a memory cell, in a region of the memory cell outside the belt region, and in a region outside the memory cell according to some embodiments. Fig. Figure 10A is a cross-sectional view of a contact formed on a belt region of a memory cell, according to some embodiments. Fig. Figure 10B is a cross-sectional view of a contact formed in an area of ​​a memory cell outside a belt region, according to some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples for implementing various functions of the disclosed content. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features are arranged between the first and second features such that the first and second features are not in direct contact. Furthermore, this disclosure may repeat reference numerals of the various examples. This repetition does not prescribe any relationship between the various embodiments and / or configurations described.

[0004] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0005] The term "nominal," as used herein, refers to a desired or target value of a property or parameter for a component or process operation, which is set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. This range of values ​​may arise from slight variations in the manufacturing processes and / or tolerances.

[0006] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a certain quantity that varies within a range of 5% around the value (e.g., +1%, ±2%, ±3%, ±0.4%, ±5% of the value). These values ​​are only examples and are not to be understood as limiting. The terms "approximately" and "essentially" may refer to a percentage of the values ​​as interpreted by those skilled in the art in the relevant field(s) with regard to the teaching herein.

[0007] Flash memory is a type of non-volatile memory that stores information in an array of memory cells made from floating-gate transistors. Each memory cell is a metal-oxide-semiconductor field-effect transistor (MOSFET), but the transistor has two gates instead of one. The memory cells function as an electrical switch, with current flowing between two terminals (e.g., a source and a drain) controlled by a floating gate (FG) and a control gate (CG) made of polysilicon. The CG is similar to the gate in other MOS transistors, but beneath it, the FG is insulated on all sides by an oxide layer. The FG is positioned between the CG and the MOSFET channel. Because the FG is electrically insulated by its insulating layer, any electrons placed on it are trapped.When the FG is charged with electrons, this charge shields the electric field from the CG, thereby increasing the cutoff voltage (VT1) of the memory cell. If a charge is present in the FG, a higher voltage (VT2) must be applied to the CG to make the channel conductive. To read a value from the transistor, an intermediate voltage between the cutoff voltages (VT1 & VT2) is applied to the CG. If the channel conducts at this intermediate voltage, the FG is considered uncharged. If it were charged, no current would flow in the channel between the source and drain terminals. In this situation, a logical "1" can be interpreted from this state of the FG. If the channel does not conduct at the intermediate voltage, this situation indicates that the FG is being charged; here, a logical "0" can be interpreted from this state of the FG.The presence of charge at the FG is "detected" by sensing whether current flows through the transistor when the intermediate voltage is applied to the CG. In a multi-stage cell device that stores more than one bit per cell, the amount of current flow can be detected (rather than simply determining whether or not current is flowing) to more accurately determine the charge level at the FG.

[0008] Within the flash memory cell area, the transistor gates are formed as densely packed traces called polysilicon traces. These polysilicon traces lie parallel to each other and are separated by a gap. Voltage is applied to the CG section of the polysilicon traces via contacts formed at regions of the CG polysilicon traces that act as contact landing pads. These contact landing pads are wider than the rest of the polysilicon trace to facilitate contact formation. They are referred to as "contact regions" or "belt regions." At the belt locations, the distance between two adjacent polysilicon traces is smallest in some embodiments.

[0009] With each technology generation (node), the spacing between adjacent polysilicon conductors decreases to increase the density of the memory cell and improve the storage capacity of the device. Therefore, structuring the area between neighboring polysilicon conductors becomes increasingly challenging—for example, to selectively remove all deposited material (such as polysilicon). This is critical for the belt regions where the spacing between adjacent polysilicon conductors is narrowest. Residue left between tightly packed polysilicon conductors can cause bridging, which can trigger electrical short circuits.

[0010] To address the above disadvantages, this disclosure is directed to a structuring process that removes excess material between polysilicon conductors near the belt regions of memory cells and reduces (or eliminates) residues left behind by the removal process. In some embodiments, the residue reduction (or elimination) is achieved by photolithography and etching operations, which facilitate the removal of excess material between closely spaced, adjacent polysilicon conductors.

[0011] Fig. Figure 1A is a partial top view of a memory cell (e.g., a flash memory cell) 100A in which polysilicon conductors 110 are formed parallel to each other at a nominal distance d. The polysilicon conductors 110 have further sections (e.g., tape regions or contact regions 120) to facilitate the formation of contacts that are in Fig. 1A are not shown. In some embodiments, the distance between adjacent polysilicon conductors near the contact regions 120 is reduced from d to d'. In some embodiments, d' is the minimum distance between two adjacent polysilicon conductors 110. In some embodiments, contact regions 120 are intentionally offset in the y-direction to allow a closer distance between adjacent polysilicon conductors 110, as shown in Fig. Figure 1 is shown. Furthermore, this design allows for the proper separation of the formed contacts to prevent bridging between them. The layout of memory cell 100 is not based on the representation shown in Figure 1. Fig. 1 is limited, and alternative layouts are possible. For example, contact regions 120 of adjacent polysilicon conductors 110 can be formed without offset in the y-direction, as in Fig. 1B is shown for memory cells 100B and 100C. The layouts from Fig. 1B falls within the spirit and scope of this disclosure, and the embodiments described herein apply equally to layouts 100A, 100B and 100C or variations thereof.

[0012] Each polysilicon conductor 110 represents a gate stack structure shared among various transistors formed within a flash cell. Furthermore, each polysilicon conductor 110 comprises a CG and an FG structure, which are arranged in Fig. 1A and Fig. Figure 1B is not shown. The CG and FG structures are both made of polysilicon and positioned parallel to each other. As shown in Fig. 1A and Fig. As shown in Figure 1B, polysilicon conductors extend longitudinally along the y-direction. Only selective components of the memory cells 100A-C are in Fig. 1A and Fig. Figure 1B is shown, and other components, features, or layers are not shown for the sake of simplicity. These other layers include, but are not limited to, insulating regions, cover layers, spacers, other polysilicon features (e.g., quenching gates), doped regions, dielectric layers, contacts, etc. These other components, features, or layers fall within the spirit and scope of this disclosure.

[0013] In some embodiments, the spacing d is between approximately 400 nm and 500 nm, while the spacing d' is between approximately 200 nm and approximately 300 nm, depending on the cell layout. The above ranges are not limiting, and other values ​​or ranges for the spacings d and d' are possible. These other values ​​or ranges are within the scope of the values. In some embodiments, the spacing d and d' are subject to design rules established by a specific technology node. By reference to Fig. In 1A, contact regions 120 of polysilicon conductors 110 are arranged offset by a distance L, which is greater than the distance d', in the y-direction. For example, and without limitation, the distance L can be approximately 600 nm. Gate contacts are formed on polysilicon conductors 110 within the specified contact regions 120. Each gate contact allows simultaneous control of multiple transistor gates. In other words, several gate structures can be "linked" and controlled with the same signal. Contact regions 120 can also be referred to as a "belt" or "belt site." In some embodiments, the contacts formed in contact regions 120, for example, provide an electrical word line signal to the gate gate of the transistor.

[0014] Exemplary and not limiting is Fig. Figure 2A shows a cross-sectional view of two adjacent polysilicon conductors / gate structures 110A and 110B. In some embodiments, Fig. 2A a cross-sectional view of Fig. 1A along the intersection line AB prior to the formation of a CG contact-on-gate structure 110B. As above regarding Fig. As discussed in section 1, near contact region 120, one of the polysilicon conduits / gate structures is wider than the other. In the example from Fig. 2A, the gate structure 110B is wider than the gate structure 110A because Fig. Figure 2A shows a cross-sectional view along the contact region 120 of gate structure 110B. Each gate structure comprises a gate structure (CG) and one or more gate structures (FGs) insulated by a dielectric layer 210. Furthermore, each CG in gate structures 110A and 110B is insulated by nitride layers 220. By way of example, and not as a limitation, the nitride layers 220 may comprise silicon nitride, and the dielectric layer 210 may comprise silicon oxide. In some embodiments, the gate structures 110A and 110B are formed on a semiconductor substrate 230, as shown in Figure 2A. Fig. 2A is shown. In other embodiments, the gate structures 110A and 110B are formed on insulation regions, such as shallow trench insulation regions. In some embodiments, gate structures formed in areas outside of contact region 120 (e.g., outside the belt region and inside the memory cell) may look different from gate structure 110A or 110B. For example, such gate structures may have a single FG extending along the entire width of the CG in the x-direction, as shown in Fig. 2B is shown for gate structures 110C and 110D.

[0015] By referring to Fig. In embodiment 2A, gate structures 110A and 110B are separated by a polysilicon layer 200, which laterally fills the space between the "inner" sidewall surfaces of the gate structures 110A and 110B. Due to the distance d' between gate structures 110A and 110B, the polysilicon layer 200 has a divot 240 with a width w between approximately 30 nm and approximately 50 nm and a height h between approximately 50 nm and approximately 70 nm. In some embodiments, the aspect ratio of the divot 240 depends on the distance d' between the gate structures 110A and 110B. For example, if the distance d' decreases (e.g., d' < < d), the aspect ratio of divot 240 increases. Conversely, if the distance d' increases (e.g., d' ≈ d), the aspect ratio of the divot decreases (e.g., the aspect ratio can be less than approximately 1), as for divot 240' in Fig. Figure 2B shows the distance between adjacent gate structures 110C and 110D equal to d. In some embodiments, the aspect ratio (h / w) of divot 240 is... Fig. 2A (e.g., near contact region 120) between approximately 2.3 and approximately 1. In some embodiments, divot 240' is made of Fig. 2B (e.g., outside the contact region 120) is wider (e.g., wider than about 50 nm) with a less aggressive aspect ratio than Divot 240 (e.g., with an aspect ratio of less than about 1).

[0016] Furthermore, quenching gate structures (EG structures) are formed on the "outer" sidewall surfaces of gate structures 110A and 110B. EG structures are formed from polysilicon, similar to CG and FG as discussed above. In some embodiments, the polysilicon layer 200 is subsequently etched to form a separation within a distance d'.

[0017] In some embodiments Fig. 2C a cross-sectional view of the gate structures 110A' and 11oB' of memory cell 100B from Fig. 1B along the CD section line. Due to the layout differences between memory cells 100B and 100A, the cross-sectional view of Fig. Regarding gate structures 110A' and 100B', 2C looks different than that of Fig. 2A. For example, the intersection line CD extends through contact region 120 of both gate structures 110A' and 110B'; therefore, the location of the intersection line CD of gate structures 110A' and 110B' has essentially the same widths along the x-direction. In Fig. 2C exhibits similar characteristics to that in Fig. 2A the polysilicon layer 200, which is arranged between gate structures 110A' and 11oB', forms a divot 240 due to the distance d' explained above.

[0018] In some embodiments, a cross-sectional view for memory cell 100C along the contact regions 120 of adjacent polysilicon conductors 110 would look similar to Fig. 2C.

[0019] In some embodiments Fig. 2A and Fig. 2C Precursor structures (e.g., starter structures) for the embodiments described herein, which can be applied equally to memory cell layouts 100A / B / C and their variants. For the sake of simplicity and without deviating from the spirit and scope of the disclosure, the embodiments described herein are described with reference to memory cell 100A.

[0020] Fig. Figure 3 is a flowchart of a manufacturing process 300, which includes a structuring process near the contact region 120 between the gate structures 110A and 110B. Fig. 1A describes some embodiments. Other manufacturing operations may be performed between the various operations of Process 300 and may be omitted purely for clarity and a simpler description. These various operations are within the scope and scope of the information provided. Furthermore, it may not be necessary to carry out all operations to perform the disclosure provided herein. Some of the operations may be performed concurrently or in a different order than those described in Fig. 3. In some embodiments, one or more operations may be performed in addition to or instead of the operations described here. Method 300 is described with reference to Fig. 4A to 9C described.

[0021] By referring to Fig. 3 begins procedure 300 with operation 310 and the process of forming an oxide and a nitride layer on gate structures separated by a polysilicon layer, such as gate structures 110A and 110B, which are separated by the polysilicon layer 200. Fig. 2A are separated. In some embodiments, the oxide layer is formed followed by the nitride layer. The oxide and nitride layers together form a hard mask stack, which facilitates the structuring process of the polysilicon layer 200. By way of example and without limitation, the oxide layer 400 can be silicon oxide (SiO2), which is thermally built up at about 680 °C to a thickness between about 30 nm and about 40 nm. The nitride layer 410 can comprise silicon nitride (Si3N4) or silicon oxynitride (SiON), which is built up at about 400 °C to a thickness between about 10 nm and 20 nm. In some embodiments, the nitride layer 410 is deposited by a substantially conformal process, such as chemical vapor deposition (CVD). The above materials, thicknesses, and growth conditions are not limiting, and other materials, thicknesses, and growth conditions are possible.These other materials, thicknesses, and growth conditions fall within the spirit and scope of this revelation.

[0022] Fig. Figure 4 shows gate structures 110A and 110B after deposition of the oxide layer 400 and nitride layer 410 after operation 310 according to some embodiments. In some embodiments, the oxide layer 400 and nitride layer 410 cover the side wall and the lower surfaces of divot 240, but do not fill divot 240 as shown in Fig. 4 is not shown.

[0023] With reference to Fig. 3. Method 300 is continued with operation 320 and the process of forming a structured photoresist layer on the nitride layer 410. In some embodiments, a lower antireflective coating layer (BARC layer) is inserted between the photoresist layer and the nitride layer 410 prior to the deposition of the photoresist layer. The BARC layer suppresses light reflections during the structuring process of the photoresist layer. Furthermore, the BARC layer minimizes the undesired generation of standing waves during the photoresist structuring process. Standing waves can increase the edge and sidewall roughness of the resulting structured photoresist structure. Additionally, the BARC layer forms a flat surface on which the photoresist layer can be formed by acting as a filler to fill small defects in the underlying layers, such as divot 240.By way of example, and without limitation, the BARC layer can be an organic compound comprising carbon, hydrogen, and oxygen. In some embodiments, the BARC layer, with a thickness of approximately 160 nm, is spin-coated onto gate structures 110A and 110B. Fig. 4 applied. Fig. Figure 5A shows the resulting structure after forming the BARC layer 500 and the structured photoresist layer 510 on the nitride layer 410. In some embodiments, the structured photoresist layer 510 has a thickness of about 120 nm. The above thicknesses for the BARC layer 500 and the photoresist layer 510 are not limiting, and other thicknesses are within the spirit and scope of this disclosure.

[0024] In some embodiments, the formation of the oxide layer 400 and the nitride layer 410 (as described with respect to operation 310) and the formation of the BARC layer 500 and the structured photoresist layer 510 (as described with respect to operation 320) is not exclusive to the contact region 120. In other words, the above oxide, nitride, and photolithographic layers (e.g., BARC layer 500 and structured photoresist layer 510) can be formed simultaneously over the entire chip area, including the entire area of ​​the memory cell and the logic areas of the chip. For example, Figure 320 shows that... Fig. 5B the formation of the oxide layer 400, nitride layer 410, BARC layer 500 and structured photoresist layer 510 after operations 310 and 320 on the structures from Fig. 2B (e.g., an area within the memory cell outside contact region 120). Accordingly, it shows Fig. 5C, the oxide layer 400, nitride layer 410, BARC layer 500, and photoresist layer 510, which are located in a logic area of ​​the chip outside the memory cell. As in Fig. Figure 5C shows that during operation 320, the photoresist layer 510 on the logic area of ​​the chip is unstructured according to some embodiments. This is intentional, as no features are formed in the logic area during the subsequent operations.

[0025] With reference to Fig. 3 carries out procedure 300 with operation 330 and the process of etching the BARC layer to form the opening 600 to expose a section of nitride layer 410 above the polysilicon layer 200 as in Fig. 6A continued. In some embodiments, further openings (e.g., opening 600) can be formed simultaneously at other locations of the memory cell outside the contact region 120—e.g., as in Fig. Figure 6B shows where the opening 600' is formed between gate structures 110C and 110D. In some embodiments, opening 600 may have a shorter width 600w along the x-direction compared to other openings formed outside the contact region 120 (e.g., 600') due to the limited distance d' between gate structures 110A and 110B. For example, 600w may be formed from Fig. 6A (e.g., within contact region 120) equal to or less than 600W (from Fig. 6B), which is formed in another area of ​​the memory cell outside the contact region 120. Furthermore, the opening 600 is defined as Fig. 6A in a subsequent operation exposes a side wall section and a lower surface section of divot 240, which may be more complicated to etch. In contrast, opening 600 exposes Fig. 6B in a subsequent operation only leaves a lower surface section of divot 240 open, which may be less complicated to etch.

[0026] In some embodiments, when the openings 600 and 600' are formed in the memory cell areas, the logic area of ​​the chip remains through the BARC layer 500 and the photoresist layer 510 as shown in Fig. 5C is shown and marked. Subsequently, during operation 330 of procedure 300, no openings are created in the logic area of ​​the chip.

[0027] By referring to the Fig. 3 and Fig. 7A continues method 300 with operation 340 and the process of removing, through opening 600, the exposed portion of the nitride layer 410 and the underlying oxide layer 400 to expose the polysilicon layer 200 between gate structures 110A and 110B. In some embodiments, during operation 340, exposed portions of the nitride layer 410 and oxide layer 400 are also removed at other locations in the memory cell where openings, such as opening 600', have been formed—as, for example, in Fig. 6B is shown. In contrast to Fig. 6B, where aperture 600' exposes a section of a single horizontal surface in divot 240', the etching of the nitride layer 410 and oxide layer 400 near the contact region 120 can be carried out Fig. 7A may be more complicated because the opening 600 exposes a combination of vertical and horizontal surfaces in divot 240. In some embodiments, etching the nitride layer 410 and the underlying oxide layer 400 through the opening 600 results in unetched sections of the oxide layer 400, as shown in Fig. 7A shown. This is undesirable because the presence of the residual oxide layer in divot 240 can hinder the subsequent removal of the polysilicon layer 200. For example, the residual oxide layer in divot 240 can lead to polysilicon residues (e.g., unetched sections of polysilicon layer 200), bridging (e.g., electrical short circuits), or combinations thereof. In some embodiments, operation 340 removes the residue through the opening 600' in memory cell areas outside the contact region 120, as shown in Fig. Figure 7B shows exposed sections of the nitride layer 410 and the underlying oxide layer 400 completely.

[0028] In some embodiments, the etching process in Operation 340 uses a dry etching process optimized to sufficiently remove the nitride layer 410 and oxide layer 400 from the divot 240. In some embodiments, the etching process includes a mixture of difluoromethane (CH₂F₂), sulfur hexafluoride (SF₆), helium (He), nitrogen (N₂), or the like. In some embodiments, the addition of N₂ to the etching chemical increases the silicon-to-nitride selectivity—for example, from about 1:1 to about 1:6. Consequently, the nitride layer 410 is efficiently removed during the etching process, and less polysilicon is etched when exposed to the etching chemical. By way of example, and not as a limitation, the oxide-to-nitride selectivity is about 1:2.

[0029] In some embodiments, the CH₂F₂ flux is about 50 sccm, the SF₆ flux about 20 sccm, the He flux about 100 sccm, and the N₂ flux between about 20 sccm and about 100 sccm. In some embodiments, the etching process duration is about 32 s and is based on silicon-to-nitride and oxide-to-nitride selectivity. In some embodiments, the etching process duration is adjusted to remove 80% of the exposed oxide layer 400. In some embodiments, a pre-charge of about 80 volts is applied to substrate 230 during the etching process. Furthermore, the etching process can be carried out in a temperature range between about 40 °C and about 60 °C. The above etching conditions are not limiting, and other etching conditions are possible. These other etching conditions are within the spirit and scope of this disclosure.

[0030] According to some embodiments, for an N2 flow below approximately 20 sccm, the silicon-to-nitride selectivity is poor, and polysilicon would be etched along with the nitride. Consequently, defects can form in the polysilicon layer. On the other hand, for an N2 flow above approximately 100 sccm, polymer generated during the etching process can prematurely interrupt the etching process, and nitride is not adequately removed.

[0031] Subsequently, the photoresist layer 510 and the BARC layer 500 are removed by an "ashing" process (e.g., a high-temperature oxidation process), and the gate structures 110A and 110B are subjected to a wet etching process with dilute hydrofluoric acid (DHF) for approximately 20 s to ensure that unetched sections of the oxide layer 400 within divot 240 are removed. In some embodiments, the water-to-HF ratio in the above DHF solution is approximately 100:1.

[0032] During the wet etching process, the nitride layer 410 is not etched, and the oxide layer 400, which is "masked" (e.g., covered) by the nitride layer 410 (e.g., on the gate structures 110A / B and EG), is not etched as described in [reference missing]. Fig. 8A shown removed. In some embodiments, exposed edges 800 of the oxide layer 400 are laterally cut out due to the etch isotropy of the wet etching process (e.g., forming an "undercut"). An undercut in the oxide layer 400 can also occur at other locations within the memory cell where edges of the oxide layer 400 are exposed beneath the nitride layer 410. The amount of undercut can be controlled by the dilution ratio of the DHF and the exposure time (e.g., duration) of the wet etching process. In some embodiments, a similar undercut can be formed in other memory cell regions outside the contact region 120, with the oxide layer 400 being shown in the wet etching process as indicated by the exposed edges 800' of the oxide layer 400 in Fig. 8B was shown.

[0033] In some embodiments, after operation 340, procedure 300 is used. Fig. Three further photolithography and etching operations were performed in other areas of the chip (e.g., in the logic area) to etch a section of the nitride layer 410 and oxide layer 400 as shown in Fig. 8C shown to remove. During these photolithography and etching operations, the entire memory cell area is covered by fresh BARC and photoresist layers, which are in Fig. 8A and Fig. 8B are not shown. These BARC and photoresist layers are subsequently treated with an ash process prior to operation 350 of procedure 300. Fig. 3 away.

[0034] With reference to Fig. 3 continues the procedure 300 with operation 350 and the process of etching the exposed polysilicon layer 200 to create a separation or distance 900 between the gate structures 110A and 110B as in Fig. 9A is shown to form. Before the polysilicon etching, the nitride layer 410 is made of Fig. 8A and Fig. 8B removed. The removal of the nitride layer 410 is achieved, for example, by a dry etching process that is selective for the nitride layer 410. By way of example, and without limitation, the dry etching process may involve organofluorinated chemicals such as tetrafluoromethane (CF4) with hydrogen or oxygen, fluoroform (CHF3), 1,1-difluoroethane (CH3CHF2), or combinations thereof. Other chemical compositions may also be used and are within the spirit and scope of this disclosure.

[0035] When the nitride layer 410 is removed, as in Fig. 9A and Fig. As shown in Figure 9B, sections of the polysilicon layer 200 that are not masked by the oxide layer 400 are removed (e.g., etched) by a dry etching process. In some embodiments, the dry etching process is anisotropic, so that lateral etching of the polysilicon layer 200 (e.g., in the x-direction) can be controlled. Furthermore, the dry etching process is selective for the polysilicon layer 200. By way of example, and without limitation, the dry etching chemical can have a selectivity between the polysilicon layer 200 and the oxide layer 400 that is higher than approximately 100:1. In some embodiments, the etching chemical comprises a mixture of CH₂F₂, SF₆, He, N₂, and the like. By way of example and without limitation, the CH2F2 flux may be around 60 sccm, the SF6 flux may be around 45 sccm, the He flux may be around 150 sccm and the N2 flux may be around 68 sccm.However, the above conditions are not limiting and other conditions may be used. These other conditions are within the spirit and scope of this disclosure. In some embodiments, the etching process has an endpoint when the dielectric layer 210 beneath the polysilicon layer 200 is exposed by separation or spacing 900.

[0036] In some embodiments, separations or distances 900 and 900' are each as in Fig. 9A and Fig. Figure 9B shows the formation. By way of example and without limitation, the separation or distance 900 has a width W between approximately 50 nm and approximately 100 nm and a height H between approximately 100 nm and approximately 120 nm. As shown in Fig. As shown in Figure 9A, the distance d' between gate structures 110A and 110B is greater than the width W of the separation or the distance 900 (e.g., d' > W). Accordingly, the distance d' between gate structures 110C and 110D is greater than the width W of the separation or the distance 900 (e.g., d' > W), as shown in Figure 9A. Fig. 9B is shown. In some embodiments, separations or gaps 900 and 900' are formed such that a section of the polysilicon layer 200 is located on the inner sidewalls of the gate structure 110A as shown in Fig. 9A shown and inner side walls of the gate structures 110C and 110D as in Fig. The aspect ratio shown in 9B remains. The aspect ratio of the separation or distance 900 can, for example, be between approximately 1 and approximately 2.4.

[0037] In some embodiments, the polysilicon etching process in Operation 350 can form polysilicon openings, including contact openings or other separation openings, in areas of the chip outside the memory cell—e.g., in the logic area of ​​the chip as in Fig. 9C shown.

[0038] In some embodiments, after operation 350 the oxide layer 400 is removed – for example, by a wet etching process using DHF – and a contact can be formed at the contact region 120 of the gate structure 110B. This is shown by way of example and is not limited to Fig. 10A the structure of Fig. 9A after forming a contact 1000 at the widest section of 110B (e.g., at contact region 120). By way of example, and without limitation, the contact 1000 can be formed by first depositing a dielectric layer 1010 to surround the gate structures 110A / 110B and fill the separation or gap 900, followed by a structuring process that forms a contact opening in the dielectric layer 1010 at contact region 120 of the gate structure 110B. The contact opening can subsequently be filled with a conductive material, such as a metal (e.g., tungsten (W), cobalt (Co), and the like). In some embodiments, an etch stop layer, which is in Fig. 10, not shown, is deposited on gate structures 110A / 110B and the separation or distance 900 before the formation of the dielectric layer 1010 to facilitate the formation of the contact opening for contact 1000. Formation of further contacts on other sections of the memory cell, or other regions of the chip, is possible during the formation of contact 1000. For example, a contact 1000' can be formed between gate structures 110C and 110D. Fig. 10B. Subsequently, the metallization or wiring layers can be formed over the gate structures 110A, 110B, 110C, and 110D. These further metallization or wiring layers, which are in Fig. 10A and Fig. 10B, which are not shown, can be electrically coupled to the CG of the gate structure 110B and the source-drain regions of the substrate 230 via contacts 1000 and 1000'.

[0039] Various embodiments according to this disclosure describe a structuring process for the tape region of a memory cell that removes excess material between polysilicon conductors and reduces (or eliminates) residues left behind by the removal process. In some embodiments, the residue removal (or elimination) is achieved by introducing photolithography and etching operations that facilitate the removal of excess material between closely spaced polysilicon conductors. In some embodiments, the structuring process includes hard-mask photolithography and hard-mask etching processes that remove the hard-mask layers of divots in a polysilicon layer between polysilicon conductors. In some embodiments, the etching process includes a dry etching process that targets the nitride and oxide layers of the hard mask, followed by a wet etching process that targets the oxide layer of the hard mask.

[0040] The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims.

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