SEMICONDUCTOR DEVICE AND METHOD

Abstract

Semiconductor device comprising: an interface layer (301) over a semiconductor fin (107), a crystallized ferroelectric layer (501) in physical contact with the interface layer (301), the crystallized ferroelectric layer (501) comprising a plurality of crystalline regions with grain boundaries between adjacent ones of the plurality of crystalline regions, each of the plurality of crystalline regions comprising one of a plurality of metallic seeds (607), the metallic seeds (607) being nickel oxide, and a conductive stack (801) over the crystallized ferroelectric layer (501).

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and then patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, with the reduction of the smallest feature sizes, additional problems arise that must be addressed. DE 10 2018 105 953 A1 discloses a method for producing a semiconductor component with negative capacitance, in which a dielectric layer is formed over a substrate. A first metal layer is formed over the dielectric layer. After the first metal layer has been formed, an annealing process is carried out, followed by a cooling process. Then a second metal layer is formed.After the cooling process, the dielectric layer becomes a ferroelectric dielectric layer exhibiting an orthorhombic crystal phase. US 6 010 744 A discloses a method for the nucleation-controlled deposition of ferroelectric thin films by chemical vapor deposition, wherein a higher density of bismuth nucleation sites is achieved. JP 6 183 601 B2 discloses a method for producing a piezoelectric element. US 2019 / 0 296 226 A1 describes a magnetic device with a magnetoresistive effect element comprising a first ferromagnet, a conductor, and an oxide provided between the first ferromagnet and the conductor, wherein the oxide contains a first oxide of a rare earth element and a second oxide of an element whose covalent radius is smaller than a covalent radius of the rare earth element. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for the sake of clarity. Fig. 1 shows steps in a process for forming a field effect transistor device according to some embodiments. Fig. 2 shows a formation of source / drain regions according to some embodiments. Fig. 3 shows a cross-sectional view of an interface layer formation according to some embodiments. Fig. 4 shows forming a metal layer according to some embodiments. Fig. 5A-5B illustrate forming a ferroelectric layer according to some embodiments. Fig. 6A to 6C illustrate a first annealing process according to some embodiments. Fig. 7A-7B illustrate a second annealing process according to some embodiments. Fig. 8 illustrates forming a conductive gate stack according to some embodiments. Fig. 9A-9B illustrate forming a cover layer according to some embodiments. Fig. 10A-10B illustrate the first annealing process with the cap layer according to some embodiments. Fig. 11A-11B illustrate the second annealing process with the cap layer according to some embodiments. Fig. 12 shows a formation of the conductive gate stack according to some embodiments. Fig. 13 shows a gate-all-around device according to some embodiments. Fig. 14A to 16B illustrate uses of additives according to some embodiments. Fig. 17 shows a grain size distribution within the crystallized ferroelectric layer according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These, of course, are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0006] With reference to Fig. 1 is a perspective view of manufacturing processes for forming negative capacitance field-effect transistors (NCFETs) 100 or ferroelectric field-effect transistors (FEFETs) that utilize ferroelectric materials in combination with dielectric materials and utilize an S-shaped electric field polarization / characteristic, resulting in a region of negative capacitance that may result in a transistor switching at a lower voltage. In one embodiment, NCFET 100 includes a substrate 101 with first trenches 103 formed therein. Substrate 101 may be a silicon substrate, although other substrates, such as semiconductor on an insulator (SOI), stress SOI, and silicon germanium on an insulator, could be used. Substrate 101 may be a p-type semiconductor, although in other embodiments, it could be an n-type semiconductor.

[0007] The first trenches 103 may be formed as an initial step in the eventual formation of first isolation regions 105. The first trenches 103 may be formed using a masking layer (not separately in Fig. 1) using a suitable etching process. For example, the masking layer may be a hard mask comprising silicon nitride formed using a process such as chemical vapor deposition (CVD), although other materials such as oxides, oxynitrides, silicon carbide, combinations of these, or the like, and other processes such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitriding may be used. After it has been formed, the masking layer may be patterned using a suitable photolithographic process to expose those portions of the substrate 101 that are removed to form the first trenches 103.

[0008] However, as one skilled in the art will appreciate, the processes and materials described above for forming the masking layer are not the only method that may be used to protect portions of the substrate 101 while exposing other portions of the substrate 101 for the formation of the first trenches 103. Any suitable process, such as a patterned and developed photoresist, may be used to expose portions of the substrate 101 that are to be removed in order to form the first trenches 103. All such methods are intended to be fully encompassed within the scope of the present embodiments.

[0009] After a masking layer is formed and patterned, the first trenches 103 are formed in the substrate 101. The exposed substrate 101 may be removed using a suitable process, such as reactive ion etching (RIE), to form the first trenches 103 in the substrate 101, although any suitable process may be used. In one embodiment, the first trenches 103 may be formed to have a first depth of less than approximately 5000 Å from the surface of the substrate 101, such as approximately 2500 Å.

[0010] However, as one of ordinary skill in the art will appreciate, the above-described process for forming the first trenches 103 is merely one possible process and is not intended to be the only embodiment. Rather, any suitable process capable of forming the first trenches 103 may be used, and any suitable process including any number of masking and removal steps may be used.

[0011] In addition to forming the first trenches 103, the masking and etching process also forms fins 107 from those portions of the substrate 101 that remain in an unremoved state. For simplicity, the fins 107 have been depicted in the figures as being separated from the substrate 101 with a dashed line, although a physical marking of the separation may or may not be present. These fins 107 may be used, as discussed below, to form the channel region of the field-effect transistors. Although Fig. 1 illustrates only two fins 107 formed by the substrate 101, any number of fins 107 may be used.

[0012] The fins 107 may be formed to have a width at the surface of the substrate 101 of between about 5 nm and about 80 nm, such as about 30 nm. Furthermore, the fins 107 may be spaced apart from each other by a distance of between about 10 nm and about 100 nm, such as about 50 nm. By spacing the fins 107 in this way, the fins 107 may each form a separate channel region while still being close enough to share a common gate (discussed further below).

[0013] After the first trenches 103 and the fins 107 have been formed, the first trenches 103 may be filled with a dielectric material, and the dielectric material may be recessed within the first trenches 103 to form the first isolation regions 105. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed after an optional cleaning and lining of the first trenches 103 using either a chemical vapor deposition (CVD) process (e.g., the HARP process), a high-density plasma (CVD) process, or another suitable formation method, as known in the art.

[0014] The first trenches 103 may be filled by overfilling the first trenches 103 and the substrate 101 with the dielectric material and then removing the excess material outside the trenches 103 and the fins 107 using a suitable process, such as chemical mechanical polishing (CMP), etching, a combination of these, or the like. In one embodiment, the removal process also removes any dielectric material disposed over the fins 107, such that the removal of the dielectric material exposes the surface of the fins 107 for further processing steps.

[0015] After the first trenches 103 have been filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fins 107. The recessing may be performed to expose at least a portion of the sidewalls of the fins 107 adjacent to the top surface of the fins 107. The dielectric material may be recessed using a wet etch by immersing the top surface of the fins 107 in an etchant such as HF, although other etchants such as H2 and other processes such as reactive ion etching, dry etching with etchants such as NH3 / NF3, chemical oxide removal, or chemical dry cleaning may be used. The dielectric material may be recessed from the surface of the fins 107 to a distance of between approximately 50 Å and approximately 500 Å, such as approximately 400 Å.In addition, the knockout may also remove any remaining dielectric material disposed over the fins 107 to ensure that the fins 107 are exposed for further processing.

[0016] However, as one of ordinary skill in the art will appreciate, the steps described above may be merely a part of the overall process flow used to fill and recess the dielectric material. For example, lining steps, cleaning steps, annealing steps, gap-filling steps, combinations of these, and the like may also be used to form the first trenches 103 and fill them with the dielectric material. All of the possible process steps are intended to be fully within the scope of the present embodiment.

[0017] After the first isolation regions 105 have been formed, a dummy gate dielectric 109, a dummy gate electrode 111 over the dummy gate dielectric 109, and first spacers 113 over each of the fins 107 may be formed. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other methods known and used in the art for forming a gate dielectric. Depending on the technique for forming the gate dielectric, a thickness of the dummy gate dielectric 109 on the top surface of the fins 107 may be different from a thickness of the gate dielectric on the sidewall of the fins 107.

[0018] The dummy gate dielectric 109 may comprise a material, such as silicon dioxide or silicon oxynitride, having a thickness in the range of approximately 0.3 nanometers to approximately 10 nanometers, such as approximately 1 nanometer. The dummy gate dielectric 109 may be formed from a high-permittivity (high-k) material (e.g., having a relative dielectric constant greater than approximately 5), such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or combinations thereof, with an equivalent oxide thickness of approximately 0.05 nanometers to approximately 10 nanometers, such as approximately 1 nanometer or less. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0019] The dummy gate electrode 111 may comprise a conductive material and may be selected from a group including W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or the like. The dummy gate electrode 111 may be deposited using chemical vapor deposition (CVD), sputter deposition, or other techniques known in the art and used to deposit conductive materials. The thickness of the dummy gate electrode 111 may range from approximately 0.5 nm to approximately 20 nm. The top surface of the dummy gate electrode 111 may have a non-planar top surface and may be planarized prior to patterning the dummy gate electrode 111 or a gate etch. At this time, ions may or may not be introduced into the dummy gate electrode 111. Ions can be introduced, for example, using ion implantation techniques.

[0020] After the dummy gate dielectric 109 and the dummy gate electrode 111 have been formed, they may be patterned to form a series of stacks 115 above the fins 107. The stacks 115 define a plurality of channel regions arranged on each side of the fins 107 beneath the dummy gate dielectric 109. The stacks 115 may be formed by depositing and patterning a gate mask (not separately described in Fig. 1) may be formed on the dummy gate electrode 111, for example, using deposition and photolithography techniques known in the art. The gate mask may include conventionally used masking and sacrificial materials, such as, but not limited to, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited to a thickness of between approximately 5 Å and approximately 200 Å. The dummy gate electrode 111 and the dummy gate dielectric 109 may be etched using a dry etch process to form the patterned stacks 115.

[0021] After the stacks 115 have been structured, the first spacers 113 can be formed. The first spacers 113 can be formed on opposite sides of the stacks 115. The first spacers 113 are typically formed by depositing a spacer layer (not separately in Fig. 1) on the previously formed structure. The spacer layer may comprise SiN, oxynitride, SiC, SiON, SiOCN, SiOC, oxide, and the like, and may be formed using methods used to form such a layer, such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. The spacer layer may comprise a different material with different etch characteristics or the same material as the dielectric material within the first isolation regions 105. The first spacers 113 may then be patterned, such as by one or more etches, to remove the spacer layer from the horizontal surfaces of the structure to form the first spacers 113.

[0022] In one embodiment, the first spacers 113 may be formed to have a thickness of between about 0.5 nm and about 50 nm, such as about 5 nm. Furthermore, after the first spacers 113 are formed, a first spacer 113 adjacent to one stack 115 may be separated from a first spacer 113 adjacent to another stack 115 by a distance of between about 5 nm and about 200 nm, such as about 20 nm. However, any suitable thicknesses and spacings may be used.

[0023] Fig. 2 shows a removal of the fins 107 from those areas not protected by the stacks 115 and the first spacers 113 and a regrowth of source / drain regions 201. The removal of the fins 107 from those areas not protected by the stacks 115 and the first spacers 113 may be performed by a reactive ion etch (RIE) using the stacks 115 and the first spacers 113 as hard masks. However, any suitable process may be used.

[0024] After these portions of the fins 107 have been removed, a hard mask (not separately shown) is arranged and patterned to cover the dummy gate electrode 111 to prevent growth, and the source / drain regions 201 may be regrown in contact with each of the fins 107. In one embodiment, the source / drain regions 201 may be regrown, and in some embodiments, the source / drain regions 201 may be regrown to form a stressor that will impart strain to the channel regions of the fins 107 arranged beneath the stacks 115. In an embodiment where the fins 107 comprise silicon and the field effect transistor is a p-type device, the source / drain regions 201 may be formed using a selective epitaxial process with a material such as silicon, or otherwise a material such asSilicon germanium, which has a different lattice constant than the channel regions, may be regrown. In other embodiments, the source / drain regions 201 may comprise materials such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, combinations of these, or the like. The epitaxial growth process may use precursors such as silane, dichlorosilane, germanium, and the like, and may continue for between approximately 5 minutes and approximately 120 minutes, such as approximately 30 minutes.

[0025] In one embodiment, the source / drain regions 201 may be formed to have a thickness of between about 0.5 nm and about 100 nm and a height above the first isolation regions 105 of between about 1 nm and about 50 nm, such as about 20 nm. In this embodiment, the source / drain regions 201 may be formed to have a height above the top surface of the first isolation regions 105 of between about 5 nm and about 250 nm, such as about 100 nm. However, any suitable height may be used.

[0026] After the source / drain regions 201 have been formed, dopants may be implanted into the source / drain regions 201 by implanting suitable dopants to complement the dopants in the fins 107. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted, or in other embodiments, n-type dopants such as phosphorus, arsenic, antimony, or the like may be implanted. These dopants may be implanted using the stacks 115 and the first spacers 113 as masks. It should be noted that one of ordinary skill in the art will recognize that many other processes, steps, or the like may be used to implant the dopants.For example, one of ordinary skill in the art will recognize that multiple implantations can be performed using different combinations of spacers and liners to form source / drain regions having a particular shape or characteristic suitable for a specific purpose. Any of these processes may be used to implant the dopants, and the above description is not intended to limit the present invention to the steps presented above.

[0027] At this point, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain regions 201 is also removed. In one embodiment, the hard mask may be removed, for example, using a wet or dry etching process that is selective to the hard mask material. However, any suitable removal process may be used.

[0028] Fig. 2 also shows a formation of an interlayer dielectric layer (ILD) 203 (shown in dashed lines in Fig. 2 to more clearly show the underlying structures) over the stacks 115 and the source / drain regions 201. The ILD layer 203 may comprise a material such as borophosphosilicate glass (BPSG), although any suitable dielectrics may be used. The ILD layer 203 may be formed using a process such as PECVD, although other processes such as LPCVD may alternatively be used. The ILD layer 203 may be formed to a thickness of between approximately 10 nm and approximately 300 nm. After being formed, the ILD layer 203 may be planarized with the first spacers 113, for example, using a planarization process such as a chemical mechanical polishing process, although any suitable process may be used.

[0029] Optionally, if desired, a first etch stop layer may be formed over the structure prior to deposition of the ILD layer 203 (e.g., over the source / drain regions 201). In one embodiment, the first etch stop layer may be formed from silicon nitride using plasma-enhanced chemical vapor deposition (PECVD), although other materials, such as SiON, SiCON, SiC, SiOC, SiC x N y , SiO x , other dielectrics, combinations thereof, or the like, and alternative techniques for forming the first etch stop layer, such as low-pressure CVD (LPCVD), PVD, or the like, could alternatively be used. The first etch stop layer 202 may have a thickness of between about 0.5 nm and about 20 nm, or between about 0.5 nm and about 5 nm.

[0030] Fig. Figure 3 shows a cross-sectional view of the structure of Fig. 2 along the line 3-3', and also shows that after forming the ILD layer 203, the material of the dummy gate electrode 111 and the dummy gate dielectric 109 can be removed and replaced to form a gate stack 803 (in Fig. 3 not shown, but below with reference to Fig. 8). In one embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 may be removed, for example, using a wet or dry etching process that uses etchants selective to the material of the dummy gate electrode 111 and the dummy gate dielectric 109. However, any suitable removal process may be used.

[0031] Fig. 3 additionally shows forming an interface layer 301 adjacent to the fin 107. In one embodiment, the interface layer 301 may be a material, such as silicon dioxide, formed by a process such as an in-situ steam generation (ISSG) process or a deposition process such as chemical vapor deposition or atomic layer deposition. In another embodiment, the interface layer 301 may be a high-k material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these, or the like, and has a first thickness T1 of between about 0.5 nm and about 2 nm, such as 1 nm.In embodiments using a deposition process, the interface layer 301 may be formed conformally, while in embodiments using ISSG, the interface layer 301 may be formed along the bottom of the opening without extending along the sidewalls.

[0032] Fig. 4 shows forming a metal layer 401 adjacent to the interface layer 301 and along sidewalls of the first spacers 113. In one embodiment, the metal layer 401 comprises a material that can be easily integrated into a ferroelectric film 501 (e.g., a ferroelectric film 501 described below with reference to Fig. 5A) and is also capable of nucleating to promote the crystallization of the ferroelectric film 501 (which will be described below with reference to Fig. 6).

[0033] In some embodiments, the material of metal layer 401 comprises a metal that can be used as a seed during the crystallization process. In some embodiments, the metal may be a metal such as nickel, or, by way of example, magnesium, aluminum, combinations of these, or the like, or it may otherwise be, by way of example, another material such as titanium (Ti), germanium (Ge), tin (Sn), combinations of these, or the like. However, any suitable material may be used.

[0034] In addition, to position and control the movement of the metal, the metal layer 401 may also include a transport element bonded to the metal. In some embodiments of the invention, the transport element is oxygen, which may be used to assist in the deposition of the material of the metal layer 401.

[0035] In certain embodiments, the metal and the transport element are combined to form the material of the metal layer 401. In one embodiment of the invention in which the metal is nickel and the transport element is oxygen, the metal layer 401 is a material, namely nickel oxide (NiO). Likewise, in unclaimed embodiments in which the metal is exemplary magnesium and the transport element is oxygen, the metal layer 401 may be a material such as magnesium oxide (MgO), and in embodiments in which the metal is exemplary aluminum and the transport element is oxygen, the metal layer 401 may be a material such as aluminum oxide (Al2O3).In yet other unclaimed embodiments, where, for example, the metal is titanium and the transport element is oxygen, the metal layer 401 may be titanium oxide (TiO2), while in unclaimed embodiments where, for example, the metal is tin and the transport element is oxygen, the metal layer 401 may be tin oxide (SnO2).

[0036] In one embodiment, the metal layer 401 may be deposited using a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations of these, or the like. Furthermore, the metal layer 401 may be deposited to a thickness of between about 0.5 nm and about 5 nm, such as 1 nm. However, any suitable deposition process and thickness may be used.

[0037] Fig. 5A shows forming a ferroelectric film 501 over the metal layer 401. In some embodiments, the ferroelectric film 501 is deposited as an amorphous matrix layer using a high-k material (e.g., having a relative dielectric constant greater than about 5), such as hafnium oxide (HfO2), aluminum scandium nitride (AlScN), zirconium oxide (ZrO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these, or the like. According to some embodiments, the ferroelectric film 501 is deposited by a process such as atomic layer deposition (ALD), chemical vapor deposition, or physical vapor deposition to a thickness of between about 3 nm and about 20 nm, such as about 5 nm. However, any suitable materials, any suitable deposition process, and any suitable thicknesses may be used for the ferroelectric film 501.

[0038] Furthermore, the thicknesses of the metal layer 401 and the ferroelectric film 501 can be modified with respect to each other so that a desired concentration of dopants can be achieved in subsequent processing. For example, in some embodiments, a ratio of the thickness of the ferroelectric film 501 to the thickness of the metal layer 401 can be between about 5 and about 20, such as about 10. If the ratio is too low (e.g., the metal layer 401 is too thick), the doping concentration can be such that the crystal size can be too small or otherwise result in the wrong crystalline phase, while if the ratio is too high (e.g., the metal layer 401 is too thin), there may not be a sufficient concentration of dopant to achieve the desired effect of controlling the crystal size. However, any suitable ratio can be used.

[0039] Fig. 5B shows a close-up view of the dashed box 504 in Fig. 5A. As clearly seen in this view, at this point in the manufacturing process, the metal layer 401 is positioned between the interface layer 301 and the overlying ferroelectric film 501. Such initial positioning allows for the subsequent diffusion of the material of the metal layer 401 into the ferroelectric film 501.

[0040] Fig. Figure 6A shows that, in order to help initiate and / or accelerate the diffusion of the material of the metal layer 401 into the ferroelectric film 501, according to the invention, an annealing process (which is described in Fig. 6A by the wavy lines labeled 603) is performed to form a nucleated ferroelectric film 601. In one embodiment, the first annealing process 603 may be a furnace annealing process, whereby the structure is placed in a furnace and surrounded by an inert environment. In one embodiment, the inert environment may be an inert gas, such as argon, neon, or the like, or may otherwise be an environment that is non-reactive with the exposed surfaces. After the structure is placed in the furnace, the furnace uses heating elements to increase the temperature of the inert environment, and therefore increase the temperature of the metal layer 401 and the ferroelectric film 501.

[0041] According to the invention, the first annealing process 603 increases the temperature of the metal layer 401 and the ferroelectric film 501 to between approximately 300°C and approximately 600°C, such as approximately 400°C. Furthermore, to allow sufficient time for the metal within the metal layer 401 to diffuse into the ferroelectric film 401, the first annealing process 603 may be performed for a time between approximately 1 minute and approximately 60 minutes. However, any suitable time and temperature may be used.

[0042] Furthermore, although a furnace annealing process was described above as one embodiment of the first annealing process 603, this is intended to be illustrative and in no way limiting. Rather, any suitable annealing process, such as rapid thermal annealing, flash annealing, laser annealing, combinations of these, or the like, may also be used. Any suitable method for annealing the metal layer 401 and the ferroelectric film 501 may be used, and all such methods are intended to be fully within the scope of the embodiments.

[0043] Fig. Figure 6B shows a close-up view of the dashed box 605 in Fig. 6A. As can be seen, during the first annealing process 603, the material of metal layer 401 diffuses into ferroelectric film 501, forming seeded ferroelectric film 601. As the material of metal layer 401 diffuses, metal layer 401 is absorbed into seeded ferroelectric film 601 and effectively disappears. Accordingly, the material of seeded ferroelectric film 601 is in physical contact with the underlying interface layer 301.

[0044] Within the seeded ferroelectric film 601, the first annealing process 603 continues until the metal atoms are evenly distributed within the seeded ferroelectric film 601 and become seeds 607. In a particular embodiment, the first annealing process 603 continues until the metal atoms, and therefore seeds 607, have a density within the seeded ferroelectric film 601 of between approximately 10,000 seeds / µm2 (which may result in a grain size of approximately 10 nm) to approximately 250,000 seeds / µm2, when measured using a transmission electron microscopy process. In other embodiments, the seeds 607 may have a concentration of between about 90,000 seeds / µm2 and about 1,000,000 seeds / µm2 (which may result in a grain size of about 1 nm), such as about 160,000 seeds / µm2.If the grain size is larger than specified, uniformity will be negatively affected, while crystallinity may deteriorate if the grain size is too small. However, any suitable concentration can be used.

[0045] Fig. 6C shows another embodiment in which the first annealing process 603 may be terminated before the metal atoms have a constant concentration distributed throughout the seeded ferroelectric film 601. In such an embodiment, there is no constant concentration of seeds 607, and instead, there is a gradient concentration of seeds 607, with a higher concentration of seeds 607 adjacent to one side of the seeded ferroelectric film 601 that was previously adjacent to the metal layer 401 and a lower concentration of seeds 607 adjacent to an opposite side of the seeded ferroelectric film 601.

[0046] Furthermore, if desired, the concentration of seeds 607 may be modified from one process to a subsequent process by modifying the thickness of the metal layer 401 during the deposition of the metal layer 401. In particular, if a greater concentration of seeds 607 is desired, a thicker metal layer 401 may be formed, while a thinner metal layer 401 may be formed if a lower concentration of seeds 607 is desired. For example, in one embodiment where a lower concentration of seeds 607 is desired (e.g., a concentration of between about 10,000 seeds / µm2 and about 90,000 seeds / µm2), the metal layer 401 may be formed to a thickness of about 0.5 nm. In another embodiment, where a higher concentration of seeds 607 is desired (e.g., a concentration of between about 160,000 seeds / µm2 and about 250,000 seeds / µm2), the metal layer 401 may be formed to a thickness of about 0.5 nm.000 nuclei / µm2), the metal layer 401 can be formed to a greater thickness of approximately 2 nm. However, any suitable concentrations and thicknesses can be used.

[0047] Furthermore, depending on the specific materials chosen for the metal layer 401 and the ferroelectric film 501, the material of the metal layer 401 may or may not react with the material of the ferroelectric film 501 while the material of the metal layer 401 diffuses into the ferroelectric film 501. For example, in an unclaimed embodiment in which, for example, magnesium oxide is used as the material of the metal layer 401 and aluminum scandium nitride (AlScN) is used as the material of the ferroelectric film 501, the magnesium oxide does not react while the magnesium oxide diffuses into the ferroelectric film 501. Therefore, at the end of the first annealing process 603, the magnesium oxide is unreacted, and magnesium oxide is used as the seed 507 in subsequent processing (described further below).

[0048] However, in other unclaimed embodiments, the material of the metal layer 401 reacts with the material of the ferroelectric film 501, while the material of the metal layer 401 diffuses into the ferroelectric film 501. For example, in an unclaimed embodiment in which, by way of example, the material of the metal layer 401 is aluminum oxide (Al2O3) and the material of the ferroelectric film 501 is a transition metal oxide, such as hafnium oxide (HfO2), the aluminum oxide not only diffuses into the ferroelectric film 501, but also reacts with the hafnium oxide to form a by-product, such as HfAlO x , to form. Therefore, it is this byproduct, rather than the original material of the metal layer 401, that is present and used as the seed 607 in subsequent processing.

[0049] Fig. Figure 7A shows that according to the invention a second tempering process (which is Fig. 7A by the wavy lines labeled 703) to help initiate crystallization of the material of the seeded ferroelectric film 601. In one embodiment, the second annealing process 703 may be a thermal annealing process, whereby the structure is placed in an inert environment (e.g., an argon environment) and a temperature of the seeded ferroelectric film 601 is increased. However, any suitable annealing process, such as rapid thermal annealing or flash annealing, may be used.

[0050] In an embodiment using a thermal annealing process, the second annealing process 703 may be performed at a temperature higher than the first annealing process 603 (which was used for diffusion and not necessarily crystallization). According to the invention, the second annealing process 703 is performed at a temperature between approximately 400°C and approximately 800°C, such as approximately 600°C, higher than the first annealing process 603.

[0051] Therefore, in some embodiments of the invention where the first annealing process 603 is performed at a temperature of between about 300°C and about 600°C, the second annealing process 703 may be performed at a temperature of between about 400°C and about 800°C, such as about 500°C. Furthermore, to allow the crystallization process to occur, the second annealing process 703 may be performed for a time period of between about 1 minute and about 60 minutes. However, any suitable time period and temperature may be used.

[0052] Fig. Figure 7B shows a close-up view of the dashed box 705 in Fig. 7A. As can be seen, during the second annealing process 703, the material of the seeded ferroelectric film 601 crystallizes using the seeds 607 (e.g., the diffused material of the metal layer 401 or the reaction byproduct of the material of the metal layer 401) as a nucleation point. Therefore, during the crystallization process, each seed 607 forms a separate crystal 707, with each separate crystal 707 either having a separate crystalline phase or otherwise having similar crystalline phases formed by different and separate crystals 707.

[0053] In a particular embodiment, the materials selected for metal layer 401 and ferroelectric film 501 result in a particular crystalline phase resulting from the crystallization process. For example, in an embodiment of the invention where nickel oxide is used for metal layer 401 and hafnium oxide is used as the material of ferroelectric film 501, crystals 707 exhibit an orthorhombic crystalline phase. However, any suitable crystalline phase may be used.

[0054] In one way or another, the crystallization of each separate crystal 707 nucleates at the separate nuclei 607 and then spreads outward from the separate nuclei 607. However, as the crystals 707 grow outward from the separate nuclei 607, a first crystal 707 growing from one nucleus 607 eventually merges into a second crystal 707 growing from a second nucleus 607. When this occurs, crystallization from the nuclei 607 ceases, forming a grain boundary between the various crystals 707.

[0055] However, because the seeds 607 are evenly distributed within the seeded ferroelectric film 601, the crystals 707 are also evenly distributed within the crystallized ferroelectric layer 701. Furthermore, because the crystals 707 are evenly distributed, the crystals 707 have a consistent grain size throughout the crystallized ferroelectric layer 701. In one embodiment where the seeds 607 have a density of between about 10,000 seeds / µm2 to about 250,000 seeds / µm2, the grain size of the crystals 707 may be between about 2 nm and about 10 nm, such as about 5 nm. However, the density and grain size may be any suitable density and any suitable grain size.

[0056] Furthermore, although embodiments use two annealing processes (e.g., the first annealing process 603 and the second annealing process 703) to diffuse and then crystallize the materials to form the crystallized ferroelectric layer 701, this is illustrative and not intended to be limiting. Rather, any number of annealing processes, such as three or more annealing processes, may be used to diffuse and then crystallize the materials, and all such processes are intended to be fully within the scope of the embodiment.

[0057] Fig. 8 shows that, after the crystallized ferroelectric layer 701 has been formed, a conductive stack 801 may be formed over the crystallized ferroelectric layer 701 to form the gate stack 803 with the crystallized ferroelectric layer 701. In one embodiment, the conductive stack 801 may be formed with a first metal material, a second metal material, and a third metal material (not separately shown in Fig. 8). However, any suitable number of material layers may be used.

[0058] The first metal material may be formed adjacent to the crystallized ferroelectric layer 701 and may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The first metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to a thickness of between about 0.5 nm and about 20 nm, although any suitable deposition process or thickness may be used.

[0059] The second metal material may be formed adjacent to the first metal material and, in a particular embodiment, may be similar to the first metal material. For example, the second metal material may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Furthermore, the second metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to a thickness of between about 0.5 nm and about 20 nm, although any suitable deposition process or thickness may be used.

[0060] The third metal material fills a remnant of the opening left by the removal of the dummy gate electrode 111. In one embodiment, the third metal material is a metallic material such as W, Al, Cu, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to fill and / or overfill the opening left by the removal of the dummy gate electrode 111. In a particular embodiment, the third metal material may be deposited to a thickness of between about 0.5 nm and about 50 nm, although any suitable material, deposition method, and thickness may be used.

[0061] After the opening left by the removal of the dummy gate electrode 111 has been filled, the materials may be planarized to remove any material located outside the opening left by the removal of the dummy gate electrode 111. In a particular embodiment, the removal may be performed using a planarization process, such as chemical mechanical polishing. However, any suitable planarization and removal process may be used.

[0062] After the materials of gate stack 803 have been formed and planarized, the materials of gate stack 803 may optionally be recessed and covered with a capping layer (not separately shown). In one embodiment, the materials of gate stack 803 may be recessed, for example, using a wet or dry etch process that uses etchants selective to the materials of gate stack 803. In one embodiment, the materials of gate stack 803 may be recessed by a distance of between about 5 nm and about 150 nm, such as about 120 nm. However, any suitable process and distance may be used.

[0063] After the materials of the gate stack 803 have been removed, the cap layer may be deposited and planarized with the first spacers 113. In one embodiment, the cap layer is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations of these, or the like, deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. The cap layer may be deposited to a thickness of between approximately 5 Å and approximately 200 Å and then planarized using a planarization process such as chemical mechanical polishing, such that the cap layer is planar with the first spacers 113.

[0064] By incorporating the nuclei 607 using the metal layer 401, an additional method can be used to control the crystalline phase of the crystallized ferroelectric layer 701. Furthermore, by controlling the thickness of the metal layer 401 and hence the concentration of the nuclei 607 within the nucleated ferroelectric layer 601, the process can be further used to control the grain size of the crystals 707 formed within the crystallized ferroelectric layer 701.

[0065] Fig. 9A-9B show another embodiment in which the metal layer 401 is formed after the formation of the ferroelectric film 501. In this embodiment, the ferroelectric film 501 is formed first, with the ferroelectric film 501 being deposited directly on the interface layer 301. In one embodiment, the ferroelectric film 501 and the metal layer 401 may be formed as described above with reference to Fig. 4 and Fig. 5A-5B. However, any suitable deposition methods and materials may be used.

[0066] Additionally, however, in this embodiment, after the metal layer 401 is formed over the ferroelectric film 501, an optional capping layer 901 may be formed over the metal layer 401. In one embodiment, the capping layer 901 may be deposited as a single layer or as a multilayer thin film over the metal layer 401 using one or more materials including metals such as silicon-doped titanium nitride (TSN), TiN, TaN, or W; other metal oxides such as amorphous silicon (a-Si); high-K dielectrics such as Al2O3, ZrO2, and TiO2; combinations thereof; or the like. The capping layer 901 may be deposited using a process such as atomic layer deposition (ALD) or the like to a thickness of between about 10 Å and about 50 Å.However, any suitable material, deposition process, and thickness may be used for the cap layer 901.

[0067] Furthermore, to prevent the metal layer 401 from prematurely crystallizing, the deposition process of the cap layer 901 is maintained at a temperature sufficiently low to ensure that crystallization, if present, is minimized. For example, in some embodiments, the deposition process of the cap layer 901 is maintained between approximately room temperature and approximately 400°C. However, any suitable temperature may be used.

[0068] Fig. Figure 9B shows a close-up view of the dashed box 903 in Fig. 9A. As clearly seen in this view, at this point in the manufacturing process, metal layer 401 is disposed over ferroelectric film 501 such that ferroelectric film 501 is in physical contact with interface layer 301. Additionally, cap layer 901 is formed over metal layer 401 such that metal layer 401 is disposed between cap layer 901 and ferroelectric film 501. Such an initial placement allows for the subsequent diffusion of the material of metal layer 401 into ferroelectric film 501 while still allowing the use of cap layer 901.

[0069] Fig. 10A-10B illustrate using the first annealing process 603 to diffuse the material of the metal layer 401 into the ferroelectric film 501 and form the seeded ferroelectric film 601. In one embodiment, the first annealing process 603 may be performed as described above with reference to Fig. 6A, such as by using a thermal annealing process in an inert environment. However, any suitable process may be used to diffuse the material of metal layer 401 into ferroelectric film 501.

[0070] Fig. 10B shows a close-up view of the dashed box 1003 in Fig. 10A. As illustrated, after the first annealing process 603, the metal layer 401 will be effectively received by the ferroelectric film 501 to form the seeded ferroelectric film 601. Therefore, the seeded ferroelectric film 601 is in physical contact with both the interface layer 301 and the cap layer 901.

[0071] Furthermore, given the selected material of the capping layer 901 (e.g., TSN), the metal layer 401 primarily diffuses into the ferroelectric film 501 rather than the material of the capping layer 901. In particular, during the first annealing process 603, there is less, if any, diffusion of the material of the metal layer 401 into the material of the capping layer 901. Therefore, the material of the seeded ferroelectric film 601 is in direct physical contact with the material of the capping layer 901, and the material of the capping layer 901 can be used to apply stress to the material of the seeded ferroelectric film 601.

[0072] Fig. 11A-11B show using the second annealing process 703 to crystallize the seeded ferroelectric film 601 into the crystallized ferroelectric layer 701 with the capping layer 901 disposed. In one embodiment, the second annealing process 703 may be performed as described above with reference to Fig. 7A, such as by using a thermal annealing process in an inert environment. However, any suitable process may be used to crystallize the seeded ferroelectric film 601 and form the crystallized ferroelectric layer 701.

[0073] Fig. 11B shows a close-up view of the dashed box 1103 in Fig. 11A. As shown, after the second annealing process 703, the seeded ferroelectric film 601 crystallizes to form the crystals 707. For example, the seeds 607 seed the formation of the crystals 707, and the crystals 707 grow outward from the separate seeds 607 until they merge into other crystals 707.

[0074] However, by using the capping layer 901, additional strain can be applied to the seeded ferroelectric film 601 during the second annealing process 703 and the crystallization process. This added strain can be used to modify the crystalline phase of the crystals 707 within the crystallized ferroelectric layer 701. In a particular embodiment using the capping layer 901, the crystals 707 can be grown to have a c-axis crystalline orientation perpendicular to the substrate. However, any suitable crystalline orientation can be used.

[0075] Fig. 12 illustrates removing the cap layer 901 and forming the conductive stack 801. In one embodiment, the cap layer 901 may be removed, for example, by using one or more etching processes, such as a wet etching process that uses etchants selective to the material of the cap layer 901, without substantially removing any surrounding material. However, any suitable removal process may be used.

[0076] After the cap layer 901 has been removed, the conductive stack 801 may be formed. In one embodiment, the conductive stack 801 may be formed as described above with reference to Fig. 8. For example, the first metal material, the second metal material, and the third metal material fill the opening left by removing the dummy gate electrode 111, and excess material may be planarized to form the conductive stack 801 and the gate stack 803. However, any suitable methods and materials may be used.

[0077] Although embodiments with reference to Fig. 9A to 12, which utilize the cap layer 901, various modifications of this embodiment may also be used without departing from the scope of the embodiments. For example, in some embodiments, the metal layer 401 may be formed over the ferroelectric film 501; the metal layer 401 may be diffused into the ferroelectric film 501, and the crystallization process and the formation of the conductive stack 801 may be performed without forming the cap layer 901. In other embodiments, the cap layer 901 may not be removed, such that the cap layer 901 forms part of the gate stack 803. These and any other suitable modifications are intended to be fully included within the scope of the embodiments.

[0078] By incorporating the nuclei 607 using the metal layer 401 on an upper surface of the ferroelectric film 501, an additional method can be used to control the crystalline phase of the crystallized ferroelectric layer 701. Furthermore, by adding the use of the cap layer 901, the process can be further used to control the grain size of the crystals 707 formed within the crystallized ferroelectric layer 701.

[0079] Fig. Figure 13 illustrates the use of metal layer 401 and ferroelectric film 501 to form crystallized ferroelectric layer 701 in an embodiment forming a gate-all-around (GAA) device 1301 with nanostructures 1303, such as nanofoils or nanowires. In such an embodiment, an alternating stack of first layers of semiconductor materials and second layers of semiconductor materials is formed.

[0080] According to some embodiments, the first layers may be formed using a first semiconductor material having a first lattice constant, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like. In some embodiments, a first layer of the first semiconductor material (e.g., SiGe) is epitaxially grown using a deposition technique such as epitaxial growth, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), although other deposition processes such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHV-CVD), reduced pressure CVD (RPCVD), a combination thereof, or the like may also be used. In some embodiments, the first layers are formed to a thickness of between about 30 Å and about 300 Å.However, any suitable thickness may be used without departing from the scope of the embodiments.

[0081] After each of the first layers has been formed, respective ones of the second layers may be formed over the first layer. According to some embodiments, the second layers may be formed using a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like, having a second lattice constant that is different from the first lattice constant of the first layer. In a particular embodiment where the first layer is silicon germanium, the second layer is a material such as silicon. However, any suitable combination of materials may be used for the first layers and the second layers.

[0082] In some embodiments, the second layer is epitaxially grown on the first layer using a deposition technique similar to that used to form the first layer. However, the second layer may use any of the deposition techniques suitable for forming the first layer, as set forth above, or any other suitable techniques. According to some embodiments, the second layer is formed to a thickness similar to that of the first layer. However, the second layer may also be formed to a thickness different from the first layer. According to some embodiments, the second layer may be formed to a thickness of between about 30 Å and about 500 Å. However, any suitable thickness may be used.

[0083] After the stack has been formed, the stack is patterned, for example, into a fin from the alternating semiconductor materials. After patterning, a dummy gate stack is formed, and exposed portions of the fin are removed. Spacers 1305 are formed, and source / drain regions 1307 are grown, for example, using an epitaxial growth process. An interlayer dielectric layer 1309 is deposited over the source / drain regions 1307, and the dummy gate is removed to re-expose the fin. After the fin has been exposed, one of the alternating stacks of materials (e.g., silicon or silicon germanium) is removed to form a stack of nanostructures 1303 (e.g., formed of silicon or silicon germanium) extending between the source / drain regions 1307.

[0084] After the stack of nanostructures 1303 has been formed and exposed, the metal layer 401 and the ferroelectric film 501 can be deposited adjacent to each other, as described above. To form the crystallized ferroelectric layer 701, the first annealing process 603 and the second annealing process 703 are used to diffuse the seeds into the ferroelectric film 501 and then crystallize the ferroelectric film 501 into the crystallized ferroelectric layer 701. However, in this embodiment, the crystallized ferroelectric layer 701 is disposed around each of the nanostructures 1303 within the stack of nanostructures 1303.

[0085] After the crystallized ferroelectric layer 701 has been formed around the nanostructures, the gate stack 803 may be deposited around the crystallized ferroelectric layer 710. In one embodiment, the gate stack 803 may be formed as described above with reference to Fig. 8. However, any suitable materials may be used for the gate stack 803. In some embodiments, after being formed, the crystallized ferroelectric layer 701 has a second thickness T2 of between about 2 nm and about 10 nm, while the conductive stack 801 has a first height H1 of between about 20 nm and about 70 nm. As such, a ratio of the second thickness T2 to the first height H1 of between about 0.03 and about 0.5 may be present. However, any suitable dimensions and ratios may be used.

[0086] Fig. 14A-14B show another embodiment in which additional additives (of which the individual atoms of additives 1503 in Fig. 14A-14B are not shown separately, but are shown in Fig. 15A-15B below) are added to the ferroelectric film 501 before crystallization, wherein Fig. 14B a close-up view of the dashed box 1403 in Fig. 13A. In one embodiment, the additives may be atoms of materials used to further drive the crystallization of the crystallized ferroelectric layer 701 toward the orthorhombic shape, such as etridium, nitrogen, germanium, combinations of these, or the like. However, any suitable additives may be used.

[0087] To introduce the desired additives, an additive layer 1401 may be formed adjacent to the ferroelectric film 501. In the Fig. 14A-14B, the additive layer 1401 may be deposited after the deposition of the metal layer 401 and before the deposition of the ferroelectric film 501, such that the additive layer 1401 is disposed between the ferroelectric film 501 and the metal layer 401.

[0088] However, in other embodiments, the additive layer 1401 may be formed in other positions. For example, the additive layer 1401 may be deposited after the deposition of the ferroelectric film 501, such that the ferroelectric film 501 is disposed between the additive layer 1401 and the metal layer 401. In another embodiment, the additive layer 1401 may be deposited before the metal layer 401, such that the metal layer 401 is disposed between the additive layer 1401 and the ferroelectric film 501. However, any suitable position may be used.

[0089] In one embodiment, the additive layer 1401 may be deposited using materials comprising the additive atoms (e.g., etridium, nitrogen, germanium, etc.). For example, in some embodiments, the additive layer may comprise materials such as lanthanum (La), gadolinium (Gd), strontium (Sr), combinations of these, or the like, deposited using methods such as chemical vapor deposition, sputtering, atomic layer deposition, combinations of these, or the like. However, any suitable materials and deposition methods may be used.

[0090] The additive layer 1401 can be formed to a thickness based on the desired concentration of additives within the ferroelectric film 501 after diffusion. In one embodiment where the desired concentration is between about 0.2% and about 50%, the additive layer 1401 can have a thickness of between about 0.2 nm and about 20 nm. However, any suitable thicknesses can be used.

[0091] Fig. 15A-15B show a resulting structure after the first annealing process 603 has been performed such that the ferroelectric film 501 receives both the material of the metal layer 401 (e.g., the seeds 607) and the material of the additive layer 1401 (e.g., the additives 1503) to form an additive received in the ferroelectric layer 1501, wherein Fig. 15B a close-up view of the dashed line 1505 in Fig. 15A. In one embodiment, the first annealing process 603 may be performed as described above with reference to Fig. 6A-6B. However, any suitable method for diffusing both the metal layer 401 and the additive layer 1401 may be used.

[0092] Fig. 16A-16B show a resulting structure after the second annealing process 703 has been performed such that the additive incorporated in the ferroelectric layer 1501 crystallizes into an additive incorporated in the crystallized ferroelectric layer 1601, wherein Fig. 16B a close-up view of the dashed box 1605 of Fig. 16A. As can be seen, during the second annealing process 703, the seeds 607 and the additives 1503 cooperate to crystallize the material of the additive incorporated in the ferroelectric layer 1501.

[0093] In one embodiment, by using additives 1503, the material of crystallized ferroelectric layer 1601 includes an even greater amount of a material that crystallizes into the orthorhombic crystalline phase to increase the ferroelectricity of the material. In one embodiment, using additives 1503 may cause between about 70% and about 95% of the material of crystallized ferroelectric layer 1601 to have the orthorhombic crystalline phase. However, any suitable amount may be used.

[0094] Furthermore, although the use of additive layer 1401 is described above as a method for introducing additives 1503, this method is intended to be illustrative and not limiting the embodiments. In another embodiment, additive 1503 may be introduced using a dopant implantation process, or by introducing the dopants using an additional deposition precursor during the deposition of ferroelectric film 501. Any suitable method for introducing additives 1503 may be used, and all such methods are intended to be fully encompassed within the scope of the embodiments.

[0095] Fig. 17 shows yet another embodiment that adjusts the first annealing process 603 and the second annealing process 703 to further control the grain size of the crystals formed using the seeds 607. In this particular embodiment, the first annealing process 603 is performed at a sufficiently high temperature such that the first annealing process 603 not only helps induce the diffusion of the seeds 607 into the ferroelectric film 501, but also induces partial crystallization of the material of the ferroelectric film 501.

[0096] For example, for partial crystallization, the first annealing process 603 may be performed at a temperature of between approximately 300°C and approximately 600°C. Furthermore, to ensure that complete crystallization does not occur, which would prevent further diffusion of the nuclei 607, the first annealing process 603 may be performed for a time period of between approximately 1 minute and approximately 60 minutes. However, any suitable time period and temperature may be used.

[0097] In partial crystallization, the material of the ferroelectric film 501 begins to crystallize as soon as the nuclei 607 penetrate into the material of the ferroelectric film 501. Since the nuclei 607 begin to penetrate into the ferroelectric film 501 at the interface between the metal layer 401 and the ferroelectric film 501, the material of the ferroelectric film 501 along the interface between the metal layer 401 and the ferroelectric film 501 begins to crystallize, while the material further away from the interface remains uncrystallized.

[0098] After the first annealing process 603 has been completed, the second annealing process 703 may be performed to continue and complete the crystallization of the material of the ferroelectric film 501. In one embodiment, the second annealing process 703 may be performed as described above with reference to Fig.7. However, any suitable process may be used.

[0099] By performing partial crystallization using the first annealing process 603, the crystals 705 have a size distribution that is present throughout the thickness of the crystallized ferroelectric layer 701. For example, crystals 705 that began crystallization first (e.g., crystals 705 formed from materials located along the previous interface between the metal layer 401 and the ferroelectric film 501) and that have the longest time to grow may have a grain size of between approximately 3 nm and approximately 10 nm. Furthermore, crystals 705 that began crystallization later (e.g.,Crystals 705 formed from materials located on an opposite side of the ferroelectric film 501 from the interface between the metal layer 401 and the ferroelectric film 501 and having the shortest growth time have a grain size of between about 1 nm and about 7 nm. However, any suitable grain sizes may be used.

[0100] According to the invention, a semiconductor device comprises: an interface layer over a semiconductor fin; a crystallized ferroelectric layer in physical contact with the interface layer, the crystallized ferroelectric layer comprising a plurality of crystalline regions with grain boundaries between adjacent ones of the plurality of crystalline regions, each of the plurality of crystalline regions comprising one of a plurality of metallic seeds; and a conductive stack over the crystallized ferroelectric layer. In one embodiment, the crystallized ferroelectric layer comprises a transition metal oxide, and the metallic seeds comprise a metal bonded to the transition metal oxide. In one embodiment, the metallic seeds are evenly distributed within the crystallized ferroelectric layer. According to the invention, the metallic seeds are nickel oxide.

[0101] According to the invention, a semiconductor device comprises: a conductive gate stack over a semiconductor fin; spacers over the semiconductor fin; and a crystallized ferroelectric layer between the conductive gate stack and the spacers, wherein the crystallized ferroelectric layer comprises a plurality of crystal regions, the crystal regions each comprising a metal seed and having a grain boundary with a diameter of between approximately 2 nm and approximately 20 nm. In one embodiment, a density of the metal seed within the crystallized ferroelectric layer is between approximately 10,000 seeds / µm2 and approximately 250,000 seeds / µm2. According to the invention, the metal seed is nickel oxide. In one embodiment, the semiconductor device further comprises an interface layer in physical contact with both the crystallized ferroelectric layer and the semiconductor fin.In one embodiment, the crystallized ferroelectric layer comprises hafnium dioxide.

[0102] According to the invention, a method of manufacturing a semiconductor device is provided, the method comprising: forming a metal material over a semiconductor fin; forming a ferroelectric layer in physical contact with the metal material; subsequently diffusing the metal material into the ferroelectric layer to form nuclei; crystallizing the ferroelectric layer using the nuclei to form a crystallized ferroelectric layer; and forming a conductive stack over the crystallized ferroelectric layer. According to the invention, the diffusion of the metal material is performed at least partially with a first annealing process. According to the invention, the subsequent crystallization of the ferroelectric layer is performed at least partially with a second annealing process. According to the invention, a temperature of the second annealing process is higher than a temperature of the first annealing process.According to the invention, the temperature of the first annealing process is between approximately 300°C and approximately 600°C, and the temperature of the second annealing process is between approximately 400°C and approximately 800°C. In one embodiment, the metal material reacts with a material of the ferroelectric layer to form nuclei. In one embodiment, the nuclei are the metal material.

Claims

[1] A semiconductor device comprising: an interface layer (301) over a semiconductor fin (107), a crystallized ferroelectric layer (501) in physical contact with the interface layer (301), the crystallized ferroelectric layer (501) comprising a plurality of crystalline regions with grain boundaries between adjacent ones of the plurality of crystalline regions, each of the plurality of crystalline regions comprising one of a plurality of metallic seeds (607), the metallic seeds (607) being nickel oxide, and a conductive stack (801) over the crystallized ferroelectric layer (501). [2] The semiconductor device according to claim 1, wherein the crystallized ferroelectric layer (501) comprises a transition metal oxide, and the metallic seeds (607) comprise a metal bonded to the transition metal oxide. [3] A semiconductor device according to claim 1 or 2, wherein the metallic seeds (607) are uniformly distributed in the crystallized ferroelectric layer (501). [4] A semiconductor device comprising: a conductive gate stack (803) over a semiconductor fin (107), spacer (113) above the semiconductor fin (107), and a crystallized ferroelectric layer (501) between the conductive gate stack (803) and the spacers (113), wherein the crystallized ferroelectric layer (501) comprises a plurality of crystal regions, the crystal regions each comprising a metal seed (607) and having a grain boundary with a diameter of between 2 nm and 20 nm, wherein the metal seed (607) is nickel oxide. [5] The semiconductor device according to claim 4, wherein a density of the metal seed (607) within the crystallized ferroelectric layer (501) is between 10,000 seeds / µm2 and 250,000 seeds / µm2. [6] A semiconductor device according to claim 4 or 5, further comprising an interface layer (301) in physical contact with both the crystallized ferroelectric layer (501) and the semiconductor fin (107). [7] A semiconductor device according to any one of the preceding claims 4 to 6, wherein the crystallized ferroelectric layer (501) comprises hafnium dioxide. [8] A method of manufacturing a semiconductor device, the method comprising: Forming a metal material over a semiconductor fin (107), Forming a ferroelectric layer (501) in physical contact with the metal material, Diffusing the metal material into the ferroelectric layer (501) to form nuclei (607), subsequently crystallizing the ferroelectric layer (501) using the seeds (607) to form a crystallized ferroelectric layer (601), and Forming a conductive stack (801) over the crystallized ferroelectric layer (601), wherein the diffusion of the metal material is carried out at least partially by means of a first annealing process, and wherein the subsequent crystallization of the ferroelectric layer (501) is carried out at least partially by means of a second annealing process, and wherein a temperature of the second annealing process is higher than a temperature of the first annealing process, and wherein the temperature of the first annealing process is between 300 °C and 600 °C, and the temperature of the second annealing process is between 400 °C and 800 °C. [9] The method of claim 8, wherein the metal material reacts with a material of the ferroelectric layer (501) to form the nuclei (607). [10] The method of claim 8 or 9, wherein the seeds (607) are the metal material.

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