Low-refractive-intensity grating structure and method for its production

Abstract

Method (200) comprising: Forming image sensors (26) in a semiconductor substrate (24); Thinning the semiconductor substrate (24) from a back side (24B) of the semiconductor substrate (24); Forming a dielectric layer (64, 72, 74) on the back side (24B) of the semiconductor substrate (24); Forming a polymer grating (76') on the back side (24B) of the semiconductor substrate (24), the polymer grating (76') having a first refractive index; Forming color filters (82, 82A-C) in the polymer grating (76'), the color filters (82, 82A-C) having a second refractive index higher than the first refractive index; and Forming microlenses (86) on the color filters (82, 82A-C), wherein the method (200) further comprises forming a deep trench isolation grid (56) extending from the backside (24B) of the semiconductor substrate (24) into the semiconductor substrate (24), the deep trench isolation grid (56) being aligned with the polymer grid (76').

Description

BACKGROUNDSolid state image sensors are operated to detect light. Typically, the solid state image sensors include complementary metal-oxide-semiconductor (CMOS)) image sensors (CIS) and charge coupled device (CCD) sensors, which are widely used in various applications such as digital camera (DSC) and handy camera, digital video (DV) and digital video recorder (DVR) applications. These solid state image sensors use an array of image sensor elements, each image sensor element including a photodiode and other elements to absorb light and convert the detected light into digital data or electrical signals.CMOS front side illumination (front side exposure) (FSI) image sensors and CMOS back side illumination (back side exposure) (BSI) image sensors are two main types of CMOS image sensors. The FSI CMOS image sensors are operable to sense light projected from their front side, while the BSI CMOS image sensors are operable to sense light projected from their rear side. When light is projected into the FSI CMOS image sensors or the BSI CMOS image sensors, photoelectrons are generated and then detected by light detecting devices in the pixels of the image sensors. The more photoelectrons are generated, the better the quantum efficiency (QE) of the image sensors, thereby improving the image quality of the CMOS image sensors. Image sensors with polymer gratings are known, for example, from US 2014 / 0 339 606 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-13 show the cross-sectional views of intermediate stages in forming an image sensor chip having a low-refractive-power grating structure, in accordance with some embodiments. FIG. 14 illustrates an image sensor chip having a low refraction grating structure, in accordance with some embodiments. FIG. 15 illustrates an image sensor chip having a low-refractive-power grating structure that is offset from the underlying grating structures, in accordance with some embodiments. FIG. 16 shows a planar view of a low-refractive-power grating structure and the respective color filters, in accordance with some embodiments. FIG. 17 shows the circuit diagram of a pixel of an image sensor, in accordance with some embodiments. FIG. 18 illustrates a process flow for forming an image sensor chip, in accordance with some embodiments.DETAILED DESCRIPTIONThe present invention provides a method having the features of claim 1 and apparatus having the features of claims 7 and 15, respectively. Exemplary embodiments are given in the dependent claims. The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "underlying", "bottom", "below", "overlying", "top", and the like may be used herein for ease of description to describe the relationship of one element or feature to (another) element(s) or feature(s) as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly.A BSI (back-exposure) image sensor chip and the method for forming the same are provided in accordance with some embodiments of the present disclosure. According to some embodiments, the BSI image sensor chip includes a low-refractive-power grid, which may be or include a polymer. Color filters are formed in the low refraction grating. The color filters have higher refraction values than the low refraction grating, and light can be reflected by total reflection from the sidewalls of the low refraction grating. The intermediate stages in forming the BSI image sensor chip are illustrated in accordance with some embodiments of the present disclosure. Some variations of some embodiments are discussed. Embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure, and one of ordinary skill in the art will readily understand modifications that may be made, but at least remain within the contemplated scope of various embodiments. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.FIGS. 1-13 inclusive illustrate the cross-sectional views of intermediates in the formation of an image sensor chip having a low-refractive-power grating in accordance with some embodiments of the present disclosure. The corresponding processes are also schematically reflected in the method sequence 200 shown in FIG. 18.FIG. 1 illustrates the formation of an initial structure of the image sensor chip 22, which may be a portion of the wafer 20 including a plurality of image sensor chips 22 therein. The image sensor chip 22 includes a semiconductor substrate 24. In accordance with some embodiments of the present disclosure, the semiconductor substrate 24 is a crystalline silicon substrate. According to other embodiments of the present disclosure, the semiconductor substrate 24 includes an elemental semiconductor such as germanium; a compound semiconductor including silicon carbon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used. Throughout the specification, the main surface 24A of the substrate 24 is referred to as a front surface of the semiconductor substrate 24, and the main surface 24B is referred to as a back surface of the semiconductor substrate 24. Surfaces 24A and 24B may lie on (100) or (001)m surface planes.Isolation regions, alternatively referred to as shallow trench isolation (STI) regions, are formed to extend into the semiconductor substrate 24 to define regions (such as active regions). In accordance with some embodiments of the present disclosure, the STI regions include a plurality of parts having different functions. For example, the STI regions include an STI lattice structure 32, as shown. The STI regions may include other STI regions (not shown), which may be used, for example, to define regions for devices such as transistors, to form metal pads from the back side of wafer 20, etc. The STI grating structure 32 is a grating for forming an image sensor array therein. A plan view of the STI grating structure 32 is shown in Figure 16. The STI grid structure 32 includes a first plurality of stripes (grid lines) extending in the X direction and a second plurality of grid lines extending in the Y direction and connected to the first plurality of grid lines.Referring to FIG. 1, image sensors 26 are formed to extend from the front surface 24A into the semiconductor substrate 24. The formation of image sensors 26 may include implantation processes. The image sensors 26 are configured to convert light signals (photons) into electrical signals. Image sensors 26 may be metal oxide semiconductor (MOS) light sensitive transistors, light sensitive diodes, or the like. Throughout the specification, image sensors 26 are alternatively referred to as photodiodes 26, although they may be other types of image sensors. According to some embodiments of the present disclosure, photodiodes 26 form an image sensor array. Each of the photodiodes 26 may be in a lattice unit in the STI lattice structure 32.FIG. 1 also shows pixel units 30 having at least some portions in the active regions defined by the STI lattice structure 32. FIG. 17 shows a circuit diagram of an example pixel unit 30, in accordance with some embodiments of the present disclosure, the pixel unit 30 includes a photodiode 26 including an anode coupled to the electrical ground GND and a cathode coupled to a source of the transmission gate transistor 34. The drain of the transmission gate transistor 34 may be coupled to a drain of the reset transistor 38 and a gate of the source follower 42. The reset transistor 38 has a gate coupled to a reset line RST. A source of the reset transistor 38 may be coupled to the pixel supply voltage VDD. Floating diffusion capacitor 40 may be coupled between the source / drain of transfer gate transistor 34 and the gate of source follower 42. Reset transistor 38 is used to preset the voltage on floating diffusion capacitor 40 to VDD. A drain of the source follower 42 is coupled to a supply voltage VDD. A source of the source follower 42 is coupled to the row selector 43. The source follower 42 provides a high impedance output to the pixel unit 30, the row selector 43 functions as a selection transistor of the respective pixel unit 30, and the gate of the row selector 43 is coupled to the selection line SEL.Referring again to FIG. 1, a transistor is illustrated as an example of the devices (such as transistors 34, 38, 42, and 44 in FIG. 17 ) in the pixel unit 30. For example, the transfer gate transistor 34 is illustrated in FIG. 1 as an example. According to some embodiments of the present disclosure, each of the photodiodes 26 is electrically coupled to a first source / drain region of the transfer gate transistor 34 that includes the gate 28 and the gate dielectric 31. The gate dielectric 31 is in contact with the front side surface 24A of the substrate 24. the first source / drain region of the transfer gate transistor 34 may be shared by the corresponding connecting photodiode 26. The floating diffusion capacitor 40 is formed in the substrate 24 by implanting a p-type impurity into the substrate 24 and an n-type impurity at different depths, for example, to form a pn junction acting as the floating diffusion capacitor 40. The floating diffusion capacitor 40 may be formed in a second source / drain region of the transfer gate transistor 34, and thus one of the capacitor plates of the floating diffusion capacitor 40 is electrically coupled to the second source / drain region of the transfer gate transistor 34. Photodiodes 26, the respective transfer gate transistors 34 and floating diffusion capacitors 40 in the same active area constitute portions of the pixel units 30, as also indicated in Fig. 1.Referring again to FIG. 1, the contact etch stop layer 29 is formed on the substrate 24 and the transistors such as transfer gate transistors 34. CESL 29 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, or multi-layers thereof. CESL 29 may be formed using a conformal deposition process such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Interlayer dielectric (ILD) 33 is formed over CESL 29. ILD 33 may include a dielectric material formed using, for example, flowable chemical vapor deposition (FCVD), spin-on coating, CVD, or other deposition process. ILD 33 may also be formed of an oxygen-containing dielectric material, which may be an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or so forth.The front side interconnect structure 44 is formed over the semiconductor substrate 24. The front side interconnect structure 44 is used to electrically connect and connect the devices in the image sensor chip 22 to other package components. The front side interconnect structure 44 includes dielectric layers 46 and metal lines 48 and vias 50 in dielectric layers 46. The front side interconnect structure 44 may include multiple metal layers. In accordance with some embodiments of the present disclosure, dielectric layers 46 include low-k dielectric layers. The low k dielectric layers have low k values, for example, lower than 3.8 and possibly lower than about 3.0.The surface dielectric layer 52 is formed as an upper dielectric layer of the wafer 20. The surface dielectric layer 52 may be formed of a non-low-k dielectric material whose k value is equal to or greater than about 3.8.Bond pads 54 are also formed at the top of wafer 20. Bond pads 54 may be formed of or include copper. The bond pads 54 may also include barrier layers surrounding the copper. The top surfaces of bond pads 54 may be coplanar with the top surface of surface dielectric layer 52.Next, referring to FIG. 2, the wafer 20 is connected to the wafer 120. The respective process is depicted as process 202 in the process flow shown in FIG. 18. According to some embodiments of the present disclosure, the joining is performed by hybrid bonding. Accordingly, the surface dielectric layer 52 in the wafer 20 is bonded to the surface dielectric layer 152 in the wafer 120 by melt bonding, thereby forming S-O-Si bonds. The bond pads 54 of the wafer 20 are also connected to the metal pads 154 of the wafer 120 by direct metal-to-metal bonding. Via bond pads 54 and 154, the circuitry in wafer 120 is electrically and signally connected to the image sensor circuitry in wafer 20.According to some embodiments of the present disclosure, the wafer 120 includes chips 222 further including logic circuits 226 formed on the surface of the semiconductor substrate 124. The logic circuits 126 may include the application circuit used to process the obtained electrical signal obtained from the BSI chip 22. For example, the logic circuitry 126 may include one or more image signal processing (ISP) circuitry used to process the image related signals obtained from the image sensor chip 22. The image signal processing (ISP) circuits may include analog-to-digital converters (ADCs), correlated double sampling (CDS) circuits, row decoders, and the like.With continued reference to FIG. 2, a back side grinding process is performed to grind back side 24B and thin semiconductor substrate 24. The respective process is depicted as process 204 in the process flow shown in FIG. 18. The resulting back side of the semiconductor substrate 24 is shown in FIG. 2 as back side 24B'. The thickness of the substrate 24 may be reduced to less than about 20 μm, less than about 15 μm, or less than about 6 μm, such that light from the back side 24B' may enter the semiconductor substrate 24 and reach the photodiodes 26.Referring to FIG. 3, deep trench isolation (DTI) regions 56 are formed. The respective process is depicted as process 206 in the process flow shown in FIG. 21. According to some embodiments of the present disclosure, the formation of DTI regions 56 includes etching the semiconductor substrate 24 and filling the resulting trenches with a high-k dielectric material such as Ta2O5, an opaque material such as a metal (e.g., tungsten), or combinations thereof. A planarization process, such as a chemical mechanical polish (CMP) process or a mechanical grinding process, is then performed to remove excess materials, leaving DTI regions 56. DTI regions 56 have a function of preventing the entrance of light and a function of preventing the cross-talk of light signals from each other. In accordance with some embodiments of the present disclosure, the DTI regions 56 form a grid, with the grid lines of the DTI regions 56 vertically aligned (matched) to the grid lines of the STI grid structure 32. The DTI regions 56 may include voids, in accordance with some embodiments. The DTI regions 56 will be collectively referred to herein as a DTI lattice structure 56. A top view of the DTI grating structure 56 is shown in FIG. 16. As shown in FIG. 16, the DTI grid structure 56 includes, in plan view, a first plurality of stripes (grid lines) extending in the X direction and a second plurality of grid lines extending in the Y direction and connected to the first plurality of grid lines.FIG. 4 shows the formation of openings 58 in which high absorption regions 60 are to be formed on the backside (BSHA) (FIG. 7 ). The respective process is depicted as process 208 in the process flow shown in FIG. 18. The openings 58 are accordingly referred to below as BSHA openings 58. The BSHA regions 60 have a function of focusing light. According to some embodiments of the present disclosure, there are a single or a plurality (such as two, three, four or more) of BSHA openings 58 that overlap the same pixel unit 30. According to some embodiments of the present disclosure, the formation of BSHA openings 58 includes forming an etch mask (not shown), such as a patterned photoresist, over the semiconductor substrate 24. the etch mask has openings aligned with the pixel units, each opening corresponding to a BSHA opening 58 to be formed. The semiconductor substrate 24 is then etched through the openings in the etch mask to form a plurality of pyramidal openings that can be achieved by a wet etching process, such that the etching along the lattice direction of the semiconductor substrate 24 results in openings in pyramidal form.FIG. 5 illustrates the formation of the dielectric layer 64 The respective process is illustrated as process 210 in the process flow shown in FIG. 18. According to some embodiments of the present disclosure, the dielectric layer 64 has a single-layer structure or a multi-layer structure. For example, the dielectric layer 64 may include a high-k silicon oxide layer and / or (a) high-k dielectric layer(s) including / including an aluminum oxide layer, a hafnium oxide layer, a tantalum oxide layer (Ta2O5), or multiple layers thereof. The silicon oxide layer may be formed by thermal oxidation or a deposition process. The corresponding deposition process of the silicon oxide layer or the high-k dielectric layer may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. The dielectric layer 64 may be formed as a conformal layer that extends into and partially fills BSHA openings 58. According to some embodiments, the dielectric layer 64 may further include an additional transparent dielectric layer over the high-k dielectric layers. The dielectric layer may be formed of silicon oxide or a similar material. The deposition process may include CVD, PECVD, ALD, or the like.According to some embodiments, after the deposition of the dielectric layer 64, an etching process is performed to etch the dielectric layer 64, forming openings 66 that penetrate the dielectric layer 64. The semiconductor substrate 24 is thus exposed to the openings 66.FIG. 6 illustrates the formation of the lattice structure 68 and the metal ground structure 70, in accordance with some embodiments of the present disclosure. The respective process is depicted as process 212 in the process flow shown in FIG. 18. According to some embodiments, the grid structure 68 and the metal ground structure 70 are formed in a deposition and patterning process. For example, metallic materials are first deposited. According to some embodiments of the present disclosure, the metallic materials include the adhesion layer 69A and the metallic material 69B over the adhesion layer 69A. The adhesion layer 69A may include a titanium layer, a titanium nitride layer, or a composite layer including a titanium layer and a titanium nitride layer over the titanium layer. The adhesion layer 69A may have a thickness in the range between about 400 Å and about 600 Å. The metallic material 69B may include tungsten, chromium, or the like, and may have a thickness in the range between about 1.5 kÅ and about 2.5 kÅ.After the deposition of the metallic materials, a patterning process is performed by etching, and the metallic material 69B and the adhesion layer 69A are patterned as the mesh pattern 68 and the ground pattern 70. As viewed from the top of the grid structure 68, as shown in FIG. 16, in an exemplary embodiment, the grid structure 68 may also include a first plurality of stripes (grid lines) extending in the X direction and a second plurality of stripes extending in the Y direction, the second plurality of grid lines being connected to the first plurality of grid lines to form the grid structure 68. The grating openings in grating structure 68 further overlap the grating openings of DTI grating structure 56 and STI grating structure 32 so that light can pass through and be trapped in the openings to reach underlying photodiodes 26. The ground pattern 70 extends into the openings in the dielectric layer 64 to make physical contact and electrically connect to the semiconductor substrate 24.According to alternative embodiments, rather than being formed of metallic materials, the grid structure 68 may be formed of or comprise a dielectric material. For example, the grating structure 68 may be formed of or include silicon oxide, silicon oxynitride, metal, low-refraction polymer, or the like. The formation process may also include depositing one or more dielectric layers and patterning the dielectric layers.Referring to FIG. 7, after forming the grid structure 68 and the ground structure 70, the dielectric layer 72 is deposited. The respective process is depicted as process 214 in the process flow shown in FIG. 18. According to some embodiments of the present disclosure, the dielectric layer 72 is formed of silicon oxide or the like. The thickness of the dielectric layer 72 may range between about 4,000 Å and about 6,000 Å. The dielectric layer 72 may be planarized in a CMP process or a mechanical polishing process such that its top surface is planar. The dielectric layer 72 may or may not have a portion that is higher than the top surfaces of the grid structure 68 and the ground structure 70. The portions of the dielectric layers 64 and 72 that fill the BSHA openings 58 (FIG. 4 ) are referred to below as BSHA regions 60.In accordance with some embodiments, as shown in FIGS. 4-7, the BSHA regions 60 are formed as a result of the formation of the dielectric layers 64 and 72. According to alternative embodiments, the BSHA openings 58 are filled to form the BSHA regions 60 at a time prior to the formation of the dielectric layers 64 and 72. In the respective forming process, after forming the BSHA openings 58, one or more transparent layers, which may include silicon oxide or a high-k dielectric material such as hafnium oxide, aluminum oxide, or the like, are deposited to be filled in BSHA openings 58. A planarization process, such as a CMP process or a mechanical polishing process, is then performed, resulting in the BSHA regions 60. The resulting BSHA regions 60 have their top surfaces coplanar with the back surface 24B' of the semiconductor substrate 24.Next, as shown in FIG. 8, the dielectric layer 74 is formed. The dielectric layer 74 may be used to isolate metal bond pads (not shown) used for the wire bonds connected to the circuits in the BSI chip. According to alternative embodiments, the dielectric layer 74 is either not formed or formed and patterned so that the portion of the dielectric 74 is removed from the regions directly above the pixels 30. As a result, the subsequently formed polymeric mesh structure 76' and / or the color filters 82 (FIG. 13 ) may alternatively be / may be in physical contact with the dielectric layer 72. In accordance with some embodiments of the present disclosure, the dielectric layer 74 is formed of silicon oxide, which may be formed by PECVD or other applicable methods. The thickness of the dielectric layer 74 may range between about 1,500 Å and about 2,500 Å. The dielectric layer 74 is sometimes referred to as a passivation layer.Referring to Fig. 8, a low refraction layer 76 is formed which may be formed as a capping layer. The respective process is depicted as process 216 in the process flow shown in FIG. 18. The low refraction layer 76 may be clear or white without color. The thickness T1 of the low refraction capability layer 76 may range between about 2,000 Å and about 5 nm. The low refraction layer 76 has a relatively low refraction value that is lower than the refraction value of the subsequently formed color filters 82 (FIG. 13 ). In some embodiments, the refractive power of the low refractive power layer 76 is less than about 2.0 and may be in the range between about 1.3 and about 2.0. The available material of the low refractive index layer 76 includes polymers that may be resins, organic compounds, or the like, and is not limited thereto. For example, the applicable polymers for forming a low refractive power layer 76 may include, and are limited to, polymethyl methacrylate (PMMA), epoxy acrylates, aliphatic urethane acrylates, aromatic urethane acrylates, polyester acrylates, acrylic acrylates, and the like, or combinations thereof.The low refraction layer 76 is then patterned to form a grating structure 76', as shown in Figure 9. The respective process is depicted as process 218 in the process flow shown in FIG. 18. In some embodiments, a patterning mask 78, such as a photoresist, is formed over the low refraction layer 76 and then patterned. Patterning of the photoresist 78 may be performed using a lithography mask 80 having opaque structures 80A and transparent structures 80B to expose the photoresist 78, followed by a development process to remove some portions of the photoresist 78. The patterned photoresist 78 is then used to etch the underlying low refractive power layer 76 and form a grating structure 76'. In alternative embodiments, the low refraction layer 76 and the resulting grating structure 76' are formed from a photosensitive material, which may be resin or other organic compound or the like. Accordingly, no etching mask 78 is formed in patterning the low refractive power layer 76. Rather, the patterning of the low-refractivity layer 76 is accomplished by using a lithography mask 80 to directly expose the photosensitive low-refractivity layer 76 to light, followed by a development process to remove some portions of the low-refractivity layer 76. After forming the grating structure 76', the grating structure 76' is fired so that it is not repatterned by the subsequent patterning processes to form color filters. A top view of the grating structure 76' is shown in Figure 16. The grid structure 76' in turn includes a first plurality of stripes (grid lines) extending in the X direction and a second plurality of grid lines extending in the Y direction and connected to the first plurality of grid lines.In some embodiments, the widths of the stripes in the lattice structure 76' have the same widths as the stripes of the underlying lattice structure 68, the DTI lattice structure 56, and the STI lattice structure 32. with this configuration, the underlying stripes of the lattice structure 68, the DTI lattice structure 56, and the STI lattice structure 32 do not extend laterally beyond the overlying stripes of the lattice structure 76', the lattice structure 68, and the DTI lattice structure 56, and do not have a top surface that is not covered by the corresponding overlying lattice structures. Because the top surfaces can reflect the light upward with the grating structures oriented vertically, the light is not undesirably reflected back from the top surfaces.According to alternative embodiments, the grating structure 76' may be formed using other methods, for example, a sacrificial layer may be deposited (or deposited) as a capping layer, followed by a lithography process. The resulting patterned sacrificial layer may have a grid structure similar to that of the photoresist 78 shown in FIG. 8. The mesh structure 76' is then filled into the trenches in the sacrificial layer, followed by removal of the sacrificial layer, leaving the polymeric mesh structure 76'.FIGS. 10-12 illustrate some example methods for forming color filters 82 (including color filters 82A, 82B, and 82C) in the grating openings of grating structure 76'. The respective process is depicted as process 220 in the process flow shown in FIG. 18. Referring to FIG. 10, first color filters 82A having a first color (such as red) are filled into some of the grating openings in the grating structure 76'. According to some embodiments, the filling process includes dispensing the respective color filter materials and removing the respective color filter materials having the first color by a photolithography process. The respective color filters are denoted by 82A. The color filters 82A are fired so that they are not removed by the subsequent lithography processes as shown in FIGS. 11 and 12.Referring to FIG. 11, second color filters 82B having a second color (such as green) are filled into some of the grating openings in the grating pattern 76'. The filling process may include a dispensing process and a photolithography process. The respective color filters are denoted by 82B. The color filters 82B are also fired so that they are not removed by the subsequent lithography processes as shown in FIG. 12.Figure 12 shows the formation of third color filters 82C which are of a third color (such as blue) and fill in the remaining grating openings in the grating structure 76'. The filling process may include a dispensing process and a lithography process. The respective color filters are denoted by 82C.According to some embodiments, the color filters 82A, 82B, and 82C are also formed of polymers that may be resins, organic compounds, or the like and that are colored to have different colors. The materials of the color filters 82A, 82B, and 82C have a relatively higher refractive index compared to the refractive index of the low-refractive-power layer 76 and the respective grating structure 76'. In some embodiments, the refraction value of the color filters 82A, 82B, and 82C is greater than about 2.0 and may range between about 2.0 and about 4.0. Further, when the refraction values of the color filters 82A, 82B, and 82C are expressed as N82, and the refraction value of the grating structure 76' is expressed as N76, the difference (N82 - N76) is high (by selecting appropriate materials), so that incident light having smaller incident angles together with the incident light having large incident angles can also exhibit total reflection. In some embodiments, the difference (N82-N76) is greater than about 0.3, greater than about 0.5, and may range between about 0.3 and about 1. The high difference of the refraction value (N82 - N76) is advantageous for total reflection of the light, as discussed with reference to Fig. 13.In some embodiments, a planarization process may be performed after the formation of color filters 82A, 82B, and 82C to further collimate the top surfaces of grid structure 76' and color filters 82A, 82B, and 82C. Accordingly, the top surfaces of the grating structure 76' and the color filters 82A, 82B and 82C are coplanar. In accordance with some embodiments, a dielectric layer 84, which may be formed of silicon oxide or similar materials, is deposited and planarized along with the grating structure 76' and the color filters 82A, 82B, and 82C. The dielectric layer 84 may be removed after planarization or remain in the final image sensor chip. According to alternative embodiments, the planarization is performed without forming the dielectric layer 84. Accordingly, the dielectric layer 84 is shown as dashed to indicate that it may or may not be formed.In subsequent processes, as shown in FIG. 13, additional components such as microlenses 86 are then formed. The respective process is depicted as process 222 in the process flow shown in FIG. 18. Each of the image sensors 26 is aligned with one of the microlenses 86. Thus, the image sensor chip 22 (and the corresponding wafer 20) is formed. There may be a protective layer 88 formed on the microlenses 86, for example, by depositing a conformal silicon oxide layer. The respective process is depicted as process 224 in the process flow shown in FIG. 18. In subsequent processes, the image sensor wafer 20 and the wafer 120 are sawed into packages 90 each including one of the image sensor chips 22 and one of the device chips 122.Forming the grating structure 76' has the advantage of reducing delamination. When the grating structure 76' is formed of metals or other dielectric materials whose properties (such as coefficient of thermal expansion (CTE)) are significantly different from those of color filters, delamination may be generated between the color filters 82 and the grating structure 76'. Because the grating structure 76' according to embodiments of the present disclosure and color filters are formed from similar materials having similar properties, delamination is reduced. Moreover, the grating structure 76' can act as an effective grating for reducing and preventing crosstalk of the light signals destined for different pixels. For example, according to Snell's law, the equation (Sin θc=(N76 / (N82)*Sin90) determines the minimum incident angle θc at which total reflection of the light 92 may still occur. By making the refraction value N82of color filters 82 higher than the refraction value N76of the grating structure 76, all the light 92 having an incident angle equal to or greater than the incident angle θchas total reflection, and thus the grating structure 76' can reduce crosstalk. In some embodiments, the grating structure 76' and the underlying grating structure 68, the DTI grating structure 56, and the STI grating structure 32 together form the cross-talk prevention structure.FIG. 14 illustrates package 90 according to alternative embodiments. Due to the formation of the grating structure 76', some of the underlying grating structures may be omitted. For example, FIG. 14 illustrates package 90 in accordance with some embodiments, wherein grid structure 68 shown in FIG. 13 is not formed. Further, the DTI grid structure 56 is shown as dashed to indicate that it may or may not be formed according to various embodiments of the present disclosure.In some embodiments, as shown in FIGS. 13 and 14, the grating structure 76' is vertically aligned with the grating structure 68, the DTI grating structure 56, and the STI grating structure 32. According to other embodiments, the grating structure 76' is vertically offset from the grating structure 68, the DTI grating structure 56, and the STI grating structure 32, as shown in FIG. 15. Although not shown in FIG. 15, the DTI lattice structure 56 may be slightly offset to the left from the overlying lattice structure 68, and / or the STI lattice structure 32 may be slightly offset to the left from the overlying DTI lattice structure 56. These embodiments may be used to detect the light projected onto the BSI chip 22 from one direction rather than all directions. For example, light can be projected from top right to bottom left. In some embodiments, the center of a grid line of the grid structure 76' is offset from the center of the corresponding grid line of the underlying grid structure 68 and / or the DTI grid structure 56 and the STI grid structure 32 by the offset distance D1. This may be greater than about 100 Å and range between about 500 Å and about 5,000 Å.FIG. 16 shows a top view of the color filters 82, the grating structure 76', the metal grating structure 68, the DTI grating structure 56, and the STI grating structure 32, in accordance with some embodiments. Each of the grid structures 76', 56, and 32 may include a first plurality of strips extending in the X direction and a second plurality of strips extending in the Y direction and connecting the first plurality of strips. The color filters 82 are formed in and therefore surrounded by the grating openings of the grating structure 76'. The lattice structures 68, 56, and 32 may be formed under and overlapped by the lattice structure 76'.The embodiments of the present disclosure have some advantageous features. Because the polymeric mesh structure has similar properties to color filters, delamination between the polymeric mesh structure and the color filters is reduced or eliminated. The polymeric lattice structure also has a lower refraction value than the color filters. Accordingly, total reflection may occur, whereby the polymer lattice structure becomes an effective light reflecting lattice.According to some embodiments of the present disclosure, a method includes forming image sensors in a semiconductor substrate; thinning the semiconductor substrate from a back side of the semiconductor substrate; forming a dielectric layer on the back side of the semiconductor substrate; forming a polymer lattice on the back side of the semiconductor substrate, the polymer lattice having a first refraction value; forming color filters in the polymer lattice, the color filters having a second refraction value higher than the first refraction value; and forming microlenses on the color filters. In an embodiment, forming the polymer lattice comprises depositing a polymer layer; and patterning the polymer layer to form the polymer lattice. In an embodiment, the method further comprises, before forming the polymer lattice, forming a metal lattice on the back side of the semiconductor substrate, wherein the polymer lattice is vertically oriented to the metal lattice. In an embodiment, the method further comprises forming high absorption regions on the backside extending from a backside of the semiconductor substrate into the semiconductor substrate, wherein lattice openings of the polymer lattice are aligned with the backside high absorption regions. In an embodiment, the method further comprises forming a deep trench isolation grid extending into the semiconductor substrate from the back side of the semiconductor substrate, wherein the deep trench isolation grid is aligned with the polymer grid. In one embodiment, the second refraction value is greater than the first refraction value by a difference greater than about 0.5. In an embodiment, the polymer grid is formed before the color filters are formed, and the color filters are filled in grid openings of the polymer grid.According to some embodiments of the present disclosure, an apparatus includes a BSI image sensor chip having a semiconductor substrate; image sensors in the semiconductor substrate; a polymer grid over the semiconductor substrate, the polymer grid being located on a back side of the semiconductor substrate; and color filters filling grid openings of the polymer grid. In one embodiment, the polymer grating has a first refraction value and the color filters have a second refraction value that is higher than the first refraction value. In one embodiment, a difference between the second refraction value and the first refraction value is greater than about 0.5. In an embodiment, a top surface of the polymer grid is coplanar with the top surfaces of the color filters. In an embodiment, the device further includes a metal grid overlying the semiconductor substrate and underlying the polymer grid, the metal grid oriented vertically to the polymer grid. In an embodiment, the device further includes a metal grid overlying the semiconductor substrate and underlying the polymer grid, the polymer grid being horizontally offset from the polymer grid. In an embodiment, the device further comprises a deep trench isolation grid in the semiconductor substrate, wherein the deep trench isolation grid is vertically aligned with the polymer grid.According to some embodiments of the present disclosure, the apparatus includes a semiconductor substrate; image sensors in the semiconductor substrate; a deep trench isolation grid in the semiconductor substrate; a metal grid over the semiconductor substrate; a polymer grid over the metal grid, wherein the first grid lines of the polymer grid, the second grid lines of the metal grid, and the third grid lines of the deep trench isolation grid are vertically aligned, and wherein the image sensors are vertically aligned with grid openings of the polymer grid, the metal grid, and the deep trench isolation grid; color filters in the grid openings of the polymer grid, wherein a first refraction value of the polymer grid is less than a second refraction value of the color filters; and microlenses over the color filters. In an embodiment, a difference between the second refraction value and the first refraction value is greater than about 0.5.

Claims

A method (200) comprising: forming image sensors (26) in a semiconductor substrate (24); thinning the semiconductor substrate (24) from a back side (24B) of the semiconductor substrate (24); forming a dielectric layer (64, 72, 74) on the back side (24B) of the semiconductor substrate (24); forming a polymer lattice (76') on the back side (24B) of the semiconductor substrate (24), the polymer lattice (76') having a first refraction value; forming color filters (82, 82A-C) in the polymer lattice (76'), the color filters (82, 82A-C) having a second refraction value that is higher than the first refraction value; and forming microlenses (86) on the color filters (82, 82A-C), the method (200) further comprising forming a deep trench isolation grid (56) extending into the semiconductor substrate (24) from the back side (24B) of the semiconductor substrate (24), the deep trench isolation grid (56) aligned with the polymer grid (76').The method (200) of claim 1, wherein forming the polymer lattice (76') comprises: depositing a polymer layer (76); and patterning the polymer layer (76) to form the polymer lattice (76').The method (200) of claim 1 or 2, further comprising, before forming the polymer lattice (76'), forming a metal lattice (68) on the back side (24B) of the semiconductor substrate (24), wherein the polymer lattice (76') is vertically oriented to the metal lattice (68).The method (200) of any preceding claim, further comprising forming high absorption regions (60) on the backside (24B) extending from a backside (24B) of the semiconductor substrate (24) into the semiconductor substrate (24), wherein lattice openings of the polymer lattice (76') are aligned with the high absorption regions (60) on the backside (24B).The method (200) of any preceding claim, wherein the second refraction value is greater than the first refraction value by a difference greater than 0.5.The method (200) of any preceding claim, wherein the polymer grid (76') is formed before the color filters (82, 82A-C) are formed, and the color filters (82, 82A-C) are filled in grid openings of the polymer grid (76').An apparatus comprising: a BSI image sensor chip (22), back-exposure image sensor chip comprising: a semiconductor substrate (24); image sensors (26) in the semiconductor substrate (24); a polymer grid (76') over the semiconductor substrate (24), the polymer grid (76') being located on a back side (24B) of the semiconductor substrate (24); and color filters (82, 82A-C) filling grid openings of the polymer grid (76'), the apparatus further comprising a deep trench isolation grid (56) in the semiconductor substrate (24), the deep trench isolation grid (56) being oriented vertically to the polymer grid.The apparatus of claim 7, wherein the polymeric mesh (76') has a first refraction value and the color filters (82, 82A-C) have a second refraction value that is higher than the first refraction value.The apparatus of claim 8, wherein a difference between the second refraction value and the first refraction value is greater than 0.5.The apparatus of any of claims 7 to 9, wherein the first sidewalls of the color filters (82, 82A-C) contact the second sidewalls of the polymeric grid (76') to form vertical interfaces.The device of any of claims 7 to 10, wherein a top surface of the polymeric grid (76') is coplanar with the top surfaces of the color filters (82, 82A-C).The device of any of claims 7 to 11, wherein the polymeric mesh (76') includes a resin.The device of any of claims 7 to 12, further comprising a metal grid (68) overlying the semiconductor substrate (24) and underlying the polymer grid (76'), the metal grid (68) being oriented vertically to the polymer grid (76').The device of any of claims 7 to 12, further comprising a metal grid (68) overlying the semiconductor substrate (24) and underlying the polymer grid (76'), the polymer grid (76') being horizontally offset from the metal grid (68).An apparatus comprising: a semiconductor substrate (24); image sensors (26) in the semiconductor substrate (24); a deep trench isolation grid (56) in the semiconductor substrate (24); a metal grid (68) over the semiconductor substrate (24); a polymer grid (76') over the metal grid (68), wherein the first grid lines of the polymer grid (76'), the second grid lines of the metal grid (68), and the third grid lines of the deep trench isolation grid (56) are vertically aligned, and wherein the image sensors (26) are vertically aligned with the grid openings of the polymer grid (76'), the metal grid (68), and the deep trench isolation grid (56); Color filters (82, 82A-C) in the grating openings of the polymer grating (76'), wherein a first refraction value of the polymer grating (76') is less than a second refraction value of the color filters (82, 82A-C); and microlenses (86) over the color filters (82, 82A-C).The apparatus of claim 15, wherein a difference between the second refraction value and the first refraction value is greater than 0.5.The device of claim 15 or 16, further comprising a dielectric layer (72) filling the metal grid (68), wherein a portion of the dielectric layer (72) extends higher than the metal grid (68).The device of any of claims 15 to 17, wherein the polymeric mesh (76') includes a resin.

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