METHOD FOR THE MANUFACTURE OF PHASE-CHANGE STORAGE ELEMENTS AND CORRESPONDING DEVICE

Abstract

A method comprising: forming a dielectric layer (42) over a substrate (20), wherein the dielectric layer (42) has a top surface; etching an opening (44) in the dielectric layer (42); forming a bottom electrode (50) within the opening (44), wherein the bottom electrode (50) has a barrier layer (46), the formation of the bottom electrode (50) comprising: depositing the barrier layer (46) in the opening (44); depositing a conductive material (48) on the barrier layer (46); and etching the barrier layer (46) and the conductive material (48), wherein the etching exposes side walls of the opening (44), and wherein, after etching the barrier layer (46) and the conductive material (48), the top surface of the conductive material (48) is convex;Forming a phase-change material layer, PCM layer (54), within the opening (44) and on the bottom electrode (50), wherein a top surface of the PCM layer (54) is at the same height as or below the top surface of the dielectric layer (42); and forming a top electrode (56) on the PCM layer (54).

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 016,337, filed on April 28, 2020, which is incorporated by reference into the present application. STATE OF THE ART

[0002] Semiconductor memories are used in integrated circuits (ICs) for electronic applications, including radios, televisions, mobile phones, and personal computing devices. One type of semiconductor memory is phase-change random-access memory (PCRAM), in which values ​​are stored in phase-change materials, such as chalcogenide. Phase-change materials can switch between an amorphous phase (in which they exhibit low resistance) and a crystalline phase (in which they exhibit high resistance) to specify bit codes. A PCRAM cell typically contains a phase-change material element (PCM element) sandwiched between two electrodes. List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1 to Fig. Figure 5 illustrates the cross-sectional views of intermediate stages in the formation of phase-change direct access memory cells (PCRAM cells) in accordance with some embodiments. Fig. 6 to Fig. Figure 8 illustrates cross-sectional views of intermediate stages in the formation of a PCRAM cell in accordance with some embodiments. Fig. Figure 9 illustrates a process flow for an electrode etching process in accordance with some embodiments. Fig. 10A to Fig. Figure 10D illustrates cross-sectional views of bottom electrodes of a PCRAM cell in accordance with some embodiments. Fig. 11 to Fig. Figure 14 illustrates cross-sectional views of intermediate stages in the formation of a PCRAM cell in accordance with some embodiments. Fig. 15 and Fig. Figure 16 illustrates cross-sectional views of intermediate stages in the formation of PCRAM cells in accordance with some embodiments. Fig. Figure 17 schematically illustrates a perspective view of a PCRAM array in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying," "below," "under," "superior," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] In accordance with some embodiments of the present disclosure, a phase-change random-access memory (PCRAM) structure is formed, comprising multiple PCRAM cells that may be arranged in an array. The PCRAM cells have a bottom electrode, a phase-change material (PCM) layer on the bottom electrode, and a top electrode on the PCM layer. In some embodiments, the bottom electrode is formed by etching an opening in a dielectric layer and then depositing a barrier material and a conductive material in the opening. A back-etching process is performed to deepen the barrier material and the conductive material within the opening, the remaining barrier material and the conductive material forming the bottom electrode.The etching process can be, for example, an atomic layer etching (ALE) process or similar, and it can remove most or all of the barrier material from the sidewalls of the aperture above the recessed bottom electrode. Removing the barrier material from the aperture sidewalls can reduce heat and electrical losses in the PCRAM cell. The PCM is deposited at the bottom electrode, and another etching process is performed to remove excess PCM material, with the remaining PCM forming the PCM layer. The etching process can recess the PCM below a top surface of the dielectric layer. The top electrode is then formed on the PCM layer.By forming a PCM layer surrounded by the dielectric layer, the PCRAM layer can have improved thermal insulation, allowing the PCRAM layer to be heated more efficiently during operation, which can improve the efficiency and performance of the PCRAM cell.

[0007] Fig. 1-8 and Fig. 11-16 are cross-sectional views showing a component area 12 a wafer 10 illustrate, in which PCRAM cells 60 are formed (see Fig. 14 and Fig. 15). Fig. 5-8 and Fig. Figures 11-14 show an enlarged section 45 the structure. Fig. Figure 9 shows a process flow for an electrode etching process. 100 and Fig. 10A-D show example soil electrodes 50 , which use the electrode etching process 100 are educated. Fig. Figure 17 illustrates a schematic of a PCRAM array. 70, which contains several PCRAM cells 60 contains.

[0008] Fig. Figure 1 illustrates a cross-sectional view of a component area. 12 a wafer 10 in accordance with some embodiments. The component areas 12 are different areas of the wafer 10 , which are separated in subsequent steps to form a plurality of component dies 12 to form PCRAM structures, such as PCRAM cells 60 (see Fig. 14-15) or a PCRAM array 70 , which contains several PCRAM cells 60 exhibits (see Fig. 17), exhibit. The wafer 10 exhibits a semiconductor substrate 20 on, for example, silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 20It may contain other semiconductor materials, such as germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or stepped substrates, may also be used. The semiconductor substrate 20 has an active surface (e.g., the surface that is in Fig. 1 facing upwards), sometimes called a front face, and an inactive surface (e.g., the surface that is in Fig. 1 (pointing downwards), sometimes called a reverse side.

[0009] Components are located on the active surface of the semiconductor substrate. 20formed. The components can be active and / or passive. For example, the components can be transistors, diodes, capacitors, resistors, or the like, and can be processed according to applicable manufacturing processes. As an example, illustrated Fig. 1 access transistors 22 , located on the front surface of semiconductor substrate 20 are formed, which are used to access PCRAM cells 60 of the component-This 12 (see Fig. 16) to access (or “select”) them. In accordance with some embodiments, the access transistors have 22 Gate dielectrics 25 , gate electrodes 26 , Source / Drain areas 24 , Source / Drain contact connector 30 and gate contact connector 32 In some embodiments, the source / drain regions may be located. 24 into the semiconductor substrate 20 extend.

[0010] As in Fig. Figure 1 shows one or more interlayer dielectric layers (ILD layers). 31 on the semiconductor substrate 20 formed, and electrically conductive elements such as the contact plugs 30 / 32 are in the ILD layers 31 formed to electrically connect with the access transistors 22 to connect the contact plugs 30 / 32 They can be formed from materials such as tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. The ILD layers 31can be formed from any dielectric material, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; a nitride such as silicon nitride or the like; a low-k dielectric material; or the like, or combinations thereof. The ILD layer(s) can be formed by any suitable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like, or a combination thereof. The contact connectors 30 / 32 or other electrically conductive elements in the ILD layer(s) 31 can be formed by any suitable process, such as deposition, damascus (e.g., single damascus, double damascus, etc.), the like, or combinations thereof. In some embodiments, the ILD layer(s) exhibits 31one or more intermetal dielectric layers (IMD layers).

[0011] Still in relation to Fig. 1 are an intermetal dielectric layer (IMD layer) 33 and metal pipes 34 above the ILD layer(s) 31 formed, in accordance with some embodiments. The IMD layer 33 It can be formed from any suitable dielectric material, for example an oxide such as silicon oxide, PSG, BSG, BPSG, USG, or the like; a nitride such as silicon nitride or the like; or the like, or combinations thereof. The IMD layer 33 It can be formed by any suitable deposition process, such as spin coating, PVD, CVD, the like, or a combination thereof. The IMD layer 33 can be a layer formed from a low-k dielectric material, which has a lower k-value than approximately 3.0.

[0012] metal pipes 34 are in the IMD layer 33 formed and electrically connected to the access transistors 22 (e.g. through the contact plugs) 30 / 32 ) coupled. In some embodiments, some or all of the metal conductors can be coupled. 34 are used as word lines (WL) that are connected to columns of PCRAM cells 60 in a PCRAM array 70 are connected, which is explained in greater detail below. Fig. 17 is described. In accordance with some embodiments, the metal conduits 34 Diffusion barrier layers and conductive material above the diffusion barrier layers. As an example process for the formation of metal conductors 34 , openings (not shown in the figures) can occur in the IMD layer 33 They can be formed using, for example, a suitable etching process. The openings accommodate underlying conductive elements, such as the contact plugs. 30 / 32The diffusion barrier layers can be formed from tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, the like, or combinations thereof, and can be formed in the openings by a deposition process such as atomic layer deposition (ALD) or the like. The conductive material can contain copper, aluminum, tungsten, silver, the like, or combinations thereof, and can be formed over the diffusion barrier layers in the openings using an electrochemical plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive material is copper, and the diffusion barrier layers are thin barrier layers that prevent the copper from penetrating the IMD layer. 33to diffuse. After the formation of the diffusion barrier layers and the conductive material, excesses of the diffusion barrier layers and the conductive material can be removed by, for example, a planarization process such as a chemical-mechanical polishing process (CMP process). The remaining diffusion barrier layer and the conductive material form the metal conductors. 34 in the IMD layer 33 Other techniques besides these can be used to repair the metal pipes. 34 to form.

[0013] Fig. Figure 2 illustrates the formation of dielectric layers 36 and metallization layers 40 over the metal pipes 34 and electrically connected to these, in accordance with some embodiments. The metallization layers 40 provide additional connections (e.g. between the metal conductors) 34 , the access transistors 22or the like) ready. The dielectric layers 36 In some embodiments, they can be considered IMD layers and can be made of dielectric material(s) similar to those above for the IMD layer. 33 The described metallization layer is formed. 40 (e.g. metallization structures) can include metal conductors and vias in the dielectric layers. 35 The metallization layer is formed. 40 It can be formed using a Damascus process, such as a single Damascus process, a double Damascus process, or the like. For example, the metallization layer can be 40 by etching into a dielectric layer 36To create openings, fill the openings with a conductive material and then perform a planarization process, such as a CMP process or a grinding process, to remove excess conductive material. The metallization layer 40 In some embodiments, it can be used in a similar way to the metal pipes. 34 can be formed, or can be formed using another suitable technique. It is welcomed that although a metallization layer 40 (featuring metal conductors and underlying vias) in Fig. Figure 2 illustrates that in other embodiments there may be additional metallization layers, which are in additional dielectric layers above the dielectric layers. 36 are formed. Alternatively, the PCRAM cells formed subsequently can be 60 ( Fig. 14) directly on the metal pipes 34can be formed without the metallization layers 40 to form. In some embodiments, the metal conductors 34 and / or the contact plugs 30 / 32 considered as part of the metallization layers. In some embodiments, metal conduction regions are part of the metallization layer. 40 formed, exhibiting a width W1 in the range of approximately 100 nm to approximately 300 nm.

[0014] Fig. 3 to Fig. 15 are different views of intermediate stages in the manufacture of PCRAM cells. 60 of a building component-This 12 (see Fig. 15) in accordance with some embodiments. Fig. 3 and Fig. 4 show the same in Fig. 1 and Fig. 2 shown cross-section and Fig. 5-8 and Fig. 10A-D and Fig. Figures 11-15 illustrate an enlarged section 45 the in Fig. 4 structure shown.

[0015] With regard to Fig. 3 is an IMD layer 42 above the dielectric layers 36 and metallization layer(s) 40 formed in accordance with some embodiments. In some embodiments, an etch stop layer (not shown in the figures) is applied to the dielectric layers. 36 and metallization layer(s) 40 before the formation of the IMD layer 42 The etch stop layer can be formed from one or more layers of dielectric material, such as aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, the like, or a combination thereof. The etch stop layer can be formed by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof. In some embodiments, the IMD layer is 42formed from a tetraethyl orthosilicate oxide (TEOS oxide) (e.g., silicon oxide deposited using a CVD process with TEOS as a precursor). In some embodiments, the IMD layer can 42 The IMD layer is formed using PSG, BSG, BPSG, USG, fluorosilicate glass (FSG), silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, SiOCH, a flowable oxide, a porous oxide, the like, or combinations thereof. 42 It can, for example, also be formed from a low-k dielectric material with a k-value lower than approximately 3.0. In some embodiments, the IMD layer 42 formed to have a thickness T1 in the range of approximately 60 nm to approximately 1000 nm. Other thicknesses are possible.

[0016] In Fig. 4 and Fig. 5 are openings 44 in the IMD layer 42 structured in accordance with some embodiments. Fig. Figure 5 shows an enlarged section 45 the in Fig. 4 cross-sectional views shown. The openings 44 lay the top metallization layer 40 free, so that the ground electrodes 50 the PCRAM cells 60 , which are subsequently located in the openings 44 are formed (see Fig. 14) electrical connection with the metallization layer(s) 40 manufacture. In some embodiments, in which the metallization layer(s) 40 The IMD layer is not formed. 42 over the metal pipes 34 formed and the openings 44 lay the metal pipes 34 free. The openings 44can be formed using acceptable photolithography and etching techniques. For example, a mask layer (not shown), such as a hard mask layer or a photoresist layer (e.g., a single-layer photoresist, a three-layer photoresist, or the like), can be applied over the IMD layer. 42 are formed and structured. The IMD layer 42 It can then be etched using the structured mask layer as an etching mask to create the openings. 44 to form the IMD layer. 42 It can be etched using an anisotropic etching process, such as a suitable dry etching process. One or more etching processes can be performed, and the openings 44 can be prevented by an etch stop layer (if present) above the metallization layer 40 extend. After the openings have formed. 44Remaining sections of the mask layer can be removed using, for example, an ashing process, an etching process, or other suitable processes.

[0017] The openings 44 exhibit tapered side walls, as in Fig. 4-5 shown, or the openings 44 They can essentially have vertical side walls. In some embodiments, the openings are 44 formed with a width W2 in the range of approximately 40 nm to approximately 80 nm. Other widths are possible. In some embodiments, the upper region of the openings can be 44 a greater width than the width of the lower area of ​​the openings 44 exhibit, as in Fig. 4-5 shown. In other embodiments, the openings have 44 a substantially constant width (e.g., width W2). In some embodiments, the width W2 of the openings can be 44 less than or approximately the same widthW1 the underlying metallization layer 40 In some embodiments, the openings can be 44 exhibit a width:height aspect ratio (e.g. the ratio W2:T1) that is in the range of approximately 1:8 to approximately 1:15.

[0018] Fig. 6 to Fig. 10D illustrates the formation of a ground electrode 50 a PCRAM cell 60 in accordance with some embodiments. In Fig. 6 are a barrier layer 46 and a conductive material 48 in accordance with some embodiments above the IMD layer 42 and within the opening 44 isolated. The barrier layer 46 can be applied uniformly to the IMD layer 42 , on the side walls of the openings 44 and on the metallization layer 40 are deposited. In some embodiments, the barrier layer 46Formed from one or more conductive materials, such as titanium, titanium nitride, tantalum, tantalum nitride, cobalt, the like, or a combination thereof. The barrier layer 46 can be formed using one or more suitable deposition processes, such as PVD, CVD, ALD, or the like. In some embodiments, the barrier layer 46 a layer of tantalum nitride deposited using an ALD process or another suitable process. In some embodiments, the barrier layer may 46 inside the openings 44 They are formed with a thickness ranging from approximately 20 nm to approximately 80 nm. Other thicknesses are possible.

[0019] After separation of the barrier layer 46 A conductive material will be used. 48 above the barrier layer 46 secluded, the openings 44 fills. In some embodiments, the conductive material 48Made from one or more conductive materials, such as titanium, titanium nitride, tantalum, aluminum, tungsten, platinum, nickel, chromium, ruthenium, or the like. The conductive material 48 It can be deposited using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like. In some embodiments, the conductive material is 48 Titanium nitride deposited using PVD.

[0020] In Fig. 7. A planarization process is carried out to remove excess barrier layer. 46 and conductive material 48 from the IMD layer 42 to remove in accordance with some embodiments. The planarization process may, for example, include a CMP process or a mechanical grinding process. The planarization can remove the top surfaces of the IMD layer. 42 , the barrier layer 46 and the conductive material 48pave.

[0021] In Fig. 8 is an electrode etching process at the barrier layer 46 and the conductive material 48 carried out to check the ground electrodes 50 to form in accordance with some embodiments. The electrode etching process etches the barrier layer. 46 and the conductive material 48 back to the barrier layer 46 and the conductive material 48 inside the openings 44 to deepen. In some embodiments, the electrode etching process can alter the barrier layer material. 46 and the conductive material 48 above the IMD layer material 42 selectively etch. In this way, the barrier layer can be removed. 46 from the side walls of the openings 44 removed without damaging the side walls of the openings 44 to cause significant etching. An example electrode etching process. 100 is below in greater detail for Fig. 9 described. The area within the openings 44 corresponding to the removed barrier layer 46 and the conductive material 48 is in Fig. 8 as a deepened area 51 specified. After performing the electrode etching process, the remaining barrier layer forms 46 and the conductive material 48 inside the openings 44 the ground electrodes 50 the PCRAM cells 60 (see Fig. 14). For example, the electrode etching process can damage the barrier layer 46 and the conductive material 48 to a depth D1 from a top surface of the IMD layer 42 to deepen, which deepened areas 51 of depth D1 forms. After performing the electrode etching process, the remaining barrier layer forms. 46 and the conductive material 48 Ground electrodes 50with a thickness T2 above the underlying metallization layer 40 .

[0022] In some embodiments, the thickness T2 of the bottom electrodes can be 50 The thickness ranges from approximately 10 nm to approximately 30 nm. Other thicknesses are possible. In some embodiments, the thickness T2 of the bottom electrodes can be 50 between approximately 25% and approximately 50% of the thickness T1 of the IMD layer 42 this may be the case, although other proportions are possible. In some embodiments, the ratio of the thickness T2 to the depth can be D1 of the deepened area 51 (e.g., thickness T2:depth D1) should be between approximately 1:1 and approximately 1:3, although other ratios are possible. In some embodiments, the thickness T3 of the subsequently formed phase-change material layers (PCM layers) is 54 (see Fig. 12) through the thickness T2 of the bottom electrodes 50 determined. In this way, by the depth D1The relative or absolute sizes of the bottom electrodes can be controlled during the electrode etching process. 50 and the PCM layers 54 They can be controlled, and thus the operating characteristics of the PCRAM cells can be adjusted. 60 They can be controlled. For example, the heating properties of the ground electrodes can be adjusted. 50 , during operation of the PCRAM cells 60 can be controlled by controlling the thickness T2. Additionally, it shows Fig. 8 the bottom electrode 50 , to have a flat top surface, but in other embodiments the bottom electrodes can 50 exhibit a convex surface, concave surface, irregular surface or combinations thereof, as detailed below. Fig. 10A-D is described.

[0023] By the ground electrodes 50The PCM layers formed using an electrode etching process as described herein can be 54 (see Fig. 12) within the IMD layer 42 This may be limited, which can improve heat transfer efficiency and thus the work performance and power consumption of the PCRAM cells. 60 can improve this. Additionally, the electrode etching process removes at least some of the barrier layer. 46 from the side walls of the openings 44 , if the barrier layer 46 is deepened. In this way, excess barrier layer can be removed. 46 inside the openings 44 , which are not part of the ground electrodes 50 is, be removed. For example, the electrode etching process can partially or completely remove the barrier layer. 46 within the sunken area 51 remove what is on the side walls of the openings 44 within the sunken area 51can expose the excess barrier layer. 46 inside the openings 44 When removed, electrical and / or heat loss may occur due to the presence of excess barrier layer. 46 This will reduce both the electrical work output and the heat transfer efficiency of the PCRAM cells. 60 can improve it.

[0024] Fig. Figure 9 illustrates a process flow for an electrode etching process. 100 in accordance with some embodiments. The electrode etching process 100 can be used, for example, to create the barrier layer 46 and the conductive material 48 to etch, to create ground electrodes 50 to form, as in Fig. 8 shown. The electrode etching process 100 includes pre-treatment 101 , an etching process 110 and a post-treatment treatment 131In some embodiments, the etching process 110 an atomic layer etching process (ALE process) or the like. In some embodiments, the electrode re-etching process is used. 100 selectively the barrier layer 46 and the conductive material 48 above the IMD layer 42 The electrode etching process 100 This is an example electrode etching process and other process parameters, process gases or etching techniques can be used.

[0025] Before carrying out the etching process 110 can the pre-treatment 101 This is carried out to remove metal oxides from surfaces (e.g., surfaces of the in Fig. (structure shown in 7) to remove. For example, the pre-etching treatment can 101 Titanium oxide or tantalum oxide from the exposed surfaces of the barrier layer 46 or the conductive material 48 Remove the metal oxides using the pre-etching treatment. 101Removing it can result in more uniform etching during the etching process. 100 allow cleaning after pre-treatment. 101 These procedures are carried out to remove process gases, reaction products, or the like.

[0026] In some embodiments, the pre-etching treatment includes 101 A plasma process, such as plasma etching. The plasma process can involve flowing one or more process gases into a process chamber and then igniting one or more process gases to create a plasma. For example, pre-etching treatment 101a plasma process using one or more process gases, such as CH4, Cl2, Ar, the like, other gases, or combinations thereof. For example, a mixture of CH4, Cl2, and Ar may be used, containing in some embodiments between approximately 3 sccm and approximately 10 sccm of CH4, between approximately 30 sccm and approximately 100 sccm of Cl2, and / or between approximately 50 sccm and approximately 100 sccm of Ar. Other mixtures are possible. The plasma process may be carried out using a plasma source power in the range of approximately 150 W to approximately 400 W and a bias power in the range of approximately 30 W to approximately 60 W. In some embodiments, no bias power is applied. The pre-etching treatment 101 This can be carried out using a pressure in the range of approximately 3 mTorr to approximately 10 mTorr, with a process gas flow rate in the range of approximately 100 sccm to approximately 250 sccm. Other process gases or process parameters are possible.

[0027] In some embodiments, the etching process includes 110 a process gas penetration 111 , followed by one or more etch cycles 120 For example, during process gas penetration 111 The structure is exposed to a process gas, such as Cl₂ or other gases. In some embodiments, the process gas can flow at a rate in the range of approximately 100 sccm to approximately 300 sccm, although other flow rates are possible. In some embodiments, during the process gas penetration... 111 The process gas does not ignite into a plasma. A purge can be performed after the etching process. 110 These procedures are carried out to remove process gases, reaction products, or the like.

[0028] After process gas penetration 111 will one or more etching cycles be performed? 120 performed. In some embodiments, each etching cycle includes 120a primary etching step 121 and an over-etching step 122 The primary etching step 121 and the etching step 122 Each step can involve the flow of one or more process gases into a process chamber and then the ignition of one or more process gases into a plasma. The primary etching step 121 Plasma etching can involve the use of one or more process gases, such as Cl₂, BCl₃, Ar, He, the like, other gases, or combinations thereof. For example, a mixture of Cl₂, BCl₃, Ar, and He can be used, which in some embodiments may contain between approximately 30% and approximately 70% Cl₂, between approximately 20% and approximately 60% BCl₃, between approximately 20% and approximately 50% Ar, and / or between approximately 20% and approximately 50% He. Other mixtures are possible. The primary etching step 121This process can be performed using a plasma source power in the range of approximately 250 W to approximately 400 W and can be performed using a bias power in the range of approximately 0 W to approximately 30 W. In some embodiments, the bias power can be used with an on-off load cycle between approximately 20% and approximately 80% or at a frequency in the range of approximately 100 Hz to approximately 1000 Hz. The primary etching step 121 This process can be carried out using a pressure in the range of approximately 3 mTorr to approximately 10 mTorr, with a process gas flow rate in the range of approximately 300 sccm to approximately 1000 sccm. In some embodiments, the primary etching step can be 121 The process can be carried out for a duration ranging from approximately 100 seconds to approximately 500 seconds. Other process gases or process parameters are possible.

[0029] The etching step 122Plasma etching can involve the use of one or more process gases, such as Cl₂, BCl₃, Ar, He, the like, other gases, or combinations thereof. For example, a mixture of Cl₂, BCl₃, Ar, and He can be used, containing in some embodiments between approximately 30% and approximately 70% Cl₂, between approximately 20% and approximately 60% BCl₃, between approximately 20% and approximately 50% Ar, and / or between approximately 20% and approximately 50% He. Other mixtures are possible. In some embodiments, the mixture of process gases used in the over-etching step 122 is used, the same mixture of process gases used in the primary etching step 121 is used. The etching step 122The process can be performed using a plasma source power in the range of approximately 150 W to approximately 250 W and can be performed using a bias power in the range of approximately 0 W to approximately 20 W. In some embodiments, the bias power can be used with an on-off load cycle between approximately 20% and approximately 50% or at a frequency in the range of approximately 100 Hz to approximately 1000 Hz. In some embodiments, the over-etching step 122 similar to the primary etching step 121 , except that the bias power required for the over-etching step 122 is used, is lower than the bias power used for the primary etching step 121 is used. For example, the bias power of the over-etching step can be 122 between approximately 10% and approximately 30% of the bias power applied in the primary etching step 121is used, although other percentages are possible. The over-etching step 122 This can be carried out using a pressure in the range of approximately 5 mTorr to approximately 15 mTorr, with a process gas flow rate in the range of approximately 300 sccm to approximately 1000 sccm. In some embodiments, the over-etching step can be 122 The process can be carried out for a duration ranging from approximately 100 seconds to approximately 300 seconds. Other process gases or process parameters are possible.

[0030] The electrode etching process described herein 100 This can allow a higher degree of control over the etching, similar to an ALE process. In some embodiments, each etch cycle etches. 120 a distance in the range of approximately 1 nm to approximately 1.5 nm, although other etching rates are possible. In some embodiments, one etching cycle removes 120 approximately a monolayer of the barrier layer 46 and / or the conductive material 48The etching cycle 120 This process can be repeated any number of times until all material is removed. In some embodiments, the etching process includes... 110 , the etching cycle 120 to be performed between about 10 and about 30 times, although the etching cycle 120 The electrode etching process can be performed with varying frequency in other embodiments. In this way, the electrode etching process can be... 100 improved control over the thickness T2 of the ground electrodes 50 and improved control over the thickness T3 of the PCM layers 54 allow (see Fig. 12).

[0031] With regard to Fig. 10A-D are ground electrodes 50 The upper surfaces are shown to have various shapes in accordance with some embodiments. In some embodiments, the process gases can be introduced during the etching cycle. 120 to control the relative etch rates of the barrier layer 46and the conductive material 48 control the shape of the top surfaces of the bottom electrodes 50 to control. In some embodiments, where the barrier layer 46 Tantalum nitride is the conductive material 48 Titanium nitride controls the flow rate of Cl2 during the etching cycle. 120 the etch rate of the barrier layer 46 and controlling the flow rate of BCl3 during the etching cycle 120 controls the etching rate of the conductive material 48 .

[0032] In relation to Fig. 10A is an example ground electrode 50 shown, for which the top surfaces of the barrier layer 46 and the conductive material 48 are approximately flat, similar to the ground electrode 50 , which in Fig. Figure 8 is shown. In some embodiments, the bottom electrodes can be 50 to be formed, approximately flat surfaces of barrier layer 46and conductive material 48 to demonstrate by the etching process 110 is controlled in such a way that the etch rate of the barrier layer is adjusted. 46 approximately the same as the etch rate of the conductive material 48 In some cases, the etching rate can be controlled by adjusting the flow rate of a suitable process gas during the etching process. 110 is controlled. As an example, in some embodiments a ratio of the Cl2 flow rate to the BCL3 flow rate of approximately 1:6 can control the barrier layer. 46 and the conductive material 48 etching at similar rates. As an example, Cl₂ can be flowed at a rate of about 30 sccm and BCl₃ at a rate of about 180 sccm. This is an illustrative example and other ratios or flow rates can be used. In some cases, images of the barrier layer can be used. 46 and the conductive material 48Improved diffusion blockage through the barrier layer with approximately flat top surfaces 46 allow.

[0033] In relation to Fig. 10B is an example ground electrode 50 shown, for which the top surface of the conductive material 48 is concave, in accordance with some embodiments. In some embodiments, the conductive material can 48 be formed to have a concave surface by the conductive material 48 during the etching process 110 at a higher rate than the barrier layer 46 is etched. For example, in some cases a ratio of approximately 1:1 to approximately 1:2 for the ratio of the Cl2 flux rate to the BCl3 flux rate can etch the conductive material. 48 at a higher rate than the barrier layer 46Etching. This is an illustrative example, and other ratios or flow rates can be used. In some cases, forming ground electrodes may be necessary. 50 , the conductive material 48 with a concave top surface (e.g., which extends below the top surface of the barrier material) 46 extends) exhibit improved diffusion blocking through the barrier layer 46 allow.

[0034] Fig. 10C shows an example soil electrode 50 , for which the top surface of the conductive material 48 is convex and extends over the top surface of the barrier layer 46 protrudes, in accordance with some embodiments. Fig. Figure 10 shows an example soil electrode 50 , for which the top surface of the barrier layer 46 is concave and extends below the top surface of the conductive material 48extends, in accordance with some embodiments. In some embodiments, a convex conductive material may be used. 48 and / or a concave barrier layer 46 are formed by the barrier layer 46 at a higher rate than the conductive material 48 during the etching process 110 is etched. For example, in some cases a ratio of approximately 1:1 to approximately 2:1 for the ratio of the Cl2 flux rate to the BCl3 flux rate can etch the barrier layer. 46 at a higher rate than the conductive material 48 Etching. This is an illustrative example and other ratios or flow rates can be used.

[0035] Back to Fig. 9. After the etching process 110 Once completed, a follow-up treatment may be necessary. 131 be carried out. In some embodiments, the post-etching treatment is used. 131a process gas, such as N2H2 or the like. The post-etching treatment 131 In some embodiments, it may include a plasma process. The plasma process can be carried out using a plasma source power in the range of approximately 200 W to approximately 400 W. The post-etching treatment 131 This process can be carried out using a pressure ranging from approximately 20 mTorr to approximately 80 mTorr, a process temperature ranging from approximately 60°C to approximately 120°C, or a process gas flow rate ranging from approximately 200 sccm to approximately 1000 sccm. Other process gases or process parameters are possible. Rinsing can be performed after the post-etching treatment. 131 These procedures are carried out to remove process gases, reaction products, or the like.

[0036] The in Fig. 9 Electrode etching process shown 100This is an example electrode etching process and may differ in other embodiments. Some described steps and processes may be omitted or repeated, or other steps or processes than those described may be included. For example, in other embodiments, an etching cycle may be omitted. 120 only one step (e.g., only the primary etching step) 121 ) comprise or may comprise more than three steps, any of which may be similar to those used for the electrode etching process 100 The described steps may differ from or be different from the steps described. Other variations of the electrode etching process 100 are possible.

[0037] In Fig. 11 is a phase change material (PCM) 53 inside the openings 44 formed and covers the ground electrodes 50 in accordance with some embodiments. As in Fig. As shown in 11, the PCM can 53to be separated in order to access the sunken areas 51 to fill and can also cover surfaces of the IMD layer 42 cover. In other embodiments, the PCM can 53 to be separated in order to access the sunken areas 51 to partially replenish. In some embodiments, the PCM 53 A chalcogenide material, such as GeSbTe (GST) or GeSbTeX, where X is a material such as Ag, Sn, In, Si, N, or the like. Other materials are possible. The PCM 53 can be formed using a suitable deposition process, such as PVD, CVD, plasma-enhanced CVD (PECVD), ALD or the like.

[0038] In Fig. 12. A PCM re-etching process was carried out to remove the PCM 53 to etch and PCM layers 54 to form in accordance with some embodiments. The PCM etching process removes PCM. 53 from the top surface of the IMD layer 42 and the remaining PCM53 forms the PCM layers 54 the PCRAM cells 60 (see Fig. 14). The PCM etching process can remove PCM layers 54 with a top surface approximately flush with the top surface of the IMD layer 42 form, or the top surfaces of the PCM layers 54 can be from the top surface of the IMD layer 42 be explored in greater depth, as in Fig. Figure 12 shows that in some embodiments the top surface of the PCM layer can be 54 from the top surface of the IMD layer 42 to a depth D2 The layers are deepened to a depth ranging from approximately 40 nm to approximately 60 nm. Other depths are possible. The PCM layers 54 from the top surface of the IMD layer 42 to deepen, allows the PCM layers 54 through the IMD layer 42to be more confined, which can improve heat transfer efficiency and the operation of the PCRAM cells 60 can improve this. Therefore, a greater depth can... D2 in increased confinement of the PCM layers 54 result. In some embodiments, a planarization process, such as a CMP process, can be performed before the PCM etching process. The PCM layers 54 can be formed to have a flat top surface, a concave top surface, a convex top surface, an irregular top surface, or the like.

[0039] In some embodiments, the PCM etching process includes a plasma process, such as plasma etching. The plasma etching process may involve feeding one or more process gases into a process chamber and then igniting the one or more process gases into a plasma. For example, the PCM etching process may include a plasma process using one or more process gases, such as HBr, Ar, He, the like, other gases, or combinations thereof. For example, a mixture of HBr, Ar, and He may be used, which in some embodiments contains between approximately 20% and approximately 40% HBr, between approximately 30% and approximately 50% Ar, and / or between approximately 10% and approximately 20% He. Other mixtures are possible. The plasma process may be carried out using a plasma source power in the range of approximately 100 W to approximately 400 W or using a bias power in the range of approximately 100 W to approximately 200 W.In some embodiments, no preload power is applied. The PCM etching process can be carried out using a pressure in the range of approximately 3 mTorr to approximately 10 mTorr, a process temperature in the range of approximately 40°C to approximately 70°C, or a process gas flow rate in the range of approximately 100 sccm to approximately 300 sccm. Other process gases or process parameters are possible.

[0040] In some cases, the formation of PCM layers can occur. 54 inside the openings 44 as described herein, an improved sidewall quality of the PCM layers 54 allow. For example, in some cases, forming a PCM layer using an etching process (e.g., as part of photolithographic structuring) can cause damage to the PCM layer during the etching process. By damaging the PCM layers 54 without etching the sidewalls of the PCM layers 54When these are formed, etching damage can occur on the side walls of the PCM layers. 54 This can be avoided. Therefore, the PCM layers formed as described herein can be avoided. 54 exhibit improved sidewall quality, which eliminates defects within the PCM layers 54 can reduce electrical or heat loss of the PCRAM cells 60 can reduce and improve the power efficiency of the PCRAM cells 60 while operations can improve.

[0041] As in Fig. As shown in 12, the PCM etching process removes the PCM 53 from the top surface of the IMD layer 42 and forms a PCM layer 54 , which has a substantially uniform thickness. In some embodiments, the PCM layers can 54The thickness T3 is in the range of approximately 10 nm to approximately 30 nm, although other thicknesses are possible. In some embodiments, the thickness T3 can be between approximately 30% and approximately 70% of the thickness T1 of the IMD layer. 42 The thickness T3 can be between approximately 30% and approximately 100% of the depth. D1 of the deepened area 51 In some embodiments, the ratio of the thickness T2 of the bottom electrode is 50 to the thickness T3 of the PCM layers 54 Between approximately 1:1 and approximately 1:3. Other distances, percentages, or ratios are possible. In this way, the absolute or relative thicknesses of the ground electrode can be determined. 50 and PCM layers 54 They can be controlled to achieve certain properties, such as size, resistance, power consumption, thermal efficiency, or the like.

[0042] In Fig. 13 is, in accordance with some embodiments, a top electrode material 55above the IMD layer 42 isolated and covers the PCM layers 54 off. The top electrode material 55 can penetrate beneath a top surface of the IMD layer 42 extend to the PCM layers 54 as in Fig. 13 shown to contact. In some embodiments, the top electrode material 55 a barrier layer and a conductive material above the barrier layer, which are not individually illustrated in the figures. The barrier layer can be similar to that used for Fig. 6 described barrier layer 46 and can be formed in a similar way. For example, the barrier layer of the top electrode material can be 55 Tantalum nitride uniformly on the IMD layer 42 and on the PCM layers 54 The deposited material is included, although other materials are possible. After deposition of the barrier layer of the top electrode material. 55A conductive material is deposited over the barrier layer. The conductive material layer can be similar to that used for... Fig. 6 described conductive material 48 and can be formed in a similar way. For example, the conductive material of the top electrode material can be 55 Titanium nitride is deposited on the barrier layer, although other materials are possible. In some embodiments, a planarization process (e.g., a CMP or grinding process) is performed on the top electrode material after deposition. In some embodiments, the top electrode material can be 55 with a thickness T4 on the top surface of the IMD layer 42 They are formed in the range of about 20 nm to about 50 nm, although other thicknesses are possible.

[0043] In Fig. 14 is the top electrode material 55 structured to accommodate top electrodes56 the PCRAM cells 60 to be formed in accordance with some embodiments. The top electrode material 55 It can be structured using acceptable photolithographic and etching techniques. For example, a mask layer (not shown), such as a hard mask layer, or a photoresist layer (e.g., a single-layer photoresist, a three-layer photoresist, or the like) can be applied over the top electrode material. 55 are formed and structured. The top electrode material 55 It can then be etched using the structured mask layer as an etching mask, with the remaining sections of the top electrode material remaining. 55 the top electrodes 56 form. The top electrode material 55 It can be etched using an anisotropic etching process, such as a suitable dry etching process. After formation of the top electrodes 56Remaining sections of the mask layer can then be removed using, for example, an ashing process, an etching process, or another suitable process. In this way, a PCRAM cell can be... 60 are formed, which form a ground electrode 50 , a PCM layer 54 and a top electrode 56 exhibits. In some embodiments, the sides of the PCM layer are 54 from the IMD layer 42 surrounded and the bottom and top of the PCM layer 54 are from the ground electrode 50 or the top electrode 56 covered.

[0044] As in Fig. As shown in Figure 14, the top electrodes can be used. 56 across the top surface of the IMD layer 42 extend and exhibit a thickness T4 above the top surface of the IMD layer 42in some embodiments, sections of the top electrodes may 56 below the top surface of the IMD layer 42 extend to the PCM layer 54 to contact. Therefore, sections of the top electrodes can 56 above the PCM layer 54 a greater thickness than the thickness T4 exhibit. In some embodiments, the top electrodes can 56 a width W3 exhibiting a range of approximately 10 nm to approximately 30 nm. The width W3 The upper electrode can be larger than, approximately the same as, or smaller than the width. W1 the underlying metallization layer 40 be.

[0045] In Fig. Figure 15 is a cross-sectional view of the component area. 12 of a wafer in accordance with some embodiments shown. The in Fig. The cross-sectional view shown in 15 is similar to those in Fig. 1-4 shown, except that PCRAM cells 60 as for Fig. 5-14 were described. As in Fig. Shown in 15 are the PCRAM cells. 60 with the metallization layer(s) 40 connected and can also be used with access transistors 22 or other components located in the semiconductor substrate 20 are educated.

[0046] In Fig. 16 is, in accordance with some embodiments, an IMD layer. 62 above the IMD layer 42 and top electrodes 56 formed, and a metallization layer 64 is in the IMD layer 62 formed. In some embodiments, some or all of the metallization layer may be formed. 64 are used as bit lines (BL) connected to rows of PCRAM cells 60 in a PCRAM array 70 are connected, which is explained in greater detail below. Fig. 17 is described. In some embodiments, an etch stop layer (not illustrated in the figure) is placed over the IMD layer. 42 and the top electrodes 56 before the formation of the IMD layer 62 isolated. The IMD layer 62 can be made from dielectric material similar to that previously used for the IMD layer 42 , the dielectric layers 36 or the IMD layer 33 The described layer can be formed and can be formed in a similar way. The metallization layer 64 It can be formed using a Damascus process, such as a single Damascus process, a double Damascus process, or the like. For example, the metallization layer can be 64 are formed by entering the IMD layer 63Etching is used to create via holes (for vias) and trenches (for metal conductors). The via holes and trenches can be filled with a conductive material, and then a planarization process such as a CMP process or a grinding process can be performed to remove excess conductive material. The metallization layer 64 In some embodiments, it can be used in a similar way to the metal pipes. 34 or the metallization layer 40 can be formed, or can be formed using another suitable technique. It is welcomed that although a metallization layer 64 (featuring metal conductors and underlying vias) in Fig. Figure 16 illustrates that there are additional metallization layers in additional IMD layers above the IMD layer. 62This can be achieved through subsequent processes. The layers above the metallization layer are then further processed. 64 and IMD layer 62 lying features formed to facilitate wafer formation 10 and the component-This 12 To complete the process, a singulation process can then be carried out to separate the component areas. 12 from wafer 10 into the individual building element-This 12 to separate.

[0047] Fig. Figure 17 schematically illustrates a perspective view of the PCRAM array. 70 , the PCRAM cells 60 as an array, in accordance with some embodiments. In the embodiment shown, word lines (WL) are electrically connected to the ground electrodes. 50 respective columns of PCRAM cells 60 in the PCRAM array 70 connected. Each column of the PCRAM array 70 has an associated word line and the PCRAM cells 60Within a column, the words are linked to the word order for that column. These word orders can be, for example, metal pipes. 34 be those connected to the access transistors 22 are connected. Bit lines (BL) are connected to the top electrodes. 56 respective rows of PCRAM cells 60 in the PCRAM array 70 connected. Each row of the PCRAM array 70 has an associated bit line and the PCRAM cells 60 The bit lines in a row are connected to the bit line for that row. The bit lines can be, for example, metal traces and vias in the metallization layer. 64 Some characteristics are not in Fig. 17 showed how the access transistors 22 , Metallization layer 40 and the like. Each PCRAM cell 60 of the PCRAM array 70can be selected by appropriately combining word lines and bit lines. For example, a specific PCRAM cell can 60 can be selected (e.g., for read and write operations) by accessing the individual word line associated with that PCRAM cell. 60 is connected, and also accesses the individual bit line associated with this PCRAM cell. 60 is connected. Other configurations of bit lines, word lines, or PCRAM cells are possible.

[0048] The resistance of the PCM layer 54 each PCRAM cell 60 It is programmable and can switch between a high-resistance state and a low-resistance state, which can correspond to the two states of a binary code. The PCRAM cell 60 The phase of the PCM layer can be changed between the high-resistance state and the low-resistance state. 54(can be changed) by heating the PCM layer 54 through the ground electrode 50 and / or the top electrode 56 It is controlled when current flows through the PCRAM cell. 60 flows. In this way, a value can be transferred to a PCRAM cell. 60 written by the resistance of its PCM layer 54 using their corresponding access transistor 22 is programmed, and a value can be stored in a PCRAM cell. 60 can be read by measuring the resistance of its PCM layer 54 with their corresponding access transistor 22 is measured. The PCRAM cells described herein 60 exhibit a completely enclosed PCM layer 54 with side walls that are essentially free of the barrier layer 46 are, which improve control over and efficiency of heating or power consumption during programming of the PCRAM cell. 60can reduce it.

[0049] Implementation methods can offer advantages. Using the techniques described here can create phase-change RAM cells (PCRAM cells) in which the sidewalls of the phase-change material layer (PCM layer) are completely confined within a dielectric layer. For example, a PCM layer can be formed that does not extend over a top surface of the dielectric layer. This can result in improved heat confinement and heat transfer efficiency, allowing the PCRAM cells to be programmed using a lower voltage and / or current. For example, by forming a PCM layer confined within a dielectric layer, heating of the PCM layer during programming can be better confined to the center of the PCM layer.Therefore, the phase change of the PCM layer can propagate from its center, which can reduce edge effects due to the bottom and / or top electrode that can decrease efficiency. Additionally, the techniques described herein allow the removal of the electrode barrier material prior to PCM layer formation. The presence of barrier material on or near the PCM layer can cause heat or electrical loss, and therefore, removing the barrier material can reduce heat or electrical loss within a PCRAM cell. Accordingly, the techniques described herein allow for improved energy efficiency of a PCRAM array. Furthermore, the techniques described herein form the PCRAM cells without etching the sidewalls of the PCM layer, which can reduce damage to the PCM layer due to etching or defects formed as a result of etching.

[0050] In some embodiments, a method comprises forming a dielectric layer over a substrate, wherein the dielectric layer has a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, wherein the bottom electrode has a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is flush with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer. In one embodiment, side walls of the PCM layer are free of the barrier layer. In another embodiment, forming the bottom electrode comprises depositing the barrier layer in the opening; depositing a conductive material on the barrier layer; and etching the barrier layer and the conductive material, wherein the etching exposes side walls of the opening.In one embodiment, after etching the barrier layer and the conductive material, the top surface of the conductive material is convex. In another embodiment, after etching the barrier layer and the conductive material, the top surface of the barrier layer is flat with the top surface of the conductive material. In one embodiment, forming the PCM layer comprises depositing a phase-change material over the bottom electrode and the dielectric layer; and etching the phase-change material to remove it from the top surface of the dielectric layer. In one embodiment, the bottom electrode has a thickness between 25% and 50% of the thickness of the dielectric layer. In another embodiment, the PCM layer has a thickness between 30% and 70% of the thickness of the dielectric layer.

[0051] In some embodiments, a process comprises depositing an intermediate metal layer (IMD layer) over a first conductive feature; forming an opening in the IMD layer exposing the first conductive material; forming a second conductive feature in the opening; performing a first back-etching process to deepen the second conductive feature in the opening; depositing a phase-change material (PCM) in the opening and over the second conductive feature; performing a second back-etching process to remove top portions of the PCM; and depositing a conductive material on the PCM. In one embodiment, forming the second conductive feature comprises depositing a layer of tantalum nitride and depositing a layer of titanium nitride on top of the tantalum nitride layer. In one embodiment, the first back-etching process is an atomic layer etching (ALE) process.In one embodiment, the first etching process comprises feeding the first process gases into a process chamber and performing a plurality of etching cycles, each cycle comprising feeding second process gases into the process chamber; igniting the second process gases into a plasma while a first bias is applied; and igniting the second process gases into a plasma while a second bias is applied that is lower than the first bias. In one embodiment, the second process gases include Cl₂, BCL₃, Ar, and / or He. In one embodiment, prior to performing the plurality of etching cycles, the first etching process comprises feeding third process gases into the process chamber and igniting the third process gases into a plasma. In one embodiment, the second etching process comprises feeding fourth process gases into a process chamber and igniting the fourth process gases into a plasma.

[0052] In some embodiments, a device comprises a metallization layer over a semiconductor substrate; an intermetal dielectric (IMD) layer over the metallization layer; and a phase-change direct-access memory (PCRAM) cell having a bottom electrode in the IMD layer, the bottom electrode being electrically connected to the metallization layer; a phase-change material (PCM) layer on the bottom electrode and within the IMD layer, the PCM layer being surrounded by the IMD layer and the top surface of the IMD layer being free of the PCM layer; and a top electrode on the PCM layer and the top surface of the IMD layer. In one embodiment, the top electrode extends below the top surface of the IMD layer to contact the PCM layer. In another embodiment, the side walls of the PCM layer physically contact the IMD layer.In one embodiment, the PCM layer contains GeSbTe (GST). In another embodiment, the PCM layer has a uniform thickness.

[0053] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 016337

[0001]

Claims

[1] Procedure, encompassing: Forming a dielectric layer over a substrate, wherein the dielectric layer has a top surface; Etching an opening in the dielectric layer; Forming a bottom electrode within the opening, wherein the bottom electrode has a barrier layer; Forming a phase-change material layer (PCM layer) inside the aperture and on the bottom electrode, wherein a top surface of the PCM layer is flush with or below the top surface of the dielectric layer; and Forming a top electrode on the PCM layer. [2] Method according to claim 1, wherein side walls of the PCM layer are free from the barrier layer. [3] Method according to claim 1 or 2, wherein forming the ground electrode comprises: Deposition of the barrier layer in the opening; Deposition of a conductive material on the barrier layer; and Etching of the barrier layer and the conductive material, whereby the etching exposes the side walls of the opening. [4] Method according to claim 3, wherein after etching the barrier layer and the conductive material the top surface of the conductive material is convex. [5] Method according to claim 3 or 4, wherein after etching the barrier layer and the conductive material the top surface of the barrier layer is flat with the top surface of the conductive material. [6] Method according to any one of the preceding claims, comprising forming the PCM layer: Deposition of a phase-change material over the bottom electrode and the dielectric layer; and Etching of the phase-change material to remove the phase-change material from the top surface of the dielectric layer. [7] Method according to any of the preceding claims, wherein the bottom electrode has a thickness that is between 25% and 50% of the thickness of the dielectric layer. [8] Method according to any of the preceding claims, wherein the PCM layer has a thickness that is between 30% and 70% of the thickness of the dielectric layer. [9] Procedures, comprehensive: Deposition of an intermediate metal layer (IMD layer) over a first conductive element; Forming an opening in the IMD layer that exposes the first conductive element; Forming a second conductive element in the opening; Performing an initial etching process to deepen the second conductive element in the opening; Deposition of a phase change material (PCM) in the opening and above the second conductive element; Performing a second etching process to remove upper sections of the PCM; and Deposition of a conductive material on the PCM. [10] Method according to claim 9, wherein forming the second conductive element comprises depositing a layer of tantalum nitride and depositing a layer of titanium nitride on the layer of tantalum nitride. [11] Method according to claim 9 or 10, wherein the first etching process is an atomic layer etching process (ALE process). [12] Method according to any one of claims 9 to 11, wherein the first etching process comprises: Introducing the first process gases into a process chamber; and Performing a plurality of etching cycles, each etching cycle comprising: Introducing a second process gas into the process chamber; Igniting the second process gases into a plasma while a first bias voltage is used; and Igniting the second process gases into a plasma while using a second bias voltage that is lower than the first bias voltage. [13] Method according to claim 12, wherein the second process gases contain Cl2, BCl3, Ar and He. [14] Method according to claim 12 or 13, wherein the first etching process further comprises: Before carrying out the majority of etching cycles, introduce third process gases into the process chamber; and Ignition of the third process gases into a plasma. [15] Method according to any one of claims 9 to 14, wherein the second etching process comprises: Introducing fourth process gases into a process chamber; and Ignition of the fourth process gases into a plasma. [16] Device comprising: a metallization layer over a semiconductor substrate; an intermetal dielectric layer (IMD layer) over the metallization layer; and a phase-change direct access memory cell (PCRAM cell), comprising: a bottom electrode in the IMD layer, wherein the bottom electrode is electrically connected to the metallization layer; a phase-change material layer (PCM layer) on the bottom electrode and within the IMD layer, wherein the PCM layer is surrounded by the IMD layer and wherein the top surface of the IMD layer is free of the PCM layer; and a top electrode on the PCM layer and the top surface of the IMD layer. [17] Device according to claim 16, wherein the top electrode extends below the top surface of the IMD layer to contact the PCM layer. [18] Device according to claim 16 or 17, wherein the side walls of the PCM layer physically contact the IMD layer. [19] Device according to any one of claims 16 to 18, wherein the PCM layer contains GeSbTe (GST). [20] Device according to any one of claims 16 to 19, wherein the PCM layer has a uniform thickness.

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