semiconductor device

Abstract

Semiconductor device comprising: a semiconductor layer (20) in which a drift layer (2) of a first conductivity type is formed; a trench-type switching element in which a gate electrode (7a) is embedded in a first trench (5a) formed in the semiconductor layer (20) so as to reach the drift layer (2); a trench-type current measuring element in which a gate electrode (7b) is embedded in a second trench (5b) formed in the semiconductor layer (20) so as to reach the drift layer (2); a third trench (5c) configured to be formed in the semiconductor layer (20) at a boundary portion between an active region (101) where the switching element is formed and a current measuring region (102) where the current measuring element is formed, and to reach the drift layer (2); a first protective layer (8a) of a second conductivity type formed below the first trench (5a) in the drift layer (2); a second protective layer (8b) of the second conductivity type formed below the second trench (5b) in the drift layer (2); and a third protective layer (8c) of the second conductivity type formed below the third trench (5c) in the drift layer (2); wherein the third protective layer (8c) has a divided partial region (15) which is divided in a first direction from the active region (101) to the current measuring region (102), and wherein in the third trench (5c) the semiconductor layer (16) having a mesa shape is formed on the divided portion (15) of the third protective layer (8c).

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to a semiconductor device, and more particularly to a semiconductor device including a trench-type switching element and a trench-type current sensing element.Description of Background ArtIn electronic power devices, insulated gate semiconductor devices such as IGBTs (insulated gate bipolar transistors) and MOSFETs (metal oxide semiconductor field effect transistors) are widely used as switching elements for controlling power supply for loads such as motors. As one of vertical MOSFETs for power control, there is a trench MOSFET having a structure in which a gate electrode is embedded in a semiconductor layer.The MOSFET for power control operates to repeat an ON state in which a large current and a low voltage occur and an OFF state in which a small current and a high voltage occur. The conduction loss, which is a loss when the MOSFET is in the ON state, is determined by the drain-source current and the ON resistance of the MOSFET. Since a trench MOSFET can have a higher channel width density than a planar MOSFET, the ON resistance per unit area can be reduced. Further, when the trench MOSFET is formed using a hexagonal system material such as SiC, it is expected that a considerable reduction in ON resistance is obtained because the current path coincides with an a-axis direction with high carrier mobility.However, the trench MOSFET has a problem that an electric field tends to concentrate at the bottom of the trench, and the concentration of an electric field tends to cause breakage of a gate oxide film. Therefore, it is important for the trench MOSFET to suppress the concentration of an electric field on the bottom of the trench. For example, JP 6 099 749 B2 discloses a technique in which a protective layer having a conductivity type opposite to that of a drift layer is provided at the bottom of a trench of a MOSFET. By providing the protective layer at the bottom of the trench, the depletion layer can be extended from the protective layer to the drift layer, and the electric field applied to the bottom of the trench can be reduced.A general power control MOSFET includes a plurality of MOSFET cells arranged in parallel, which are unit elements of a MOSFET, an active region that conducts current in the ON state, and an outer peripheral region provided so as to surround the active region and in which a guard ring, a metal wire, and the like are arranged. The electric field distribution becomes singular at the boundary portion between the active region and the outer peripheral region, and depending on the shape of the outer peripheral region, the singular electric field distribution causes a reduction in the withstand voltage of the MOSFET. JP 6 099 749 B2 also discloses a technique in which a trench and a protection layer are also provided in an outer peripheral region as in an active region, thereby flattening the electric field distribution of the entire MOSFET and improving the withstand voltage of the MOSFET.Further, when a load driven by the MOSFET is in a short-circuit state for some reason, the MOSFET may be immediately in a state of a large current and a high voltage. In this state, there is a possibility that the MOSFET is broken by heat generated by a large power. As a method for preventing the breakage of the MOSFET, there is a method for monitoring a current flowing through the MOSFET and turning off the MOSFET when an overcurrent occurs. As a technique for monitoring a current flowing through a MOSFET, a technique for mounting an element called a current sensing element on the MOSFET is well known.The current sensing element is obtained by electrically separating some MOSFET cells from the active region, and contributes to detection of an overcurrent by flowing a part of the current flowing through the MOSFET to the overcurrent detection circuit. Hereinafter, a MOSFET cell used as the current sensing element is referred to as a "current sensing cell", and a region where the current sensing cell is disposed is referred to as a "current sensing region". Unless otherwise specified, the "MOSFET cell" refers to a MOSFET cell in the active region, not a current sensing cell.Usually, the current sensing region is provided in a region surrounded by the outer peripheral region together with the active region. In addition, the current sensing cell and the MOSFET cell share a drain electrode; however, a source electrode of the current sensing cell is isolated from a source electrode of the MOSFET cell. The reason is that when the source electrode of the current sensing cell and the source electrode of the MOSFET cell are electrically connected, a part of the current flowing through the active region flows into the current sensing region and becomes noise and the overcurrent cannot be correctly detected.When a current sensing element is mounted on a semiconductor device at the boundary portion between the current sensing region where the current sensing cells are arranged and the active region where the MOSFET cells are arranged, the electric field distribution tends to be singular as at the boundary portion between the active region and the outer peripheral region, and such singular electric field distribution may be a cause of a reduction in withstand voltage of the MOSFET.Further semiconductor devices are known from US 2019 / 0 189 756 A1 and JP 2018-121 020 A.SUMMARYAn object of the present invention is to improve the withstand voltage of a semiconductor device including a trench-type switching element and a trench-type current sensing element.This object is achieved by the features of the independent claims. The dependent claims have advantageous embodiments of the invention in their content.A semiconductor device according to partial aspects of the present invention includes a semiconductor layer in which a drift layer of a first conductivity type is formed, a trench-type switching element in which a gate electrode is embedded in a first trench formed in the semiconductor layer to reach the drift layer, and a trench-type current sensing element in which a gate electrode is embedded in a second trench formed in the semiconductor layer to reach the drift layer. A third trench reaching the drift layer is formed in the semiconductor layer at the boundary portion between the active region where the switching element is formed and the current sensing region where the current sensing element is formed. A first protection layer of a second conductivity type is formed below the first trench in the drift layer. A second protection layer of the second conductivity type is formed below the second trench in the drift layer. A third protection layer of the second conductivity type is formed below the third trench in the drift layer. The third protection layer has a divided portion divided in a first direction from the active region to the current sensing region.In the semiconductor device according to partial aspects of the present invention, the first protection layer is provided below the first trench and the second protection layer is provided below the second trench, and thus electric field concentration at the bottom of the first and second trenches can be suppressed. In addition, the third trench and the third protection layer are provided at the boundary portion between the active region and the current sensing region, and thus it can be suppressed that the electric field distribution becomes singular at the boundary portion between the active region and the current sensing region. Further, since the third protection layer includes the divided portion, a short circuit between the active region and the current sensing region is prevented via the third protection layer. Therefore, concentration of an electric field is suppressed due to the provision of the current measurement region, and it is possible to contribute to improvement in withstand voltage of the semiconductor device.These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first preferred embodiment; FIGS. 2 and 3 are views for explaining a method of forming a protection layer in manufacturing the semiconductor device according to the first preferred embodiment; FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second preferred embodiment; FIGS. 5 to 12 are views for explaining a method of forming a protection layer in manufacturing the semiconductor device according to the second preferred embodiment; FIG. 13 is a cross-sectional view illustrating a configuration of a semiconductor device according to a third preferred embodiment; FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device according to a fourth preferred embodiment; FIG. 15 is a plan view illustrating a configuration of a semiconductor device according to a fifth preferred embodiment; and FIGS. 16 and 17 are cross-sectional views illustrating a configuration of a semiconductor device according to the fifth preferred embodiment.DESCRIPTION OF THE PREFERRED EMBODIMENTSPreferred embodiments of the present invention will be described below. In the following description, the first conductivity type is an N type and the second conductivity type is a P type. Conversely, the first conductivity type may be a P type and the second conductivity type may be an N type. Further, in each preferred embodiment, the switching element included in the semiconductor device is a MOSFET; it is sufficient if the switching element is a trench-type element, and the switching element may be, for example, an IGBT or the like.< Preferred Embodiment>FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to the first preferred embodiment. As illustrated in FIG. 1, the semiconductor device according to the first preferred embodiment is formed using a semiconductor substrate 1 of a first conductivity type. In the present preferred embodiment, as the semiconductor substrate 1, a silicon carbide (SiC) semiconductor substrate is used. Switching elements such as MOSFETs and IGBTs formed using wide band gap semiconductors such as silicon carbide (SiC) are attracting attention as next-generation switching elements, and the switching elements are expected to be used for industrial fields that cope with a high voltage of about 1 kV or higher. Wide band gap semiconductors include, in addition to SiC, gallium nitride (GaN)-based materials and diamond, for example.On the semiconductor substrate 1, a semiconductor layer 20 that is an epitaxial growth layer of silicon carbide is formed. As illustrated in FIG. 1, an active region 101 in which a MOSFET cell is formed, a current sensing region 102 in which a cell of a current sensing element is formed, and an outer peripheral region 103 provided around the active region 101 and the current sensing region 102 are defined in the semiconductor substrate 1 and the semiconductor layer 20. In the cross-sectional view of FIG. 1, the active region 101, the current sensing region 102, and the outer peripheral region 103 are illustrated in this order from the left; the order in which the regions are arranged is not limited thereto, however. The same region may occur twice or more, such as the active region 101, the current sensing region 102, the active region 101, and the outer peripheral region 103, depending on the layout of each region and the position as viewed in cross section.In the semiconductor layer 20, a drift layer 2 that is a region of a first conductivity type is formed over the active region 101, the current measurement region 102, and the outer peripheral region 103. The impurity concentration of the first conductivity type of the drift layer 2 is set lower than that of the semiconductor substrate 1.A base region 3 aof a second conductivity type serving as a base region of the MOSFET is formed in a surface part of the drift layer 2 in the active region 101. A base region 3 bof the second conductivity type serving as a base region of the current sensing element is formed in a surface part of the drift layer 2 in the current sensing region 102. In the present preferred embodiment, the base regions 3 aand 3 bare formed simultaneously in the same ion implantation process. Therefore, the base regions 3a and 3b have the same depth and impurity concentration.A source region 4a of the first conductivity type serving as a source region of the MOSFET is formed in a surface portion of the base region 3a in the active region 101. A source region 4 bof the first conductivity type serving as a source region of the current sensing element is formed in a surface region of the base region 3 bin the current sensing region 102. In the present preferred embodiment, the source regions 4a and 4b are simultaneously formed in the same ion implantation process. Therefore, the source regions 4a and 4b have the same depth and impurity concentration.In the semiconductor layer 20 of the active region 101, a trench 5 awhich is a first trench is formed to reach the drift layer 2 below the base region 3 a, and a gate insulating film 6 aand a gate electrode 7 aof the MOSFET are embedded in the trench 5 a. The gate insulating film 6a is formed on an inner surface (side surface and bottom surface) of the trench 5a, and the gate electrode 7a is disposed so as to oppose the source region 4a and the base region 3a via the gate insulating film 6a.Similarly, in the semiconductor layer 20 of the current sensing region 102, a trench 5 b, which is a second trench, is formed to reach the drift layer 2 below the trench region 3 b, and a gate insulating film 6 band a gate electrode 7 bof the current sensing element are embedded in the trench 5 b. The gate insulating film 6b is formed on an inner surface of the trench 5b, and the gate electrode 7b is disposed so as to oppose the source region 4b and the base region 3b via the gate insulating film 6b.In the semiconductor layer 20 at the boundary portion between the active region 101 and the current sensing region 102, a trench 5 c, which is a third trench, is formed to have a width larger than the trenches 5 aand 5 band reach the drift layer 2. The trench 5c plays a role in isolating the active region 101 from the current sensing region 102. Further, in the semiconductor layer 20 of the outer peripheral region 103, a trench 5 d, which is a fourth trench, is formed to reach the drift layer 2.In the drift layer 2, protective layers 8 ato 8 dof the second conductivity type are formed below the trenches 5 ato 5 d, respectively. That is, the protection layer 8 a, which is a first protection layer, is formed below the trench 5 ain which the gate electrode 7 aof the MOSFET is embedded. The protection layer 8 b, which is a second protection layer, is formed below the trench 5 bin which the gate electrode 7 bof the current sensing element is embedded. In addition, the protection layer 8 c, which is a third protection layer, is formed below the trench 5 con the boundary portion between the active region 101 and the current sensing region 102. Further, below the trench 5 dof the outer peripheral region 103, the protection layer 8 d, which is a fourth protection layer, is formed in an inner peripheral portion of the outer peripheral region 103 (i.e., a region adjacent to the active region 101 or the current sensing region 102), and a guard ring 13 of the second conductivity type is formed on an outer side of the protection layer 8 din the outer peripheral region 103. It is desirable that the impurity concentration of the protection layers 8 ato 8 dis higher than the impurity concentration of the guard ring 13.Here, the protection layer 8 cformed below the trench 5 cat the boundary portion between the active region 101 and the current sensing region 102 includes a divided portion 15 divided in the first direction from the active region 101 to the current sensing region 102. As described above, the trench 5 ctakes a role in isolating the active region 101 from the current sensing region 102, and the protection layer 8 cincludes the divided portion 15, so that a short circuit between the active region 101 and the current sensing region 102 via the protection layer 8 cis prevented.In the present preferred embodiment, the trenches 5 ato 5 dare formed simultaneously in the same etching process, and the depths of the trenches 5 ato 5 dare all the same. Further, the gate insulating films 6 aand 6 bare simultaneously formed in the same process for forming insulating films, and the materials and thicknesses of the gate insulating films 6 aand 6 bare the same. Further, the gate electrodes 7a and 7b are formed in the same process for forming electrodes, and the materials of the gate electrodes 7a and 7b are the same. Further, the protective layers 8 ato 8 dare also formed simultaneously in the same ion implantation process, and the protective layers 8 ato 8 dhave the same depth and impurity concentration. Note that the details of the process for forming the protective layers 8 ato 8 dare described below.On the semiconductor layer 20, an interlayer insulating film 9 is formed so as to cover the gate electrodes 7a and 7b. Further, a source electrode 10 aof the MOSFET is formed on the interlayer insulating film 9 in the active region 101, and a current sensing electrode 10 bserving as a source electrode of the current sensing element is formed on the interlayer insulating film 9 in the current sensing region 102. The source electrode 10a is connected to the base region 3a and the source region 4a of the MOSFET through a contact hole formed in the interlayer insulating film 9, and the current sensing electrode 10b is connected to the base region 3b and the source region 4b of the current sensing element through a contact hole formed in the interlayer insulating film 9. The source electrode 10 aand the current sensing electrode 10 bare formed simultaneously in the same process of forming electrodes, but are patterned so that the source electrode 10 ais insulated from the current sensing electrode 10 b.Further, a drain electrode 11 is formed on the back surface of the semiconductor substrate 1. The drain electrode 11 is formed continuously across the active region 101 and the current sensing region 102, and is shared between the MOSFET and the current sensing element.As can be seen from the above, in the semiconductor device according to the first preferred embodiment, the configuration of the MOSFET cell formed in the active region 101 and the configuration of the current measurement cell formed in the current measurement region 102 are basically the same. Further, although not illustrated, in this preferred embodiment, the MOSFET cell and the current sensing cell also have the same configuration in plan view. In this case, the current division ratio of the current flowing through the current sensing region 102 to the current flowing through the active region 101 is largely determined by the ratio of the number of MOSFET cells provided in the active region 101 to the number of current sensing cells provided in the current sensing region 102. Note that, in order to obtain a desired current division ratio, some of the current sensing cells arranged in the current sensing region 102 may be dummy cells in which the source region 4 bor the gate electrode 7 bis omitted.Note that the configuration of the active region 101 and the current sensing region 102 in plan view may be any structure such as a grid type in which MOSFET cells and current sensing cells having a square, hexagonal, or circular shape are arranged vertically and horizontally in plan view, or a stripe type in which MOSFET cells and current sensing cells are arranged in a stripe pattern.In the semiconductor device according to the first preferred embodiment, the protection layer 8 ais provided below the trench 5 ain which the gate electrode 7 aof the MOSFET is embedded, and the protection layer 8 bis provided below the trench 5 bin which the gate electrode 7 bof the current sensing element is embedded, so that the concentration of the electric field at the bottoms of the trenches 5 aand 5 bis suppressed. In addition, the trench 5 cand the protection layer 8 care provided at the boundary portion between the active region 101 and the current sensing region 102, and thus it can be suppressed that the electric field distribution becomes singular at the boundary portion between the active region 101 and the current sensing region 102. Similarly, the trench 5 dand the protection layer 8 dare provided in the outer peripheral region 103, and thus it is possible to suppress the electric field distribution at the boundary portion between the active region 101 and the outer peripheral region 103 or the electric field distribution at the boundary portion between the current sensing region 102 and the outer peripheral region 103 from becoming singular. Therefore, with the semiconductor device according to the first preferred embodiment, concentration of an electric field is suppressed due to the provision of the current sensing portion 102, and it is possible to contribute to improvement in withstand voltage.As described above, the protection layer 8 cformed below the trench 5 con the boundary portion between the active region 101 and the current sensing region 102 includes the divided portion 15 divided in the first direction from the active region 101 to the current sensing region 102, and thus a short circuit between the active region 101 and the current sensing region 102 via the protection layer 8 cmay be prevented. However, since the electric field tends to concentrate on the divided portion 15 of the protective layer 8 c, it is preferable to set the width of the divided portion 15 accordingly in order to further improve the withstand voltage. Specifically, the width of the divided portion 15 of the protection layer 8 cis preferably equal to or less than the interval between the trenches 5 ain which the gate electrodes 7 aof the MOSFET are embedded and equal to or less than the interval between the trenches 5 bin which the gate electrodes 7 bof the current sensing element are embedded. That is, the width of the divided portion 15 is desirably equal to or less than the width of a mesa-shaped semiconductor layer formed between the trenches 5 aor between the trenches 5 b.In the active region 101, the interval between the trenches 5a is almost equal to the interval between the protective layers 8a, and in the current sensing region 102, the interval between the trenches 5b is almost equal to the interval between the protective layers 8b. The interval between the protective layers 8a largely influences the withstand voltage of the MOSFET, and the broader the interval, the lower the withstand voltage. The interval between the protective layers 8 b largely influences the withstand voltage of the current sensing element, and the broader the interval, the lower the withstand voltage.Therefore, when the width of the divided portion 15 is wider than the interval between the trenches 5 aor the interval between the trenches 5 b, the withstand voltages of the MOSFET and the current sensing element can be reduced by the influence of the divided portion 15. Conversely, when the width of the divided portion 15 is equal to or less than the interval between the trenches 5 aand the interval between the trenches 5 b, the withstand voltage at the divided portion 15 may be higher than that of the active region 101 and the current sensing region 102. Therefore, it is possible to further suppress a reduction in withstand voltage due to the provision of the current sensing portion 102.A method of manufacturing the semiconductor device according to the first preferred embodiment will be described herein. First, the first conductivity type semiconductor layer 20 having a lower impurity concentration than the semiconductor substrate 1 is formed on the first conductivity type semiconductor substrate 1 by epitaxial growth. Then, by selective ion implantation using a mask formed by photolithography, the second conductivity type base regions 3 aand 3 band the first conductivity type source regions 4 aand 4 bare formed in the surface part of the semiconductor layer 20. At this time, the first conductivity type region of the semiconductor layer 20 remaining without the base regions 3 aand 3 band the source regions 4 aand 4 bbecomes the drift layer 2.Thereafter, as illustrated in FIG. 2, a resist mask 91 having an opening for the formation region of the protective layers 8 ato 8 dis formed on the semiconductor layer 20 in which the trenches 5 ato 5 dare formed, and the protective layers 8 ato 8 dare formed by selective ion implantation using the resist mask 91 as illustrated in FIG. 3. At this time, a part of the resist mask 91 is formed in the trench 5 csuch that the protection layer 8 cformed below the trench 5 cat the boundary portion between the active region 101 and the current sensing region 102 includes the divided portion 15. Further, another part of the resist mask 91 is formed on the formation region of the guard ring 13 in the trench 5 din the outer peripheral region 103.After removal of the resist mask 91, the guard ring 13 of the second conductivity type is formed by selective ion implantation using the mask below the trench 5 d. Subsequently, the gate insulating films 6a and 6b and the gate electrodes 7a and 7b are formed in the trenches 5a and 5b, and the interlayer insulating film 9 is formed to cover them. Then, after contact holes reaching the base regions 3 aand 3 band the source regions 4 aand 4 bare formed in the interlayer insulating film 9, the source electrode 10 aand the current sensing electrode 10 bare formed on the interlayer insulating film 9. Further, by forming the drain electrode 11 on the back surface of the semiconductor substrate 1, the semiconductor device having the configuration illustrated in FIG. 1 is completed.The method for manufacturing the semiconductor device according to the first preferred embodiment can be obtained, with respect to a conventional method for manufacturing a semiconductor device, by changing the shape of the mask for forming the trenches 5 ato 5 dsuch that the trench 5 cis formed at the boundary portion between the active region 101 and the current sensing region 102, and moreover, changing the shape of the resist mask 91 defining the structure of the protective layers 8 ato 8 dsuch that the protective layer 8 cis formed with the divided portion 15 below the trench 5 c. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device. Therefore, according to the method of manufacturing the semiconductor device according to the present preferred embodiment, a semiconductor device including a trench-type switching element and a trench-type current sensing element can be achieved without increasing the manufacturing cost and reducing the withstand voltage.< Preferred Embodiment>FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor device according to the second preferred embodiment. In FIG. 4, the same elements as those illustrated in FIG. 1 are denoted by the same reference numerals.As illustrated in FIG. 4, in the semiconductor device according to the second preferred embodiment, in the trench 5 c, at the boundary portion between the active region 101 and the current sensing region 102, a semiconductor layer 16 having a mesa shape including a part of the semiconductor layer 20 is erected on the divided portion 15 of the protection layer 8 c. A second conductivity type region similar to the base regions 3 aand 3 bmay be formed in an upper layer portion of the semiconductor layer 16 having the mesa shape. Here, the semiconductor layer 16 having the mesa shape is referred to as the "mesa-shaped semiconductor 16" hereinafter. The other configurations are the same as those in FIG. 1, and the description thereof is omitted here.A method of manufacturing the semiconductor device according to the second preferred embodiment will be described herein. Similarly to the first preferred embodiment, first, the first conductivity type semiconductor layer 20 is formed on the first conductivity type semiconductor substrate 1, and by selective ion implantation, the second conductivity type base regions 3 aand 3 band the first conductivity type source regions 4 aand 4 bare formed in the surface part of the semiconductor layer 20.Subsequently, as illustrated in FIG. 5, a resist mask 92 having an opening for the formation regions of the trenches 5 ato 5 dis formed on the semiconductor layer 20. At this time, the formation region of the mesa-shaped semiconductor 16 is covered by the resist mask 92. The trenches 5a to 5d are formed in the semiconductor layer 20 by selective etching using the resist mask 92 as a mask as illustrated in FIG. 6. At this time, the mesa-shaped semiconductor 16 is formed in the trench 5 cin the boundary portion between the active region 101 and the current sensing region 102.After removing the resist mask 92, as illustrated in FIG. 7, a resist mask 93 having an opening for the formation region of the protective layers 8 ato 8 dis formed on the semiconductor layer 20 in which the trenches 5 ato 5 dare formed. A part of the resist mask 93 is formed on the formation region of the guard ring 13 in the trench 5 dof the outer peripheral region 103. The protective layers 8a to 8d are then formed by selective ion implantation using the resist mask 93 as illustrated in FIG. 8. At this time, the divided portion 15 of the protection layer 8 cis formed below the mesa-shaped semiconductor 16. Therefore, the width of the mesa-shaped semiconductor 16 is preferably equal to or less than the interval between the trenches 5 ain which the gate electrode 7 aof the MOSFET is embedded and equal to or less than the interval between the trenches 5 bin which the gate electrodes 7 bof the current sensing element are embedded.Then, similarly to the first preferred embodiment, below the trench 5 d, the guard ring 13 of the second conductivity type is formed. Subsequently, the gate insulating films 6a and 6b and the gate electrodes 7a and 7b are formed in the trenches 5a and 5b, and the interlayer insulating film 9 is formed thereon. Then, after contact holes reaching the base regions 3 aand 3 band the source regions 7 aand 7 bare formed in the interlayer insulating film 9, the source electrode 10 aand the current sensing electrode 10 bare formed on the interlayer insulating film 9. Further, by forming the drain electrode 11 on the back surface of the semiconductor substrate 1, the semiconductor device having the configuration illustrated in FIG. 4 is completed.The method for manufacturing the semiconductor device according to the second preferred embodiment can be obtained, with respect to the conventional method for manufacturing a semiconductor device, by changing the shape of the resist mask 92, which is a mask for forming the trenches 5 ato 5 d, so that the trench 5 cincluding the mesa-shaped semiconductor 16 is formed at the boundary portion between the active region 101 and the current sensing region 102, and further changing the shape of the resist mask 93, which defines the structure of the protective layers 8 ato 8 d, so that the protective layer 8 cis formed below the trench 5 c. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device. Therefore, according to the method of manufacturing the semiconductor device according to the present preferred embodiment, a semiconductor device including a trench-type switching element and a trench-type current sensing element can be obtained without increasing the manufacturing cost and reducing the withstand voltage.As can be seen by comparing FIGS. 8 and 3, in the second preferred embodiment, since the mesa-shaped semiconductor 16 is erected on the divided portion forming region 15, the thickness of the resist mask 93 to be formed on the divided portion forming region 15 is less than the thickness of the resist mask 91 to be formed on the divided portion forming region 15 in the first preferred embodiment. Conversely, the resist mask 91 formed at the bottom of the trench 5 cused in the first preferred embodiment is thicker than the resist mask 93 used in the second preferred embodiment.Generally, the controllability of processing decreases as the thickness of a photoresist increases. Therefore, when the shape of the divided portion 15 of the protective layer 8 cis defined by using the thick resist mask 91 as in the first preferred embodiment, the width of the divided portion 15 varies, and there is a possibility that the withstand voltage of the semiconductor device varies and poor separation between the active region 101 and the current sensing region 102 may occur. Further, the width of the divided portion 15 is preferably equal to or less than the interval between the trenches 5 ain which the gate electrodes 7 aof the MOSFET are embedded and equal to or less than the interval between the trenches 5 bin which the gate electrodes 7 bof the current sensing elements are embedded. Therefore, depending on the combination of the depth of the trench 5 cand the width of the divided portion 15, the aspect ratio of the resist mask 91 provided on the formation region of the divided portion 15 becomes large, and in the worst case, the resist mask 91 may collapse.On the other hand, in the second preferred embodiment, the shape of the divided portion 15 is defined by the mesa-shaped semiconductor 16. That is, the mesa-shaped semiconductor 16 plays a role as a mask for ion implantation for forming the divided portion 15. Since the controllability of the width of the mesa-shaped semiconductor 16 is higher than the controllability of the width of the photoresist, the controllability of the width of the divided portion 15 can be improved as compared with the first preferred embodiment. This can prevent variations in the withstand voltage of the semiconductor device and poor separation between the active region 101 and the current sensing region 102.In the above description, the resist mask 92 is used as an etching mask for forming the trenches 5 ato 5 d; however, an oxide film mask 94 may be used instead as illustrated in FIG. 9. In this case, as illustrated in FIG. 10, the trenches 5 ato 5 dare formed by selective etching using the oxide film mask 94 as a mask. At this time, the mesa-shaped semiconductor 16 is formed in the trench 5 cin the boundary portion between the active region 101 and the current sensing region 102.Then, as illustrated in FIG. 11, while leaving the oxide film mask 94, a resist mask 95 covering the formation region of the guard ring 13 is formed in the trench 5 din the outer peripheral region 103, and selective ion implantation is performed using the oxide film mask 94 and the resist mask 95 as masks to form the protective layers 8 ato 8 das illustrated in FIG. 12. At this time, below the mesa-shaped semiconductor 16, the divided portion 15 of the protection layer 8 cis formed.According to this method, since the oxide film mask 94 used as an etching mask for forming the trenches 5a to 5d is also used as a mask for ion implantation for forming the trenches 5a to 5d, the protective layers 8a to 8d are respectively formed self-aligned at the bottoms of the trenches 5a to 5d. Therefore, the alignment accuracy between the trenches 5 ato 5 dand the protection layers 8 ato 8 dmay be improved.The method of manufacturing the semiconductor device described in connection with FIGS. 9 to 12 can be obtained with respect to the conventional method of manufacturing a semiconductor device so as to change the shape of the oxide film mask 94 defining the structure of the trenches 5a to 5d and the resist mask 95 defining the structure of the protective layers 8a to 8d. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device.< Preferred Embodiment>FIG. 13 is a cross-sectional view illustrating a configuration of a semiconductor device according to the third preferred embodiment. In FIG. 13, the same elements as those illustrated in FIGS. 1 and 4 are denoted by the same reference numerals.As illustrated in FIG. 13, in the semiconductor device according to the third preferred embodiment, in the trenches 5 c, at the boundary portion between the active region 101 and the current sensing region 102 along the first direction from the active region 101 to the current sensing region 102, a plurality of divided portions 15 of the protection layers 8 cand a plurality of mesa-shaped semiconductors 16 are provided thereon. The other configurations are the same as those in FIG. 4, and description thereof is omitted here.As described in the second preferred embodiment, in view of controllability of processing, the mesa-shaped semiconductor 16 is superior to a photoresist. However, when the length of the boundary between the active region 101 and the current sensing region 102 (the length in a second direction perpendicular to the first direction) is long, the mesa-shaped semiconductor 16 also becomes long. Therefore, there is a concern that the mesa-shaped semiconductor 16 is formed to have a partially narrow width at the time of etching for forming the trenches 5 ato 5 d, or that the mesa-shaped semiconductor 16 is interrupted due to the influence of a foreign matter or the like. In this case, the width of the divided portion 15 is partially narrowed or the divided portion 15 is interrupted in the second direction, thereby causing variations in the withstand voltage of the semiconductor device or poor separation between the active region 101 and the current sensing region 102.In the semiconductor device according to the third preferred embodiment, along the first direction from the active region 101 to the current sensing region 102, the plurality of divided portions 15 of the protection layers 8 cand the plurality of mesa-shaped semiconductors 16 are provided thereon. Therefore, for example, even when variation in width or interruption in the second direction occurs in some of the plurality of divided portions 15, variation in withstand voltage of the semiconductor device and poor separation between the active region 101 and the current sensing region 102 can be prevented.Note that, in the trench between the mesa-shaped semiconductors 16, the interlayer insulating film 9 may be embedded as illustrated in FIG. 13, or the same insulating films and electrodes as the gate insulating films 6 aand 6 band gate electrodes 7 aand 7 bmay be embedded. When an insulating film and an electrode are embedded in the trench between the mesa-shaped semiconductors 16, it is desirable that such an electrode is insulated from the gate electrodes 7a and 7b and has a floating potential. In this case, it is further desirable that the mesa-shaped semiconductor 16 be provided with the same second conductivity type region as the base regions 3 aand 3 band not be provided with the first conductivity type region such as the source regions 4 aand 4 b. This serves to prevent the MOSFET from being formed in the mesa-shaped semiconductor 16 and causing an unintended operation.The method for manufacturing the semiconductor device according to the third preferred embodiment can be obtained, with respect to the method for manufacturing the semiconductor device of the second preferred embodiment, by changing the shape of the resist mask 92 (or oxide film mask 94) defining the structure of the trenches 5 ato 5 dand the resist mask 93 (or resist mask 95) defining the structure of the protective layers 8 ato 8 d. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device.Note that in the third preferred embodiment, the configuration in which the plurality of divided portions 15 of the protection layers 8 cand the plurality of mesa-shaped semiconductors 16 are provided along the first direction is indicated, but in a configuration in which the mesa-shaped semiconductor 16 is not provided on the divided portion 15 as in the first preferred embodiment, for example, a plurality of divided portions 15 may be provided in the first direction. Also in this case, when a variation in the width of the divided portion 15 or a break occurs in the second direction, the effect of preventing a variation in the withstand voltage of the semiconductor device and poor separation between the active region 101 and the current sensing region 102 can be obtained.< Preferred Embodiment>FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device according to the fourth preferred embodiment. In FIG. 14, the same elements as those illustrated in FIGS. 1 and 4 are denoted by the same reference numerals.As illustrated in FIG. 14, in the semiconductor device according to the fourth preferred embodiment, along the first direction from the active region 101 to the current measurement region 102, in the trenches 5 cin the boundary portion between the active region 101 and the current measurement region 102, a plurality of divided portions 15 of the protection layers 8 cand a plurality of mesa-shaped semiconductors 16 are provided thereon, and they are arranged between the active region 101 and the current measurement region 102 at equal intervals. The other configurations are the same as those in FIG. 4, and description thereof is omitted here.Since the mesa-shaped semiconductor 16 has a height equal to the depth of the trench 5 c, if the number of the mesa-shaped semiconductors 16 is one as in the second preferred embodiment (FIG. 4 ) or if the interval between the plurality of mesa-shaped semiconductors 16 is large as in the third preferred embodiment (FIG. 13 ), a level difference of the same extent as the height of the mesa-shaped semiconductor 16 will be formed on the surface of the interlayer insulating film 9 formed on the trench 5 con the boundary portion between the active region 101 and the current sensing region 102.On the other hand, in the semiconductor device of the fourth preferred embodiment, as illustrated in FIG. 14, a plurality of mesa-shaped semiconductors 16 are uniformly provided from the end of the trench 5 con the active region 101 side to the end on the current sensing region 102 side, and the interval between the mesa-shaped semiconductors 16 is narrowed. The interval between the mesa-shaped semiconductors 16 is here equal to the width of the trench 5 ain the active region 101 and the width of the trench 5 bin the current measurement region 102. As a result, the surface of the interlayer insulating film 9 formed on the trench 5c becomes flat.For example, when an external electrode is mounted on a semiconductor device and they are sealed in a package to form a module, there is no problem as long as the package is filled with a soft insulating material such as a gel. However, when a hard insulating material such as a resin is molded, stress concentrates on a portion of the surface of the semiconductor device where flatness is poor, so that a level difference on the surface of the semiconductor device causes cracking. Since the semiconductor device of the present preferred embodiment has high flatness of the surface, concentration of stress can be suppressed and a defect rate when a semiconductor device is modularized can be reduced.The method for manufacturing the semiconductor device according to the fourth preferred embodiment can be obtained, with respect to the method for manufacturing the semiconductor device of the second preferred embodiment, by changing the shape of the resist mask 92 (or oxide film mask 94) defining the structure of the trenches 5 ato 5 dand the resist mask 93 (or resist mask 95) defining the structure of the protective layers 8 ato 8 d. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device.< Preferred Embodiment>FIGS. 15 to 17 are views illustrating a configuration of the semiconductor device according to the fifth preferred embodiment. FIG. 15 is a plan view of the semiconductor device, FIG. 16 is a cross-sectional view taken along a line A 1-A 2 in FIG. 15, and FIG. 17 is a cross-sectional view taken along a line B 1-B 2 in FIG. 15. In these drawings, the same elements as those illustrated in FIGS. 1 and 4 are denoted by the same reference numerals. Note that FIG. 15 illustrates the configuration of the upper surface of the semiconductor layer 20, and the illustration of the interlayer insulating film 9, the source electrode 10 a, the current sensing electrode 10 b, and the like formed on the semiconductor layer 20 is omitted.In the semiconductor device according to the fifth preferred embodiment, as illustrated in FIGS. 15 to 17, a plurality of mesa-shaped semiconductors 16 are formed side by side in the second direction perpendicular to the first direction from the active region 101 to the current sensing region 102 in the trenches 5 cin the boundary portion between the active region 101 and the current sensing region 102. Further, each of the mesa-shaped semiconductors 16 is continuously formed from a portion near the end of the trench 5 con the active region 101 side to a portion near the end on the current sensing region 102 side. That is, the length of the mesa-shaped semiconductor 16 in the first direction is shorter than the width of the trench 5 c, but is close to the width of the trench 5 c.The length of the mesa-shaped semiconductor 16 in the first direction is longer than the length in the second direction, and the mesa-shaped semiconductor 16 is provided in the second direction at the same interval as the interval of the cells of the MOSFET. That is, the length of the mesa-shaped semiconductor 16 in the second direction is equal to the interval of the trenches 5 aof the active region 101, and the interval of the mesa-shaped semiconductors 16 in the second direction is equal to the width of the trench 5 aof the active region 101.Further, as illustrated in FIGS. 15 and 17, the divided portion 15 of the protection layer 8 cprovided below the trench 5 cin the boundary portion between the active region 101 and the current sensing region 102 is formed not only below the mesa-shaped semiconductor 16 but also in a region between the mesa-shaped semiconductors 16 to divide the protection layer 8 cin the first direction. The other configurations are the same as those in FIG. 4, and description thereof is omitted here.In the semiconductor device according to the fifth preferred embodiment, the mesa-shaped semiconductor 16 is continuously formed from a portion near the end of the trench 5 con the active region 101 side to a portion near the end on the current measurement region 102 side, and the interval of the mesa-shaped semiconductor 16 in the second direction is as narrow as the width of the trench 5 aof the active region 101, and thus the surface of the interlayer insulating film 9 formed on the trench 5 cmay be formed flat and the same effect as in the fourth preferred embodiment may be obtained.The method for manufacturing the semiconductor device according to the fourth preferred embodiment can be obtained with respect to the method for manufacturing the semiconductor device according to the second preferred embodiment such that the shape of the resist mask 92 defining the structure of the trenches 5 ato 5 dand the resist mask 93 defining the structure of the protective layers 8 ato 8 dis changed. That is, there is no need to increase the number of masks or the number of manufacturing processes with respect to the conventional method of manufacturing a semiconductor device.In the present invention, any preferred embodiment may be combined.

Claims

A semiconductor device comprising: a semiconductor layer (20) in which a drift layer (2) of a first conductivity type is formed; a trench-type switching element in which a gate electrode (7a) is embedded in a first trench (5a) formed in the semiconductor layer (20) so as to reach the drift layer (2); a trench-type current sensing element in which a gate electrode (7b) is embedded in a second trench (5b) formed in the semiconductor layer (20) so as to reach the drift layer (2); a third trench (5c) configured to be formed in the semiconductor layer (20) at a boundary portion between an active region (101) where the switching element is formed and a current sensing region (102) where the current sensing element is formed and to reach the drift layer (2); a first second conductivity type protection layer (8a) formed below the first trench (5a) in the drift layer (2); a second second conductivity type protection layer (8b) formed below the second trench (5b) in the drift layer (2); and a third second conductivity type protection layer (8c) formed below the third trench (5c) in the drift layer (2); wherein the third protection layer (8c) has a divided portion (15) divided in a first direction from the active region (101) to the current sensing region (102), and wherein in the third trench (5c), the semiconductor layer (16) having a mesa shape is formed on the divided portion (15) of the third protection layer (8c).The semiconductor device according to claim 1, wherein a width of the divided portion (15) of the third protection layer (8c) is equal to or less than an interval of the first trenches (5a) and an interval of the second trenches (5b).The semiconductor device according to claim 1 or 2, wherein a plurality of the divided portions (15) of the third protection layer (8c) are provided along the first direction.The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the divided portions (15) of the third protection layer (8c) and a plurality of the semiconductor layers (16) having the mesa shape are provided along the first direction.The semiconductor device according to claim 4, wherein the divided portions (15) of the third protection layer (8c) and the semiconductor layers (16) having the mesa shape are provided at equal intervals along the first direction.A semiconductor device comprising: a semiconductor layer (20) in which a drift layer (2) of a first conductivity type is formed; a trench-type switching element in which a gate electrode (7a) is embedded in a first trench (5a) formed in the semiconductor layer (20) so as to reach the drift layer (2); a trench-type current sensing element in which a gate electrode (7b) is embedded in a second trench (5b) formed in the semiconductor layer (20) so as to reach the drift layer (2); a third trench (5c) configured to be formed in the semiconductor layer (20) at a boundary portion between an active region (101) where the switching element is formed and a current sensing region (102) where the current sensing element is formed and to reach the drift layer (2); a first second conductivity type protection layer (8a) formed below the first trench (5a) in the drift layer (2); a second second conductivity type protection layer (8b) formed below the second trench (5b) in the drift layer (2); and a third second conductivity type protection layer (8c) formed below the third trench (5c) in the drift layer (2); wherein the third protection layer (8c) has a divided portion (15) divided from the active region (101) to the current sensing region (102) in a first direction, and a plurality of the semiconductor layers (16) having the mesa shape are formed side by side in a second direction perpendicular to the first direction in the third trench (5c).The semiconductor device according to claim 6, wherein a length of the semiconductor layer (16) having the mesa shape in the first direction is longer than a length in the second direction.The semiconductor device according to claim 7, wherein the semiconductor layers (16) having the mesa shape in the second direction are provided at the same interval as an interval of cells of the switching element.The semiconductor device according to any one of claims 1 to 8, further comprising: a fourth trench (5d) configured to be formed in the semiconductor layer (20) in an outer peripheral region (103) provided around the active region (101) and the current measurement region (102) and to reach the drift layer (2); and a fourth protection layer (8d) of the second conductivity type provided below the fourth trench (5d) in the drift layer (2).A semiconductor device comprising: a semiconductor layer (20) in which a drift layer (2) of a first conductivity type is formed; a trench-type switching element in which a gate electrode (7a) is embedded in a first trench (5a) formed in the semiconductor layer (20) so as to reach the drift layer (2); a trench-type current sensing element in which a gate electrode (7b) is embedded in a second trench (5b) formed in the semiconductor layer (20) so as to reach the drift layer (2); a third trench (5c) configured to be formed in the semiconductor layer (20) at a boundary portion between an active region (101) where the switching element is formed and a current sensing region (102) where the current sensing element is formed and to reach the drift layer (2); a first second conductivity type protection layer (8a) formed directly below the first trench (5a) in the drift layer (2); a second second conductivity type protection layer (8b) formed directly below the second trench (5b) in the drift layer (2); and a third second conductivity type protection layer (8c) formed directly below the third trench (5c) in the drift layer (2); wherein the third protective layer (8c) has a divided portion (15) divided in a first direction from the active region (101) to the current sensing region (102), and wherein first end surfaces of the third protective layer (8c) which are opposed to each other form the divided portion (15), and wherein second end surfaces of the third protective layer (8c) which are opposed to the first end surfaces are disposed between opposed side walls of the third trench (5c).

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