Semiconductor Device and Method

Abstract

Procedure, comprehensive: Forming a first compound structure (24) over a first substrate (22), wherein the first compound structure (24) comprises dielectric layers and metallization structures therein; Structuring the first connection structure (24) to form a first opening (34) that exposes a section of the first substrate (22); Coating the first opening (34) with a barrier layer (40); Forming and structuring a photoresist (42), wherein the structuring of the photoresist (42) forms an opening through the photoresist to expose the barrier layer (40) at a bottom of the first opening (34); Etching a second opening (44) through the barrier layer (40) and the exposed section of the first substrate (22), wherein the structured photoresist (42) serves as a mask for removing the exposed section; Deposition of a lining (50) in the first opening (34) and the second opening (44), wherein the lining (50) is in physical contact with the barrier layer (40); Filling the first opening (34) and the second opening (44) with a conductive material (63); Thinning of the first substrate (22) to expose a section of the conductive material (64) in the second opening (44), wherein the conductive material (64) extends through the first interconnect structure (24) and the first substrate (22) and forms a substrate through-hole (64A, 264A); Forming a second interconnection structure (80) over the first interconnection structure (24) and the substrate via (64A, 264A), wherein the second interconnection structure (80) comprises dielectric layers (82, 84, 90) and metallization structures therein, wherein the metallization structures of the second interconnection structure (80) are electrically coupled to the metallization structures of the first interconnection structure (24) and to the substrate via (64A, 264A); Formation of a first dielectric layer (90) over the second interconnect structure (80); and Forming first bond pads (94) in the first dielectric layer (90), wherein the first bond pads (94) are electrically coupled to the metallization structures of the second interconnection structure (80).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Improvements in integration density primarily result from iterative reductions in minimum feature size, allowing more components to be integrated in a given area. As the demand for ever smaller electronic devices has increased, there has been a need for smaller and more creative packaging techniques for semiconductor die. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and high component density.PoP technology generally enables the production of semiconductor devices with enhanced functionalities and a small footprint on a printed circuit board (PCB).

[0002] US 2015 / 0028494 A1 discloses an integrated circuit device comprising a through-silicon via (TSV) structure and a method for manufacturing the integrated circuit device. US 2018 / 0025970 A1 discloses an integrated circuit offering high performance and high functional density. Further prior art can be found in KR 101 761 016 B1 and US 2012 / 0289062 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. Indeed, the dimensions of various features may be exaggerated or reduced as desired for clarity. Fig. 1 to 19 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 20 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 21 to 25 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 26 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 27 to 33 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 34 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 35 to 36 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 37 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 38 to 43 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 44 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 45 to 46 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 47 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 48 to 53 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 54 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. Fig. 55 to 56 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. Fig. 57 illustrates a cross-sectional view of an intermediate stage in the formation of a multi-stack die package according to another embodiment. DETAILED DESCRIPTION

[0004] The invention is defined by claims 1, 11 and 17. Embodiments of the invention are provided in the dependent claims, in the description and in the figures. The following disclosure provides many different embodiments or examples of implementing different features of the invention. Specific examples of the components and arrangements are described below to simplify the present disclosure. The formation of a first feature over or on top of a second feature in the following description may, for example, include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in and of itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "deeper," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0006] Embodiments discussed herein may be explained in a specific context, namely a device structure that can be integrated into a package (e.g., a chip-on-wafer (CoW) package structure or a wafer-on-wafer (WoW) package structure). The device structure includes a passivation layer between a through-substrate via (TSV) and the interconnect or redistribution structure to prevent contamination intrusion into the interconnect or redistribution structure that might occur during formation of the via. In some embodiments, the passivation layer may include a nitride layer, an undoped silicate glass (USG) layer, the like, or a combination thereof.Contaminants from the formation of the substrate via may include liquid or moisture used in the formation of the substrate via and / or chemicals, such as sulfur, used during the etching of the substrate via. In conventional structures, these contaminants can penetrate the exposed sidewalls of the interconnect layers during the formation of the substrate via and damage the metallization structures and dielectric layers of the interconnect. By blocking the contaminant, damage to the metallization structures of the interconnect layers due to the contaminant can be prevented.

[0007] Furthermore, the teachings of this disclosure also apply to any device or package structures where a passivation layer can prevent contaminants from damaging an interconnect or redistribution structure. Other embodiments contemplate other applications, such as other package types or other configurations that would be readily apparent to those skilled in the art upon reading this disclosure. It should be noted that embodiments discussed herein do not necessarily illustrate every component or feature that may be present in a structure. For example, multiple versions of a component may be omitted from a figure, such as when discussion of one of the components may be sufficient to convey aspects of the embodiment.Furthermore, method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0008] Fig. 1 to 19 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment.

[0009] Fig. 1 illustrates a cross-sectional view of an integrated circuit die 20A according to some embodiments. The integrated circuit die 20A is packaged in later processing to form an integrated circuit package. The integrated circuit die 20A may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit die (PMIC)), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or combinations thereof.

[0010] The integrated circuit die 20A may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die 20A may be processed according to applicable manufacturing processes to form integrated circuits. The integrated circuit die 20A includes, for example, a semiconductor substrate 22, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 22 may also include other semiconductor materials, such as germanium; a composite semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenic, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, may also be used. Substrate 22 has an active area (e.g., the area shown in FIG. Fig. 1 upward-facing surface), sometimes referred to as a front surface, and an inactive surface (e.g. the one in Fig. 1 downward-facing surface), sometimes referred to as a back.

[0011] Devices (not shown) may be formed on the front surface of substrate 22. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, the like, or a combination thereof. An interlayer dielectric layer (ILD) (not separately illustrated) is disposed over the front surface of substrate 22. The ILD surrounds and may cover the devices. The ILD may include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0012] Conductive plugs (not separately illustrated) extend through the ILD to electrically and physically couple the devices. For example, if the devices are transistors, the conductive plugs may couple the gates and source / drain regions of the transistors. The conductive plugs may be formed from tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure 24 is located above the ILD and the conductive plugs. The interconnect structure 24 connects the devices to form an integrated circuit. The interconnect structure 24 may be formed, for example, by metallization structures in dielectric layers on the ILD. The metallization structures include metal lines and vias formed in one or more low-k dielectric layers.The metallization structures of the interconnect structure 24 are electrically coupled to the devices through the conductive plugs. The metallization structures can be formed using any suitable process, such as a single damascene process, a double damascene process, a plating process, combinations thereof, or the like.

[0013] After forming the connecting structure 24, as in Fig. As shown in Figure 2, a stop layer 30 is deposited over a top surface of the interconnect structure 24 by chemical mechanical polishing (CMP). The CMP stop layer 30 is used to prevent a subsequent CMP process from removing too much material by being resistant to the subsequent CMP process and / or by providing a detectable stop point for the subsequent CMP process. In some embodiments, the CMP stop layer 30 may comprise one or more layers of dielectric material.Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN or the like), oxynitrides (such as SiON or the like), oxycarbides (such as SiOC or the like), carbonitrides (such as SiCN or the like), carbides (such as SiC or the like), combinations thereof, or the like, and may be formed using spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, the CMP stop layer 30 has a thickness between about 20 nm and about 2000 nm.

[0014] As in Fig. 3, a photoresist 32 is formed and patterned on the stop layer 30. The photoresist 32 may be formed by spin coating or the like and exposed for patterning. The pattern of the photoresist corresponds to an upper portion of the subsequently formed substrate via (TSV) 64A (see, for example, Fig. 13). The patterning forms at least one opening through the photoresist 32 to expose the stop layer 30.

[0015] In Fig. 5, the remaining photoresist 32 serves as a mask during an etching process to remove the exposed portion of the stop layer 30 and the underlying portions of the dielectric layer(s) of the interconnect structure 24 to expose the front surface of the substrate 22. A single etch process may be used to etch an opening 34 in the stop layer 30 and the interconnect structure 24, or a first etch process may be used to etch the stop layer 30 and a second etch process may be used to etch the dielectric layers of the interconnect structure 24. In some embodiments, the opening 34 is formed using a plasma dry etch process. The opening 34 exposes a top surface of the substrate 22. In some embodiments, the etching process(es) may be any acceptable etching process, such as wet or dry etching.

[0016] As in Fig. 5, after the opening 34 is formed, the photoresist 32 is removed. The photoresist 32 may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist 32 is removed, a burn-in process 36 is performed (sometimes referred to as a thermal or heating process). The burn-in process 36 may help remove moisture and liquid from the opening 34 that may have accumulated in the etching process for the opening 34 and the processing of the photoresist 32. The burn-in process 36 may be performed at a temperature of 150°C to 450°C for 1 to 30 minutes. In some embodiments, the burn-in process 36 uses a kiln or oven to heat the wafer. In some embodiments, the burn-in process 36 is a Rapid Thermal Anneal (RTA) or Rapid Thermal Processing (RTP) process.After the burn-in process 36, the opening 34 may have a width w1 in a range of about 0.5 µm to about 5 µm and the thickness t of the connection structure 24 may be in a range of about 0.5 µm to about 5 µm.

[0017] As in Fig. 6, after the burn-in process 36, a passivation layer 40 (sometimes referred to as a barrier layer 40) is conformally deposited on the stop layer 30 and on the bottom surface and sidewalls of the opening 34. The passivation layer 40 can help prevent the diffusion of materials (such as water vapor and process byproducts) of the subsequently formed substrate vias 64A (see, e.g., Fig. 13) into the interconnect 24 during subsequent processing. In some embodiments, the interconnect 24 includes low-k dielectric layers and copper metallization structures, and the passivation layer prevents water vapor and process byproducts from penetrating the interconnect 24 and causing interconnect corrosion. In some embodiments, the passivation layer 40 may include silicon nitride (SiN) and the like, and may, for example, have a dielectric constant in a range of about 6.5 to about 8. The passivation layer 40 may be conformally deposited and formed using a deposition process such as CVD, PECVD, ALD, plasma-enhanced ALD (PEALD), the like, or a combination thereof. The passivation layer 40 may be deposited to a thickness of about 0.05 μm to about 0.2 μm.

[0018] As in Fig. 7, a photoresist 42 is formed and patterned on the passivation layer 40. The photoresist 42 may be formed by spin coating or the like and exposed for patterning. The pattern of the photoresist corresponds to a lower portion of the subsequently formed TSV 64A (see, for example, Fig. 13). The patterning forms at least one opening through the photoresist 42 to expose the passivation layer 40 at the bottom of the opening 34.

[0019] The remaining photoresist 42 serves as a mask during an etching process to remove the exposed portion of the passivation layer 40 and underlying portions of the substrate 22, as shown in Fig. 8. To etch an opening 44 in the exposed portion of the passivation layer 40 and the substrate 22, a single etch process may be performed, or a first etch process may be used to etch the passivation layer 40 and a second etch process may be used to etch the substrate 22. In some embodiments, the etch process is a reactive ion etch (RIE) process, such as a deep RIE (DRIE) process. In some embodiments, the DRIE process includes one or more etch cycles and one or more passivation cycles, where the etch cycle(s) uses, for example, SF6 and the passivation cycle(s) uses, for example, C4F8. Using a DRIE process with the passivation cycle(s) and the etch cycle(s) enables a highly anisotropic etch process. In some embodiments, the etch process(es) may be any acceptable etch process, such as wet or dry etching.The opening 44 in the substrate 22 may have a depth d1 in a range of about 2 µm to about 20 µm.

[0020] Because the passivation layer 30 covers the exposed sidewalls of the interconnect 24 in the opening 34 during the process of forming the opening 44, potential contamination from the etching process is prevented by blocking penetration into the interconnect 24 for the opening 44. By blocking the contamination, damage to the metallization structures of the interconnect structures, for example, from sulfur used to etch the substrate vias, is prevented.

[0021] As in Fig. As illustrated in Figure 9, after forming the opening 44, the photoresist 42 is removed. The photoresist 42 may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After removal of the photoresist 42, the opening 44 may have a width w2 that is smaller than the width w1 of the opening 34. In one embodiment, the width w2 is in a range from about 0.1 µm to about 4.5 µm.

[0022] In Fig. 10, a liner layer 50 is conformally deposited on the passivation layer 40, including on the passivation layer 40 within the opening 34 and on the bottom surface and sidewalls of the opening 44. In some embodiments, the liner layer 50 includes one or more layers of dielectric materials and may be used to physically and electrically isolate the later-formed vias from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN or the like), oxynitrides (such as SiON or the like), combinations thereof, or the like. The liner layer 50 may be formed using CVD, PECVD, ALD, the like, or a combination thereof. In some embodiments, the liner layer 50 has a thickness in a range of about 0.1 μm to about 1 μm.

[0023] In a subsequent step, as in Fig. 11, a growth layer 60 is formed over liner layer 50. In some embodiments, growth layer 60 is a metal layer, which may be a single layer or a composite layer consisting of a plurality of sublayers formed from different materials. In some embodiments, growth layer 60 includes a titanium layer and a copper layer over the titanium layer. The growth layer may be formed, for example, using physical vapor deposition (PVD) or the like. In some embodiments, a barrier layer (not shown) may be formed on liner layer 50 prior to forming growth layer 60. The barrier layer may include, for example, Ti and TiN.

[0024] In Fig. 12, a conductive material 62 is formed on the growth layer 60 and fills the openings 34 and 44. The conductive material may be formed by plating, such as electroplating, including electrochemical plating, electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like.

[0025] After the conductive material 62 has been formed, an annealing process is then performed. The annealing process may be performed at a temperature between about 150°C and about 450°C for a duration of between 1 minute and about 60 minutes. The annealing process may prevent subsequent extrusion of the conductive material of the TSV 64A (sometimes referred to as TSV pumping). TSV pumping is caused by a mismatch in the coefficient of thermal expansion (CTE) between the conductive material 62 and the substrate 22 and may cause damage to structures (e.g., metallization structures) over the TSV.

[0026] After the annealing process, a planarization process is performed to remove portions of the conductive material 62, the growth layer 60, the liner layer 50, the passivation layer 40, and the stop layer 30 outside the openings 34 and 44 to form a TSV 64A, as shown in Fig. 13. Upper surfaces of the TSV 64A and the top dielectric layer of the interconnect structure 24 are substantially coplanar after the planarization process, within process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. The upper portion of the TSV 64A (formed in the interconnect structure 24) has a greater width than the lower portion of the TSV 64A (formed in the substrate 22). As also shown in Fig. As shown in Figure 13, the passivation layer 40 has a cup shape with a hole (the hole is caused by opening 44) in the bottom of the cup.

[0027] With reference to Fig. 14 is placed above the structure in Fig. 13, an interconnect structure 80 is formed. The interconnect structure 80 includes dielectric layers 82 and 84 and metallization structures and vias 86. More or fewer dielectric layers and metallization structures and vias can be formed than in Fig. 14. The interconnect structure 80 is connected to the interconnect structure 24 and TSV 64A by metallization structures and vias formed in the dielectric layer(s) 82. The metallization structures and vias may be formed using similar processes and materials as the interconnect structure 24, and the description will not be repeated herein.

[0028] In some embodiments, the dielectric layers 82 are made of a similar material as the dielectric layers of the interconnect structure 24, e.g., a low-k dielectric. In other embodiments, the dielectric layers 82 are formed of a silicon-containing oxide (which may or may not contain oxygen). For example, the dielectric layers 82 may contain an oxide such as silicon oxide, a nitride such as silicon nitride, or the like. The dielectric layers 84 may be formed of a silicon-containing oxide.

[0029] The metallization structures and vias 86 may be formed using any suitable process, such as a single damascene process, a double damascene process, a plating process, combinations thereof, or the like. An example of forming the metallization structures and vias 86 using a damascene process includes etching dielectric layers 82 and 84 to form openings, depositing a conductive barrier layer into the openings, plating a metallic material, such as copper or a copper alloy, and performing planarization to remove the excess portions of the metallic material.In other embodiments, the formation of the dielectric layers 82 and 84 and the metallization structures and vias 86 may include forming the dielectric layer 82 or 84, patterning the dielectric layer 82 or 84 to form openings, forming a metal growth layer (not shown), forming a patterned plating mask (such as a photoresist) to cover some portions of the metal growth layer while leaving other portions exposed, plating the metallization structures and vias 86, removing the plating mask, and etching unwanted portions of the metal growth layer.

[0030] Fig. 14 further illustrates dielectric layers 90 formed on the interconnect structure 80. Although Fig. 14 illustrates two dielectric layers 90, more or fewer than two dielectric layers 90 may be formed. Bond pad vias 92 and bond pads 94 are formed in the dielectric layers 90. The bond pad vias 92 and bond pads 94 may be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, combinations thereof, or the like. The top surfaces of the bond pads 94 are coplanar with the top surface of the topmost dielectric layer 90. Planarization is achieved by a CMP process or a mechanical grinding process. The bond pads 94 may, for example, be formed from copper or include copper.

[0031] According to some embodiments, the integrated circuit die 20A is formed as shown in Fig. 15, by thinning the substrate 22 prior to the subsequent dicing process. The thinning may be performed by a planarization process, such as a mechanical grinding process or a CMP process. The thinning process exposes the TSV 64A. After thinning, the via 64A provides electrical connection from a backside of the substrate 22 to a frontside of the substrate 22 (e.g., the interconnects 24 / 80 / 90).

[0032] With reference to Fig. 16, the integrated circuit die 20A is bonded to a package structure 100. The bonding of the integrated circuit die 20A to the package structure 100 can be achieved by hybrid bonding, in which both direct metal-to-metal bonding (between the bond pads 94 and 106) and dielectric-to-dielectric bonding (such as Si-O-Si bonding between dielectric surface layers of the integrated circuit die 20A and the package structure 100) are formed. Furthermore, there may be a single integrated circuit die 20A or a plurality of dies 20A bonded to the same package structure 100. The plurality of dies 20A bonded to the same package structure 100 can be identical or different dies from one another to form a homogeneous or a heterogeneous structure.

[0033] The package structure 100 includes a substrate 102 similar to the substrate 22 of the integrated circuit die 20A, and an interconnect structure 104 including bond pads 106. The interconnect structure 104 and the bond pads 106 may be similar to the interconnect structures 24 / 80 / 90 and bond pads 94 described above, respectively, and their descriptions are not repeated herein. The interconnect structure 104 may be formed, for example, by metallization structures in dielectric layers on the ILD. The metallization structures include metal lines and vias formed in one or more low-k dielectric layers. The metallization structures may be formed using any suitable process, such as a single damascene process, a double damascene process, a plating process, combinations thereof, or the like.An example of forming the metallization structures by a damascene process includes etching the dielectric layers to form openings, depositing a conductive barrier layer into the openings, plating a metallic material such as copper or a copper alloy, and performing planarization to remove the excess portions of the metallic material.

[0034] The die 20A is arranged upside down such that the front sides of the die 20A face the package structure 100 and the back sides of the dies 20A face away from the package structure 100. The die 20A is bonded to the package structure 100 at an interface 108. As shown in Fig. 16, the hybrid bonding process bonds the topmost dielectric layer of interconnect 104 of package structure 100 directly to the topmost dielectric layer 90 of die 20A at interface 108 by fusion bonding. In one embodiment, the bond between the topmost dielectric layer of interconnect 104 and the topmost dielectric layer 90 of die 20A may be an oxide-to-oxide bond. The hybrid bonding process further bonds the bond pads 94 of die 20A to the bond pads 106 of package structure 100 at interface 108 by direct metal-to-metal bonding. Thus, the electrical connection between die 20A and package structure 100 may be provided by the physical connection of bond pads 94 to bond pads 106.

[0035] The hybrid bonding process starts, for example, with aligning the die 20A with the package structure 100, for example, by aligning the bond pads 94 with the bond pads 106. Once the die 20A and the package structure 100 are aligned, the bond pads 94 may overlap the corresponding bond pads 106. Next, the hybrid bonding includes a pre-bonding step in which the die 20A is brought into contact with the package structure 100. The hybrid bonding process continues by performing an anneal, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the copper in the bond pads 94 and the bond pads 106 diffuses together, thus forming the direct metal-to-metal bond.

[0036] Next, as in Fig. 17, a gap-fill process is performed to encapsulate the integrated circuit die 20A in an encapsulant 110. Once formed, the encapsulant 110 encapsulates the integrated circuit die 20A, the interconnect structure 80, and the dielectric layers 90. The encapsulant 110 may comprise an oxide. Alternatively, the encapsulant may be a mold composite, a mold underfill, a resin, an epoxy, or the like. The encapsulant 110 may be applied by compression molding, transfer molding, or the like, and may be applied in a liquid or semi-liquid form and then subsequently cured. After the encapsulant 110 is deposited, a planarization process is performed to level a back surface of the integrated circuit die 20A with the top surface of the encapsulant 110 and to expose the TSVs 64A.Surfaces of the TSVs 64A, the substrate 22, and the encapsulant 110 are substantially coplanar after the planarization process, subject to process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In some embodiments, planarization may be omitted, for example, if the TSVs 64A are already exposed.

[0037] In Fig. 18, a redistribution structure 112 is deposited on the encapsulant 110, the TSVs 64A, and the integrated circuit die 20A. The redistribution structure 112 may include redistribution lines (RDLs), such as metal traces (or metal lines) and vias underlying and connected to the metal traces. The redistribution lines of the redistribution structure 112 are physically and electrically connected to the TSVs 64A of the die 20A.

[0038] According to some embodiments of the present disclosure, the RDLs are formed by plating processes, wherein each of the RDLs includes a growth layer (not shown) and a plated metallic material over the growth layer. The growth layer may be formed, for example, using PVD or the like. Then, a photoresist is formed and patterned on the growth layer. The photoresist may be formed by spin coating or the like and exposed for patterning. The pattern of the photoresist corresponds to the RDLs. The patterning forms openings through the photoresist to expose the growth layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the growth layer. The conductive material may be formed by plating, such as electroplating or electroless plating or the like.The growth layer and the plated metallic material can be formed from the same or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the growth layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the growth layer are removed, such as using an acceptable etching process, such as wet and / or dry etching. The remaining portions of the growth layer and the conductive material form the RDLs.

[0039] Dielectric or passivation layers can be formed over each layer of metal traces. In some embodiments, the dielectric or passivation layers are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. In other embodiments, the dielectric or passivation layers are formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric or passivation layers can be formed by spin coating, lamination, CVD, the like, or a combination thereof.

[0040] Openings may be formed in the upper dielectric or passivation layer via a patterning process, exposing part or all of the upper metal layer of the redistribution structure 112. The patterning process may be any acceptable process, such as exposing the dielectric or passivation layer if the dielectric layer is a photosensitive material, or by etching, for example, using anisotropic etching.

[0041] As in Fig. 19, bumps 114 are formed through the openings in the dielectric layers of the redistribution structure 112 to contact metallization structures in the redistribution structure 112. The bumps 114 may be metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, ball grid array (BGA) bumps, or the like. In one embodiment, the bumps 114 are C4 bumps. The bumps 114 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The bumps 114 may also be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the bumps 114.The metal top layer may contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

[0042] Further in Fig. 19 conductive connectors 116 are formed on the bumps 114. The conductive connectors 116 can be formed from a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 116 are formed by initially forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a solder layer is formed on the structure, reflow can be performed to form the conductive connectors 116 into the desired bump shapes.

[0043] The Fig. The embodiment shown in Figure 19 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 20A and the package structure 100 may be bonded in a face-to-back configuration. The backside of the die 20A (e.g., exposed ends of the TSVs 64A and the substrate 22) could, for example, be bonded to the frontside of the package structure 100.

[0044] Fig. Figure 20 illustrates a cross-sectional view of a wafer-on-wafer structure according to some embodiments. This embodiment is similar to the one shown in Fig. 1 to 19, except that this embodiment is a wafer-on-wafer structure rather than a chip-on-wafer structure. Details of this embodiment that are similar to those of the previously described embodiment are not repeated herein.

[0045] In Fig. 20 is a wafer-on-wafer structure bonded in a face-to-face configuration, where the upper structure is a wafer 20A. The wafer 20A is formed in a similar manner to the die 20A described above, and the description will not be repeated here. In this embodiment, the steps of singulating the die 20A and forming the encapsulant 110 in the previous embodiment are no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 20A and the package structure 100 are both wafers and have the same size.

[0046] In other embodiments, wafer 20A may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 20A (e.g., exposed ends of TSVs 64A and substrate 22) could be bonded to the frontside of package structure 100.

[0047] Fig. Figures 21 to 25 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the one shown in Fig. 1 to 19, except that in this embodiment, the TSV 64B is formed after the connection 80 (e.g., a TSV-last process) and not before the connection 80 as in the embodiment of Fig. 1 to 19 (e.g., a TSV middle process). Details of this embodiment that are similar to those of the previously described embodiments are not repeated here.

[0048] Fig. Figure 21 illustrates a cross-sectional view of an integrated circuit die 20B according to some embodiments. The integrated circuit die 20B may be formed using similar processes and materials as the integrated circuit die 20A described above, and the description will not be repeated herein.

[0049] A passivation layer 88 is formed over the interconnect structure 80. The passivation layer 88 may be formed from a silicon-containing oxide. For example, the passivation layer 88 may contain an oxide such as silicon oxide, a nitride such as silicon nitride, or the like.

[0050] In Fig. 22, after forming the passivation layer 88, a TSV 64B is formed through the passivation layer 88, the interconnects 80 and 24, and at least partially into the substrate 22. The TSV 64B may be formed using similar processes and materials as the TSV 64A described above, and the description will not be repeated herein.

[0051] One of the final steps of forming the TSV 64B is a planarization process (similar to that described above with reference to TSV 64A) to remove portions of the conductive material 62, the growth layer 60, the liner layer 50, the passivation layer 40, and the stop layer 30 outside the opening 34. Upper surfaces of the TSV 64B and the passivation layer 88 are substantially coplanar after the planarization process, subject to process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. The upper portion of the TSV 64B has a greater width than the lower portion of the TSV 64B (formed in the substrate 22). As shown in Fig. 22, the passivation layer 40 has a cup shape with a bottom hole.

[0052] Fig. Figure 23 illustrates dielectric layers 90, bond pad vias 92, and bond pads 94 formed on the passivation layer 88 and the TSV 64B. These structures have been previously described, and the descriptions will not be repeated here. In this embodiment, one or more of the bond pad vias 92 may be in physical and electrical contact with the TSV 64B, while other bond pad vias 92 may be in physical and electrical contact with the metallization structures of the interconnect 80.

[0053] In Fig. 24, the integrated circuit die 20B is thinned by thinning the substrate 22 prior to the subsequent dicing process. This thinning process was described above with reference to TSV 64A, and the description will not be repeated here.

[0054] Fig. 25 illustrates subsequent processing of the integrated circuit die 20B in Fig. 24. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0055] The Fig. The embodiment shown in Figure 25 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 20B and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 20B (e.g., exposed ends of the TSVs 64B and the substrate 22) could be bonded to the frontside of the package structure 100.

[0056] Fig. Figure 26 illustrates a cross-sectional view of a wafer-on-wafer structure according to some embodiments. This embodiment is similar to the one shown in Fig. 21 to 25, except that this embodiment is a wafer-on-wafer structure rather than a chip-on-wafer structure. Details of this embodiment that are similar to those of the previously described embodiments are not repeated herein.

[0057] In Fig. 26 is a wafer-on-wafer structure bonded in a face-to-face configuration in which the upper structure is a wafer 20B. The wafer 20B is formed in a similar manner to the die 20B described above, and the description will not be repeated here. In this embodiment, the steps of singulating the die 20B and forming the encapsulant 110 in the previous embodiment are no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 20B and the package structure 100 are both wafers and have the same size.

[0058] In other embodiments, wafer 20B may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 20B (e.g., exposed ends of TSVs 64B and substrate 22) could be bonded to the frontside of package structure 100.

[0059] Fig. Figures 27 to 33 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 1 to 19, except that this embodiment includes a non-conformal passivation layer. Details of this embodiment that are similar to those of the previously described embodiments are not repeated herein.

[0060] Fig. Figure 27 illustrates an intermediate stage of processing according to the method described in Fig. 5 and the description of the formation of this intermediate processing stage is not repeated here. Fig. Figure 27 is a cross-sectional view of an integrated circuit die 120A according to some embodiments. The integrated circuit die 120A is similar to the integrated circuit die 20A, and the description will not be repeated herein.

[0061] Further on in Fig. 27 a passivation layer 180 non-conformal on the stop layer 30 and on the bottom surface and the side walls of the opening 34 (see Fig. 5). The passivation layer 180 has a thickness of about 0.5 µm to about 5 µm. In some embodiments, the non-conformal passivation layer 180 is an oxide deposited by a PECVD process, high-density plasma CVD (HDP-CVD), the like, or a combination thereof. In one embodiment, the non-conformal passivation layer 180 is a layer of undoped silicate glass (USG). The non-conformal deposition of the passivation layer 180 results in an air gap or cavity 181 in the opening 34.

[0062] As in Fig. As illustrated in Figure 28, a photoresist 182 is formed and patterned on the non-conformal passivation layer 180. The photoresist 182 may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to a lower portion of a later-formed TSV. The patterning forms at least one opening through the photoresist 182 to expose the non-conformal passivation layer 180.

[0063] The remaining photoresist 182 serves as a mask during a subsequent etching process to remove portions of the passivation layer 180. The etching process to remove portions of the non-conformal passivation layer 180 forms an opening 184, as shown in Fig. 29. The substrate 22 is exposed at the bottom of the opening 184.

[0064] The photoresist 182 serves as a mask during a further subsequent etching process to remove portions of the substrate 22, as in Fig. 30. The etching process for removing portions of the substrate 22 increases the depth of the opening 184. The opening 184 in the substrate 22 may have a depth of about 5 µm to 10 µm.

[0065] Because the passivation layer 180 covers the exposed sidewalls of the interconnect 24 in the opening 184 during the process of forming and expanding the opening 184, potential contamination from the etching process for the opening 184 is prevented by blocking penetration into the interconnect 24. By blocking the contamination, damage to the metallization structures of the interconnect structures, for example, from sulfur used to etch the substrate vias, is prevented.

[0066] In Fig. 31, after etching the opening 184, a TSV 164A is formed in the opening 184 through the interconnect 24 and at least partially into the substrate 22. The TSV 164A may be formed using similar processes and materials as the TSV 64A described above, and the description will not be repeated herein.

[0067] One of the final steps of forming TSV 164A is a planarization process (similar to that described above with reference to TSV 64A) to remove portions of conductive material 62, growth layer 60, liner layer 50, passivation layer 180, and stop layer 30 outside of opening 34. Top surfaces of TSV 164A, passivation layer 180, and liner layer 50 are substantially coplanar after the planarization process, subject to process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In this embodiment, because the same mask (e.g., photoresist 182) was used to etch the openings in interconnect 24 and substrate 22, TSV 164A has a substantially constant width along the entire length of TSV 164A.

[0068] Fig. 32 illustrates subsequent processing of the integrated circuit die 120A in Fig. 31. This subsequent processing is the Fig. 14 and Fig. 15 is similar to the processing illustrated and described and the description is not repeated here.

[0069] Fig. 33 illustrates subsequent processing of the integrated circuit die 120A in Fig. 32. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0070] The Fig. The embodiment shown in Figure 33 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 120A and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 120A (e.g., exposed ends of the TSVs 164A and the substrate 22) could be bonded to the frontside of the package structure 100.

[0071] In Fig. 34, the structure is a wafer-on-wafer structure bonded in a face-to-face configuration, where the top structure is a wafer 120A. The wafer 120A is formed in a similar manner to the die 120A described above, and the description will not be repeated here. In this embodiment, the steps of singulating the die 120A and forming the encapsulant 110 in the previous embodiment are no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 120A and the package structure 100 are both wafers and have the same size.

[0072] In other embodiments, wafer 120A may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 120A (e.g., exposed ends of TSVs 164A and substrate 22) could be bonded to the frontside of package structure 100.

[0073] Fig. 35 to 36 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 27 to 33, except that this embodiment is a TSV-last process (similar to the one described above in Fig. 21 to 25) and not a TSV middle process as in Fig. 27 to 33. Details of this embodiment that are similar to those of the previously described embodiments are not repeated here.

[0074] Fig. 35 illustrates a cross-sectional view of an integrated circuit die 120B according to some embodiments. The integrated circuit die 120B may be formed using similar processes and materials as the integrated circuit die 120A described above, and the description will not be repeated herein.

[0075] The connections 80 and 90 and passivation layer 88 are formed by similar processes and materials as the embodiment in Fig. 21 to 25 and the description is not repeated here. In addition, the TSV 164B, similar to the embodiment in Fig. 21 to 25, after and through the connection 80 and the passivation layer 88 and the description is not repeated here.

[0076] Fig. 35 illustrates an intermediate stage of processing according to the method described above for Fig. 24 and the description of the formation of this processing intermediate is not repeated here.

[0077] Fig. 36 illustrates subsequent processing of the integrated circuit die 120B in Fig. 35. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0078] The Fig. The embodiment shown in Figure 36 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 120B and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 120B (e.g., exposed ends of the TSVs 164B and the substrate 22) could be bonded to the frontside of the package structure 100.

[0079] In Fig. 37 shows a wafer-on-wafer structure bonded in a face-to-face configuration, where the top structure is a wafer 120B. The wafer 120B is formed in a similar manner to the die 120B described above, and the description will not be repeated here. In this embodiment, the steps of singulating the die 120B and forming the encapsulant 110 in the previous embodiment are no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 120B and the package structure 100 are both wafers and have the same size.

[0080] In other embodiments, wafer 120B may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 120B (e.g., exposed ends of TSVs 164B and substrate 22) could be bonded to the frontside of package structure 100.

[0081] Fig. 38 to 43 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 1 to 19, except that this embodiment includes selective deposition of a passivation layer. Details of this embodiment that are similar to those of the previously described embodiments are not repeated herein.

[0082] Fig. Figure 38 illustrates an intermediate stage of processing according to the method described above for Fig. 5 and the description of the formation of this processing intermediate is not repeated here. Fig. Figure 38 shows a cross-sectional view of an integrated circuit die 220A according to some embodiments. The integrated circuit die 220A is similar to the integrated circuit die 20A, and the description is not repeated here.

[0083] Furthermore, in Fig. 38 the opening 34 in Fig. 5 to form opening 234 after a subsequent etching process to remove portions of the substrate 22 using the photoresist 32 as a mask. The opening 234 in the substrate 22 may have a depth of approximately 5 µm to 10 µm.

[0084] In Fig. 39, a burn-in process 38 is performed. The burn-in process 38 is similar to the burn-in process 36 described above, and the description will not be repeated here. The burn-in process 38 can help remove moisture and liquid from the openings 234 that have accumulated during the etching process for the openings 34 and 234 and the processing of the photoresist 32. Even if the sidewalls of the interconnect 24 were exposed during the formation of the opening 234 and during the processing of the photoresist 32, the additional burn-in process 38 removes the remaining moisture and liquid and can help prevent damage to the interconnect structure 24.

[0085] In Fig. 40, the passivation layer 40 is selectively deposited on the stop layer 30 and on the exposed sidewalls of the connection 24 in the opening 234. The passivation layer 40 can help to facilitate the diffusion of the materials of the subsequently formed substrate vias 26,4A (see, for example, Fig. 41) into the interconnect 24 during subsequent processing. In some embodiments, the exposed sidewalls and bottom of the substrate in the opening 234 are substantially free of the passivation layer 40. In some embodiments, the passivation layer 40 may partially cover the exposed sidewalls and bottom of the substrate in the opening 234 while completely covering the exposed interconnect 24 in the opening 234. In some embodiments, the passivation layer 40 may decrease in thickness on the sidewall of the opening 234 when moving from a top of the opening 234 (e.g., near the stop layer 30) to a bottom of the opening 234 (e.g., near the bottom surface in the substrate 22).

[0086] In some embodiments, the passivation layer 40 may comprise silicon nitride or the like, and may, for example, have a dielectric constant in a range of about 6.5 to about 8. The passivation layer 40 may be conformally deposited and formed using a deposition process such as CVD, PECVD, ALD, plasma-enhanced ALD (PEALD), the like, or a combination thereof. The passivation layer 40 may be deposited to a thickness of about 0.05 μm to about 0.5 μm.

[0087] In Fig. 41, after forming the selective passivation layer 40, a TSV 264A is formed in the opening 234 through the interconnect 24 and at least partially into the substrate 22. The TSV 264A may be formed using similar processes and materials as the TSV 64A described above, and the description will not be repeated herein.

[0088] One of the final steps of forming TSV 264A is a planarization process (similar to that described above with reference to TSV 64A) to remove portions of conductive material 62, growth layer 60, liner layer 50, passivation layer 40, and stop layer 30 outside of opening 234. Top surfaces of TSV 264A, passivation layer 40, and liner layer 50 are substantially coplanar after the planarization process, subject to process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In this embodiment, because the same mask (e.g., photoresist 32) was used to etch the openings in interconnect 24 and substrate 22, TSV 264A has a substantially constant width along the entire length of TSV 264A.

[0089] Fig. 42 illustrates subsequent processing of the integrated circuit die 220A in Fig. 41. This subsequent processing is the Fig. 14 and Fig. 15 is similar to the processing illustrated and described and the description is not repeated here.

[0090] Fig. 43 illustrates subsequent processing of the integrated circuit die 220A in Fig. 42. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0091] The Fig. The embodiment shown in Figure 43 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 220A and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 220A (e.g., exposed ends of the TSVs 264A and the substrate 22) could be bonded to the frontside of the package structure 100.

[0092] In Fig. 44, the structure is a wafer-on-wafer structure bonded in a face-to-face configuration, where the top structure is a wafer 220A. The wafer 220A is formed in a similar manner to the die 220A described above, and the description will not be repeated here. In this embodiment, the singulation step of singulating the die 220A and forming the encapsulant 110 in the previous embodiment is no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 220A and the package structure 100 are both wafers and have the same size.

[0093] In other embodiments, wafer 220A may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 220A (e.g., exposed ends of TSVs 264A and substrate 22) could be bonded to the frontside of package structure 100.

[0094] Fig. 45 to 46 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 38 to 43, except that this embodiment is a TSV-last process (similar to the one described above in Fig. 21 to 25) and not a TSV middle process as in Fig. 38 to 43. Details of this embodiment that are similar to those of the previously described embodiments are not repeated here.

[0095] Fig. 45 illustrates a cross-sectional view of an integrated circuit die 220B according to some embodiments. The integrated circuit die 220B may be formed using similar processes and materials as the integrated circuit die 220A described above, and the description will not be repeated herein.

[0096] The connections 80 and 90 and passivation layer 88 are formed by similar processes and materials as the embodiment in Fig. 21 to 25 and the description is not repeated here. In addition, the TSV 264B, similar to the embodiment in Fig. 21 to 25, after and through the connection 80 and the passivation layer 88 and the description is not repeated here.

[0097] Fig. 45 illustrates an intermediate stage of processing according to the method described above for Fig. 24 and the description of the formation of this processing intermediate is not repeated here.

[0098] Fig. 46 illustrates subsequent processing of the integrated circuit die 220B in Fig. 45. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0099] The Fig. The embodiment shown in Figure 46 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 220B and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 220B (e.g., exposed ends of the TSVs 264B and the substrate 22) could be bonded to the frontside of the package structure 100.

[0100] In Fig. 47 shows a wafer-on-wafer structure bonded in a face-to-face configuration, in which the upper structure is a wafer 220B. The wafer 220B is formed in a similar manner to the die 220B described above, and the description will not be repeated here. In this embodiment, the singulation step of singulating the die 220B and forming the encapsulant 110 in the previous embodiment is no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 220B and the package structure 100 are both wafers and have the same size.

[0101] In other embodiments, wafer 220B may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 220B (e.g., exposed ends of TSVs 264B and substrate 22) could be bonded to the frontside of package structure 100.

[0102] Fig. 48 to 53 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 1 to 19, except that this embodiment includes a passivation layer only on the sidewalls of the interconnect 24 in the TSV opening, and the TSV also has a substantially constant width across the entire length of the TSV. Details of this embodiment that are similar to those of the previously described embodiments are not repeated herein.

[0103] Fig. Figure 48 illustrates an intermediate stage of processing according to the method described above for Fig. 6 and the description of the formation of this processing intermediate is not repeated here. Fig. Figure 48 shows a cross-sectional view of an integrated circuit die 320A according to some embodiments. The integrated circuit die 320A is similar to the integrated circuit die 20A, and the description is not repeated here.

[0104] In Fig. 48, the passivation layer 40 is Fig. 5. The opening 334 in the substrate 22 may have a depth of approximately 5 µm to 10 µm. The patterned passivation layer 40 may help facilitate the diffusion of the materials of the subsequently formed substrate vias 264A (see, for example, Fig. 41) into the connection 24 during subsequent processing.

[0105] In some embodiments, the passivation layer 40 is patterned to be separated from horizontal surfaces of the structure in Fig. 5 such that the passivation layer 40 forms spacers along the sidewalls of the interconnect 24 in the opening 34. In some embodiments, the passivation layer 40 is formed using an etching process, such as an anisotropic etching process.

[0106] In Fig. 49 the opening 34 in Fig. 48 to form opening 334 after a further etching process to remove portions of the substrate 22 using the photoresist stop layer 30 and the patterned passivation layer 40.

[0107] Because the patterned passivation layer 40 covers the exposed sidewalls of the interconnect 24 in the opening 34 during the process of forming the opening 334, potential contamination from the etching process is prevented by blocking penetration into the interconnect 24 for the opening 334. By blocking the contamination, damage to the metallization structures of the interconnect structures, for example, from sulfur used to etch the substrate vias, is prevented.

[0108] In Fig. 50, a burn-in process 38 is performed. The burn-in process 38 is similar to the burn-in process 38 described above, and the description will not be repeated here. The burn-in process 38 can help remove moisture and liquid from the openings 334 that have accumulated during the etching process for the openings 34 and 334.

[0109] In Fig. 51, after the burn-in process 38, a TSV 364A is formed in the opening 334 through the interconnect 24 and at least partially into the substrate 22. The TSV 364A may be formed using similar processes and materials as the TSV 64A described above, and the description will not be repeated herein.

[0110] One of the final steps of forming TSV 364A is a planarization process (similar to that described above with reference to TSV 64A) to remove portions of conductive material 62, growth layer 60, liner layer 50, passivation layer 40, and stop layer 30 outside of opening 334. Top surfaces of TSV 364A, passivation layer 40, and liner layer 50 are substantially coplanar after the planarization process, subject to process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In this embodiment, because the same mask (e.g., stop layer 30 and passivation layer 40) was used to etch the openings in interconnect 24 and substrate 22, TSV 364A has a substantially constant width along the entire length of TSV 364A.

[0111] Fig. 52 illustrates subsequent processing of the integrated circuit die 320A in Fig. 41. This subsequent processing is the Fig. 14 and Fig. 15 is similar to the processing illustrated and described and the description is not repeated here.

[0112] Fig. 53 illustrates subsequent processing of the integrated circuit die 320A in Fig. 52. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0113] The Fig. The embodiment shown in Figure 53 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 320A and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 320A (e.g., exposed ends of the TSVs 364A and the substrate 22) could be bonded to the frontside of the package structure 100.

[0114] In Fig. 54, the structure is a wafer-on-wafer structure bonded in a face-to-face configuration, where the top structure is a wafer 320A. The wafer 320A is formed in a similar manner to the die 320A described above, and the description will not be repeated here. In this embodiment, the singulation step of singulating the die 320A and forming the encapsulant 110 in the previous embodiment is no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 320A and the package structure 100 are both wafers and have the same size.

[0115] In other embodiments, wafer 320A may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 320A (e.g., exposed ends of TSVs 364A and substrate 22) could be bonded to the frontside of package structure 100.

[0116] Fig. 55 to 56 illustrate cross-sectional views of intermediate stages in the formation of a multi-stack die package according to one embodiment. This embodiment is similar to the Fig. 48 to 53, except that this embodiment is a TSV-last process (similar to the one described above in Fig. 21 to 25) and not a TSV middle process as in Fig. 48 to 53. Details of this embodiment that are similar to those of the previously described embodiments are not repeated here.

[0117] Fig. Figure 55 illustrates a cross-sectional view of an integrated circuit die 320B according to some embodiments. The integrated circuit die 320B may be formed using similar processes and materials as the integrated circuit die 320A described above, and the description will not be repeated herein.

[0118] The connections 80 and 90 and passivation layer 88 are formed by similar processes and materials as the embodiment in Fig. 21 to 25 and the description is not repeated here. In addition, the TSV 364B, similar to the embodiment in Fig. 21 to 25, after and through the connection 80 and the passivation layer 88 and the description is not repeated here.

[0119] Fig. Figure 55 illustrates an intermediate stage of processing according to the method described above for Fig. 24 and the description of the formation of this processing intermediate is not repeated here.

[0120] Fig. 56 illustrates subsequent processing of the integrated circuit die 320B in Fig. 55. This subsequent processing is the Fig. 16 to 19 and the description is not repeated here.

[0121] The Fig. The embodiment shown in Figure 56 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 320B and the package structure 100 may be bonded in a face-to-back configuration. For example, the backside of the die 320B (e.g., exposed ends of the TSVs 364B and the substrate 22) could be bonded to the frontside of the package structure 100.

[0122] In Fig.57 shows a wafer-on-wafer structure bonded in a face-to-face configuration, in which the upper structure is a wafer 320B. The wafer 320B is formed in a similar manner to the die 320B described above, and the description will not be repeated here. In this embodiment, the singulation step of singulating the die 320B and forming the encapsulant 110 in the previous embodiment is no longer required, and these steps can be omitted from this embodiment. In this embodiment, the wafer 320B and the package structure 100 are both wafers and have the same size.

[0123] In other embodiments, wafer 320B may be bonded to package structure 100 in a face-to-back configuration. For example, the backside of wafer 320B (e.g., exposed ends of TSVs 364B and substrate 22) could be bonded to the frontside of package structure 100.

[0124] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of the 3D assemblies or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enables testing of the 3D packaging or the 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0125] Embodiments may achieve advantages. The device structure includes a passivation layer between a through-substrate via (TSV) and the interconnect or redistribution structure to prevent ingress of contaminants into the interconnect or redistribution structure that may occur during formation of the via. In some embodiments, the passivation layer may include a nitride layer, an undoped silicate glass (USG) layer, the like, or a combination thereof. The contaminants from the formation of the substrate via may include liquid or moisture used in the formation of the substrate via and / or chemicals, such as sulfur, used during the etching of the substrate via.In conventional structures, these contaminants can penetrate the exposed sidewalls of the interconnect layers during substrate via formation and damage the metallization structures and dielectric layers of the interconnect. Blocking the contaminants can prevent damage to the metallization structures of the interconnect layers due to the contaminants.

[0126] One embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization structures therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate and forming a through-substrate via.

[0127] Embodiments may include one or more of the following features. The method, wherein the second opening has a smaller diameter than the first opening. The second opening has an equal diameter to the first opening. The method further includes forming a second interconnect structure over the first interconnect structure and the substrate via, the second interconnect structure including dielectric layers and metallization structures therein, the metallization structures of the second interconnect structure being electrically connected to the metallization structures of the first interconnect structure and to the substrate via and forming a first dielectric layer over the second interconnect structure, and forming first bond pads in the first dielectric layer, the first bond pads being electrically coupled to the metallization structures of the second interconnect structure.The method further includes hybrid bonding the first dielectric layer and the first bond pads to a second dielectric layer and second bond pads of a package structure, the package structure including a second substrate and a third interconnect structure over the second substrate, the second dielectric layer and the second bond pads being part of the third interconnect structure.The method further includes, after hybrid bonding the first dielectric layer and the first bond pads to the second dielectric layer and the second bond pads of the package structure, forming a first redistribution structure over the first substrate and the substrate via, the first redistribution structure including dielectric layers and metallization structures therein, the metallization structures of the first redistribution structure being electrically coupled to the substrate via, and forming a first set of conductive bumps over and in electrical coupling with the first redistribution structure. The method further includes, prior to forming the first redistribution structure, encapsulating the first substrate, the first interconnect structure, the second interconnect structure, and the first dielectric layer with an encapsulant, the first redistribution structure being formed over the encapsulant.The barrier layer is silicon nitride, while the liner is an oxide. The barrier layer is located only on the sidewalls of the first opening.

[0128] One embodiment includes forming a first dielectric layer over a first substrate, the first dielectric layer having a first metallization structure therein. The method further includes forming a first patterned mask over the first dielectric layer. The method further includes performing a first etch process using the first patterned mask as a mask, wherein the first etch process forms a first opening through the first dielectric layer to expose a first portion of the first substrate. The method further includes performing a second etch process using the first patterned mask as a mask, wherein the second etch process etches the exposed first portion of the first substrate to form a second opening in the first substrate, the second opening having a same diameter as the first opening.The method further includes selectively depositing a barrier layer on exposed sidewalls of the first dielectric layer in the first opening, wherein sidewalls of the second opening are free of the barrier layer. The method further includes forming a liner on the barrier layer in the first opening and on the sidewalls of the first substrate in the second opening. The method further includes filling the first opening and the second opening with a conductive material. The method further includes thinning the first substrate to expose a portion of the conductive material in the second opening, wherein the conductive material extends through the first dielectric layer and the first substrate forms a through-substrate via.

[0129] Embodiments may include one or more of the following features. The method, wherein the barrier layer is silicon nitride and wherein the liner is an oxide.The method further includes forming a second dielectric layer over the first dielectric layer and the substrate via, the second dielectric layer having a second metallization structure therein, the second metallization layer being electrically coupled to the first metallization structure and the substrate via, forming a third dielectric layer over the second dielectric layer and forming first bond pads in the third dielectric layer, the first bond pads being electrically coupled to the second metallization structure, and hybrid bonding the third dielectric layer and the first bond pads to a fourth dielectric layer and second bond pads of a package structure, the package structure including a second substrate.The method further includes, after hybrid bonding the third dielectric layer and the first bond pads to the fourth dielectric layer and the second bond pads of the package structure, encapsulating the first substrate, the first dielectric layer, the second dielectric layer, and the third dielectric layer with an encapsulant, forming a first redistribution structure over the first substrate, the substrate via, and the encapsulant, the first redistribution structure including dielectric layers and metallization structures therein, the metallization structures of the first redistribution structure being electrically coupled to the substrate via, and forming a first set of conductive bumps over and in electrical coupling with the first redistribution structure. The conductive material has a smaller width in the first opening than in the second opening.The method further includes, prior to selectively depositing the barrier layer on exposed sidewalls of the first dielectric layer in the first opening, performing a burn-in process on at least the first opening and the second opening.

[0130] One embodiment includes a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization structures therein. The structure also includes a substrate via extending through the first interconnect structure and the first substrate, the substrate via including a conductive material extending through the first interconnect structure and the first substrate. The structure also includes a barrier layer between the first interconnect structure and the conductive material. The structure also includes a liner between the barrier layer and the first substrate.

[0131] Embodiments may include one or more of the following features: The structure, wherein the barrier layer is in physical contact with the first interconnect structure and wherein the liner is in physical contact with the first substrate. The barrier layer is silicon nitride, wherein the liner is an oxide. The barrier layer is undoped silicate glass (USG), and the liner is an oxide.

Claims

[1] Method comprising: Forming a first interconnect structure (24) over a first substrate (22), the first interconnect structure (24) comprising dielectric layers and metallization structures therein; Structuring the first interconnect structure (24) to form a first opening (34) exposing a portion of the first substrate (22); Coating the first opening (34) with a barrier layer (40); Forming and patterning a photoresist (42), wherein patterning the photoresist (42) forms an opening through the photoresist to expose the barrier layer (40) at a bottom of the first opening (34); Etching a second opening (44) through the barrier layer (40) and the exposed portion of the first substrate (22), wherein the patterned photoresist (42) serves as a mask for removing the exposed portion; Depositing a liner (50) in the first opening (34) and the second opening (44), the liner (50) being in physical contact with the barrier layer (40); Filling the first opening (34) and the second opening (44) with a conductive material (63); Thinning the first substrate (22) to expose a portion of the conductive material (64) in the second opening (44), the conductive material (64) extending through the first interconnect structure (24) and the first substrate (22) and forming a substrate via (64A, 264A); Forming a second interconnect structure (80) over the first interconnect structure (24) and the substrate via (64A, 264A), the second interconnect structure (80) comprising dielectric layers (82, 84, 90) and metallization structures therein, the metallization structures of the second interconnect structure (80) being electrically coupled to the metallization structures of the first interconnect structure (24) and to the substrate via (64A, 264A); Forming a first dielectric layer (90) over the second interconnect structure (80); and Forming first bond pads (94) in the first dielectric layer (90), wherein the first bond pads (94) are electrically coupled to the metallization structures of the second interconnect structure (80). [2] The method of claim 1, wherein the second opening (44) has a smaller diameter than the first opening (34). [3] The method of claim 1, wherein the substrate via (64A, 264A) after thinning provides an electrical connection from a backside of the substrate (22) to a frontside of the substrate (22). [4] Method according to one of the preceding claims, wherein the thinning of the first substrate (22) is carried out before a subsequent dicing process. [5] The method of claim 1, further comprising: Hybrid bonding the first dielectric layer (90) and the first bond pads (94) to a second dielectric layer and second bond pads (106) of a package structure (100), wherein the package structure (100) comprises a second substrate (102) and a third interconnect structure (104) over the second substrate (102), wherein the second dielectric layer and the second bond pads (106) are part of the third interconnect structure (104). [6] The method of claim 5, further comprising, after hybrid bonding the first dielectric layer (90) and the first bond pads (94) to the second dielectric layer and the second bond pads (106) of the package structure (100), forming a first redistribution structure (112) over the first substrate (22) and the substrate via (64A, 264A), the first redistribution structure (112) comprising dielectric layers and metallization structures therein, the metallization structures of the first redistribution structure (112) being electrically coupled to the substrate via (64A, 264A); and forming a first set of conductive bumps (114) over and in electrical coupling with the first redistribution structure (112). [7] The method of claim 6, further comprising: prior to forming the first redistribution structure (112), encapsulating the first substrate (22), the first interconnect structure (24), the second interconnect structure (80) and the first dielectric layer (90) with an encapsulant (110), wherein the first redistribution structure (112) is formed over the encapsulant (110). [8] A method according to any one of the preceding claims, wherein the barrier layer (40) is silicon nitride and wherein the liner (50) is an oxide. [9] A method according to any one of the preceding claims, wherein the barrier layer (40) is located only on side walls of the first opening (34). [10] The method of claim 1, further comprising: before coating the first opening (34) with the barrier layer (40), performing a burn-in process on at least the first opening (34) and the exposed portion of the first substrate (22). [11] A method comprising: Forming a first dielectric layer over a first substrate (22), the first dielectric layer having a metallization structure therein; Forming a first patterned mask (32) over the first dielectric layer; Performing a first etching process using the first patterned mask (32) as a mask, the first etching process forming a first opening (34) through the first dielectric layer exposing a first portion of the first substrate (22); Performing a second etching process using the first patterned mask (32) as a mask, wherein the second etching process etches the exposed first portion of the first substrate (22) to form a second opening (44) in the first substrate (22), the second opening (44) having the same diameter as the first opening (34); selectively depositing a barrier layer (40) on exposed sidewalls of the first dielectric layer in the first opening (34), wherein sidewalls of the second opening (44) and a bottom of the substrate (22) in the second opening (44) are partially covered by the barrier layer (40); Forming a liner (50) on the barrier layer (40) in the first opening (34) and on the sidewalls of the first substrate (22) in the second opening; Filling the first opening (34) and the second opening (44) with a conductive material (62); and Thinning the first substrate (22) to expose a portion of the conductive material (62) in the second opening (44), the conductive material (62) extending through the first dielectric layer and the first substrate (22) forming a substrate via (64A, 264A); Forming a second dielectric layer over the first dielectric layer and the substrate via (64A, 264A), wherein the second dielectric layer has a second metallization structure therein, the second metallization structure being electrically coupled to the first metallization structure and the substrate via (64A, 264A); Forming a third dielectric layer over the second dielectric layer; and Forming first bond pads (94) in the third dielectric layer, wherein the first bond pads (94) are electrically coupled to the second metallization structure; and Hybrid bonding the third dielectric layer and the first bond pads (94) to a fourth dielectric layer and second bond pads (106) of a package structure (100), wherein the package structure (100) comprises a second substrate (102). [12] The method of claim 11, wherein the barrier layer (40) is silicon nitride and wherein the liner (50) is an oxide. [13] The method of claim 11 or 12, wherein the substrate via (64A, 264A) after thinning provides an electrical connection from a backside of the substrate (22) to a frontside of the substrate (22). [14] The method of claim 11, further comprising: after hybrid bonding the third dielectric layer and the first bond pads (94) to the fourth dielectric layer and the second bond pads (106) of the package structure (100), encapsulating the first substrate (22), the first dielectric layer, the second dielectric layer and the third dielectric layer with an encapsulant (110); Forming a first redistribution structure (112) over the first substrate (22), the substrate via (64A, 264A), and the encapsulant (110), the first redistribution structure (112) comprising dielectric layers and metallization structures therein, the metallization structures of the first redistribution structure (112) being electrically coupled to the substrate via (64A, 264A); and Forming a first set of conductive bumps (114) over and in electrical coupling with the first redistribution structure (112). [15] The method of any one of claims 11 to 14, wherein the conductive material (62) has a smaller width in the first opening (34) than in the second opening (44). [16] A method according to any one of claims 11 to 15, further comprising: prior to selectively depositing the barrier layer (40) on exposed sidewalls of the first dielectric layer in the first opening (34), performing a burn-in process on at least the first opening (34) and the second opening (44). [17] Structure comprising: a first interconnect structure (24) over a first substrate (22), the first interconnect structure (24) comprising dielectric layers and metallization structures therein; a substrate via (64A, 264A) extending through the first interconnect structure (24) and the first substrate (22), the substrate via (64A, 264A) comprising: a conductive material (62) extending through the first interconnect structure (24) and the first substrate (22); a barrier layer (40) between the first interconnect structure (24) and the conductive material (62) and partially between the conductive material (62) and the first substrate (22); a liner (50) between the conductive material (62) and the first substrate (22); a second interconnect structure (80) over the first interconnect structure (24) and the substrate via (64A, 264A), the second interconnect structure (80) comprising dielectric layers (82, 84, 90) and metallization structures therein, the metallization structures of the second interconnect structure (80) being electrically coupled to the metallization structures of the first interconnect structure (24) and to the substrate via (64A, 264A); a first dielectric layer (90) over the second interconnect structure (80); and first bond pads (94) in the first dielectric layer (90), wherein the first bond pads (94) are electrically coupled to the metallization structures of the second interconnect structure (80). [18] The structure of claim 17, wherein the barrier layer (40) is in physical contact with the first interconnect structure (24) and wherein the liner (50) is in physical contact with the first substrate (22). [19] The structure of claim 17 or 18, wherein the barrier layer (40) is silicon nitride and wherein the liner (50) is an oxide. [20] A structure according to any one of claims 17 to 19, wherein the barrier layer (40) is undoped silicate glass, USG, and wherein the liner (50) is an oxide.

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