TRANSISTORS WITH NANOSTRUCTURES AND MANUFACTURING METHODS

Abstract

Semiconductor device comprising: a first transistor (310) comprising: a plurality of first channel elements (208-3) arranged one above the other and spaced from one another, and a first gate structure (250) enclosing each of the plurality of first channel elements (208-3); and a second transistor (320) comprising: a plurality of second channel elements (208-2) arranged one above the other and spaced from one another, and a second gate structure (250) arranged over the plurality of second channel elements (208-2), wherein each of the plurality of first channel elements (208-3) has a first width (W1) and a first height (H1) which is smaller than the first width, wherein each of the plurality of second channel elements (208-2) has a second width (W2) and a second height (H2) greater than the second width; wherein the first gate structure (250) comprises a first gate dielectric layer (240) in contact with the first channel elements (208-3) and a first gate electrode (242) spaced from the first channel elements, wherein the second gate structure (250) comprises a second gate dielectric layer (240) in contact with the second channel elements (208-2) and a second gate electrode (242) spaced from the second channel elements, wherein the first gate electrode (242) completely encloses each of the plurality of first channel elements (208-3), wherein the second gate electrode (242) does not completely enclose any of the plurality of second channel elements (208-2); and wherein a distance dimension (P) of the plurality of first channel elements (208-3) is identical to a distance dimension (P) of the plurality of second channel elements (208-2).

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs in which each generation features smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process typically provides benefits by increasing production efficiency and reducing associated costs. However, such downsizing has also increased the complexity of IC processing and manufacturing.

[0002] For example, as integrated circuit (IC) technologies evolve toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing turn-off current, and mitigating short-channel effects (SCEs). A multi-gate device typically refers to a device with a gate structure, or a portion of one, disposed over more than one side of a channel region. Fin-type field-effect transistors (FinFETs) and multiple-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high-power, low-leakage applications.A FinFET has a raised channel surrounded by a gate on more than one side (for example, the gate surrounds a top and side wall of a "fin" of semiconductor material extending from a substrate). An MBC transistor has a gate structure that may extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor can also be referred to as a surrounding gate transistor (SGT) or a wrap-around gate (GAA) transistor. The channel region of an MBC transistor can be formed from nanowires, nanosheets, or other nanostructures, which is why an MBC transistor can also be referred to as a nanowire transistor or a nanosheet transistor.

[0003] A channel region of an MBC transistor may have a sheet-like shape, with the channel region's width being greater than its height to improve the drive current of the MBC transistor. Such an MBC transistor may be suitable for a high drive current application, but may not be ideal for other applications where packaging density and cell size are more critical. Therefore, conventional MBC transistors have generally been sufficient for their intended purposes but are not satisfactory in all respects.

[0004] US 2014 / 0210013 A1 describes a semiconductor device comprising a first and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode. The first and second transistors have different dimensions in a first direction, whereas the first and second transistors have the same dimension in a second direction. US 2020 / 0020692 A1 describes a method for fabricating a nanowire channel transistor in a first region of a semiconductor device and a FinFET in a second region of the semiconductor device, wherein a gate electrode of the nanowire channel transistor does not completely surround the nanowire channels. US 2019 / 0355850 A1 also describes the fabrication of a nanowire channel transistor whose gate electrode does not completely surround the nanowire channels. US 2019 / 0371888 A1 describes a method for manufacturing a first and a second gate all-around transistor, in which the nanowire channels of the first gate all-around transistor are trimmed, while the nanowire channels of the second gate all-around transistor are protected by a protective layer. US 2020 / 0043926 A1 describes a method for fabricating gate-all-around nanosheet FETs with adjustable power. The method comprises disposing first and second vertical structures with different widths over a substrate, wherein the first and second vertical structures have an upper portion comprising a multilayer nanosheet stack with alternating first and second nanosheet layers. US 2019 / 0198629 A1 describes a method for manufacturing a device with a FinFET and a Nano-Sheet FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale and are for illustrative purposes only. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. Fig. 1 collectively illustrates a flowchart of a method of forming a semiconductor device having multiple device regions in accordance with one or more aspects of the present disclosure. The Fig. 2A - 26A, 2B - 26B and 15C - 26C show cross-sectional views of a workpiece during a manufacturing process in accordance with the Fig. 1 in accordance with one or more aspects of the present disclosure. The Fig. 27-29 illustrate cross-sectional views of channel elements in accordance with one or more aspects of the present disclosure, wherein the combination of Fig. 27 and Fig. 28 shows an embodiment of transistors according to the claim, whereas the combination of the Fig. 27 and Fig. 29 shows a non-claimed example of transistors. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms of spatial relationships such as "below," "beneath," "low," "above," "upper," and the like may be used herein for the purpose of more easily describing the relationship of one element or feature depicted in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be arranged in a different orientation (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus also be interpreted accordingly. Furthermore, when a number or range of numbers is described with "at," "approximately," and the like, the term is intended to include numbers that are within + / - 10% of the described number, unless otherwise specified.For example, the term “about 5 nm” includes the dimension range from 4.5 nm to 5.5 nm.

[0008] The present disclosure relates to multi-gate transistors and manufacturing methods in general, and more particularly to a semiconductor device having more than one type of channel elements to meet various device requirements.

[0009] MBC transistors are promising candidates for next-generation devices. For applications requiring high drive current and high switching speed, MBC transistor channel elements can have a sheet-like shape, and such channel elements can be referred to as nanosheet channel elements. A nanosheet channel element has a width that is greater than its height to improve drive current. For some other applications, such as system-on-a-chip (SoC) and static random access memory (SRAM) applications, drive current is not the most important requirement. Instead, lower power consumption and smaller cell height are the key considerations. When MBC transistors with nanowire channel elements are used for the latter applications, the drive current can be significantly reduced due to the smaller effective width.Here, the term nanowire channel element refers to a channel element whose width is essentially equal to its height.

[0010] The present disclosure provides a semiconductor device having vertical nanosheet channel elements in a first area and horizontal nanosheet channel elements in a second area. When the first device area is for high drive current applications and the second device area is for high-density applications, the horizontal nanosheet channel elements provide increased drive current and improved speed. The vertical nanosheet channel elements provide a small footprint to increase density, yet still allow sufficient effective width for satisfactory drive current levels. Alternatively, the first area may be an n-type device area, and the second area may be a p-type device area.The horizontal nanosheet channel elements have primary surfaces suitable for n-type charge carriers, and the vertical nanosheet channel elements have primary surfaces suitable for p-type charge carriers. The present disclosure provides example processes for forming such a semiconductor device.

[0011] The various aspects of the present disclosure will now be described in more detail with reference to the figures. Fig. 1 is a flowchart illustrating a method 100 for manufacturing a semiconductor device in accordance with various embodiments of the present disclosure. The method 100 is only an example. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be replaced, omitted, or shifted for further embodiments of the method. For simplicity, not all steps are described in detail herein. The method 100 is described below in connection with the Fig. 2A-26A, 2B-26B, and 15C-26C, which are fragmentary cross-sectional views of a workpiece at various stages of fabrication in accordance with embodiments of the present disclosure. Fig. 27-29 illustrate cross-sectional views of channel elements in channel regions in accordance with various aspects of the present disclosure. A workpiece 200 is shown in Fig. 2A-26A, 2B-26B, 15C-26C, and 27-29. Since a semiconductor device is formed from the workpiece 200, the workpiece 200 may be referred to as a semiconductor device 200, depending on the context.

[0012] Referring to the Fig. 1, Fig. 2A and Fig. 2B, the method 100 includes block 102 in which a workpiece 200 is provided. Fig. 2A illustrates a fragmentary cross-sectional view of the workpiece 200 along the Y direction, and Fig. Figure 2B shows a fragmentary cross-sectional view along the X-direction. As shown in the Fig. 2A and Fig. 2B, the workpiece 200 includes a substrate 202 and a stack 204 disposed above the substrate 202. The stack 204 includes sacrificial layers 206 and channel layers 208 stacked vertically in an alternating arrangement. In other words, the stack 204 includes a plurality of channel layers 208 interspersed with a plurality of sacrificial layers 206. In one embodiment, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may include various layers, such as conductive or insulating layers formed on a semiconductor substrate. Depending on design requirements, the substrate 202 may include various doping configurations, as is known in the art.For example, different doping profiles (e.g., n-wells, p-wells) may be formed on the substrate 202 in regions intended for different device types (e.g., n-type transistors or p-type transistors). The appropriate doping may include ion implantation of dopants and / or diffusion processes. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Further, the substrate 202 may optionally include an epitaxial layer (epilayer), may be strained for performance improvement, may include a silicon-on-insulator (SOI) structure, and / or include other suitable enhancement features.

[0013] Compositions of the sacrificial layers 206 and the channel layers 208 vary. In one embodiment, the sacrificial layers 206 may be formed of silicon germanium (SiGe), and the channel layers 208 may be formed of silicon (Si). However, other semiconductor material combinations are also possible, such as those that provide different oxidation rates and / or etch selectivities between the sacrificial layers and the channel layers. For example, either the sacrificial layers 206 and / or the channel layers 208 may include other materials, such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.As an example, the epitaxial growth of the layers of stack 204 may be performed by a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, channel layers 208 may include the same material as substrate 202. In some embodiments, sacrificial layers 206 and channel layers 208 are substantially free of dopants (i.e., they have an extrinsic dopant concentration of approximately 0 cm -1 ). -3 up to approximately 1×1017 cm -3 on), for example, no intentional doping is carried out during the epitaxial growth process.

[0014] It should be noted that three (3) layers of the sacrificial layers 206 and three (3) layers of the channel layers 208 are arranged alternately, as shown in the Fig. 2A and Fig. 2B, as well as in other figures, which are for illustrative purposes only. It should be understood that any number of epitaxial layers may be formed in the epitaxial stack 204. The number of layers depends on the desired number of channel elements for the device 200. In some embodiments, a number of second semiconductor layers 208 is between 2 and 8. In some embodiments, a first thickness T1 of each of the channel layers 208 is greater than the second thickness T2 of each of the sacrificial layers 206 to form both vertical nanosheet channel elements and horizontal channel elements. In some cases, a ratio of the first thickness T1 to the second thickness T2 may be between about 0.8 and about 4, for example, between about 1.5 and about 4. The first thickness T1 may be between about 6 nanometers (nm) and about 16 nm, and the second thickness T2 may be between about 2 nm and about 6 nm.

[0015] Referring to the Fig. 1, Fig. 3A, Fig. 3B, Fig. 4A and Fig. 4B, the method 100 includes a block 104 in which a first fin-shaped structure 210-1 is formed in a first surface 1000 (or the first device surface 1000) of the substrate 202 and a second fin-shaped structure 210-2 is formed in 211 in a second surface 2000 (or a second device surface 2000) of the substrate 202. Fig. 3A illustrates a fragmentary cross-sectional view of the first surface 1000 along the Y direction, and Fig. 3B illustrates a fragmentary cross-sectional view of the first surface 1000 along the X direction. Fig. 4A illustrates a fragmentary cross-sectional view of the second surface 2000 along the Y direction, and Fig. 4B illustrates a fragmentary cross-sectional view of the second surface 2000 along the X-direction. As shown in the Fig. 3B and Fig. 4B, the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 are formed from the stack 204 and a portion of the substrate 202. The first fin-shaped structure 210-1 has a first fin width F1 along the Y-direction, and the second fin-shaped structure 210-2 has a second fin width F2 along the Y-direction. The second fin width F2 is smaller than the first fin width F1. In some cases, the first fin width F1 may be between about 14 nm and about 64 nm, and the second fin width F2 may be between about 4 nm and about 8 nm. The smaller second fin width F2 helps to reduce the footprint of the transistor formed in the second area 2000, thereby increasing the packing density of the transistors in the second area 2000.

[0016] Although not shown, a hard mask layer may be disposed on top of the fins over the stack 204 and may be patterned to form an etch mask for patterning the stack 204 and the substrate 202 into the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2. The hard mask layer on top of the fins may be a single layer or a multi-layer. In some implementations, the hard mask layer on top of the fins may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or a combination thereof. In embodiments in which the hard mask layer on top of the fins is a multi-layer, the hard mask layer on top of the fins may include a silicon oxide layer deposited over the stack 204 and a silicon nitride layer deposited on the silicon oxide layer.Operations at block 104 may include photolithography processes and etching processes. An example process may include photoresist coating (e.g., spin-coating) onto the hard mask layer on top of the fins, soft firing, mask alignment, exposure, post-exposure firing, photoresist development, rinsing, drying (e.g., spin-drying and / or hard firing), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, those described in the . Fig. 3B and Fig. 4B, patterning also etches into the substrate 202 such that each of the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 includes a base portion 202B formed from the substrate 202 and an upper portion formed from the stack 204. The upper portion includes the sacrificial layers 206 and the channel layers 208 of the stack 204. In some embodiments, the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 may be fabricated using double-patterning or multi-patterning processes. Typically, double-patterning and multi-patterning processes combine photolithography and self-alignment processes, thereby enabling the creation of structures having, for example, pitch dimensions smaller than those otherwise achievable using a single, direct photolithography process.For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned material layer using a self-aligned process. Then, the material layer is removed, and the remaining spacers or mandrels may be used to pattern the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 by etching the stack 204 and the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As shown in FIGS. Fig. 3B and Fig. 4B, the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 extend lengthwise along the X direction.

[0017] Reference is also made to the Fig. 3B and Fig. 4B. After the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 have been formed in the first area 100 and the second area 2000, respectively, an isolation element 212 is formed between adjacent fin-shaped structures (e.g., a first fin-shaped structure 210-1 and an adjacent first fin-shaped structure 210-1 or a second fin-shaped structure 210-2 and an adjacent second fin-shaped structure 210-2). The isolation element 212 may also be referred to as a trench isolation (STI) element 212. As an example, in some embodiments, a dielectric layer is first deposited over the workpiece 200 to fill the trenches between the first fin-shaped structures 210-1 and the second fin-shaped structures 210-2 with the dielectric material.In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVC) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or another suitable process. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is then further recessed by a dry etch process, a wet etch process, and / or a combination thereof to form the STI elements 212.After recessing, at least the upper portions of the first fin-shaped structures 210-1 and the second fin-shaped structures 210-2 protrude beyond the STI elements 212.

[0018] Further referring to the Fig. 1, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A and Fig. 8B, the method 100 includes a block 106 in which dummy gate stacks 220 are formed over channel regions 21CC of the first fin-shaped structure 210-1 and over channel regions 22CC of the second fin-shaped structure 210-2. In some embodiments, a gate replacement process (or gate last process) is applied, in which the dummy gate stacks 220 serve as placeholders for functional gate structures and are to be removed and replaced by the functional gate structures in a subsequent process. Other processes and designs are also possible. Reference is now made to the Fig. 5A, Fig. 5B, Fig. 6A and Fig. 6B. To form the dummy gate stacks 220, a dummy dielectric layer 214, a dummy gate electrode layer 216, and a hard mask on top of the gate 218 are sequentially deposited over the first surface 1000 and the second surface 2000 using a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, or an ALD process. In some implementations, the dummy dielectric layer 214 may be formed of silicon oxide, silicon nitride, or another suitable dielectric material, and serves to prevent damage to the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 during subsequent processes (e.g., the formation of the dummy gate stacks). The dummy gate electrode layer 216 may be formed of polysilicon.The hard mask on top of the gate 218 may be a single layer or a multi-layer, and may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, or a combination thereof. In cases where the hard mask on top of the gate 218 is a multi-layer, the hard mask on top of the gate 218 may include a silicon oxide layer and a silicon nitride layer on top of the silicon oxide layer.

[0019] Reference is now made to the Fig. 7A, Fig. 7B, Fig. 8A and Fig. 8B. After deposition, the hard mask on top of the gate 218, the dummy gate electrode layer 216, and the dummy dielectric layer 214 are patterned by a patterning process, which may include a lithography process (e.g., photolithography or e-beam lithography) and an etching process. The photolithography process may further include photoresist coating (e.g., spin-on coating), soft firing, mask alignment, exposure, post-exposure firing, photoresist development, rinsing, drying (e.g., spin-drying and / or hard firing), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. Referring to the Fig. 7A and Fig. 8A, dummy gate stacks 220 are formed over the substrate 202 and are disposed at least partially over the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2. After patterning, the dummy dielectric layer 214 and the dummy gate electrode layer 216 are formed into dummy gate stacks 220. The portions of the first fin-shaped structure 210-1 disposed beneath the dummy gate stacks 220 are the channel regions 21CC of the first fin-shaped structure 210-1. With respect to the first fin-shaped structure 210-1 in the first area 1000, the dummy gate stacks 220 may also define source / drain regions 21SD adjacent to and on opposite sides of the channel region 21CC. As shown in Fig. 7A, each of the channel regions 21CC may be sandwiched along the X-direction between two source / drain regions 21SD. Likewise, the portions of the second fin-shaped structure 210-2 disposed below the dummy gate stacks 220 are the channel regions 22CC of the second fin-shaped structure 210-2. With respect to the second fin-shaped structure 210-2 in the second area 2000, the dummy gate stacks 220 may also define source / drain regions 22SD adjacent to and on opposite sides of the channel region 22CC. As shown in Fig. As shown in Figure 8A, each of the channel regions 22CC may be sandwiched between two source / drain regions 22SD along the X-direction. Since the dummy gate stacks 220 are not formed over the source / drain regions 21SD of the first fin-shaped structure 210-1 or over the source / drain regions 22SD of the second fin-shaped structure 210-2, the source / drain regions 21SD are Fig. 7B and the source / drain regions 22SD in Fig. 8B is not arranged under a dummy gate stack 220.

[0020] Referring to the Fig. 1, Fig. 9A, Fig. 9B, Fig. 10A and Fig. 10B, the method 100 includes a block 108 in which a gate spacer layer 222 is disposed over the substrate 202, as well as along the sidewalls of the dummy gate stack 220. In some embodiments, spacer material for forming the gate spacer layer 222 is conformally disposed over the workpiece 200, as well as over top surfaces and sidewalls of the dummy gate stack 220. The term "conformal" may be used herein to simply describe a layer having a substantially uniform thickness over various regions. The gate spacer layer 222 may have a single-layer construction or multiple layers. In some embodiments, which are described in the Fig. 9A and Fig. 10A, the gate spacer layer 222 has a single-layer construction. The gate spacer layer 222 may include silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, another suitable dielectric material, or a combination thereof. The spacer material may be deposited over the dummy gate stack 220 using processes such as a CVD process, a subatmospheric CVD (SACVC) process, a flowable CVD process, an ALD process, or another suitable process. The spacer material is then etched back in an anisotropic etch process to form the gate spacer layer 221.The anisotropic etch process exposes portions of the first fin-shaped structure 210-1 and the second fin-shaped structure 210-2 that are adjacent to and not covered by the dummy gate stack 220 (e.g., in source / drain regions 21SD in the first area 1000 or 22SD in the second area 2000). Portions of the spacer material directly above the dummy gate stack 220 may be partially or completely removed by this anisotropic etch process, while the spacer layer 222 remains on sidewalls of the dummy gate stacks 220.

[0021] Referring to the Fig. 1, Fig. 9A, Fig. 9B, Fig. 10A and Fig. 10B, the method 100 includes a block 110 in which the source / drain regions 21SD in the first area 1000 and the source / drain regions 22SD in the second area 2000 are recessed to form source / drain trenches 224. In some implementations, the recessing is performed by etching the source / drain regions 21SD in the first area 1000 and the source / drain regions 22SD in the second area 2000 using the dummy gate stack 220 and the gate spacer layer 222 as an etch mask. The recessing may comprise a dry etching process, which may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some embodiments, which are described in the Fig. 9A and Fig. 10A, the upper portion of the first fin-shaped structure 210-1 and that of the second fin-shaped structure 210-2 are recessed to form source / drain trenches 224. The source / drain trenches 224 expose sidewalls of the sacrificial layers 206 and the channel layers 208. In some implementations, at least a portion of the base portions 202B of the first fin-shaped structure 210-1 and the second fin-shaped structure 210-1, respectively, are also recessed. That is, the source / drain trench 224 may extend into the base portions 202B in the first area 1000 and in the second area 2000. The bottoms of the source / drain trenches 224 are shown in the Fig. 9B and Fig. 10B and may have a concave shape.

[0022] Referring to the Fig. 1, Fig. 11A, Fig. 11B, Fig. 12A and Fig. 12B, the method 100 includes a block 112 in which inner spacers 226 are formed. In an example process, the formation of the inner spacers 226 includes selectively and partially removing the sacrificial layers 206 to form inner spacer recesses (which are not explicitly shown as they are now filled with inner spacers 226) and forming inner spacers 226 in the inner spacer recesses. Once the sacrificial layers 206 in the source / drain trenches 224 have been selectively exposed and partially recessed to form inner spacer recesses, the exposed channel layers 208 remain substantially unetched. In an embodiment in which the channel layers 208 consist essentially of Si and sacrificial layers 206 consist essentially of SiGe, the selective deepening of the sacrificial layers 206 may comprise a SiGe oxidation process followed by SiGe oxide removal.In those embodiments, the SiGe oxidation process may include the use of ozone. In some embodiments, the selective deepening may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layers 206 are deepened is controlled by the duration of the etching process. In some embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. In some embodiments, the selective wet etching process may include the use of a hydrofluoride (HF) etchant or an NH4OH etchant.

[0023] Forming the inner spacers 226 in the inner spacer recesses includes depositing an inner spacer layer over the workpiece 200 and etching back the inner spacer layer outside the inner spacer recesses to form the inner spacers 226. In some embodiments, the inner spacer layers may be deposited over the workpiece 200 by CVD, PECVD, LPCVD, ALD, or another suitable process. The inner spacer layer may be formed from alumina, zirconia, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, low-k material, another suitable metal oxide, or a combination thereof. The deposited inner spacer layer may then be etched back to form inner spacers 226 in the inner spacer recesses.

[0024] Referring to the Fig. 1, Fig. 13A, Fig. 13B, Fig. 14A and Fig. 14B, the method 100 includes a block 114 in which first source / drain elements 228-1 are formed in the source / drain trenches 224 in the first area 1000 and second source / drain elements 228-2 are formed in the source / drain trenches 224 in the second area 2000. The first source / drain elements 228-1 and the second source / drain elements 228-2 may comprise n-type source / drain elements for n-type devices and p-type epitaxial source / drain elements for p-type epitaxial devices. In some embodiments, both the first source / drain elements 228-1 and the second source / drain elements 228-2 are of the same type and may be formed simultaneously. In some other embodiments, the first source / drain elements 228-1 and the second source / drain elements 228-2 have different types and may be formed separately.For example, the first source / drain elements 228-1 may be n-type source / drain elements, and the second source / drain elements 228-2 may be p-type source / drain elements. The first source / drain elements 228-1 and the second source / drain elements 228-2 may be formed using suitable epitaxial processes, such as CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. In some implementations, the epitaxial growth of the first source / drain elements 228-1 and the second source / drain elements 228-2 may be selective for the surfaces of the channel layers 208 and the substrate 202 (or the base portions 202B).Since the first fin-shaped structure 210-1 is wider along the Y-direction than the second fin-shaped structure 210-2, the first source / drain element 228-1 is also wider along the Y-direction than the second source / drain element 228-2. Example epitaxial n-type source / drain elements may include Si, GaAs, GaAsP, SiP, or another suitable material. The epitaxial n-type source / drain elements may be doped in situ during the epitaxial process by introducing doping species including n-type dopants, such as phosphorus (P) or arsenic (As), and / or other suitable dopants, as well as combinations thereof. If the epitaxial n-source / drain elements are not doped in situ, an implantation process (i.e., a junction implantation process) is performed to dope the epitaxial n-source / drain elements.Example p-type epitaxial source / drain elements may contain Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material. The p-type epitaxial source / drain elements may be doped in situ during the epitaxial process by introducing doping species containing p-type dopants, such as boron (B) or BF2, and / or other suitable dopants, as well as combinations thereof. If the p-type epitaxial source / drain elements are not doped in situ, an implantation process (i.e., a junction implantation process) is performed to dope the p-type epitaxial source / drain elements.

[0025] Referring to the Fig. 1, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B and Fig. 16C, the method 100 includes a block 116 in which a contact etch stop layer (CESL) 230 and an interlayer dielectric layer (ILD layer) 232 are formed from the first source / drain elements 228-1 and the second source / drain elements 228-2. Fig. 15A illustrates a fragmentary cross-sectional view of the first surface 1000 along the Y direction. The Fig. 15B and Fig. 15C illustrate fragmentary cross-sectional views of the channel region 21CC and the source / drain region 21SD in the first area 1000. Fig. 16A illustrates a fragmentary cross-sectional view of the second surface 2000 along the Y direction. The Fig. 16B and Fig. 16C illustrate fragmentary cross-sectional views of the channel region 22CC and the source / drain region 22SD in the second area 2000. In some embodiments, the CESL 230 is first deposited over the workpiece 200, such as over the first source / drain elements 228-1 in the first area 2000, the second source / drain elements 228-2 in the second area 2000, and over upper surfaces of the isolation element 212. In some examples, the CESL 230 may include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 230 may be formed by CVD or ALD. After the CESL 230 is deposited, the ILD layer 232 is deposited over the workpiece 200, such as over the CESL 230.In some embodiments, the ILD layer 232 includes materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 232 may be deposited using a PECVD process, a spin-on coating process, or another suitable deposition technique. In some embodiments, the workpiece 200 may be annealed after the formation of the ILD layer 232 to improve the integrity of the ILD layer 232. After the deposition and annealing of the ILD layer 232, the workpiece 200 may be planarized, for example, using a chemical mechanical polishing (CMP) process, to form a flat top surface for further processing.

[0026] Referring to the Fig. 1, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B and Fig. 18C, the method 100 includes a block 118 in which first channel elements 208-1 in the first area 1000 and second channel elements 208-2 in the second area 2000 are enabled. In an example process, the operations at block 118 include removing the dummy gate stacks 220 and selectively removing the sacrificial layers 206. Fig. 17A illustrates a fragmentary cross-sectional view of the first surface 1000 along the Y direction. The Fig. 17B and Fig. 17C illustrate fragmentary cross-sectional views of the channel region 21CC and the source / drain region 21SD in the first area 1000. Fig. Figure 18A illustrates a fragmentary cross-sectional view of the second surface 2000 along the Y direction. The Fig. 18B and Fig. 18C illustrate fragmentary cross-sectional views of the channel region 22CC and the source / drain region 22SD in the second area 2000. First, reference is made to the Fig. 17A, Fig. 17B, Fig. 18A and Fig. 18B. In the depicted embodiment, a selective etch process completely removes the dummy gate stacks 220 to expose sacrificial layers 206 and channel layers 208 in channel regions 21CC in the first area 1000 and in channel regions 22CC in the second area 2000. As shown in the Fig. 17C and Fig. 18C, the CESL 230 and the ILD layer 232 protect the first source / drain elements 228-1 and the second source / drain elements 228-2 from damage during the operations at block 118. The etching process may be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. The etching process may be selected to be selective for the dummy gate stacks 220 and substantially not etch the CESL 230, the ILD layer 232, and the gate spacer layer 222. Still referring to FIG. Fig. 17A, Fig. 17B, Fig. 18A and Fig. 18B, a selective etch process selectively etches the sacrificial layer 206 while minimally or not at all etching the channel layers 208, the gate spacer layer 222, the ILD layer 232, and the inner spacers 226. Various etch parameters, such as etchant composition, etch temperature, etch solution concentration, etch duration, etch pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etch parameters, or combinations thereof, can be tuned to achieve a selective etch of the sacrificial layers 206. For example, an etchant is selected for the etch process that etches the material of the sacrificial layers 206 (silicon germanium in the depicted embodiment) at a higher rate than the material of the channel layers 208 (silicon in the depicted embodiment).This means that the etchant in the selective etching process has a higher etch selectivity with respect to the material of the sacrificial layers 206. The etching process may be a dry etching process, a wet etching process, another suitable etching process, or any combination thereof. In some embodiments, a dry etching process (e.g., an RIE process) uses a fluorine-containing gas (e.g., SF6) to selectively etch the sacrificial layers 206. In some embodiments, a ratio of the fluorine-containing gas to an oxygen-containing gas (e.g., O2 or O3), an etching temperature, and / or an RF power may be adjusted to selectively etch silicon germanium or silicon. In some embodiments, a wet etching process uses an etching solution containing ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the sacrificial layers 206.In some embodiments, a chemical vapor etching process using hydrochloric acid (HCl) may selectively etch the sacrificial layers 206. Upon completion of the operations at block 118, the channel layers 208 in the channel regions 21CC in the first area 1000 may be exposed from the sacrificial layers 206 to form first channel elements 208-1, and the channel layers 208 in the channel regions 22CC in the second area 2000 may be exposed from the sacrificial layers 206 to form second channel elements 208-2. Operations at block 118 form gate trenches 234 over the channel regions 21CC in the first area 1000 and over the channel regions 22CC in the second area 2000.

[0027] In the following, reference is made to the Fig. 17A and Fig. 18A. As in Fig. 17A, each of the first channel elements 208-1 in the channel regions 21CC includes a first channel portion 28C and a first connecting portion 28K. The first channel portions 28C are fully exposed above the base portion 202B and are not disposed below the gate spacer layer 222. The first connecting portion 28K is disposed below the gate spacer layer 222 and is disposed either between two inner spacers 226 or between the gate spacer layer 222 and an inner spacer 226. As shown in Fig. As shown in Figure 18A, each of the second channel elements 208-2 in the channel regions 22CC includes a second channel portion 30C and a second connecting portion 30K. The second channel portions 30C are fully exposed above the base portion 202B and are not disposed below the gate spacer layer 222. The second connecting portion 30K is disposed below the gate spacer layer 222 and is disposed either between two inner spacers 226 or between the gate spacer layer 222 and an inner spacer 226.

[0028] Referring to the Fig. 1, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B and Fig. 20C, the method 100 includes a block 120 in which first channel elements 208-1 in the first surface 1000 are trimmed to form the third channel elements 208-3. Fig. 19A illustrates a fragmentary cross-sectional view of the first surface 1000 along the Y direction. The Fig. 19B and Fig. 19C illustrate fragmentary cross-sectional views of the channel region 21CC and the source / drain region 21SD in the first area 1000. Fig. Figure 20A illustrates a fragmentary cross-sectional view of the second surface 2000 along the Y direction. The Fig. 20B and Fig. 20C illustrate fragmentary cross-sectional views of the channel region 22CC and the source / drain region 22SD in the second surface 2000. To selectively trim the first channel elements 208-1, in some embodiments, a photoresist mask 236 or a masking layer 236 may be formed over the second surface 2000 while exposing the first surface 1000. Forming the photoresist mask 236 may include depositing a photoresist material over the workpiece 200 and patterning the photoresist material using photolithography techniques to expose the first surface 1000. In some implementations, the photoresist layer may be deposited using spin-on coating or another suitable method. In some embodiments, trimming the first channel elements 208-1 may include using an etch process that is selective for the first channel elements 208-1, which may be formed of silicon.In some other embodiments, the trimming process may comprise a two-step process. A first stage of an example two-step process comprises partially oxidizing the first channel elements 208-1 to form a silicon oxide layer. A second stage of the example two-step process comprises selectively removing the silicon oxide layer. For example, selectively removing the silicon oxide layer may comprise using dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). After trimming the first channel elements 208-1, the photoresist mask 236 over the second surface 2000 may be removed using a suitable process, such as ashing. At this point, the third channel elements 208-3 are substantially formed in the first surface 2000 and the second channel elements 208-2 are substantially formed in the second surface 2000. As described in connection with FIGS. Fig. 27, Fig. 28 and Fig. 29, each of the third channel elements 208-3 has a width greater than its height and thus has a horizontal nanosheet orientation, and each of the second channel elements 208-2 has a height greater than its width and thus has a vertical nanosheet orientation.

[0029] In the following, reference is made to the Fig. 19A and Fig. 20A. As in Fig. 19A, the third channel elements 208-3 have been formed by trimming the first channel elements 208-1, the first channel section 28C in Fig. 17A to form third channel portions 28C', while the first channel portion 28K is protected and remains untrimmed. That is, each of the third channel elements 208-3 includes a third channel portion 28C' and the first connecting portion 28K. Due to the masking of the photoresist mask 236, the second channel elements 208-2 do not undergo any dimensional changes at block 120. Since the third channel elements 208-3 in the first area 1000 and the second channel elements 208-2 in the second area 2000 were formed from the same stack 204, a pitch of the third channel elements 208-3 may be substantially equal to a pitch of the second channel elements 208-2. By trimming at block 120, a difference between a height of the third channel portion 28C' (along the Z direction) and a height of the first connecting portion 28K (along the Z direction) may be between approximately 1 nm and approximately 8 nm.In contrast, a difference between a height of the second channel portion 30C (along the Z direction) and a height of the second connecting portion 30K (along the Z direction) may be insignificant, for example, between approximately 0 nm and approximately 1 nm. Both a thickness of the first connecting portion 28k and a thickness of the second connecting portion 30K may be substantially equal to the first thickness T1 of the channel layer 208, which is between approximately 6 nm and approximately 16 nm.

[0030] Referring to the Fig. 1, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B and Fig. 24C, the method 100 includes a block 122 in which gate structures 250 are formed over the third channel elements 208-3 in the first area 1000 and the second channel elements 208-2 in the second area 2000. The Fig. 21A and Fig. 23A illustrate a fragmentary cross-sectional view of the first surface 1000 along the Y-direction. The Fig. 21B, Fig. 23B, Fig. 21C and Fig. 23C illustrate fragmentary cross-sectional views of the channel region 21CC and the source / drain region 21SD in the first area 1000 along the X direction. The Fig. 22A and Fig. 24A illustrate fragmentary cross-sectional views of the second surface 2000 along the Y-direction. The Fig. 22B, Fig. 24B, Fig. 22C and Fig. 24C illustrate fragmentary cross-sectional views of the channel region 22CC and the source / drain region 22SD in the second surface 2000 along the X-direction. Each of the gate structures 250 may include an interface layer 238, a gate dielectric layer 240, and a gate electrode 242. Referring first to the Fig. 21A, Fig. 21B, Fig. 22A and Fig. 22B, at block 122, the interface layer 238 may be conformally formed on the third channel elements 208-3 in the first surface 1000 and on the second channel elements 208-2 in the second surface 2000. In some implementations, the interface layer 238 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0031] Now referring to the Fig. 23A, Fig. 23B, Fig. 24A and Fig. 24B, the gate dielectric layer 240 is then deposited over the interface layer 238 to enclose the third channel elements 208-3 in the first area 1000 and the second channel elements 208-2 in the second area 2000. The gate dielectric layer 240 may include one or more high-k dielectric materials. High-k dielectric materials as used and described herein include dielectric materials having a high dielectric constant, for example, higher than that of thermal silicon oxide (~3.9).Examples of high-k dielectric material for the gate dielectric layer 240 may include hafnium oxide (HfO), titanium oxide (TiO2), hafnium-zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium-silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium-silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium-lanthanum oxide (HfLaO), lanthanum-silicon oxide (LaSiO), aluminum-silicon oxide (AlSiO), hafnium-tantalum oxide (HfTaO), hafnium-titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), Silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material. The gate dielectric layer 240 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. In some cases, where the second thickness T2 (in . Fig. 2A) of the sacrificial layers 206 is between approximately 2 nm and approximately 4 nm, the gate dielectric layer 240 in the channel region 22CC in the second area 2000 may fuse between adjacent second channel elements 208-2, as shown in the Fig. 24A and Fig. 24B. In these cases, the fused gate dielectric layer 240 between adjacent second channel elements 208-2 may prevent further layers, such as the gate electrode 242, from completely enclosing the second channel elements 208-2. In other cases, in which the second thickness T2 (in Fig. 2A) of the sacrificial layers 206 is more than approximately 4 nm, it is rather unlikely that the gate dielectric layer 240 in the channel region 22CC in the second area 2000 will fuse between adjacent second channel elements 208-2. In those alternative cases, further layers, such as the gate electrode 242, may completely enclose the second channel elements 208-2.

[0032] Further referring to the Fig. 23A, Fig. 23B, Fig. 24A and Fig. 24B, gate electrode 242 is then deposited over gate dielectric layer 240. Although not specifically illustrated, gate electrode 242 may include one or more work function layers and one or more metal fill layers. In some implementations, different work function layer stacks may be formed in n-type device regions and p-type device regions. While in those implementations, n-type device regions and p-type device regions may share certain common work function layers, n-type device regions may include one or more work function layers that are not present in p-type device regions. Likewise, in alternative implementations, p-type device regions may include one or more work function layers that are not present in n-type device regions.A p-type work function layer contains any suitable p-type work function material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium silicon (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function materials, or combinations thereof. An n-type work function layer contains any suitable n-type work function material, such as titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC), titanium-aluminum-silicon carbide (TiAlSiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum-silicon nitride (TaSiN), tantalum-aluminum (TaAl), tantalum-aluminum carbide (TaAlC), tantalum-silicon-aluminum carbide (TaSiAlC), titanium-aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof.It should be noted that p-type work function layers are not limited to use in p-type device regions, and n-type work function layers are not limited to use in n-type device regions. P-type work function layers and n-type work function layers may be used in n-type device regions and p-type device regions to achieve desired threshold voltages. In some embodiments, the gate electrode 242 may include one or more metal fill layers. For example, a CVD process or a PVD process deposits the one or more metal fill layers on top of the n-type work function layer(s) and the p-type work function layer(s) such that a metal fill layer fills all remaining portions of the gate trenches 234.The metal fill layer may contain a suitable conductive material, such as aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), or copper (Cu). The metal fill layer may additionally or jointly contain other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0033] In some cases where the second thickness T2 (in Fig. 2A) of the sacrificial layers 206 is between approximately 2 nm and approximately 4 nm, the gate dielectric layer 240 in the channel region 22CC in the second area 2000 may fuse between adjacent second channel elements 208-2, as shown in the Fig. 24A and Fig. 24B. In those cases, the fused gate dielectric layer 240 between adjacent second channel elements 208-2 may prevent the gate electrode 242 from extending between two adjacent second channel elements 208-2. Thus, in those cases, the gate electrode 242 does not completely enclose the second channel elements 208-2. In other cases, in which the second thickness T2 (in Fig. 2A) of the sacrificial layers 206 is more than approximately 4 nm, it is rather unlikely that the gate dielectric layer 240 in the channel region 22CC in the second area 2000 will fuse between adjacent second channel elements 208-2. In those alternative and unclaimed cases, the gate electrode 242 may extend between two adjacent second channel elements 208-2 and completely enclose the second channel elements 208-2.

[0034] Referring to the Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B and Fig. 24C, the workpiece 200 is planarized to provide a flat surface. In some embodiments, the planarization is performed to remove excess interface layer 238, gate dielectric layer 240, and gate electrode 242 above the workpiece 200. The planarization may, for example, comprise a CMP process and may be performed until a top surface of the ILD layer 232 is substantially coplanar with a top surface of the gate electrode 242.

[0035] Referring to the Fig. 1, Fig. 25A, Fig. 25B, Fig. 26A and Fig. 26B, the method 100 includes a block 124 in which further processes are performed. Manufacturing may then continue with the fabrication of the semiconductor device 200. For example, various contacts may be formed to enable operation of the MBC transistors in the semiconductor device 200. For example, first source / drain contacts 254 may be formed to couple to the first source / drain elements 228-1 in the first area 1000, and second source / drain contacts 255 may be formed to couple to the second source / drain elements 228-2 in the second area 2000.An example process for forming the first source / drain contacts 254 and the second source / drain contacts 255 may include forming source / drain contact openings through the ILD layer 232 and the CESL 230, forming silicide features 252, and forming the first source / drain contacts 254 and the second source / drain contacts 255 in the source / drain contact openings. In some embodiments, the silicide features 252 may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN). The first source / drain contacts 254 and the second source / drain contacts 255 may include tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). To form further interconnect structures, 200 gate contacts, additional ILD layers, additional CESL layers and additional conductive features can be formed over the workpiece.Since the first fin-shaped structure 210-1 is wider along the Y direction than the second fin-shaped structure 210-2, as described above, the first source / drain element 228-1 is also wider along the Y direction than the second source / drain element 228-2. Consequently, a bottom surface of a first source / drain contact 254 is also wider along the Y direction than a bottom surface of the second source / drain contact 255. As shown in FIGS. Fig. 25C and Fig. As shown in Figure 26C, the bottom surface of the first source / drain contact 254 has a first contact width C1 along the Y direction, and the bottom surface of the second source / drain contact 255 has a second contact width C2. In some cases, the first contact width C1 is larger than the second contact width C2. A ratio of the first contact width C1 to the second contact width C2 (i.e., C1 / C2) may be between about 2 and about 10.

[0036] Depending on the configurations of the stack 204, the channel elements of the semiconductor device 200 can have different Fig. 27 - 29. Firstly, referring to Fig. 27, each of the third channel sections 28C' (of the third channel elements 208-3) in channel regions 21CC in the first surface 1000 may have a first width W1 and a first height H1. The first width W1 is greater than the first height H1. For this reason, each of the third channel sections 28C' (of the third channel elements 208-3) has its upper and lower surfaces as its primary channel surfaces. Since the primary channel surfaces of the third channel elements 208-3 extend parallel to the XY plane, the third channel elements 208-3 may be considered horizontal nanosheet channel elements. In some embodiments, the first width W1 is between about 10 nm and about 60 nm, and the first height H1 is between about 3 nm and about 8 nm. Referring now to Fig. 28, each of the second channel sections 30C (of the second channel elements 208-2) in channel regions 22CC in the first surface 1000 may have a second width W2 and a second height H2. The second height H2 is greater than the second width W2. For this reason, each of the second channel elements 208-2 has its sidewall surfaces as its primary channel surfaces. Because the primary channel surfaces of the second channel elements 208-2 extend parallel to the XZ plane, the second channel elements 208-2 may be considered vertical nanosheet channel elements. In some embodiments, the second width W2 is between about 3 nm and about 7 nm, and the second height H2 is between about 5 nm and about 15 nm. In some cases, the third channel sections 28C' (of the third channel elements 208-3) are wider and shorter than the second channel sections 30C (of the second channel elements 208-2).This means that the first width W1 is greater than the second width W2, and the first height H1 is smaller than the second height H2. Compared to MBC transistors having third channel elements 208-3 in the first area, the smaller second width W2 allows MBC transistors having second channel elements 208-2 in the second area 2000 to have a smaller package size and a higher packing density in the ZY plane. While their second width W2 is smaller, the larger second height H2 (compared to the first height H1) of the second channel elements 208-2 provides additional channel width for satisfactory drive current levels. It should be noted that the third channel elements 208-3 and the second channel elements 208-2 have the same pitch, which can be between approximately 8 nm and approximately 18 nm, since they are formed from the same stack 204.

[0037] To complete the operations at block 124, a first transistor 310 may be formed in the first area 1000, as illustratively shown in Fig. 25A, and a second transistor 320 may be formed in the second area 2000, as illustratively shown in Fig. 26A. Both the first transistor 310 and the second transistor 320 are MBC transistors because they have vertically stacked channel elements. In some embodiments, the first transistor 310 and the second transistor 320 are intended for different applications. For example, the first transistor 310 has larger drive currents than the second transistor 320 and can be used for higher drive current or higher speed applications. The second transistor 320 has a smaller width along the Y direction than the first transistor and can be used for high-density applications, such as SoC and SRAM applications. In other words, in these embodiments, the first area 1000 is a high drive current device region, and the second area 2000 is a high-density region.As explained in more detail below, in some alternative embodiments, the first transistor 310 may be more suitable for n-type devices, and the second transistor 320 may be more suitable for p-type devices in terms of charge carrier mobility. In those alternative embodiments, the first surface 1000 is an n-type device surface, and the second surface 2000 is a p-type device surface.

[0038] Now we turn to the Fig. 27 - 29. Since the third channel sections 28C' (of the third channel elements 208-3) are selectively trimmed at block 120 in the method 100, as in Fig. 27, the gate dielectric layer 240 deposited on the third channel portions 28C' (of the third channel elements 208-3) does not fuse under the third channel portions 28C' (of the third channel elements 208-3), and the gate structure 250, including the gate electrode 242, may completely enclose the third channel portions 28C' (of the third channel elements 208-3) in the first area 1000. The gate electrode 242 may also extend between the lowermost third channel element 208-3 and the base portion 202B in the first area 1000. The second channel portions 30C (of the second channel elements 208-2) in the second area 2000 are not trimmed at block 120 of the method 100 and have smaller spacings between channel elements. If, as shown in Fig. 28, the second thickness T2 of the sacrificial layer 206 in the stack 204 is between approximately 2 nm and approximately 4 nm, the gate dielectric layer 240 may fuse on adjacent second channel portions 30C (of the second channel elements 208-2), and the gate electrode 242 may not extend between adjacent second channel portions 30C (of the second channel elements 208-2) or between the lowermost second channel element 208-2 and the base portion 202B. If, as shown in Fig. 29, the second thickness T2 of the sacrificial layer 206 in the stack 204 is more than 4 nm, such as between about 4 nm and about 6 nm, the gate dielectric layer 240 does not fuse on adjacent second channel portions 30C (of the second channel elements 208-2), and the gate electrode 242 may extend between adjacent second channel portions 30C (of the second channel elements 208-2) or between the lowermost second channel element 208-2 and the base portion 202B.

[0039] In addition to providing reduced size while providing satisfactory channel width, the second channel elements 208-2 may also be suitable for p-type devices. If the substrate 202 is a silicon substrate having an orientation <100> (i.e., it has its primary planar surface at the crystal plane (100)), the primary channel surfaces of the third channel elements 208-3 are arranged at the crystal plane (100), while the primary channel surfaces of the second channel elements 208-2 are arranged at the crystal plane (110). Since the electron mobility is greatest at the crystal plane (100) and the hole mobility is greatest at the crystal plane (110), the drive current can be maximized when the third channel elements 208-3 are used for n-MBC transistors and the second channel elements 208-2 are used for p-MBC transistors.

[0040] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] A semiconductor device comprising: a first transistor (310) comprising: a plurality of first channel elements (208-3) arranged one above the other and spaced from one another, and a first gate structure (250) enclosing each of the plurality of first channel elements (208-3); and a second transistor (320) comprising: a plurality of second channel elements (208-2) arranged one above the other and spaced from one another, and a second gate structure (250) arranged over the plurality of second channel elements (208-2), wherein each of the plurality of first channel elements (208-3) has a first width (W1) and a first height (H1) which is smaller than the first width, wherein each of the plurality of second channel elements (208-2) has a second width (W2) and a second height (H2) greater than the second width; wherein the first gate structure (250) comprises a first gate dielectric layer (240) in contact with the first channel elements (208-3) and a first gate electrode (242) spaced from the first channel elements, wherein the second gate structure (250) comprises a second gate dielectric layer (240) in contact with the second channel elements (208-2) and a second gate electrode (242) spaced from the second channel elements, wherein the first gate electrode (242) completely encloses each of the plurality of first channel elements (208-3), wherein the second gate electrode (242) does not completely enclose any of the plurality of second channel elements (208-2); and wherein a distance dimension (P) of the plurality of first channel elements (208-3) is identical to a distance dimension (P) of the plurality of second channel elements (208-2). [2] The semiconductor device of claim 1, wherein the pitch is between about 8 nm and about 18 nm. [3] A semiconductor device according to claim 1 or 2, wherein the first width (W1) is larger than the second width (W2). [4] A semiconductor device according to any preceding claim, wherein the first height (H1) is smaller than the second height (H2). [5] A semiconductor device according to any preceding claim, further comprising a gate spacer layer (222) disposed along sidewalls of the first gate structure (250) and sidewalls of the second gate structure (250). [6] A semiconductor device according to claim 5, wherein the second gate dielectric layer (240) has a first portion adjacent to one of the plurality of second channel elements (208-2) and a second portion adjacent to another of the plurality of second channel elements, wherein the first section is in contact with the second section. [7] A semiconductor device comprising: a first transistor (310) comprising: a first channel element (208-3) above and spaced from a first base portion (202B), a third channel element (208-3) above and spaced from the first channel element (208-3), and a first gate structure (250) enclosing the first channel element (208-3) and the third channel element (208-3) and having a first interface layer (238), a first gate dielectric layer (240) and a first gate electrode (242), wherein the first interface layer (238) is arranged on the first base portion (202B), on the first channel element (208-3) and on the third channel element (208-3), wherein the first gate dielectric layer (240) is disposed on the first interface layer (238), and wherein the first gate electrode (242) extends between the first channel element (208-3) and the third channel element (208-3); and a second transistor (320) comprising: a second channel element (208-2) above and spaced from a second base portion (202B), a fourth channel element (208-2) above and spaced from the second channel element (208-2), and a second gate structure (250) disposed over the second channel element (208-2) and comprising a second interface layer (238), a second gate dielectric layer (240), and a second gate electrode (242), wherein the second interface layer (238) is arranged on the second channel element (208-2) and on the second base portion (202B), wherein the second gate dielectric layer (240) is disposed on the second interface layer (238), wherein the second gate electrode (242) does not extend between the second channel element (208-2) and the second base portion (202B); wherein the second gate structure (250) is arranged above the fourth channel element (208-2), wherein the second gate electrode (242) does not extend between the second channel element (208-2) and the fourth channel element (208-2); and wherein a distance dimension (P) of the first channel element (208-3) and the third channel element (208-3) is identical to a distance dimension (P) of the second channel element (208-2) and the fourth channel element (208-2). [8] A semiconductor device according to claim 7, further comprising: a gate spacer layer (222) disposed along sidewalls of the first gate structure (250) and sidewalls of the second gate structure (250). [9] A semiconductor device according to claim 7 or 8, wherein the first channel element (208-3) extends lengthwise along a direction (X) between a first source / drain element (228-1) and a second source / drain element (228-1), wherein the first channel element (208-3) has a channel portion (28C') directly below the first gate structure (250) and a connecting portion (28K) along the direction (X) between the channel portion and the first source / drain element (228-1), and wherein a height of the connecting portion (28K) is greater than a height (H1) of the channel portion (28C'). [10] Semiconductor device according to one of claims 7 to 9, wherein the second channel element (208-2) extends lengthwise along a direction (X) between a third source / drain element (228-2) and a fourth source / drain element (228-2), wherein the second channel element (208-2) has a channel portion (30C) directly below the second gate structure (250) and a connecting portion (30K) along the direction (X) between the channel portion and the third source / drain element (228-2), and wherein a height of the connecting portion (30K) is greater than a height (H2) of the channel portion (30C). [11] A semiconductor device according to any one of claims 7 to 10, wherein the pitch (P) is between about 8 nm and about 18 nm. [12] Semiconductor device according to one of claims 7 to 11, wherein the first channel element (208-3) has a first width (W1) and a first height (H1) which is smaller than the first width, and wherein the second channel element (208-2) has a second width (W2) and a second height (H2) which is greater than the second width. [13] The semiconductor device according to claim 12, wherein the first width (W1) is greater than the second width (W2). [14] A semiconductor device according to claim 12 or 13, wherein the first height (H1) is smaller than the second height (H2). [15] Method comprising: Applying a stack (204) comprising a plurality of channel layers (208) interspersed with a plurality of sacrificial layers (206) on a substrate (202); Structuring the stack (204) and the substrate (202) into a first fin-shaped structure (210-1) and a second fin-shaped structure (210-2); Forming a first dummy gate stack (220) over a first channel region (21CC) of the first fin-shaped structure (210-1) and a second dummy gate stack (220) over a second channel region (22CC) of the second fin-shaped structure (210-2); Forming source / drain elements (228-1, 228-2) embedding the first channel region (21CC) and the second channel region (22CC); Removing the first dummy gate stack (220) and the second dummy gate stack (220); selectively removing the sacrificial layers (206) in the first channel region (21CC) to release channel layers (208-1) in the first channel region; selectively removing the sacrificial layers (206) in the second channel region (22CC) to form first channel elements (208-2) in the second channel region; selectively trimming the channel layers (208) in the first channel region (21CC) to form second channel elements (208-3) in the first channel region; Forming a first gate structure (250) over the second channel elements (208-3); and Forming a second gate structure (250) over the first channel elements (208-2); wherein the first gate structure (250) comprises a first gate dielectric layer (240) in contact with the second channel elements (208-3) and a first gate electrode (242) spaced from the second channel elements, wherein the second gate structure (250) comprises a second gate dielectric layer (240) in contact with the first channel elements (208-2) and a second gate electrode (242) spaced from the first channel elements, wherein the first gate electrode (242) completely encloses each of the plurality of second channel elements (208-3), and wherein the second gate electrode (242) does not completely enclose any of the plurality of first channel elements (208-2). [16] Method according to claim 15, wherein the first fin-shaped structure (210-1) and the second fin-shaped structure (210-2) extend lengthwise along a direction (X), wherein a width (F1) of the first fin-shaped structure (210-1) is greater than a width (F2) of the second fin-shaped structure (210-2). [17] Method according to claim 16, wherein a thickness (T1) of each of the plurality of channel layers (208) is smaller than the width (F1) of the first fin-shaped structure (210-1), wherein the thickness (T1) of each of the plurality of channel layers (208) is greater than the width (F2) of the second fin-shaped structure (210-2). [18] Method according to one of claims 15 to 17, wherein the selective removal of the sacrificial layers (206) in the first channel region (21CC) and the selective removal of the sacrificial layers in the second channel region (22CC) are carried out simultaneously, wherein the selective trimming of the channel layers (208) in the first channel region (21CC) comprises masking the second channel region (22CC) with a masking layer. [19] Method according to one of claims 15 to 18, wherein each of the first channel elements (208-2) has a first height (H2), wherein each of the second channel elements (208-3) has a second height (H1) which is smaller than the first height (H2).

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