INDUCTOR CURRENT DRIVE FOR ATTENTIONING LOAD DROP TRANSIENTS IN DC / DC REGULATORS

Abstract

Voltage regulator circuit comprising the following: a switching circuit configured to adapt a switching duty cycle to regulate an output voltage of an output node of the voltage regulator circuit using an error signal representative of a difference between a target voltage value and the output voltage; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor and designed to divert the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage; an output capacitor coupled to the output node; a comparator circuit coupled to the output node; wherein the switching circuit comprises an upper switching circuit coupled to a switching circuit node and an input node of the voltage regulator circuit, and a lower switching circuit coupled to the switching circuit node and a circuit ground node; the shunt circuit has the following features: a shunt switch coupled to the output node and the circuit ground; and a current matching amplifier comprising inputs coupled to the lower switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an activation input; and wherein the comparator circuit is configured to compare the output voltage with the specified maximum output voltage and to provide an activation signal for the current matching amplifier to divert the inductor current away from the output capacitor.

Description

AREA OF REVELATION

[0001] This document relates to regulator circuits and in particular to the attenuation of output transients in DC / DC regulator circuits. BACKGROUND

[0002] Regulator circuits can be used to produce a regulated output from a circuit input. For example, a buck-set voltage regulator circuit uses an input voltage to produce a regulated output voltage lower than the input voltage, and a boost-set regulator circuit produces a regulated output voltage higher than the input voltage. Switching is used to charge and discharge an inductor in the circuit to produce a regulated output. In these types of circuits, and also in non-inductor-based regulator circuits, an output load current transient can cause an unwanted voltage transient on the regulated output voltage.

[0003] JP 2012- 253 949 A discloses a DC-DC converter and an electronic device.

[0004] US 2012 / 0 286 576 A1 apparently a single-coil regulator with multiple outputs with synchronized current mode hysterical control.

[0005] US 3 641 422 A discloses a broadband boost converter power supply. SUMMARY OF THE REVELATION

[0006] This document refers generally to electronic circuits for voltage regulation and in particular to improvements in mitigating the effects of load drop transients on regulator circuits.

[0007] In some aspects, a voltage regulator circuit includes a switching circuit configured to adjust a switching cycle to regulate an output voltage at an output node of the voltage regulator circuit using an error signal representative of a difference between a target voltage value and the output voltage; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; a shunt circuit coupled in parallel to the inductor and configured to divert the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage; an output capacitor coupled to the output node; and a comparator circuit coupled to the output node.wherein the switching circuit comprises an upper switch circuit coupled to a switching circuit node and an input node of the voltage regulator circuit, and a lower switch circuit coupled to the switching circuit node and a circuit ground node; wherein the shunt circuit comprises: a shunt switch coupled to the output node and the circuit ground; and a current matching amplifier having inputs coupled to the lower switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an activation input; and wherein the comparator circuit is configured to compare the output voltage with the predetermined maximum output voltage and to provide an activation signal for the current matching amplifier to divert the inductor current away from the output capacitor.

[0008] In some aspects, a method for operating a voltage converter circuit includes activating and deactivating a switching circuit to charge and discharge an inductor to generate an output voltage and provide an inductor current to an output node of the voltage regulator circuit; adjusting a switching duty cycle of the switching circuit to regulate the output voltage using an error signal representative of a difference between a target voltage value and the output voltage; comparing the output voltage to a predetermined maximum output voltage; and diverting the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage; wherein the diversion of the inductor current includes generating an matching current to balance the inductor current and diverting the matched current away from the output capacitor at the output node.

[0009] In some aspects, a voltage regulator circuit includes a switching circuit configured to adjust a switching duty cycle to regulate the output voltage of an output node of the voltage regulator circuit using an error signal representative of a difference between a target voltage value and the output voltage; an inductor coupled to the switching circuit configured to provide an inductor current to the output node; and a shunt circuit coupled to the inductor configured to allow the inductor current to flow away from the output node when the output voltage exceeds a predetermined maximum output voltage, and to restore the inductor current to the output node when the output voltage drops to a target voltage lower than the predetermined maximum output voltage.an output capacitor coupled to the output node; wherein the switching circuit comprises an upper switch circuit coupled to a switching circuit node and an input node of the voltage regulator circuit, and a lower switch circuit coupled to the switching circuit node and a circuit ground node; wherein the shunt circuit loop comprises the lower switch circuit and a shunt switch coupled to the output node and the circuit ground; wherein the voltage regulator circuit further comprises: a current matching amplifier having inputs coupled to the lower switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an activation input;and a comparator circuit coupled to the output node, wherein the comparator circuit is configured to compare the output voltage with the specified maximum output voltage and to provide an activation signal for the current matching amplifier to allow the inductor current to flow in the shunt circuit loop and away from the output capacitor.

[0010] This section is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or comprehensive explanation of the invention. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the drawings, which are not necessarily drawn to scale, the same digits may describe similar components in different views. The same digits with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, but do not limit, various embodiments discussed in this document. Fig. Figure 1 is a circuit diagram of an example of a voltage regulator circuit. Fig. Figure 2 shows current and voltage waveforms for a conventional regulator circuit subjected to a load drop. Fig. Figure 3 is a flowchart of a procedure for operating a voltage regulator circuit. Fig. 4 represents current and voltage waveforms for the voltage regulator circuit of Fig. 1 dar. Fig. Figure 5 is a circuit diagram of another example of a voltage regulator circuit. Fig. 6 represents current and voltage waveforms for the voltage regulator circuit of Fig. 5 dar. Fig. Figure 7 is a circuit diagram of an example of a boost voltage regulator circuit. Fig. Figure 8 is a circuit diagram of an example of a buck / boost voltage regulator circuit. DETAILED DESCRIPTION

[0012] Fig. Figure 1 is a circuit diagram of an example of a voltage regulator circuit 100. The circuit contains a top-gate transistor M1, a bottom-gate transistor M2, and an inductor 102 (L). In this example, M1 and M2 are field-effect transistors (FETs). The voltage regulator circuit 100 can have an output capacitor 104, which is electrically coupled to an output node, and can supply an output voltage V to an output load. OUTThe voltage regulator circuit 100 includes a switching circuit 110, which has a gate driver 114 and inputs M1 and M2. The gate driver 114 is configured (e.g., by a logic circuit arrangement) to use a clock signal to provide a switching duty cycle that has a charging section and a discharging section. The voltage regulator circuit 100 absorbs electrical energy during the charging section of the switching duty cycle.

[0013] The inductor 102 can be coupled between the output capacitor 104 and the switching circuit node 108. The bottom-gate transistor M2 can be electrically coupled between the switching circuit node 108 and the circuit ground, and the top-gate transistor M1 can be coupled between the switching circuit node 108 and an input node connected to an input voltage V. IN electrically coupled, to be electrically coupled.

[0014] During the charging phases of successive cycles, transistor M1 is switched on or activated to raise the voltage of switching node 108 to almost the input voltage V. IN to increase the current. This initial activation drives a gradually increasing current through inductor 102 and to the output capacitor 104 and the load. During the discharge phase of the switching duty cycles, M2 is switched on to pull the switching circuit node 108 almost to circuit ground. This second activation provides a gradually decreasing current from the energy stored in inductor 102 to the output capacitor 104 and the load.

[0015] The duration of the charging phase of the switching cycle can be automatically adjusted to control the output voltage V. OUTto maintain a predetermined level. This adjustment can be achieved using a circuit feedback loop incorporating an error amplifier circuit 112. The error amplifier circuit 112 generates an error signal that corresponds to a difference between a target voltage value and the voltage V. OUT The output voltage is representative of the output node of the voltage regulator circuit 100. The output voltage can be scaled (e.g., using an ohmic voltage divider) to provide a scaled representation of the output voltage for the error amplifier circuit 112 as a feedback voltage, instead of the actual output voltage. The error amplifier circuit 112 compares the feedback voltage (V) FB ) with a voltage reference (V REG ) to generate the error signal. V REGThis can be the desired regulated output voltage or a scaled voltage derived from the desired regulated output voltage.

[0016] The switching circuit 110 can incorporate logic circuitry to implement pulse-width modulation (PWM) switching control. The switching circuit 110 sets the duration of the charging and discharging phases of the switching duty cycle according to the output voltage. For example, the switching circuit 110 can turn on transistor M1 with the gate on top for a duration based on a comparison of the error signal and a reference waveform signal, and then turn on transistor M2 with the gate off for the remainder of each clock period.

[0017] Activating transistor M1 generates a gradually increasing current in the inductor, and activating transistor M2 generates a gradually decreasing current in the inductor during each switching cycle. This rising and then falling current maintains the feedback voltage at a value essentially equal to the reference voltage V. REF This activation sequence maintains the output voltage V. OUT at the output terminal, regardless of the current demand at the load, at the desired level.

[0018] In the Fig. In the example shown, the circuit topology and the target voltage value generate a regulated voltage for V OUT , which is lower than the voltage at input V IN the voltage regulator circuit (e.g., a buck regulator circuit). Other examples include voltage regulator circuit topologies for generating a regulated voltage. OUT, which is higher than V IN (e.g., a boost regulator circuit), and circuit topologies for generating a regulated V OUT , which can be either lower or higher than V IN (e.g. a buck / boost regulator circuit).

[0019] An output load transient in the negative direction (e.g., a load drop in which the load is removed and a load current I) LOAD (which is reduced to zero) of a DC-DC voltage regulator typically results in a positive voltage transient on the regulated output voltage V. OUTThis is due to a) the finite response time of the voltage regulator to correct the amount of current supplied to the load, and b) the combined near-instantaneous effects of the electrical series resistance (ESR) and electrical series inductance (ESL) in the output capacitor. This problem is exacerbated for inductor-based DC / DC regulators, where the inductor current I LThe current cannot be changed immediately, and the inductor current typically continues to be fed to the output capacitor for additional cycles until the current can be reduced to zero. This continued feeding of inductor current to the reduced load causes the regulated output voltage to continue rising, posing a risk of exceeding the output voltage specifications, especially if the application requires tight control of the output voltage. This positive voltage transient can cause a system shutdown by triggering an overvoltage monitoring circuit or, worse, damage circuits connected to the output node due to the overvoltage stress.

[0020] Fig. Figure 2 shows current and voltage waveforms for a conventional buck converter circuit subjected to a load drop (e.g., I falls). LOAD of the value I MAX(drops to zero at time t1, as shown in the graph above). Immediately before the load drop event, the inductor current waveform shows I L , in the middle graph normal ripple at the DC / DC switching frequency, and the output voltage, V OUT , shows a corresponding voltage ripple with the same frequency, because C OUT the AC component of I L is suspended (because of I COUT = I L - I LOAD After t1, the total inductor current 205 (including the DC component, I) MAX ) supplied to the output capacitor until the inductor current 205 can be reduced to zero. This applies regardless of whether the buck converter control scheme switches off both M1 and M2 or simply switches on M2. As in Fig. As shown in the lower graph, the output voltage response to this additional current is a voltage overshoot of 210. The magnitude of the overshoot depends on the value of C. OUTfrom, and higher values ​​of C OUT This results in a reduced voltage overshoot of 215. However, there are increased costs in the bill of materials (BOM) and board space associated with increasing the output capacitance. Additionally, because inductor current continues to be supplied to the output node, increasing the capacitance of C eliminates the need for this. OUT It doesn't eliminate the additional overshoot, it only reduces it.

[0021] To eliminate or limit voltage overshoot, the inductor current can be diverted from the output capacitor C. OUT and the output node V OUT The current is diverted away. This causes the inductor current to be reduced to zero without a further increase in the output voltage.

[0022] Fig. Figure 3 is a flowchart of a procedure for operating a voltage regulator circuit, such as the voltage regulator circuit of Fig. 1. At 305, a switching circuit is activated and deactivated to charge and discharge an inductor, generating an output voltage and providing an inductor current to an output node of the voltage regulator circuit. At 310, a switching duty cycle of the switching circuit is adjusted to regulate the output voltage using an error signal representative of a difference between a target voltage value and the output voltage. In specific examples, PWM is used to regulate the output voltage.

[0023] At 315, the output voltage is compared to a predetermined maximum output voltage. The predetermined maximum output voltage can be higher than the desired regulated voltage. At 320, the inductor current is diverted away from the output node if the output voltage exceeds the predetermined maximum output voltage.

[0024] Back to Fig. Figure 1 of the voltage regulator circuit includes a shunt circuit to dissipate the inductor current. This shunt circuit diverts the inductor current away from the output node and the output capacitor when the output voltage exceeds a predetermined maximum output voltage. The shunt circuit includes transistor M3, which is connected in parallel to inductor L. Transistor M3 acts as a shunt switch controlled by a hysteresis comparator 120. The output of comparator 120 is active, or high, when the output voltage reaches a predetermined maximum output voltage value (V). HI ) increases. Due to its hysteresis, the output of comparator 120 does not return to inactive or low levels before the output voltage reaches a value lower than V. HI (e.g. the desired regulated voltage level V) REG ) falls off.

[0025] Fig. 4 represents current and voltage waveforms for the voltage regulator circuit of Fig. 1. The upper graphic in Fig. Figure 4 shows the voltage regulator circuit, which is subject to the same load drop transient that occurs at time t1, as in Fig. 2. In Fig. 4 are the waveforms for I L and V OUT The same applies before t1 as in Fig. 2. Immediately after t1, the total inductor current 405 (including the DC component, I) MAX ) initially supplied to the output capacitor, which results in V OUT initially increases. However, if V OUT on V HI increases (in the lower graph of Fig. (4 at time t2), comparator 120 is triggered and transistor M3 is switched on. As shown in the waveform for I M3As shown, the inductor current 405 is then diverted away from the output capacitor and flows instead into M3, which operates as a "load-drop shunt". While M3 is switched on, the main control loop transistors M1 and M2 are both switched off. With M3 switched on, the inductor current can be reduced to zero without any further increase in the output voltage 410.

[0026] Because the flowing inductor current does not reach the output capacitor C OUT The current flowing in the inductor doesn't necessarily have to drop to zero "quickly." The speed at which the current falls to zero depends on the size of transistor M3. A smaller M3 (i.e., a higher on-state resistance R) DS(ON) ) accelerates the fall to zero and is less expensive in terms of silicon component area, however, M3 should not be too small because it affects the energy E (E = ½LI) stored in the inductor MAX 2) must be diverted. Additionally, if the waste exceeds M3 V OUT plus a diode drop, then switch on the body diode of M2, which limits the voltage drop across M3 and potentially C OUT brings it back into the current loop. The decay follows an exponential curve due to the decay of the changing current multiplied by the resistance (IR) in M3. An example of a good compromise for performance between cost and power dissipation is to choose the size of M3 so that it is close to 5-10% of the size of M2. The low hysteresis voltage level of comparator 120 should be set so that when the output voltage subsequently drops close to the target voltage value V REG When the current drops (due to leakage current or because a new load is switched on), M3 is switched off and normal control loop operation resumes.

[0027] Fig. Figure 5 is a circuit diagram of another example of a 500-volt voltage regulator circuit. The circuit is a buck converter circuit as in Fig. 1 and includes the inductor 502, the transistor with top switch (M1), the transistor with bottom switch (M2), a comparator 520 with hysteresis and the error amplifier 512 as shown in Fig. 1 on. The difference to Fig. 1 is that the shunt circuit includes a current matching amplifier 522 and a transistor M4, which is powered by V OUT The current matching amplifier 522 is connected to ground and has a shunt switch. The inputs of the current matching amplifier 522 are connected to the bottom-switch transistor M2 and the shunt-switch transistor M4. The output of the current matching amplifier 522 is connected to the control gate of M4, and the current amplifier has an activation input connected to the output of the comparator 520.

[0028] Fig. 6 represents current and voltage waveforms for the voltage regulator circuit of Fig. 5. The operating principle is the same as that of the circuit of Fig. 1 up to time t2. In the upper diagram, the voltage regulator circuit shows the same load drop transients that occur at time t1, as in Fig. 4 exposed, and before the load drop transients the inductor current waveform shows, I L , in Fig. 6 a normal ripple at the DC / DC switching frequency. After time t1, the total inductor current 605 (including the DC component, I) is initially MAX ) the output capacitor C OUT supplied. At time t2, comparator 520 triggers (e.g., the output goes high) if V OUT on V HI increases.

[0029] At this point, transistor M1 with the switch in the upper position is switched off, and the shunt-switch transistor M4 is switched on, and the current-matching amplifier 522 is activated by the output of comparator 520. The current-matching amplifier 522 controls M4 to generate a positive drain current in M4 so that it matches the negative drain current of M2. Fig. Figure 6 shows the waveform for I M4 the inductor current flowing through M4. To the extent that these drain currents of M2 and M4 "match", the resulting fraction of the inductor current that flows to the output capacitor C is OUT The voltage supplied is zero, and the output voltage 610 is not exceeded by more than V HI increase, as shown in the lower graph of Fig. Figure 6 shows that the size of transistor M4 can be equal to or proportional to M2 (e.g., size(M4) = size(M2 / k), where k is a positive integer). As in the example of Fig. 1. The inductor current flowing in M2 and M4 does not go to the output capacitor C. OUT and does not need to reach zero quickly. The shunt switch connection is removed when V OUT the voltage drops to less than the low hysteresis voltage level of comparator 520, and the circuit returns to normal operation.

[0030] The circuits in the examples of the Fig. 1 and Fig. The five circuits are buck-stop voltage regulator circuits. The approaches given in the examples for attenuating load drop transients in the circuit output can be used in other types of regulator circuits.

[0031] Fig. Figure 7 is a circuit diagram of an example of a boost voltage regulator circuit 700. In the example, the inductor 702 has an input node V. INThe voltage regulator circuit and a switching circuit node 708 are connected. The switching circuit has a first switching transistor M1, which is coupled to the switching circuit node 708 and the circuit ground node, and a second switching transistor M2, which is coupled to the output node and the switching circuit node. The gate driver for the switching circuit is not shown. The shunt switching transistor M3 is coupled in parallel to the inductor 702 and is connected to the switching circuit node 708 and the input node V. IN coupled. If the output voltage V OUT If the trigger voltage of the hysteresis comparator 720 is exceeded, the shunt switching transistor M3 switches on to conduct the inductor current and direct the inductor current away from the output capacitor C. OUT to derive in order to limit the transient of the output voltage.

[0032] Fig.Figure 8 is a circuit diagram of an example of a buck / boost voltage regulator circuit 800. In the example, the inductor 802 is coupled to a first switching circuit node 808 and a second switching circuit node 809. The switching circuit has a first switching transistor MA, which is connected to an input node V. IN and the first switching circuit node 808, and a second switching transistor MB, which is coupled to the first switching circuit node 808 and a circuit ground node. The switching circuit further comprises a third switching transistor MC, which is coupled to the second switching circuit node 809 and the circuit ground node, and a fourth switching circuit MD, which is coupled to the second switching circuit node 809 and the output node V. OUTThe shunt switching transistor M3 is coupled to the first switching node 808 and the second switching node 809. As in the other examples, it switches when the output voltage V OUT When the trigger voltage of the hysteresis comparator 820 is exceeded, the shunt switching transistor M3 switches on to control the inductor current I. L to conduct. This diverts the inductor current away from the output capacitor and the output node in order to limit the output voltage in the event of a load drop transient.

[0033] The method, circuits and systems described herein provide DC / DC regulator circuits that divert inductor current away from the output capacitor in an accurate and safe manner to limit output voltage transients and prevent system shutdown or circuit damage.

[0034] The foregoing detailed description contains references to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referenced in this document are hereby incorporated in their entirety by reference, as if they were individually incorporated by reference. In the event of inconsistent uses between this document and those documents so incorporated by reference, the use in the incorporated reference(s) should be considered to complement that in this document; for irreconcilable inconsistencies, the use in this document shall prevail.

[0035] In this document, the term "a" is used as is customary in patent documents, so that it includes one or more than one, irrespective of any other instances or use of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive "or", so that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise specified. In the appended claims, the terms "comprising" and "in which" are used as the simple English equivalents of the corresponding terms "comprising" and "whereby".Furthermore, in the following claims, the terms "include" and "comprise" are open terms; that is, a system, device, article, or process that has elements in addition to those listed after such a term in a claim is still considered to fall within the scope of protection of that claim. Additionally, in the following claims, the terms "first," "second," and "third," etc., are used merely as distinguishing features and are not intended to impose numerical requirements on their objects. The process examples described herein may be implemented, at least partially, by a machine or a computer.

[0036] The foregoing description is intended to be explanatory and not limiting. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, as might be seen by a person skilled in the art when reviewing the foregoing description. The summary is provided to enable the reader to quickly grasp the nature of the technical disclosure. It is provided with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Furthermore, various features may be grouped together in the foregoing detailed description to streamline the disclosure. This should not be interpreted as implying that an unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may consist of fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby included in the detailed description, each claim being independent as a separate embodiment. The scope of protection of the invention should be determined with reference to the appended claims, together with the full scope of protection of equivalents for which such claims are valid.

Claims

[1] Voltage regulator circuit comprising the following: a switching circuit configured to adapt a switching duty cycle to regulate an output voltage of an output node of the voltage regulator circuit using an error signal representative of a difference between a target voltage value and the output voltage; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit coupled in parallel to the inductor and designed to divert the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage; an output capacitor coupled to the output node; a comparator circuit coupled to the output node; wherein the switching circuit comprises an upper switching circuit coupled to a switching circuit node and an input node of the voltage regulator circuit, and a lower switching circuit coupled to the switching circuit node and a circuit ground node; the shunt circuit has the following features: a shunt switch coupled to the output node and the circuit ground; and a current matching amplifier comprising inputs coupled to the lower switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an activation input; and wherein the comparator circuit is configured to compare the output voltage with the specified maximum output voltage and to provide an activation signal for the current matching amplifier to divert the inductor current away from the output capacitor. [2] Voltage regulator circuit according to claim 1, comprising the following: an output capacitor coupled to the output node; and a comparator circuit coupled to the output node and configured to compare the output voltage with the specified maximum output voltage and to activate the shunt circuit to divert the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage. [3] Voltage regulator circuit according to claim 1 or 2, comprising the following: a comparator circuit coupled to the output node; wherein the shunt circuit has a shunt switch coupled in parallel to the inductor; and the shunt switch has a control gate coupled to an output of the comparator circuit; and wherein the comparator is configured to compare the output voltage with the specified maximum output voltage and a target voltage lower than the specified maximum output voltage, to activate the shunt switch when the output voltage exceeds the specified maximum output voltage, and to deactivate the shunt switch after activating the shunt switch when the output voltage drops to the target voltage. [4] Voltage regulator circuit according to claim 3, where the inductor is coupled to the output node; wherein the switching circuit comprises: an upper switching circuit coupled to a switching circuit node and an input node of the voltage regulator circuit; and a lower switching circuit coupled to the switching circuit node and a circuit ground node; and wherein the shunt switch is coupled in parallel to the inductor and is coupled to the switching node and the output node. [5] Voltage regulator circuit according to claim 3 or 4, wherein the inductor is coupled to an input node of the voltage regulator circuit; wherein the switching circuit comprises: a first switching circuit coupled to a switching circuit node and a circuit ground node; and a second switching circuit coupled to the output node and the switching circuit node; and wherein the shunt switch is coupled in parallel to the inductor and is coupled to the switching node and the input node. [6] Voltage regulator circuit according to one of claims 3 to 5, the switching circuit has the following features: a first switching circuit coupled to an input node of the voltage regulator circuit and a first switching circuit node; a second switching circuit coupled to the first switching node and a circuit ground node; a third switching circuit coupled to a second switching node and the circuit ground node; and a fourth switching circuit coupled to the second switching node and the output node; and wherein the inductor and the shunt switch are coupled to the first switching node and the second switching node. [7] Method for operating a voltage regulator circuit, wherein the method comprises: Activating and deactivating a switch circuit to charge and discharge an inductor in order to generate an output voltage and provide an inductor current for an output node of the voltage regulator circuit; Adjusting a toggle duty cycle of the switch circuit to regulate the output voltage using an error signal that is representative of a difference between a target voltage value and the output voltage; Comparing the output voltage with a specified maximum output voltage; and Diverting the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage; wherein the diverting of the inductor current involves generating an matching current to match the inductor current and diverting the matched current away from the output capacitor at the output node. [8] The method of claim 7, comprising the following: Charging an output capacitor to generate the output voltage; and where the diverting of the inductor current involves diverting the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage. [9] Method according to claim 8, wherein the diverting of the inductor current further comprises activating a circuit shunt connection to divert the current away from the output capacitor when the output voltage exceeds the predetermined maximum output voltage, and deactivating the circuit shunt connection when the output voltage drops to a target voltage lower than the predetermined maximum output voltage. [10] Method according to any one of claims 7 to 9, wherein the activation and deactivation of the switch circuit comprises pulse width modulation of the switch circuit to charge the inductor in order to generate an output voltage lower than an input voltage into the voltage regulator circuit. [11] Method according to any one of claims 7 to 10, wherein the activation and deactivation of the switch circuit comprises pulse width modulation of the switch circuit to charge the inductor in order to generate an output voltage higher than an input voltage into the voltage regulator circuit. [12] Method according to any one of claims 7 to 11, wherein the activation and deactivation of the switch circuit comprises pulse width modulation of the switch circuit to charge the inductor in order to generate an output voltage lower than an input voltage into the voltage regulator circuit. [13] Voltage regulator circuit comprising the following: a switching circuit configured to adapt a switching duty cycle to regulate an output voltage at an output node of the voltage regulator circuit using an error signal representative of a difference between a target voltage value and the output voltage; an inductor coupled to the switching circuit and configured to provide an inductor current to the output node; and a shunt circuit loop coupled to the inductor and configured to divert the inductor current away from the output node when the output voltage exceeds a predetermined maximum output voltage, and to restore the inductor current to the output node when the output voltage drops to a target voltage lower than the predetermined maximum output voltage; an output capacitor coupled to the output node; wherein the switching circuit comprises an upper switching circuit coupled to a switching circuit node and an input node of the voltage regulator circuit, and a lower switching circuit coupled to the switching circuit node and a circuit ground node; wherein the shunt circuit loop comprises the lower switch circuit and a shunt switch coupled to the output node and the circuit ground; the voltage regulator circuit further comprises the following: a current matching amplifier comprising inputs coupled to the lower switch circuit and the shunt switch, an output coupled to a control gate of the shunt switch, and an activation input; and a comparator circuit coupled to the output node, wherein the comparator circuit is configured to compare the output voltage with the specified maximum output voltage and to provide an activation signal for the current matching amplifier to allow the inductor current to flow in the shunt circuit loop and away from the output capacitor. [14] Voltage regulator circuit according to claim 13, comprising the following: an output capacitor coupled to the output node; and a comparator circuit coupled to the output node and configured to compare the output voltage with the specified maximum output voltage and to activate the shunt circuit loop to divert the inductor current away from the output capacitor when the output voltage exceeds the specified maximum output voltage. [15] Voltage regulator circuit according to claim 14, where the inductor is coupled to the output node; wherein the switching circuit comprises: an upper switching circuit coupled to a switching circuit node and an input node of the voltage regulator circuit; and a lower switching circuit coupled to the switching circuit node and a circuit ground node; and wherein the shunt circuit loop has a shunt switch which is coupled in parallel to the inductor and is coupled to the switching node and the output node. [16] Voltage regulator circuit according to claim 14 or 15, wherein the inductor is coupled to an input node of the voltage regulator circuit; wherein the switching circuit comprises: a first switching circuit coupled to a switching circuit node and a circuit ground node; and a second switching circuit coupled to the output node and the switching circuit node; and wherein the shunt circuit loop has a shunt switch which is coupled in parallel to the inductor and is coupled to the switching node and the input node. [17] Voltage regulator circuit according to one of claims 14 to 16, the switching circuit has the following features: a first switching circuit coupled to an input node of the voltage regulator circuit and a first switching circuit node; a second switching circuit coupled to the first switching node and a circuit ground node; a third switching circuit coupled to a second switching node and the circuit ground node; and a fourth switching circuit coupled to the second switching node and the output node; and wherein the inductor is coupled to the first switching node and the second switching node and the shunt circuit loop has a shunt switch which is coupled in parallel to the inductor to the first switching node and the second switching node.

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