Method for embedding an ELD-DAC in a SAR quantizer

Abstract

Successive Approximation Register (SAR) analog-to-digital converter (ADC) with a digital-to-analog converter (DAC) with an embedded An excess loop delay (ELD) DAC, wherein the DAC receives a SAR control signal and generates a reference level, and the ELD DAC receives an ELD feedback signal that provides ELD feedback during a sample of an analog input signal, the DAC and the embedded ELD DAC comprising a first set of DAC units and a second set of DAC units, one or more, but less than all, of the DAC units being shared between the first and second sets of DAC units, one of the first and second sets of DAC units receiving the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receiving the ELD feedback signal during a sample phase.

Description

AREA OF REVELATION

[0001] This document generally, but not exclusively, concerns integrated circuits and, in particular, analog-to-digital converter (ADC) circuits. BACKGROUND

[0002] An analog-to-digital converter (ADC) circuit can be used to convert an analog signal into a digital signal, which can then be further processed or used in the digital domain. Continuous-time (CT) delta-sigma (DS) ADCs are good for precision and low-power applications and use successive approximation register (SAR) ADCs as quantizers to reduce power. A SAR ADC circuit can perform bit trials to compare portions of the analog signal to a reference voltage to determine the digital bit values of a digital word representing a particular sample of the analog signal. A SAR ADC can use a capacitor array of a digital-to-analog converter (DAC) to perform the bit trials to determine the respective digital bit values of the digital word. SAR ADCs are desirable because they require low power.However, the successive nature of the conversion means that the conversion is relatively slow, and excess loop delay (ELD) DACs are commonly used in addition to the DACs of the SAR ADC to compensate for the delay introduced by the SAR conversion.

[0003] US 2016 / 0 233 872 A1 describes a method and apparatus for compensating excessive loop delay in continuous-time sigma-delta analog-to-digital converters.

[0004] US 2018 / 0 219 558 A1 describes a hybrid second-order noise coupling technique for continuous-time delta-sigma modulators.

[0005] US 9,385,740 B2 describes an analog-to-digital converter based on successive approximation, SAR ADC, and corresponding method. SUMMARY OF REVELATION

[0006] Against this background, it is an object of the present invention to provide further improved analog-to-digital converter (ADC) circuits and in particular an improved digital-to-analog converter (DAC).

[0007] The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims.

[0008] This document describes analog-to-digital converter (ADC) circuits and, in particular, an improved digital-to-analog converter (DAC) including an embedded excess loop delay (ELD) DAC used in successive approximation register (SAR) quantizers, which in turn are used in ADCs such as continuous-time (CT) delta-sigma (CTDS) ADCs.

[0009] A SAR ADC converts an input signal into a digital code by successively comparing the sampled input signal to various reference levels. In exemplary embodiments, the input signal may be in the charge domain, the voltage domain, the current domain, or in a multi-domain configuration. Gain of an ELD DAC in a SAR quantizer is a key factor for delta-sigma loop stability when the SAR ADC is used in a CTDS ADC. This document describes methods and apparatus for enhancing (without any reference voltage tuning) the use of DAC units, such as capacitors, in the SAR ADC to save power, area, and, when capacitors are used as DAC units, load capacitance. The DAC units may also include current sensors, voltage sensors, and the like.

[0010] In exemplary embodiments, methods and apparatus are described for controlling excess loop delay compensation (ELD-DAC) DAC gain by efficiently utilizing DAC units such as capacitors in the ELD-DAC and DACs of the SAR ADC. In exemplary embodiments, feedback values are calculated to control the ELD gain, which is normalized by a DAC gain, and dedicated sampling capacitors are provided to enable gain tuning through a capacitance ratio. Furthermore, the ELD-DAC and DAC of the SAR ADC are designed to partially share DAC units to minimize the total DAC units used in the SAR quantizer while maintaining operational flexibility.

[0011] According to a first aspect, a DAC of a SAR ADC is provided that includes an embedded ELD DAC. The DAC receives a SAR control signal and generates a reference level, and the ELD DAC receives an ELD feedback signal that provides ELD feedback during sampling of an analog input signal. The DAC and the embedded ELD DAC are characterized by a first set of DAC units and a second set of DAC units, wherein one or more, but not all, of the DAC units are shared between the first and second sets of DAC units. During operation, one of the first and second sets of DAC units receives the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receives the ELD feedback signal during a sampling phase.

[0012] In exemplary embodiments, the DAC units are used to set a gain of the DAC and a gain of the ELD-DAC, which is normalized by a gain of the DAC. In an exemplary configuration, the first set of DAC units has values that are normalized by 2 N where N = 0 to N = n-1 or N = 0 to N = n-2 for respective DAC units of an n-bit SAR ADC, and the second set of DAC units has respective values given by 2 Nwhere N = -x to N = nx-1 or N = -x+1 to N = nx-1, where nx DAC units are shared between the first and second sets of DAC units. During operation, the first set of DAC units receives the SAR control signal and the second set of DAC units receives the ELD feedback signal for ELD gains less than one, while the first set of DAC units receives the ELD feedback signal and the second set of DAC units receives the SAR control signal for ELD gains greater than one.

[0013] In exemplary embodiments, the DAC is incorporated into a delta-sigma analog-to-digital converter (DS-ADC). The DS-ADC includes a sample / hold circuit that samples the analog input signal, a comparator that compares a difference between the sampled analog input signal and the ELD feedback signal with the reference level, and a SAR and ELD logic circuit that converts outputs of the comparator into the SAR control signal representing the analog input signal and the ELD feedback signal versus the reference level. The SAR and ELD logic circuit further outputs the SAR control signal, the ELD feedback signal, and the analog-to-digital conversion results. In exemplary embodiments, the DAC generates the reference level for input to the comparator during respective bit trials.The DS-ADC may further include a loop filter that receives the analog input signal and the analog-to-digital conversion results and provides an output to the sample / hold circuit.

[0014] In further exemplary embodiments, the ELD feedback signal is applied to the ELD DAC during the sampling phase and the SAR control signal is applied to the DAC during the bit trial phase, and any ELD DAC units not shared with DAC units of the DAC are driven to a fixed DAC unit value during the bit trial phase.

[0015] In yet further exemplary embodiments, the sample / hold circuit includes an additional sampling capacitor connected between the analog input signal and ground. The additional sampling capacitor is separate from the first and second sets of DAC units and provides flexible gain control. In exemplary embodiments, the DAC units are capacitors used to adjust a gain of the DAC and a gain of the ELD-DAC, wherein a signal gain k sig of the analog input signal is controlled by capacitance ratios during top plate scanning as follows: ksig=(CSa+CD+CEs) / CD, where C Sa is a capacitance of the additional capacitor, C D is a sum of the capacitances of capacitors of the DAC receiving the SAR control signal, and C Esis a sum of the capacitances of capacitors of the ELD-DAC excluding any capacitors shared between the first and second sets of capacitors. In other embodiments, the signal gain k sig of the analog input signal is controlled by capacitance ratios during a sub-plate scan as follows: ksig=(CSa+CDs) / CD, where C Sa is a capacitance of the additional sampling capacitor, C Ds is a sum of capacitances of the capacitors of the DAC that receives the SAR control signal used to sample the analog input signal, and C D is a sum of the capacitances of the DAC capacitors. On the other hand, the ELD gain k ELD controlled by the following capacity ratio: kELD=CE / CD. where C E is a sum of the capacities of the ELD-DAC.

[0016] In other exemplary embodiments, the sample / hold circuit receives first and second differential analog inputs applied to respective DACs and embedded ELD DACs, each DAC and embedded ELD DAC comprising a first set of DAC units and a second set of DAC units, wherein one or more, but less than all, of the DAC units are shared between the first and second sets of DAC units. Furthermore, one of the first and second sets of DAC units receives the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receives the ELD feedback signal during a sample phase.During operation, one of the first and second sets of DAC units of the respective DACs and embedded ELD DACs receives the SAR control signal during the bit trial phase, and another of the first and second sets of units of the respective DACs and embedded ELD DACs receives the ELD feedback signal during a sample.

[0017] According to a second aspect, a successive approximation register (SAR) analog-to-digital converter (ADC) is provided, comprising a sample / hold circuit that samples an analog input signal and an excess loop delay (ELD) feedback signal, a comparator that compares, for each sample of the analog input signal, the sampled ELD feedback signal with the sampled analog input signal to generate a delta, a SAR and excess loop delay (ELD) logic circuit, and a digital-to-analog converter (DAC).The SAR and ELD logic circuit performs bit trials for each sample of the analog input signal to generate a successive approximation register (SAR) control signal, wherein the bit trials for each bit trial comprise generating a reference level based on the SAR control signal, comparing the delta to the reference level, and outputting the SAR control signal from the comparison result. The SAR and ELD logic circuit further generates the ELD feedback signal and analog-to-digital conversion results. The DAC receives the ELD feedback signal while sampling the analog input signal during a sampling phase and performs bit trials during a bit trial phase. The DAC comprises an embedded ELD DAC and comprises a first set of DAC units and a second set of DAC units, wherein one or more, but not all, DAC units are shared between the first and second sets of DAC units.During operation, one of the first and second sets of DAC units receives the SAR control signal during the bit trial phase, and another of the first and second sets of DAC units receives the ELD feedback signal during the sampling phase. In exemplary embodiments, the sample / hold circuit includes a sampling capacitor connected between the analog input signal and ground. The sampling capacitor is separate from the first and second sets of DAC units and provides flexible gain control.

[0018] According to a third aspect, a method of analog-to-digital conversion is provided, including sampling an analog input signal and an excess loop delay (ELD) feedback signal fed back during a sampling of the analog input signal. For each sample of the analog input signal, the method comprises: subtracting the sampled ELD feedback signal from the sampled analog input signal to generate a delta; performing bit trials to generate a successive approximation register (SAR) control signal, wherein the bit trials comprise, for each bit trial, generating a reference level based on the SAR control signal, comparing the delta to the reference level, and outputting the SAR control signal from the comparison result. The bit trials are performed by a DAC having an embedded ELD DAC.The DAC and the ELD DAC together comprise a first set of DAC units and a second set of DAC units, with one or more, but not all, of the DAC units being shared between the first and second sets of DAC units. One of the first and second sets of DAC units receives the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receives the ELD feedback signal during a sample phase. The analog-to-digital conversion results are generated and output.

[0019] In exemplary embodiments, the DAC units are capacitors. In such embodiments, sampling the analog input signal using top-plate sampling comprises sampling capacitances C S = C Sa + C D + C Es where C S is a sum of capacitances used in sampling, C Sais a capacitance of an additional sampling capacitor connected between the analog input signal and ground, C D is a sum of capacitances of capacitors of the DAC and C Es is a sum of capacitances of capacitors of the embedded ELD-DAC excluding any capacitors shared between the DAC and the ELD-DAC.

[0020] In such embodiments, sampling of the analog input signal may also use sub-plate sampling on sampling capacitances C S = C Sa + C Ds where C S is a sum of capacitances used in sampling, C Sa is a capacitance of an additional sampling capacitor connected between the analog input signal and ground, and C Dsis a sum of capacitances of capacitors of the DAC used to sample the analog input signal. The ELD feedback signal can also be set to C E be sampled, where C E is a sum of capacitances of ELD capacitors.

[0021] In some exemplary embodiments, where the DAC includes a first set of capacitors having respective capacitance values determined by 2 N where N = 0 to N = n-1 or N = 0 to N = n-2 for respective capacitors of an n-bit SAR ADC, and a second set of capacitors with respective capacitance values determined by 2 Nwhere N = -x to N = nx-1 or N = -x+1 to N = nx-1, the operations further include dividing nx capacitors between the first and second sets of capacitors. In such embodiments, the ELD feedback signal is provided to one of the first and second sets of capacitors during a sample of the analog input signal, and the SAR control signal is provided to the other of the first and second sets of capacitors during respective bit attempts. In such embodiments, a set of capacitors to which the ELD feedback signal is provided depends on whether a gain of the ELD feedback signal is greater or less than one.

[0022] This summary is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation. Fig. 1 is a functional block diagram of an example of a continuous-time delta-sigma ADC (CTDS-ADC) including a successive approximation register (SAR) analog-to-digital converter (SAR-ADC) circuit. Fig. 2 is a functional block diagram of a 3-bit SAR ADC for illustrating an operation of a SAR ADC. Fig. 3 illustrates timing diagrams for the operation of the 3-bit SAR ADC from Fig. 2. Fig. Figure 4 illustrates a 3-bit SAR ADC approximation of V in using the 3-bit SAR ADC Fig. 2. Fig. 5A-5F together illustrate the operation of the 3-bit SAR ADC example from Fig. 2-4, where the DAC has a capacitive structure and is sampled onto an upper plate. Fig. Figure 6 illustrates a block diagram of a SAR ADC with an embedded ELD DAC. Fig. Figure 7 illustrates an exemplary capacitive top-plate sampling DAC structure for a DAC of a SAR ADC and an ELD DAC. Fig. Figure 8 illustrates an exemplary capacitive top-plate sampling DAC structure for a DAC of a SAR ADC and an embedded ELD DAC that fully share the capacitors for use with the ELD signal during the sampling phase and with the SAR control signal during the bit trial phase. Fig. 9 illustrates a block diagram of a SAR ADC with a DAC and an embedded ELD DAC sharing some, but not all, DAC units in an example embodiment. Fig. Figure 10A illustrates an example capacitor configuration for partially sharing DAC and ELD-DAC capacitors to provide an ELD feedback gain less than one. Fig. Figure 10B illustrates an example capacitor configuration for partially sharing DAC and ELD-DAC capacitors to provide an ELD feedback gain greater than one. Fig. Figures 11A-11F illustrate how partial sharing of the DAC capacitances and ELD-DAC capacitances can be used to achieve an ELD feedback gain of 0.25. Fig. Figure 12 illustrates an example capacitor configuration for partially splitting DAC and ELD-DAC capacitors to provide an ELD feedback gain of 0.5. Fig. Figure 13 illustrates another embodiment in which the signal gain is further controlled by providing an additional sampling capacitor. Fig. Figure 14 is a functional block diagram of an example of a differential SAR quantizer sharing a DAC and an ELD DAC. Fig. Figure 15 illustrates an exemplary differential top-plate sampling SAR quantizer configuration that uses capacitors as DAC units and completely shares a DAC and an ELD DAC. Fig. 16 is a flowchart illustrating a technique for performing a successive approximation register analog-to-digital conversion with an embedded excess loop delay compensation operation in an exemplary embodiment. Fig. 17 is a functional block diagram of an example of a continuous-time delta-sigma ADC (CTDS-ADC) including a successive approximation register (SAR) analog-to-digital converter (SAR-ADC) with embedded ELD-DAC circuitry in an example embodiment. DETAILED DESCRIPTION

[0024] The following description with reference to Fig. 1-17 illustrates specific embodiments sufficiently to enable one skilled in the art to practice them. Other embodiments may incorporate structural, logical, process, and other changes. Portions and features of some embodiments may be included in or substituted for those of other embodiments. Embodiments presented in the claims include all available equivalents of those claims. These embodiments are presented for illustrative purposes only and are not intended to limit or restrict the scope of the disclosure or the claims presented herein.

[0025] As noted in the background above, successive approximation register analog-to-digital converters (SAR-ADCs) are desirable as quantizers in continuous-time (CT) delta-sigma (DS) ADCs because of their low power requirements. However, the successive nature of the conversion means that the conversion is relatively slow, and excess loop delay compensation (ELD) DACs are commonly used in addition to the SAR ADC's DACs when SAR ADCs are used as quantizers in CTDS ADCs to compensate for the delay introduced by the SAR conversion. CTDS ADCs are well-suited for precision and low-power applications and use SAR ADCs as quantizers to reduce power. This disclosure describes, among other things, techniques for improving (without any reference voltage tuning) the use of DAC units in SAR ADCs to save power, area, and input load.

[0026] A flash ADC is a type of analog-to-digital converter that uses a linear voltage ladder or capacitive voltage divider with comparators at each intersection of the linear voltage ladder or capacitive voltage divider to compare the input voltage to voltage references. The outputs of the comparators are fed into a digital encoder, which converts the inputs to a binary value. Flash ADCs are very fast compared to many other types of ADCs and have a relatively simple design. However, a flash ADC can require a large number of comparators compared to other ADCs, especially when increasing resolution. For example, a flash ADC requires 2 n - 1 comparator for an n-bit conversion. The size, power consumption, and cost of all the comparators generally make flash ADCs impractical for accuracies greater than 8 bits (255 comparators).

[0027] There are significant advantages to increasing quantizer resolution, such as jitter tolerance and relaxing delta-sigma designs, but using high-resolution flash ADCs is impractical for most ADC applications, such as continuous-time delta-sigma (CTDS) ADCs. Employing SAR ADCs can save power and area for higher-resolution quantizers. However, SAR ADCs require much longer conversion time than flash ADCs and require excess loop delay (ELD) compensation. To eliminate the additional compensation and a DAC and summing amplifier, ELD DACs can be embedded within SAR quantizers. Improved designs for embedding ELD DACs within SAR quantizers are described below.

[0028] Fig. 1 is a functional block diagram of an example CTDS ADC 100 including a SAR ADC circuit 110. It should be understood that in certain embodiments, a discrete-time (DT) delta-sigma (DS) ADC may also be used. As noted above, SAR ADCs are generally desirable for use as a medium for high-resolution quantizers in CTDS ADCs due to their low power characteristics. As illustrated, the analog input voltage V INapplied to a loop filter 120. To compensate for a conversion delay error introduced by the SAR ADC circuit 110, an ELD DAC circuit 130 may be provided to feed back delayed versions of the output of the SAR ADC circuit 110 to add the output of the loop filter 120 at a summer 140. In particular, the ELD DAC circuit 130 functions to feed back the previous output code of the SAR ADC circuit 110 and to multiply the previous reference code for loop stability.

[0029] A SAR ADC circuit 110 is a type of ADC that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before converging to an output for each conversion. The SAR ADC circuit 110 may include a sample-and-hold circuit to capture the input voltage. An analog voltage comparator compares the input voltage to the output of a DAC of the SAR ADC and outputs the result of the comparison to a SAR logic subcircuit that provides an approximate digital reference code to the DAC of the SAR ADC. The DAC of the SAR ADC converts the digital reference code to a voltage reference and supplies the comparator with an analog voltage equal to the digital reference code output by the SAR.During operation, the SAR is initialized so that the most significant bit (MSB) equals a reset or center value, which is fed into the DAC of the SAR-ADC, which then provides the analog equivalent of this digital code (0) to the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds the input voltage, the comparator causes the SAR to reset the bit; otherwise, the bit remains as 1. The next bit is set to 1, and the same test is performed. This binary search continues until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage versus the input full scale range of + / -V. Ref and will be issued by the SAR at the end of implementation.

[0030] Fig. Figure 2 is a functional block diagram of a 3-bit SAR ADC 200 for illustrating operation of a SAR ADC 110. As illustrated, the input voltage V IN sampled by a sample / hold circuit 210 with a timing determined by the timing circuit 220 upon application of the sampling signal Samp ( Fig. 3). The sampled voltage of V IN is applied to a comparator 230 to compare the sampled voltage with the feedback voltage value V DAC of the previous output code from the 3-bit SAR logic circuit 240, as provided by a 3-bit DAC 250. A SAR logic circuit 240 controls ADC operation during the bit trials. When the bit trials are complete, the digital value of the sampled and held voltage is available as output D[2:0]. The full scale for the SAR ADC is 2*V. Ref . As shown in the time series diagrams from Fig. 3, the comparator 230 is controlled with a timing determined by trial pulses from the timing circuit 220 for a comparison of the sampled voltage against each feedback SAR reference code to enable the successive approximation of the sampled voltage to produce SAR outputs D k-1 , D k , D k+1 , D k+2 to provide.

[0031] For example, as in Fig. 4 is illustrated for simplicity as an asymmetric operation, the 3-bit SAR logic 240 with a V DAC which is the center of a full scale input voltage of 0. In the illustrated case, V IN in the first attempt is greater than 0, so that D[2] = 1. In the second attempt, V IN with the center of the upper range (½V Ref ) compared. Since V in less than ½V Ref is, D[1] = 0. Then, in the third attempt, V INwith the midpoint of the range between ½V Ref and 0 (1 / 4V Ref ) compared. Since V ln greater than 1 / 4V Ref , D[0] = 1. Accordingly, the 3-bit approximation of V IN an output code D[2:0] = 101.

[0032] Fig. 5A-5F together illustrate the operation of the 3-bit SAR ADC example from Fig. 2-4, where the DAC has a capacitive structure and is sampled onto an upper plate.

[0033] As in Fig. 5A for a DAC 500 having respective capacitances 4C, 2C, C and C, the sampling switch 510 is for top plate sampling of V in and closed to charge the respective capacitors of the DAC 500, so that each capacitor has a charge equal to its capacitance times the input voltage minus any offset voltage. The total charge Q0 when V in sampled, Q0 =0 (4C+2C+C+C)Vin , where V in = V DAC = V X0 applies.

[0034] As in Fig. 5B, the sampling switch 510 is open to measure the amount of charge for V in on the respective capacitors of the DAC 500 (holding the sampled voltage) and V DAC is controlled by the subplate voltages. The total charge Q1 is Q1 = (4C+2C+C+C)V in , where V in = V DAC = V X1 The first bit test is performed to determine whether V in is greater than 0. Assuming V DAC < 0, bit D[2] is set to 0.

[0035] As in Fig. 5C, the sampling switch 510 remains open and, if the first bit attempt was set as D[2]=0, V Ref fed back to the most significant bit capacitor 4C. In this state, the total charge Q2 at the node of V DACQ2 = 4C(V X2 - V Ref )+(2C+C+C)V X2 , where V DAC = V X2 applies. Assuming V DAC > 0, bit D[1] is set to 1 as the output of the second bit attempt.

[0036] As in Fig. 5D, the sampling switch 510 remains open and, if the second attempt was set as D[1]=1, -V Ref fed back to the second most significant bit capacitor 2C. The total charge Q3 is Q3 = 4C(V X3 - V Ref )+4C(V X3 + V Ref )+(C+C)V x3 , where V DAC = V X3 applies. Assuming V DAC < 0, the bit D[0] is set to 0 as the output of the third bit trial. This completes the bit trial phase for a 3-bit SAR ADC.

[0037] Fig. Figure 5E illustrates the state of the capacitors for subsequent bit attempts for a higher resolution SAR ADC.

[0038] Fig. Figure 5F illustrates the resulting approximation of V in for the respective steps in Fig. 5A-5E for an output code D[2:0] = 010.

[0039] Accordingly, the SAR-ADC 110 performs N timing comparisons, where N is the number of bits of the ADC, which is a relatively slow operation. However, the SAR-ADC 110 requires a relatively small area, far fewer comparators, and much less power than a flash ADC.

[0040] However, the ELD-DAC 130 is added to the delta-sigma loop to address the conversion delay introduced by the SAR-ADC 110. The ELD-DAC 130 also consumes power and area. It is desirable to embed at least a portion of the ELD-DAC 130 within the SAR-ADC 110 to reduce the area and power consumed by the ELD-DAC 130. This can be achieved in several ways.

[0041] For example, Fig. 6 illustrates a SAR ADC 600 with an embedded scaled ELD DAC 610. As illustrated, the SAR and ELD logic circuit 620 provides a combined ELD DAC 610 and DAC 630 with an ELD signal and a SAR control signal, respectively. A gain of the ELD DAC 610 and a gain of the DAC 630 are determined by respective external reference voltages V Ref1 and V Ref2A comparator 640 compares the combined output of the ELD-DAC 610 and DAC 630 and provides the SAR and ELD control logic with a comparison result. The SAR and ELD control logic circuit 620 controls operation during the bit trials based on the comparison result. When the bit trials are complete, the SAR converts the difference between the input and the ELD signal into a digital code, dout. Unfortunately, this approach requires a second set of external reference voltages, which requires additional area and power for external reference voltage generation. Additionally, the circuit requires tuning to compensate for any errors in the reference voltages, and calibration is required to find the optimal operating conditions.

[0042] Fig. Figure 7 illustrates a capacitive top-plate sampling DAC structure for a DAC with an embedded ELD DAC. In this example, the SAR capacitors 700 and the ELD capacitors 710 are connected to the top plate for sampling under the control of switch 720 during respective bit attempts at comparator 730. In this example, the ELD capacitors 720 have gain control values k provided for gain adjustment. The gains affect, for example, the performance and stability of the delta-sigma loop in a CTDS ADC 100. The input signal gain is proportional to the SAR capacitors 700 plus the ELD capacitors 710 (=(4C+2C+C) + (4kC+2kC+C) in this example).The SAR feedback gain is proportional to the SAR capacitors 700 plus the unit capacitance (=(4C+2C+C)+C), while the ELD feedback gain is proportional to the ELD capacitors 710 plus the unit capacitance (=(4kC+2kC+kC)+kC). The ELD is updated at the beginning of the bit trial phase; however, these ratios must be guaranteed to maintain the stability of the delta-sigma loop. Accordingly, the total capacitance is proportional to the gain k, and the gain of the ELD DAC and the DAC of the SAR ADC are tied to each other to maintain stability.

[0043] Fig. Figure 8 illustrates an exemplary capacitive top-plate sampling DAC structure for a DAC of the SAR ADC and an embedded ELD DAC that fully share capacitors 800 for use with the ELD feedback signal during the sampling phase (switch 810 closed) and with the feedback SAR signal during the bit trial phase (switch 810 open) during respective trials at comparator 820. As with the capacitive DAC structure in Fig. 7, for example, the gains affect the performance and stability of the delta-sigma loop in a CTDS ADC 100. The input signal gain is proportional to the capacitors 800. The SAR feedback gain is proportional to the capacitors 800 plus the unity capacitance (=(4C+2C+C)+C), while the ELD feedback gain is proportional to the capacitors 800 plus the unity ELD capacitance (=(4C+2C+C)+C). Accordingly, the gain is only 1, and there is less flexibility for the CTDS ADC design. Partially shared capacitors in embedded ELD-DAC

[0044] The architectures described below embed ELD DACs within the DACs of a SAR ADC in a manner that allows for lower and higher gain options while limiting capacity, area, and power requirements. The embedded ELD DACs in the following embodiments are characterized in at least two ways.

[0045] First, capacitors are partially shared between the DAC of the SAR-ADC and the ELD-DAC. In exemplary embodiments, portions of a DAC of the SAR-ADC are used as an ELD-DAC to achieve lower gain (gain < 1), while portions of an ELD-DAC are used as a DAC of the SAR-ADC to achieve higher gain (gain > 1). In this way, capacitor efficiency is improved while providing gains other than unity without using external gain control circuitry, thereby minimizing circuit area and power and minimizing circuit complexity.

[0046] Second, signal gain is adjusted by adding an additional sampling capacitor. This additional sampling capacitor eliminates the need for a separate set of reference voltages to precisely control the gain. Furthermore, an additional sampling capacitor has the advantage of requiring a smaller area and lower power than an external reference voltage circuit.

[0047] Fig. Figure 9 illustrates a block diagram of a SAR ADC 900 with a DAC 630 and an embedded ELD DAC 610 sharing DAC units in an exemplary embodiment. The differences between Fig. 9 and Fig. 6 are that the ELD-DAC 610 and the DAC 630 share DAC units in a combined DAC 910 and that Fig. 9 is used only as a reference. Despite the description below in the voltage domain, it is understood that the systems and methods described herein can be used in the charge domain, the current domain, and a multi-domain configuration.

[0048] Although the following embodiments are described in connection with a top-plate scanning operation, it is understood that bottom-plate scanning may also be used. It is also understood that the operations may be single-ended or differential.

[0049] The goal of the embodiments described herein is to control signal, SAR ADC, and ELD DAC gains, for example, to provide better CTDS ADC loop stability. The designs described herein achieve this goal while providing minimal overhead to conserve power and area. For example, by partially overlapping the capacitor sets of the SAR ADC and ELD DAC, gain control for the SAR ADC and ELD DAC can be achieved with lower area and power.

[0050] Fig. Figure 10A illustrates an exemplary capacitor configuration for partially sharing the SAR ADC's DAC capacitors and ELD DAC capacitors to provide an ELD feedback gain less than one. As illustrated, the SAR capacitors 1000 (4C, 2C, and C) share a capacitance C with the ELD capacitors 1010 (C, 0.5C, 0.25C). In this example, the ELD subcapacitors 0.5C and 0.25C 1020 are added to the SAR capacitors 1000 to provide the ELD capacitors that are in the same 2 n-relationship to each other. Furthermore, since the SAR capacitances 1000 range up to 4C, while the ELD capacitances 1010 range up to C, the ELD feedback gain can be controlled down to 0.25 (C / 4C). This variable gain is achieved with considerably less capacitance space due to the capacitance sizes of C, 0.5C, 0.25C compared to the capacitances of 4C, 2C, C used when the DAC of the SAR ADC and the ELD DAC are completely separate. Accordingly, the ELD feedback gain is, in contrast to the configuration of Fig. 8 flexible because the ELD gain can be reduced by shifting bits.

[0051] On the other hand, Fig. 10B shows an exemplary capacitor configuration for partially sharing the SAR ADC's DAC capacitors and ELD DAC capacitors to provide a SAR feedback gain greater than one. As illustrated, the ELD capacitors 1030 (4C, 2C, and C) share a capacitance C with the SAR capacitors 1040 (C, 0.5C, 0.25C). It should be understood that the SAR capacitors and ELD capacitors are Fig. 10A are reversed. In this example, the SAR subcapacitors 0.5C and 0.25C 1050 are added to the ELD capacitors 1030 to provide the SAR capacitors that are in the same 2 n-relationship to each other. Furthermore, since the ELD capacitances 1030 range up to 4C, while the SAR capacitances 1040 range up to C, the SAR feedback gain can be controlled up to 4 (4C / C). This variable gain is achieved with considerably less capacitance space due to the capacitance sizes of C, 0.5C, 0.25C compared to the capacitances of 4C, 2C, C used when the DAC of the SAR ADC and the ELD DAC are completely separate. Accordingly, the SAR feedback gain is, in contrast to the configuration of Fig. 8 flexible because the SAR gain can be increased by shifting bits.

[0052] Fig. 11A-11F illustrate how a partial sharing of the DAC capacitances 1000 and ELD DAC capacitances 1010 ( Fig. 10) can be used to achieve an ELD gain of 0.25. In the sampling phase, the ELD gain is adjusted by the ELD-DAC capacitances, while bit trials during the bit trial phase are run through the comparator 1100 under the control of the SAR and ELD logic 1110, which in turn generates the 3-bit translation SAR output D[2:0] as well as the SAR feedback code SAR[2:0] and the ELD feedback code ELD[2:0]. As for a combined 3-bit SAR / ELD-DAC in Fig. 11A, the SAR capacitors 1000 receive the output feedback SAR code SR[2:0] at SAR capacitances 4C, 2C, and C, respectively. However, the 3-bit ELD-DAC feedback code ELD[2:0] is fed back to the capacitance C of the SAR capacitors 1000 and the ELD subcapacitances 0.5C and 0.25C, respectively, as illustrated. This operation is controlled by the same timing signals Samp and Trial as described above with reference to Fig. 2-4. During bit attempts, SAR[x] = 1 implies that a voltage of -V Ref is applied to the DAC of the SAR ADC during the next bit attempt, while SAR[x] = 0 implies that a V Ref voltage is applied to the DAC of the SAR ADC during the next bit attempt, where x=2, 1, or 0, indicating bits for a 3-bit output. During the sampling phase, ELD[x] = 1 implies that V Ref is applied to the ELD-DAC, while ELD[x] = 0 implies that a -V Ref voltage is applied to the ELD DAC, where x=2, 1 or 0. During the sampling phase, the ELD feedback code ELD[2:0] is applied to the SAR output D k-1 [2:0] shown, while D k-1is the SAR output from the previous conversion cycle. During bit attempts, the undivided ELD subcapacitors 1020 are driven to a fixed value and remain in this state for all bit attempts. In this example, the fixed value is mapped to ground with a value of 0.

[0053] As in Fig. 11B, during an input scan of the first sample, the ELD-DAC feedback code ELD[2:0] (=D k-1 =

[011] ). The ELD feedback is applied to the ELD capacitors 1010 during the sampling phase for an ELD subtraction phase by applying -V Ref to the SAR capacity C as ELD[2] = [0], V Ref to the ELD capacity 0.5C as ELD[1] = [1] and V Ref0.25C is applied to the ELD capacitance as ELD[0] = [1]. Once the ELD has been adjusted during the sampling phase, the bit trials for the first sample can begin. It should be noted that since charge subtraction occurs immediately during the sampling phase, the charge on the capacitors already represents the subtraction value.

[0054] Fig. Figure 11C illustrates the first trial during the bit trial phase of the partially shared DAC 1000 and ELD DAC 1010. During the first trial, initiated by trial bit 1130, switch 1120 is opened and all capacitors initially grounded. The charge of the sampled signal is distributed across the capacitors. Assuming that comparator 1100 outputs a state of 1 during this state, the SAR and ELD logic block will set bits D[2] to 1 and SAR[2] to 1.

[0055] Fig. Figure 11D illustrates the second trial during the bit trial phase of the partially split DAC and ELD-DAC. During the second trial, initiated by the trial bit 1140, switch 1120 remains open and, since SAR[2] = [1], the voltage -V Ref applied to the SAR capacitance 4C. Assuming that the comparator 1100 outputs a state of 0 in this state, the SAR and ELD logic block will set D[1] to 0 and SAR[1] to 0.

[0056] Fig. Figure 11E illustrates the third attempt during the bit attempt phase of the partially split DAC and ELD-DAC. During the third attempt, initiated by the attempt bit 1150, switch 1120 remains open and, since SAR[1] = [0], the voltage +V Refapplied to the SAR capacitance 2C. Assuming that the comparator 1100 outputs a state of 1 in this state, the SAR and ELD logic block will set D[0] to 1 and SAR[0] to 1. At this point, the SAR output D k [2:0] is set to

[101] and this marks the end of the first implementation cycle.

[0057] As in Fig. 11F, the second conversion cycle begins by sampling a second input sample, switch 1120 is closed, and, from the first conversion, the ELD-DAC feedback code ELD[2:0] is received and applied to the SAR output D k [2:0] =

[101] . The ELD feedback is applied to the ELD capacitors 1010 by applying +V Ref to the SAR capacity C for ELD[2] = [1], - V Ref to the ELD capacity 0.5C for ELD[1] = [0] and +V Ref0.25C is applied to the ELD capacitance for ELD[0] = [1]. Once the ELD has been adjusted, the bit attempts for the second sample can begin. Since the charge subtraction takes place immediately during the sampling phase, the charge on the capacitors again already represents the subtraction value.

[0058] Fig. Figure 12 illustrates an example capacitor configuration for partially sharing the DAC capacitors of the SAR ADC and the ELD DAC capacitors to provide an ELD feedback gain of 0.5. As illustrated, the SAR capacitors 1000 (4C, 2C, and C) share capacitances 2C and C with the ELD capacitors 1200 (2C, C, 0.5C). In this example, only the ELD subcapacitor 0.5C 1210 is added to the SAR capacitors 1000 to provide the ELD capacitors that are in the same 2 n-relationship to each other. Furthermore, since the SAR capacitances 1000 are in the range up to 4C, while the ELD capacitances 1200 are in the range up to 2C, the ELD feedback gain can be controlled down to 0.5 (2C / 4C). This variable gain is achieved with considerably less capacitance space, since only the 0.5C capacitance is added to the DAC capacitances. The experiments would be carried out in a similar manner as above with respect to Fig. 11, except that the digital ELD output codes would be applied to two of the capacitors of the SAR capacitors 1000 due to the additional bit shifting.

[0059] More generally, the relationship between the respective sets of capacitor arrays of the DAC of the SAR-ADC can be described as follows. A first set of capacitors has respective capacitance values C, which are determined by 2 Nwhere N = 0 to N = n-1 for the respective capacitors of an n-bit SAR ADC. Accordingly, for the 3-bit SAR ADC described here, n = 3 and N = 0-2. Accordingly, the capacitance values are represented as 1 (2 0 ), 2 (2 1 ) and 4 (2 2 ). In addition, for embodiments where the DAC of the SAR ADC is one bit smaller than the ELD DAC, the values C can be divided by 2 N where N = 0 to N = n-2 for respective capacitors of an n-bit SAR ADC. A second set of capacitors has respective capacitance values C, which are determined by 2 N related, where N = -x to N = nx-1, where nx capacitors are shared between the first and second sets of capacitors. In the above examples, n = 3 if a capacitor is shared for a 3-bit SAR ADC. Since nx = 1, x = 2 and 2 -x= 1 / 4. Accordingly, the second set of capacitors has values of 1 / 4 of the first set. On the other hand, if two capacitors are shared for a 3-bit SAR ADC, n = 3 and nx = 2. Thus, x = 1 and 2 -x = 1 / 2. Accordingly, the second set of capacitors has values of 1 / 2 of the first set of capacitors. Furthermore, for embodiments where the DAC of the SAR ADC is one bit smaller than the ELD DAC, the values C can be divided by 2 N where N = -x+1 to N = nx-1 for respective capacitors of an n-bit SAR ADC. As with reference to Fig. As described in Figures 10-11, the ELD gain can be less than one or greater than one according to the set of capacitors to which the ELD digital output code is applied for gain adjustment.

[0060] Fig. Figure 13 illustrates another embodiment in which the signal gain is further controlled by providing an additional sampling capacitor 1300. Although the illustrated additional sampling capacitor C sa 1300 is connected to the upper plate, it is understood that the additional sampling capacitor C sa 1300 can also be connected to the lower plate. The additional sampling capacitor C sa 1300 is always connected to ground and acts to provide an offset voltage that allows the SAR sampling to be held in a narrower range for refined gain control. For example, if V in is in the voltage range of 0-3 V, the additional sampling capacitor C sa1300 can be used to level shift down to a 1.1 V comparator range for refined gain control. This also allows the overall signal gain to be adjusted independently of the gain control for the SAR-ADC and ELD-DAC. Furthermore, external reference generation is possible through the use of the additional sampling capacitor C sa 1300 may not be necessary.

[0061] In Fig. 13, the gains are controlled by the capacitance ratios. For example, all gains can be normalized by a gain of the DAC of the SAR-ADC and the signal gain k sig can be defined for a top plate scan as follows: ksig=(CSa+CD+CEs) / CD, where C Sa is a capacitance of the additional sampling capacitor, C D a sum of the capacitances of the SAR capacitors is 1000, C Eis a sum of the capacitances of the ELD capacitors 1010 and C Es is a sum of the capacitances of the ELD subcapacitors 1020. In the case of sub-plate sampling, the signal gain k sig of the analog input signal is controlled by capacitance ratios as follows: ksig=(CSa+CDs) / CD, where C Sa is a capacitance of the additional sampling capacitor, C Ds is a sum of capacitances of capacitors of the DAC of the SAR-ADC used to sample the analog input signal, and C D is a sum of the capacitances of the DAC capacitors. Furthermore, the ELD gain k ELD be defined as follows: kELD=CE / CD.

[0062] It should be understood that in the case of lower-plate sampling, the divided DAC units are already used in ELD signal sampling and cannot also sample the input signal. As a result, only the undivided part of the SAR-ADC's DAC can be used for sampling. Furthermore, it is not necessary to sample an input signal on all undivided DAC capacitors. Unlike upper-plate sampling, which requires that all capacitors be sampled, it is possible to select which capacitor in the SAR-ADC's DAC is used to sample the input signal. For example, only the most significant bit (MSB) capacitor of the SAR-ADC's DAC, which is typically half of the SAR-ADC's DAC, samples the input signal to reduce the complexity of a control circuit without an additional sampling capacitor. Then, C Sa = 0 (no additional sampling capacitor), C Ds = C D / 2 (only half of the DAC samples an input signal), so k sig = (0+C D / 2) / C D = 0.5 applies.

[0063] Fig. Figure 14 is a functional block diagram of an example of a differential SAR quantizer 1400 including a differential divided-capacitance SAR / ELD DAC. In this example, a differential analog input voltage is sampled and held using a hold circuit that opens / closes switches 1410 / 1420 under the control of a sample signal qsa from timing circuit 1430 to generate differential input voltages V inp and V inm to the SAR / ELD-DAC 1440. The differential output voltages are gain controlled by the SAR / ELD-DAC 1440, as described above with reference to Fig. 9-13, and the output of the SAR / ELD DAC 1440 is compared to the sampled and held voltage using the comparator circuit 1450. The bit values of the SAR / ELD DAC 1440 are adjusted based on the output of the comparator circuit 1450.

[0064] Bit attempts are performed under control of SAR / ELD logic 1460 during the bit attempt phase in response to a conversion signal cnv from timing circuit 1430 to generate the digital value of the sampled and held voltage, which is output by SAR / ELD logic 1460 as dout. SAR / ELD logic 1460 notifies timing circuit 1430 when the conversion has been completed by providing an end-of-conversion (eoc) signal to timing circuit 1430.

[0065] In some example implementations, the SAR / ELD DAC 1440 may comprise two switched capacitor DAC (CDAC) arrays of the type described in Fig. 15. In this embodiment, a first CDAC 1500, referred to as a "P-DAC," is connected to a non-inverting input of the comparator 1450, and a second CDAC, referred to as an "N-DAC" 1510, is connected to an inverting input of the comparator 1450. Each CDAC includes a plurality of capacitors, each capacitor having a first and second plate. Each of the capacitors of the CDAC array 1500 / 1510 has an associated switch operable to selectively connect a first plate, e.g., the lowest or "bottom" plate, to either a first reference voltage V Refp or a second reference voltage V Refn to connect. In general, V Refn Mass and is V Refp relative to V Refnpositive. The respective CDAC arrays 1500 / 1510 can implement the partially overlapping DAC of the SAR-ADC and ELD-DAC, which is described here with reference to Fig. 9-13 is described.

[0066] Fig. Figure 16 is a flowchart illustrating a technique for performing analog-to-digital conversion in an exemplary embodiment. As illustrated, the method begins at 1600 by sampling an analog input signal to C s at 1610. If the top plate scanning is used, C S = C Sa + C D + C es , where C S is the sum of the capacitance used in sampling, C Sa the additional sampling capacity is, C D is the sum of the DAC capacitance and C es is the sum of the ELD-DAC capacitance excluding any shared capacitance between the DAC and the ELD-DAC. On the other hand, if sub-plate sampling is used, C S= C Sa + C Ds , where C Ds is the sum of the DAC capacitance used in the sampling operation. The ELD signal is also applied to C E sampled, where C Eis the sum of the capacitances of the ELD capacitors. At 1620, the ELD signal is subtracted from the sampled analog signal to generate a delta. Then, operations 1630-1660 are repeated for each bit during the bit trials. Specifically, a reference level based on the SAR control signal is generated at 1630. The delta found at 1620 is compared to the reference level at 1640. An SAR control signal is output at 1650 based on the comparison result at 1640. If additional bits need to be tested at 1660, operations 1630-1650 are repeated for each bit. Once all bits have been tested, the SAR reference code is generated at 1670. If additional samples are available, operations 1610-1670 are repeated at 1680. Once all samples have been processed, operations end at 1690.

[0067] As noted above, in some exemplary embodiments, the DAC of the SAR ADC includes a first set of capacitors having respective capacitance values C defined by 2 N where N = 0 to N = n-1 or N = 0 to N = n-2 for respective capacitors of an n-bit SAR ADC, and a second set of capacitors with respective capacitance values C, which are determined by 2 Nrelated, where N = -x to N = nx-1 or N = -x+1 to N = nx-1, where nx capacitors are shared between the first and second sets of capacitors. The digital ELD output is provided to one of the first and second sets of capacitors, which receive the digital ELD reference code during sampling of the analog input voltage. The set of capacitors to which the digital ELD output code is supplied depends on whether the ELD gain is greater or less than one. The embedded ELD-DAC adjusts the ELD gain during sampling of the analog input voltage. On the other hand, the digital SAR reference code is supplied to the other of the first and second sets of capacitors of the DAC during respective bit trials at operations 1630-1650.

[0068] Fig. Figure 17 is a functional block diagram of an example of a delta-sigma ADC (DS-ADC) including a successive approximation register (SAR) analog-to-digital converter (SAR-ADC) circuit in an exemplary embodiment. As illustrated, the SAR-ADC is Fig. 9 with the loop filter 120 for converting the analog signal V IN into the digital signal D[N-1:0].

[0069] The techniques and circuit configurations described here can be implemented in an integrated circuit device. Reducing the total capacitance required to perform ADC operations can enable an integrated circuit to operate in a smaller area with reduced power consumption, particularly for battery-powered applications.

[0070] The above description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also contemplate examples in which only those elements shown or described are provided.Furthermore, the inventors of the present invention also intend examples that utilize any combination or permutation of those elements shown or described (or one or more aspects thereof), either with reference to a particular example (or one or more aspects thereof) or with reference to other examples (or one or more aspects thereof) shown or described herein. In the event of inconsistent usage between this document and any other documents incorporated by reference, the usage in this document will control.

[0071] Throughout this document, the terms "ein," "eine," or "einer" are used as is customary in patent documents to include one or more than one, regardless of any other instances or uses of "at least one" or "an or more." Throughout this document, the term "or" is used to refer to a non-exclusive "or," such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise specified. Throughout this document, the terms "including" and "wherein" are used as the plain English equivalents of the respective terms "aufeinander" and "wobei."Furthermore, the terms "including" and "comprising" in the following claims are open-ended terms, meaning that a system, apparatus, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim is still considered within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0072] Geometric terms such as "parallel," "perpendicular," "round," or "square" are not intended to require absolute mathematical precision unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as "round" or "generally round," a component that is not exactly circular (e.g., one that is slightly elongated or a multifaceted polygon) is still encompassed by that description.

[0073] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be tangibly stored on one or more transient, non-transitory, or non-transitory tangible computer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or flash drives, random access memories (RAMs), read-only memories (ROMs), and the like.

[0074] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, as would be apparent to one of ordinary skill in the art upon review of the above description. The Abstract is provided to comply with 37 CFR §1.72(b) to enable the reader to quickly ascertain the nature of the technical disclosure. It is presented with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as an intent that any unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, each claim standing on its own as a separate embodiment, and it is intended that such embodiments may be combined with one another in various combinations and permutations. The scope of the invention should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0075] In the present disclosure, methods and apparatus are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by efficiently utilizing DAC unit elements in the ELD-DAC and DACs for the SAR-ADC. The ELD-DAC and DAC may partially share DAC units (e.g., capacitors or current sources) to minimize the total DAC units used to limit area and power consumption while maintaining flexibility in operation. Different configurations can provide ELD gains less than or greater than one. A dedicated sampling capacitor may also be provided to provide flexible gain control through a capacitance ratio.

Claims

[1] Successive Approximation Register (SAR) analog-to-digital converter (ADC) with a digital-to-analog converter (DAC) with an embedded An excess loop delay (ELD) DAC, wherein the DAC receives a SAR control signal and generates a reference level, and the ELD DAC receives an ELD feedback signal that provides ELD feedback during a sample of an analog input signal, the DAC and the embedded ELD DAC comprising a first set of DAC units and a second set of DAC units, one or more, but less than all, of the DAC units being shared between the first and second sets of DAC units, one of the first and second sets of DAC units receiving the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receiving the ELD feedback signal during a sample phase. [2] The ADC of claim 1, wherein the DAC units are used to adjust a gain of the DAC and a gain of the ELD-DAC, wherein the first set of DAC units has values divided by 2 N are related, where N = 0 to N = n-1 or N = 0 to N = n-2 for respective DAC units of an n-bit SAR ADC, and the second set of DAC units has respective values divided by 2 N related, where N = -x to N = nx-1 or N = -x+1 to N = nx-1, where nx DAC units are shared between the first and second set of DAC units. [3] The ADC of claim 2, wherein the first set of DAC units receives the SAR control signal and the second set of DAC units receives the ELD feedback signal for ELD gains less than one. [4] The ADC of claim 2 or 3, wherein the first set of DAC units receives the ELD feedback signal and the second set of DAC units receives the SAR control signal for ELD gains greater than one. [5] An ADC according to any preceding claim, further comprising: a sample / hold circuit that samples the analog input signal; a comparator that compares a difference between the sampled analog input signal and the ELD feedback signal with the reference level; and a SAR and excess loop delay (ELD) logic circuit that converts outputs of the comparator into the SAR control signal representing the analog input signal and the ELD feedback signal relative to the reference level, the SAR and ELD logic circuit further outputting the SAR control signal, the ELD feedback signal, and analog-to-digital conversion results, where the DAC generates the reference level for input to the comparator during respective bit attempts. [6] The ADC of claim 5, further comprising a loop filter that receives the analog input signal and the analog-to-digital conversion results and provides an output to the sample and hold circuit. [7] An ADC according to claim 5 or 6, wherein the ELD feedback signal is applied to the ELD-DAC during the sampling phase and the SAR control signal is applied to the DAC during the bit trial phase and any DAC units of the ELD-DAC that are not shared with DAC units of the DAC are driven to a fixed DAC unit value during the bit trial phase. [8] An ADC according to any one of claims 5 to 7, wherein the sample / hold circuit comprises an additional sampling capacitor connected between the analog input signal and ground, the additional sampling capacitor being separate from the first and second sets of DAC units and providing flexible gain control. [9] The ADC of claim 8, wherein the DAC units are capacitors used to adjust a gain of the DAC and a gain of the ELD-DAC, and wherein a signal gain k sig of the analog input signal is controlled by capacitance ratios during top plate scanning as follows: ksig=(CSa+CD+CEs) / CD, where C Sa is a capacitance of the additional capacitor, C D is a sum of the capacitances of capacitors of the DAC receiving the SAR control signal, and C Esis a sum of the capacitances of capacitors of the ELD-DAC excluding any capacitors shared between the first and second sets of DAC units. [10] The ADC of claim 8, wherein the DAC units are capacitors used to adjust a gain of the DAC and a gain of the ELD-DAC, and wherein a signal gain k sig of the analog input signal is controlled by capacitance ratios during sub-plate scanning as follows: ksig=(CSa+CDs) / CD, where C Sa is a capacitance of the additional sampling capacitor, C Ds is a sum of capacitances of capacitors of the DAC that receives the SAR control signal used to sample the analog input signal, and C D is a sum of capacitances of capacitors of the DAC. [11] ADC according to one of claims 5 to 10, wherein an ELD gain k ELDcontrolled by the following capacity ratio: kELD=CE / CD. where C E is a sum of the capacitances of capacitors of the ELD-DAC. [12] The ADC of any one of claims 5 to 10, wherein the sample / hold circuit receives first and second differential analog inputs applied to respective DACs and embedded ELD DACs, each DAC and embedded ELD DAC comprising a first set of DAC units and a second set of DAC units, one or more, but less than all, of the DAC units being shared between the first and second sets of DAC units, one of the first and second sets of DAC units receiving the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receiving the ELD feedback signal during the sample phase. [13] The ADC of claim 12, wherein one of the first and second sets of DAC units of the respective DACs and embedded ELD DACs receives the SAR control signal during the bit trial phase and another of the first and second sets of DAC units of the respective DACs and embedded ELD DACs receives the ELD feedback signal during the sampling phase. [14] Successive Approximation Register (SAR) analog-to-digital converter (ADC) having: a sample / hold circuit that samples an analog input signal and an excess loop delay (ELD) feedback signal; a comparator that compares, for each sample of the analog input signal, the sampled ELD feedback signal with the sampled analog input signal to generate a delta; a SAR and excess loop delay (ELD) logic circuit that performs bit trials for each sample of the analog signal to generate a successive approximation register (SAR) control signal, wherein the bit trials comprise, for each bit trial, generating a reference level based on the SAR control signal, comparing the delta to the reference level, and outputting the SAR control signal from the comparison result, wherein the SAR and ELD logic circuit further generates the ELD feedback signal and analog-to-digital conversion results; and a digital-to-analog converter (DAC) that receives the ELD feedback signal during a sampling of the analog input signal during a sampling phase and performs bit trials during a bit trial phase, the DAC comprising an embedded ELD DAC and comprising a first set of DAC units and a second set of DAC units, one or more, but less than all, of the DAC units being shared between the first and second sets of DAC units, one of the first and second sets of DAC units receiving the SAR control signal during the bit trial phase, and another of the first and second sets of DAC units receiving the ELD feedback signal during the sampling phase. [15] The ADC of claim 14, wherein the sample / hold circuit comprises a sampling capacitor connected between the analog input signal and ground, the sampling capacitor being separate from the first and second sets of DAC units and providing flexible gain control. [16] A method for analog-to-digital conversion, comprising: Sampling an analog input signal and an excess loop delay (ELD) feedback signal fed back during a sampling of the analog input signal; and for each sample of the analog input signal: Subtracting the sampled ELD feedback signal from the sampled analog input signal to generate a delta; Performing bit trials to generate a successive approximation register (SAR) control signal, wherein the bit trials comprise, for each bit trial, generating a reference level based on the SAR control signal, comparing the delta to the reference level, and outputting the SAR control signal from the comparison result, wherein the bit trials are performed by a digital-to-analog converter (DAC) comprising an embedded ELD DAC and comprising a first set of DAC units and a second set of DAC units, wherein one or more, but less than all, of the DAC units are shared between the first and second sets of DAC units, one of the first and second sets of DAC units receives the SAR control signal during a bit trial phase, and another of the first and second sets of DAC units receives the ELD feedback signal during a sample phase; and Generating analog-to-digital conversion results. [17] The method of claim 16, wherein the DAC units are capacitors and sampling the analog input signal using top plate sampling on sampling capacitances C S = C Sa + C D + C Es where C S is a sum of capacitances of capacitors used in sampling, C Sa is a capacitance of an additional sampling capacitor connected between the analog input signal and ground, C D is a sum of capacitances of capacitors of the DAC and C Es is a sum of capacitances of capacitors of the embedded ELD-DAC excluding any capacitors shared between the DAC and the ELD-DAC. [18] The method of claim 16 or 17, wherein the DAC units are capacitors and the sampling of the analog input signal using sub-plate sampling on sampling capacitances C S = C Sa+ C Ds where C S is a sum of capacitances used in sampling, C Sa is a capacitance of an additional sampling capacitor connected between the analog input signal and ground, and C Ds is a sum of capacitances of capacitors of the DAC used to sample the analog input signal. [19] A method according to any one of claims 16 to 18, wherein the DAC comprises a first set of capacitors having respective capacitance values determined by 2 N where N = 0 to N = n-1 or N = 0 to N = n-2 for respective capacitors of an n-bit SAR ADC, and a second set of capacitors with respective capacitance values determined by 2 N are related, where N = -x to N = nx-1 or N = -x+1 to N = nx-1, further comprising parts of nx capacitors between the first and second sets of capacitors. [20] The method of claim 19, further comprising providing the ELD feedback signal to one of the first and second sets of capacitors during a sample of the analog input signal and providing the SAR control signal to the other of the first and second sets of capacitors during respective bit attempts, wherein a set of capacitors to which the ELD feedback signal is provided depends on whether a gain of the ELD feedback signal is greater or less than one.

Images