Semiconductor device

Abstract

Semiconductor device providing a charging current to charge a target element (39), comprising: - a semiconductor layer (1) of a first conductivity type; - a first semiconductor region (2) of a second conductivity type formed on a main surface of the semiconductor layer (1) and electrically connected to a first electrode (71) of the target element (39); - a second semiconductor region (3a) of the first conductivity type, formed on the main surface of the semiconductor layer (1) and located adjacent to the first semiconductor region (2); - a third semiconductor region (5a) of the second conductivity type formed on a surface of the second semiconductor region (3a) and supplied with a power supply voltage (VCC); - a source electrode (10b) which is connected to the third semiconductor area (5a) and supplied with the power supply voltage (VCC); - a drain electrode (10c) connected to the first semiconductor region (2) and electrically connected to the first electrode (71); - a back-gate electrode (10a) connected and grounded to a region in the second semiconductor region (3a) that is separated from the third semiconductor region (5a); and - a gate electrode (9a) arranged such that it faces a channel region located in the second semiconductor region (3a) between the third semiconductor region (5a) and the first semiconductor region (2), wherein a gate insulating film (15) is arranged between them, wherein: - a breakdown voltage between the source electrode (10b) and the back-gate electrode (10a) is greater than the power supply voltage (VCC), - a fourth semiconductor region (21) of the second conductivity type is formed in the second semiconductor region (3a) and is arranged such that it surrounds the perimeter of the third semiconductor region (5a) and isolates the third semiconductor region (5a) from the second semiconductor region (3a); - the fourth semiconductor region (21) extends from the perimeter of the third semiconductor region (5a) to a region in the second semiconductor region (3a) which is opposite the first semiconductor region (2) and separated from the first semiconductor region (2), and - the channel area is located in the second semiconductor area (3a) between the fourth semiconductor area (21) and the first semiconductor area (2).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] Conventionally, a semiconductor device provided with a bootstrap capacitor is known (see, for example, European Patent Application EP 0 743 752 A1). The bootstrap capacitor is included in a bootstrap circuit used to ensure a suitable power supply to a driver circuit biased at a high potential. In the above-mentioned semiconductor device, the bootstrap capacitor, which serves as the target element to be charged, is generally charged in a very short time. Therefore, as disclosed in European Patent Application EP 0 743 752 A1, the bootstrap capacitor is charged via an LDMOS (laterally diffused metal oxide semiconductor) transistor, which can serve as a substitute for a high-breakdown voltage diode.

[0003] US 2015 / 0 115 342 A1 discloses a semiconductor device comprising a substrate of a first conductivity type, a first circuit region, an isolation region, a second circuit region, and a rectifier element. The rectifier element comprises a second conductivity type layer, a first high-concentration second conductivity type region, a second high-concentration second conductivity type region, an element isolation film, a first insulating layer, and a first conductive film. A first contact is coupled to the first high-concentration second conductivity type region, and a second contact is coupled to the second high-concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact, and the third contact are isolated from each other. SUMMARY OF THE INVENTION

[0004] In the above-mentioned semiconductor device, to prevent the semiconductor device from being damaged by the operation of a parasitic transistor including the LDMOS transistor, the source potential control circuit and the back-gate potential control circuit are connected. The two control circuits control the potentials of the source electrode and the back-gate electrode of the LDMOS transistor, thus preventing the parasitic transistor from operating. Such a complicated circuit including the source potential control circuit and the back-gate potential control circuit is a major factor increasing the manufacturing cost of the semiconductor device.

[0005] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a semiconductor device capable of reducing the manufacturing cost.

[0006] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1 and alternatively in a semiconductor device according to the invention with the features of claim 4. Advantageous further developments are the subject of the respective dependent claims.

[0007] A semiconductor device according to the present invention is a semiconductor device that provides a charging current to charge a target element and includes, among other things, a semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a source electrode, a drain electrode, the back-gate electrode, and a gate electrode. The first semiconductor region is electrically connected to the first electrode of the target element. The first semiconductor region is formed on the main surface of the semiconductor layer. The second semiconductor region is formed on the main surface of the semiconductor layer and is arranged adjacent to the first semiconductor region.The third semiconductor region is formed on the surface of the second semiconductor region and is supplied with a power supply voltage. The source electrode is connected to the third semiconductor region and is supplied with the power supply voltage. The drain electrode is connected to the first semiconductor region and is electrically connected to the first electrode. The back-gate electrode is connected to a region in the second semiconductor region that is separate from the third semiconductor region and is grounded. The gate electrode is arranged to oppose a channel region located in the second semiconductor region between the third semiconductor region and the first semiconductor region, with a gate insulating film interposed therebetween. The breakdown voltage between the source electrode and the back-gate electrode is greater than the power supply voltage.

[0008] The foregoing and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a first embodiment; Fig. 2 is a schematic cross-sectional view showing a part of the Fig. 1 illustrated semiconductor device; Fig. 3 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a comparative example; Fig. 4 is a schematic cross-sectional view showing a part of the Fig. 3 illustrated semiconductor device according to the comparative example; Fig. 5 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a second embodiment; Fig. 6 is a schematic cross-sectional view showing a part of the Fig. 5 illustrated semiconductor device; Fig. 7 is a schematic plan view illustrating a part of a semiconductor device according to a third embodiment; Fig. Figure 8 is a schematic sectional view taken along a line VIII-VIII in Fig. 7; Fig. 9 is a schematic sectional view taken along a line IX-IX in Fig. 7; Fig. 10 is a schematic plan view illustrating a part of a semiconductor device according to a fourth embodiment; Fig. 11 is a schematic sectional view taken along a line XI-XI in Fig. 10; Fig. 12 is a schematic sectional view taken along a line XII-XII of Fig. 10; Fig. 13 is a circuit diagram illustrating a potential detection circuit in a semiconductor device according to a fifth embodiment; Fig. 14 is a schematic plan view illustrating a part of a semiconductor device on which the Fig. 13 illustrated circuit is mounted; Fig. 15 is a schematic sectional view taken along a line XV-XV in Fig. 14; Fig. 16 is a schematic sectional view taken along a line XVI-XVI in Fig. 14; Fig. 17 is a schematic sectional view taken along a line XVII-XVII in Fig. 14; Fig. 18 is a schematic sectional view taken along a line XVIII-XVIII in Fig. 14; Fig. 19 is a schematic plan view illustrating a part of a semiconductor device according to a sixth embodiment; Fig. 20 is a schematic sectional view taken along a line XX-XX in Fig. 19; Fig. 21 is a schematic sectional view taken along a line XXI-XXI in Fig. 19; Fig. 22 is a schematic sectional view taken along a line XXII-XXII in Fig. 19; and Fig. 23 is a circuit diagram illustrating a potential detection circuit in the semiconductor device according to a seventh embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the present disclosure will be described below. It should be noted that the same or corresponding components are denoted by the same reference numerals, and their descriptions will not be repeated. First embodiment<Konfiguration einer Halbleitervorrichtung>

[0010] Fig. 1 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a first embodiment, and Fig. 2 is a schematic cross-sectional view showing a part of the Fig. 1 illustrated semiconductor device. Fig. 2 illustrates a cross-sectional configuration of a region where an N-channel MOS transistor 30 with high breakdown voltage (also referred to as NchMOS) is formed and a region where a high-potential circuit is formed in the semiconductor device.

[0011] The Fig. 1 and Fig. The semiconductor device illustrated in FIG. 2 is a semiconductor device mainly including a high-breakdown-voltage control IC 25 and a bootstrap capacitor 39, and configured to control a transistor 36 and a transistor 35. The high-breakdown-voltage control IC 25 mainly includes a transistor 30, which is a high-breakdown-voltage N-channel MOS transistor, a high-potential circuit 26, and a low-potential circuit 27. The high-potential circuit 26 includes a transistor 31, which is a P-channel MOS transistor, and a transistor 32, which is an N-channel MOS transistor. The low-potential circuit 27 includes a transistor 33, which is a P-channel MOS transistor, and a transistor 34, which is an N-channel MOS transistor.

[0012] The high breakdown voltage control IC 25 includes a first node 71, a second node 72, a third node 73, a fourth node 74, a fifth node 75, a sixth node 76, and a seventh node 77. The first electrode of the bootstrap capacitor 39 is connected to the first node 71 (node ​​VB). The source of the transistor 31 is connected to the first node 71. The drain of the transistor 31 is connected to the drain of the transistor 32 and the second node 72. The source of the transistor 32 is connected to the third node 73 (node ​​VS). The second electrode of the bootstrap capacitor 39 is connected to the third node 73 via the eighth node 78. The gate electrode of the transistor 36, which is a high-voltage power semiconductor element, is connected to the second node 72. The drain of transistor 36 is connected to the high voltage power supply node 70.The source of transistor 36 is connected to the eighth node 78.

[0013] The source of transistor 33 in low-potential circuit 27 is connected to the seventh node 77 (node ​​VCC). The drain of transistor 33 is connected to the drain of transistor 34 and the fourth node 74. The source of transistor 34 is connected to the fifth node 75 (node ​​COM) and the sixth node 76 (node ​​COM). The gate electrode of transistor 35, a low-voltage power semiconductor element, is connected to the fourth node 74. The drain of transistor 35 is connected to the eighth node 78. The source of transistor 35 is connected to the fifth node 75 via the ninth node 79. The ninth node 79 is grounded.

[0014] The positive electrode of power supply 38 is connected to the seventh node 77. The negative electrode of power supply 38 is connected to the sixth node 76. The gate electrode of transistor 30 is connected to a gate drive circuit 37. The gate drive circuit 37 is connected to the sixth node 76 and the seventh node 77. The source of transistor 30 is connected to the seventh node 77. The drain of transistor 30 is connected to the source of transistor 31 and the first node 71. The back gate electrode of transistor 30 is grounded via the fifth node 75.

[0015] Fig. 2 is a schematic cross-sectional view showing the transistor 30 and the high potential circuit 26 of the Fig. 1 illustrated semiconductor device. As shown in Fig. 2, the semiconductor device is formed, for example, on a semiconductor layer 1, which is a P-type semiconductor substrate having a first conductivity type. The main surface of the semiconductor layer 1 is formed with an N-type diffusion region 2 of an N-conductivity type and a P-type diffusion region 3a of a P-conductivity type, which are arranged adjacent to each other. The N-type diffusion region 2 serves as a drift layer of the transistor 30 and contributes to electrical conduction and breakdown voltage withstand capability. The main surface of the P-type diffusion region 3a is formed with a P-type diffusion region 4a. + -type and an N-type diffusion layer 21. The P-type diffusion region 4a + -type and the N-type diffusion layer 21 are separated from each other. A diffusion region 5a of the N +-type is formed in a part of the surface of the N-type diffusion layer 21. The N-type diffusion layer 21 and the N-type diffusion region 5a + -type serve as a source region for the transistor 30. Insulating films 14f and 14a of insulation are formed from a LOCOS oxide film or the like on the main surface of the semiconductor layer 1 and configured to insulate the diffusion region 4a from the P + -type sandwiched between them. The insulating film 14a of an insulation is sandwiched between the diffusion region 4a of the P + -type and the diffusion region 5a of the N + -type. The insulating film 14a of insulation and an insulating film 14b of insulation are formed to separate the diffusion region 5a from the N +-type is sandwiched therebetween. The insulating film 14b of insulation is disposed in the N-type diffusion layer 21 at a position separated from an edge of the N-type diffusion region 2.

[0016] An insulating film 15 is formed as a gate insulating film for the transistor 30 on the surface of the N-type diffusion layer 21, the P-type diffusion region 3a and the N-type diffusion region 2 on the other side of the insulating film 14b of insulation with respect to the N-type diffusion region 5a. +-type. An insulating film 14c of insulation is formed on the surface of the N-type diffusion region 2 on the other side of the insulating film 15 with respect to the insulating film 14b of insulation. A gate electrode 9a of the transistor 30 is formed on the insulating film 15. The gate electrode 9a extends from the insulating film 15 to both the insulating film 14b of insulation and the insulating film 14c of insulation. A back-gate electrode 10a of the transistor 30 is connected to the diffusion region 4a of the P + -type. A source electrode 10b of the transistor 30 is connected to the diffusion region 5a of the N + -type. The source electrode 10b is connected to the positive electrode of the power supply 38. The back-gate electrode 10a is grounded.

[0017] A diffusion region 5b of the N +-type is formed on the surface of the N-type diffusion region 2 on the other side of the insulating film 14c of insulation with respect to the gate electrode 9a. The N-type diffusion region 5b + -type is separated from the insulating film 14c of insulation. An insulating film 15 is extended from the insulating film 14c of insulation to a position on the surface of the diffusion region 5b of the N + -type is formed on the surface of the N-type diffusion region 2. A polysilicon electrode 9b is formed extending from the insulating film 15 to a position on the surface of the insulating film 14c of an insulation layer. The polysilicon electrode 9b serves as a field plate.

[0018] The diffusion region 5b of the N + -type is connected through a drain electrode 10c of the transistor 30. The drain electrode 10c is connected to the first node 71 and the first electrode of the bootstrap capacitor 39.

[0019] The high-potential circuit 26 is formed with a P-type diffusion region 3b on the surface of the N-type diffusion region 2. The transistor 31 is formed on the surface of the N-type diffusion region 2, and the transistor 32 is formed on the surface of the P-type diffusion region 3b. Specifically, a P-type diffusion region 4b + -type and a diffusion area 4c from the P + -type on the surface of the N-type diffusion region 2. The P-type diffusion region 4b + -type is arranged so that it faces the diffusion region 5b of the N + -type, with the insulating film 14d being arranged therebetween. The diffusion region 4b of the P + -type is a source region for the transistor 31. The diffusion region 4c of the P + -Type is from the diffusion area 4b of the P + -type. The diffusion area 4c of the P +-type is a drain region for the transistor 31. The area between the diffusion region 4b of the P + -Type and the diffusion area 4c of the P + -type forms a channel region for the transistor 31. An insulating film 15 is separated from the diffusion region 4b by the P + -Type up to the diffusion area 4c from P + -type extending on the surface of the N-type diffusion region 2. The diffusion region 4b formed between the P + -Type and the diffusion area 4c of the P + -type insulating film 15 serves as a gate insulating film of the transistor 31. A gate electrode 9c of the transistor 31 is formed on the insulating film 15.

[0020] A diffusion region 5c of the N + -type and a diffusion region 5d of N + -type are formed on the surface of the P-type diffusion region 3b. The N-type diffusion region 5c + -type is arranged so that it faces the diffusion area 4c of the P+ -type, with the insulating film 14e of insulation arranged therebetween. The diffusion region 5c of the N + -type is a drain region for the transistor 32. The diffusion region 5d of the N + -Type is from the diffusion region 5c of the N + -type. The diffusion region 5d of the N + -type is a source region for the transistor 32. The region between the diffusion region 5c of the N + -type and the diffusion region 5d of the N + -type serves as a channel region for the transistor 32. An insulating film 15 is separated from the diffusion region 5c of the N + -Type up to the diffusion range 5d from N + -type extending on the surface of the P-type diffusion region 3b. The diffusion region 5c of the N + -type and the diffusion region 5d of the N +-type insulating film 15 serves as a gate insulating film of the transistor 32. A gate electrode 9d of the transistor 32 is formed on the insulating film 15. A P-type diffusion region 4d is formed on the surface of the P-type diffusion region 3b and the N-type diffusion region 5d. + -Type arranged adjacently.

[0021] The drain electrode 10c of the transistor 30 is connected to the diffusion region 4b of the P + -type transistor 31 is electrically connected. The diffusion region 4c of the P + -type, which is the drain region for the transistor 31, is connected via the electrode 10d to the diffusion region 5c of the N + -type transistor 31. An electrode 10e is formed to separate the diffusion region 5d from the N + -Type and the diffusion area 4d of the P + -type. The electrode 10e is electrically connected to the third node 73 and the second electrode of the bootstrap capacitor 39.

[0022] An interlayer insulating film 11 is formed to cover the gate electrodes 9a, 9c, and 9d and the polysilicon electrode 9b. A portion of the back gate electrode 10a, the source electrode 10b, the drain electrode 10c, and the electrodes 10d and 10e extend on the upper surface of the interlayer insulating film 11. A passivation film 12 is formed on the interlayer insulating film 11.

[0023] In the above-mentioned semiconductor device, the N-type diffusion layer 21 is configured to form a part of the source region for the transistor 30 and to have a breakdown voltage equal to or greater than the power supply voltage with respect to the P-type diffusion region 4a. +-type than the back gate layer. The breakdown voltage can be arbitrarily adjusted by changing the impurity concentration in the N-type diffusion layer 21, the size of the N-type diffusion layer 21, or the like.

[0024] Each of the back gate electrode 10a, the source electrode 10b, the drain electrode 10c, and the electrodes 10d and 10e can be made of any conductive material, such as any metal. For example, each electrode can be made of aluminum (Al). The gate electrodes 9a, 9c, and 9d can be made of silicon, for example.

[0025] The N-type diffusion region 2 also serves as a well to electrically isolate the high-potential circuit 26 from the semiconductor layer 1. However, the high-potential circuit 26 may be electrically isolated by any other means. For example, the high-potential circuit 26 may be electrically isolated from the semiconductor layer 1 by inserting a buried diffusion layer directly beneath the high-potential circuit 26. Furthermore, the P-type diffusion region 3a may be used as the back gate of the transistor 30. As shown in Fig. As illustrated in Figure 2, the drain region for transistor 30 is preferably formed contiguously with the N-type diffusion region 2 where the high-potential circuit 26 is formed, which makes it possible to reduce the footprint of the semiconductor device. If there is no influence on the breakdown voltage of the semiconductor device, a buried diffusion layer may be introduced to electrically connect the N-type diffusion region 2 where the high-potential circuit 26 is formed and the drain region for transistor 30. <Effekt einer Halbleitervorrichtung>

[0026] The semiconductor device according to the present disclosure is a semiconductor device that provides a charging current to a bootstrap capacitor 39 serving as a target element to be charged, and includes, for example, a semiconductor layer 1 of a first conductivity type (P-type) as a P-type substrate, a diffusion region 5b of N+ -type and an N-type diffusion region 2 as a first semiconductor region of a second conductivity type (N-type), a P-type diffusion region 4a + -type and a P-type diffusion region 3a as a second semiconductor region of the first conductivity type, a N-type diffusion region 5a + -type as a third semiconductor region of the second conductivity type, a source electrode 10b, a drain electrode 10c, a back-gate electrode 10a and a gate electrode 9a. The first semiconductor region (the diffusion region 5b of the N + -type and the N-type diffusion region 2) is electrically connected to the first electrode of the bootstrap capacitor 39. The first semiconductor region (the N-type diffusion region 5b) + -type and the N-type diffusion region 2) is formed on the main surface of the semiconductor layer 1. The second semiconductor region (the P-type diffusion region 4a +-type and the P-type diffusion region 3a) is formed on the main surface of the semiconductor layer 1 at a position adjacent to the first semiconductor region (the N-type diffusion region 2). The N-type diffusion region 5a + -type as the third semiconductor region is supplied with the power supply voltage (Vcc). The diffusion region 5a of the N + -type is on the surface of the second semiconductor region (the diffusion region 4a of the P + -type and the P-type diffusion region 3a). The source electrode 10b is connected to the third semiconductor region (the N-type diffusion region 5a). + -type) and is supplied with the power supply voltage. The drain electrode 10c is connected to the first semiconductor region (the diffusion region 5b of the N +-type and the N-type diffusion region 2) and is electrically connected to the first electrode of the bootstrap capacitor 39. The back-gate electrode 10a is connected to a region in the second semiconductor region (the P-type diffusion region 4a). + -type and the P-type diffusion region 3a) which is surrounded by the third semiconductor region (the N-type diffusion region 5a + -type) and is grounded. The gate electrode 9a is formed as a gate insulating film in the second semiconductor region (the diffusion region 4a of the P + -type and the P-type diffusion region 3a) and arranged so as to face, via the insulating film 15, a channel region formed between the third semiconductor region (the N-type diffusion region 5a + -type) and the first semiconductor region (the diffusion region 5b of the N +-type and the N-type diffusion region 2). The breakdown voltage between the source electrode 10b and the back-gate electrode 10a is greater than the power supply voltage.

[0027] With the above configuration, since a voltage greater than the power supply voltage (Vcc) can be applied to the source electrode 10b and the back-gate electrode 10a can be fixed at the ground potential, the bootstrap capacitor 39 can be charged without providing an additional circuit for controlling the potential of the source electrode and the potential of the back-gate electrode, as in the related art. In other words, the charging operation on the bootstrap capacitor 39 can be performed by fixing the potential of the source electrode 10b and the potential of the back-gate electrode 10a and controlling only the voltage of the gate electrode 9a. As a result, it is possible to simplify the configuration of the circuit required to charge the bootstrap capacitor 39, making it possible to reduce the manufacturing cost of the semiconductor device.

[0028] The semiconductor device includes an N-type diffusion layer 21 as the fourth semiconductor region of the second conductivity type. The fourth semiconductor region (the N-type diffusion layer 21) is formed in the second semiconductor region (the P-type diffusion region 4a). + -type and the P-type diffusion region 3a) and arranged to cover the periphery of the third semiconductor region (the N-type diffusion region 5a + -type) and the third semiconductor region (the diffusion region 5a of the N + -type) from the second semiconductor region (the diffusion region 4a of the P + -type and the P-type diffusion region 3a). The N-type diffusion layer 21 extends in the second semiconductor region (the P-type diffusion region 4a + -type and the diffusion region 3a of the P-type) from the circumference of the diffusion region 5a of the N +-type up to a region corresponding to the first semiconductor region (the diffusion region 5b of the N + -type and the N-type diffusion region 2) and from the first semiconductor region (the N-type diffusion region 5b + -type and the N-type diffusion region 2). The channel region is in the second semiconductor region (the P-type diffusion region 4a + -type and the P-type diffusion region 3a) between the N-type diffusion layer 21 and the first semiconductor region (the N-type diffusion region 5b + -type and the diffusion region 2 of N-type).

[0029] Thus, the formation of the N-type diffusion layer 21 makes the breakdown voltage between the source electrode 10b and the back-gate electrode 10a greater than the power supply voltage. With such a configuration, the semiconductor device is able to perform the charging operation on the bootstrap capacitor 39 as described above.

[0030] The semiconductor device may have a breakdown voltage of 300 V or higher. In the present disclosure, the breakdown voltage refers to a maximum voltage that can be applied between the drain electrode 10c and the source electrode 10b.

[0031] Consequently, the semiconductor device according to the present disclosure can be used as a high breakdown voltage semiconductor to perform gate driving of a power semiconductor that controls a high-voltage power source such as a power source of an electric motor or the like.

[0032] The effect of the semiconductor device according to the present embodiment will be described in more detail in comparison with a semiconductor device according to a comparative example. Fig. 3 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a comparative example, and Fig. 4 is a schematic cross-sectional view showing a part of the Fig. 3 illustrated semiconductor device according to the comparative example.

[0033] The Fig. 3 according to the comparative example has basically the same circuit configuration as that of the semiconductor device shown in Fig. 1 according to the present embodiment, except that a source potential control circuit 140 is connected to the source electrode of the transistor 30 serving as a high breakdown voltage MOS transistor, and a back-gate potential control circuit 139 is connected to the back-gate electrode of the transistor 30. Fig. 4 is a schematic cross-sectional view of the transistor 30 and the high potential circuit 26 in the Fig. 3. The semiconductor device according to the comparative example shown in Fig. 4, has basically the same configuration as that shown in Fig. 2 according to the present embodiment, except that the configuration of the transistor 30 is different from that in the Fig. 2 is different. Specifically, in the semiconductor device shown in Fig. 4, a P-type diffusion region 6 is formed within the N-type diffusion region 2. A P-type diffusion region 4a + -type and a diffusion region 5a of N + -type are formed on the surface of the P-type diffusion region 6 and separated from each other. A P-type diffusion region 4e +-type is formed on the main surface of the semiconductor layer 1 and separated from the P-type diffusion region 6 with the insulating film 14a of insulation interposed therebetween. A back-gate electrode 10a is connected to the P-type diffusion region 4a. + -type. A source electrode 10b is connected to the diffusion region 5a of the N + -type. An electrode 10f is connected to the diffusion region 4e of the P + -type. As described above, the back-gate potential control circuit 139 is connected to the back-gate electrode 10a, and the source potential control circuit 140 is connected to the source electrode 10b. The electrode 10f is grounded.

[0034] In the semiconductor device according to the comparative example as described above, in order to prevent the unintentional operation of the transistor 30 and suppress the operation of the parasitic bipolar element, the back-gate potential control circuit 139 and the source potential control circuit 140 are provided, which complicates the circuit configuration of the semiconductor device according to the comparative example and leads to an increase in manufacturing cost.

[0035] In contrast, the semiconductor device according to the present embodiment is formed with the N-type diffusion layer 21 so that a voltage sufficiently larger than the power supply voltage (Vcc) is applied to the N-type diffusion region 5a. +-type, which serves as a source region. Furthermore, the back-gate electrode 10a is grounded. Therefore, the semiconductor device according to the present embodiment is able to prevent operation of the parasitic bipolar element with a simple circuit configuration, without having to provide the back-gate potential control circuit 139 and the source potential control circuit 140 as in the comparative example.

[0036] When transistor 30 is used to charge the bootstrap capacitor 39, the high-potential circuit 26 transitions to a low potential when the output of the high-potential circuit 26 is LOW and the transistor 36 serving as a switching element is off, the output of the low-potential circuit 27 is high, and the transistor 35 serving as a switching element is on. In this state, the bootstrap capacitor 39 can be charged by the transistor 30, which is a high-breakdown voltage NchMOS transistor. The charging period is determined by an output command to each of the high-potential circuit 26 and the low-potential circuit 27 in the charging system. Therefore, the charging period can be logically determined by the system.The logically determined charging period can be sent to the gate drive circuit 37 of the transistor 30 to control the gate of the transistor 30 at an optimal time to charge the bootstrap capacitor 39.

[0037] Further, according to the semiconductor device of the present embodiment, since the back gate electrode 10a of the transistor 10 is formed as shown in Fig. 2, the P-type diffusion region 3a serving as the back gate may be formed in contact with the semiconductor layer 1 without involving the N-type diffusion region 2 constituting the drain layer of the transistor 30, whereby the parasitic PNP transistor consisting of the back gate, the drain, and the semiconductor layer 1 as in the semiconductor device according to the comparative example can be eliminated.

[0038] Regarding the parasitic NPN transistor consisting of the source, backgate, and drain, in the semiconductor device according to the present embodiment, the source and backgate are constantly and inversely biased by the power supply voltage (Vcc). Therefore, the parasitic operation in the state where the source of the transistor 30 becomes the emitter of the NPN transistor (in other words, the drain of the transistor 30 is in a high-potential state and serves as the collector) can be effectively suppressed. As a result, it is possible to prevent the semiconductor device from being damaged by the parasitic operation. Note that the parasitic operation in the reverse direction, in other words, the parasitic operation in a state where the drain of the transistor 30 serves as the emitter of the NPN transistor, contributes to the charging operation on the bootstrap capacitor 39 and will not cause any problem.When the potential of the drain electrode of the transistor 30 becomes equal to the power supply voltage (Vcc) or higher, the charging operation is automatically terminated.

[0039] As described above, according to the semiconductor device of the present embodiment, it is possible to simplify the configuration of the system while eliminating the formation of the parasitic bipolar transistor and suppressing the parasitic operation, which makes it possible to reduce the manufacturing cost and improve the reliability (robustness) of the semiconductor device. Second embodiment<Konfiguration einer Halbleitervorrichtung>

[0040] Fig. 5 is a circuit diagram illustrating a bootstrap charging system in a semiconductor device according to a second embodiment, and Fig. 6 is a schematic cross-sectional view showing a part of the Fig. 5 illustrated semiconductor device. Fig. 6 illustrates a schematic cross-sectional view of a portion of the transistor 30 in the semiconductor device.

[0041] The Fig. 5 and Fig. 6 has basically the same configuration as that shown in Fig. 1 and Fig. 2, but differs from the semiconductor device shown in Fig. 1 and Fig. 2 in that a limit resistor 41 is connected to the source of the transistor 30.

[0042] As in Fig. 5, the source of transistor 30 is connected to the seventh node 77 via the limit resistor 41. The limit resistor 41 can be configured in various ways. For example, as shown in Fig. 6, the planar shape of the N-type diffusion layer 21 may be modified to provide a distance L1 between the N-type diffusion region 5a + -type and the channel region below the gate electrode 9a. As a result, the N-type diffusion layer 21, which is located between the N-type diffusion region 5a, serves +-type, to which the source electrode 10b is connected, and the channel region located below the gate electrode 9a, serves as the cutoff resistor. The resistance value of the cutoff resistor can be adjusted by changing the impurity concentration of the N-type diffusion layer 21 and the shape of the N-type diffusion layer 21. The cutoff resistor has an effect of preventing the bootstrap capacitor 39 or any other elements in the semiconductor device from being damaged by a rush current flowing from the source to the drain of the transistor 30 when the parasitic NPN transistor in the semiconductor device operates. <Effekt einer Halbleitervorrichtung>

[0043] The semiconductor device according to the present embodiment may further include a limit resistor 41. The limit resistor 41 is arranged on a current path from the power supply 38, which provides the power supply voltage (Vcc), to the channel region.

[0044] Consequently, the inclusion of the limit resistor 41 enables a reduction in the probability that the bootstrap capacitor 39 or the like is damaged by the rush current flowing from the source electrode 10b to the drain electrode 10c when the parasitic NPN transistor operates in the semiconductor device.

[0045] In the semiconductor device according to the present embodiment, the boundary resistor 41 may be a portion of the N-type diffusion layer 21 serving as the fourth semiconductor region and disposed between the N-type diffusion region 5a +-type semiconductor region, which serves as the third semiconductor region, and the channel region. Consequently, the resistance value of the barrier resistor 41 can be easily adjusted by changing the impurity concentration and shape of the N-type diffusion layer 21.

[0046] Generally, in the drive circuit of a power stage for which the semiconductor device according to the present embodiment is used, a large current is supplied to a load with a large inductance, such as an electric motor. Therefore, the potential of the third node 73 (VS), which is an intermediate connection point between the switching elements, may be affected by the jump in inductance and become a negative potential. If the voltage of the third node 73 becomes a negative voltage equal to (the potential (VB) of the first node 71 - the potential (VS) of the third node) or lower, the voltage of the first node 71 is also biased to a negative voltage. As a result, the drain of the transistor 30 becomes a negative potential, inducing operation of the parasitic NPN transistor.

[0047] Specifically, the drain of transistor 30 serves as the emitter, and the semiconductor layer 1 and the back gate of transistor 30 are forward biased toward the drain to inject holes into the drain (the emitter), thereby serving as the base. The source serves as the collector of the parasitic NPN transistor to inject electrons into the emitter (the drain). Since the bipolar transistor basically operates at a low impedance, a rush current is generated and flows from the source to the drain of transistor 30, which can damage the components in the semiconductor device, such as the bootstrap capacitor. By forming the N-type diffusion layer 21 as shown in Fig. 5 and Fig. However, as illustrated in Figure 6, it is possible to impart a suitable electrical resistance to the source of transistor 30. As a result, when the parasitic NPN transistor is operating, the N-type diffusion layer 21 can serve as a boundary resistance. Third embodiment<Konfiguration einer Halbleitervorrichtung>

[0048] Fig. 7 is a schematic plan view illustrating a part of a semiconductor device according to a third embodiment, Fig. Figure 8 is a schematic sectional view taken along a line VIII-VIII in Fig. 7, and Fig. 9 is a schematic sectional view taken along a line IX-IX in Fig. 7. The Fig. 7 to 9 has basically the same configuration as that shown in Fig. 1 and Fig. 2, but differs in the configuration of the gate of transistor 30 and the structure to withstand the breakdown voltage between the source and the back gate.

[0049] In other words, in the Fig. 7 to 9, the transistor 30 has a trench gate structure. Specifically, a trench 51 is formed to separate the diffusion region 5a from the N + -type, which serves as the source region for the transistor 30. The P-type diffusion region 3a comprises a first region 3aa located outside the trench 51 and a second region 3ab located inside the trench 51. The second region 3ab is arranged within the trench 51 so as to be flush with the bottom of the N-type diffusion region 5a. + -type. The first region 3aa is arranged so that it is in contact with the underside of the diffusion region 4a of the P +-type is in contact. The P-type diffusion region 6 extends across the bottom of the first region 3aa to a position on the bottom of the second region 3ab within the trench 51. The N-type diffusion region 2 extends within the trench 51 across a portion 51a of the trench 51. The P-type diffusion region 6, which extends across the other portion 51b of the trench 51 within the trench 51, is in contact with the N-type diffusion region 2 within the trench 51. In order to ground the second region 3ab of the P-type diffusion region 3a, the P-type diffusion region 6 is in contact with the second region 3ab within the trench 51. The N-type diffusion region 2 is in contact with the second region 3ab of the P-type diffusion region 3a within the trench 51. An insulating film 15 is formed on the inner wall of the trench 51 as a gate insulating film. A gate electrode 9a is formed on the insulating film 15.A region in the second region 3ab, which faces the part 51a of the trench 51, serves as the channel region for the transistor 30. The gate electrode 9a is formed to fill the interior of the trench 51. The trench 51 extends from the main surface of the semiconductor layer 1 to a position in the P-type diffusion region 6 or the N-type diffusion region 2 that is further or deeper than the bottom of the second region 3ab.

[0050] A field plate 20 made of a conductive film is arranged on the insulating film 14c of insulation at a position closer to the trench 51 and a position further away from the trench 51, respectively. <Effekt einer Halbleitervorrichtung>

[0051] In the semiconductor device according to the present embodiment, the main surface of the semiconductor layer 1 is formed with a trench 51. The part 51a of the trench 51 divides the channel region and the first semiconductor region (the diffusion region 5b of the N + -type and the N-type diffusion region 2). The insulating film 15, which serves as a gate insulating film, is formed on the surface of the inner wall of the part 51a of the trench opposite the channel region. The gate electrode 9a is formed within the trench 51. The trench 51 extends from the main surface of the semiconductor layer 1 to a level deeper than the bottom of the second semiconductor region (the P-type diffusion region 4a). +-type and the P-type diffusion region 3a). The other part 51b of the trench 51 is formed in a region between the back-gate electrode 10a and the source electrode 10b. The second semiconductor region (the P-type diffusion region 3a) includes a first region 3aa and a second region 3ab. The first region 3aa is closer to the back-gate electrode 10a than the other part 51b of the trench 51. The second region 3ab is closer to the source electrode 10b than the other part 51b of the trench 51 and includes a channel region. The first semiconductor region (the N-type diffusion region 2) extends over a region located below the part 51a of the trench 51 so as to be in contact with the channel region. Furthermore, the semiconductor device includes an extended region (P-type diffusion region 6) of the first conductivity type (P-type).The P-type diffusion region 6 is formed in the semiconductor layer 1 as an extended region in contact with the first region 3aa and the second region 3ab. The P-type diffusion region 6 extends from the bottom of the first region 3aa through a region located below the other part 51b of the trench 51 to the bottom of the second region 3ab.

[0052] Consequently, the adoption of a so-called trench gate structure utilizing the trench 51 makes it possible to improve the breakdown voltage between the source electrode 10b and the back gate electrode 10a, which makes it possible to set the breakdown voltage between the source electrode 10b and the back gate electrode 10a larger than the power supply voltage (Vcc).

[0053] In the semiconductor device, the trench 51 may be formed on the main surface of the semiconductor layer 1 and arranged to surround the third semiconductor region (the diffusion region 5a of the N + -type). Therefore, the diffusion region 5a can be separated from the N + -type to which the source electrode 10b is connected, can be separated from the surrounding region, which makes it possible to arrange an element that functions differently from the bootstrap circuit in the region where the high breakdown voltage NchMOS transistor 30 is formed.

[0054] In the structure of the semiconductor device described in the first embodiment, an N-type diffusion layer 21 is formed so as to improve the breakdown voltage between the source region and the back gate. In this case, to prevent the breakdown voltage from decreasing due to the concentration of an electric field at a corner portion of the N-type diffusion layer 21, it is generally necessary to introduce a deeper diffusion layer or reduce the concentration of the P-type diffusion region 3a electrically connected to the back gate. These measures may increase the current gain of the parasitic NPN transistor unless the structure is designed accordingly, reducing the reliability of the semiconductor device.

[0055] Therefore, in the present embodiment, in order to improve the breakdown voltage between the source and the back gate, a diffusion region 5a serving as a source region is formed from the N + -type within the trench 51 of the trench gate structure. As a result, the corner portion of the diffusion layer 21 is of N-type as shown in Fig. 2, which makes it possible to prevent the breakdown voltage from being reduced by the concentration of an electric field. As shown in Fig. As illustrated in Figure 8, the junction between the source and the back gate is predominantly a one-dimensional junction between the lower portion of the diffusion region 5a located within the trench 51 from the N +-type and the upper portion of the second region 3ab in the P-type diffusion region. Furthermore, the gate electrode 9a within the trench 51 serves as a field plate to expand the depletion layer, thereby reducing the electric field. Therefore, the breakdown voltage in the region in contact with the trench 51 is improved. The breakdown voltage between the source and the back gate is therefore not limited by the boundary such as the end portion of the N-type diffusion layer 21 as in Fig. 2 illustrates this. As a result, it is possible to improve the breakdown voltage of the semiconductor device and make the breakdown voltage stable. Fourth embodiment<Konfiguration einer Halbleitervorrichtung>

[0056] Fig. 10 is a schematic plan view illustrating a part of a semiconductor device according to a fourth embodiment, Fig. 11 is a schematic sectional view taken along a line XI-XI in Fig. 10, and Fig. 12 is a schematic sectional view taken along a line XII-XII of Fig. 10. The Fig. 10 to 12 has basically the same configuration as that shown in Fig. 7 to 9, except that the structure of the P-type diffusion region 3a is different from that of the semiconductor device shown in Fig. 7 to 9. In other words, in the semiconductor device illustrated in Fig. 10 to 12, a part of the P-type diffusion region 3a extends from the trench 51 to the insulating film 14c of an insulation. The P-type diffusion region 3a includes a first region 3aa located below the P-type diffusion region 4a. + -type, a second region 3ab, which is located below the diffusion region 5a of the N +-type and located within the trench 51, a third region 3ac extending from the trench 51 to the insulating film 14c of an insulation, and a fourth region 3ad located around the trench 51 and connecting the first region 3aa and the third region 3ac. As shown in Fig. As illustrated in Figure 10, a plurality of trenches 51 are formed along the boundary between the P-type diffusion region 3a and the N-type diffusion region 2 and are separated from each other. The fourth region 3ad is disposed between the plurality of trenches 51. The third region 3ac is in contact with the N-type diffusion region 2. The third region 3ac extends from the surface of the trench 51 to the insulating film 14c of an insulation. <Effekt einer Halbleitervorrichtung>

[0057] In the semiconductor device according to the present embodiment, the second semiconductor region (the diffusion region 4a of the P +-type and the P-type diffusion region 3a) further comprises a third region 3ac and a fourth region 3ad. The third region 3ac is located on the other side of the part 51a of the trench 51 with respect to the second region 3ab. The fourth region 3ad is located outside the trench 51 and connects the first region 3aa and the third region 3ac.

[0058] Since the first region 3aa and the third region 3ac are connected by the fourth region 3ad, the third region 3ac is grounded. Therefore, the depletion of the N-type diffusion region 2 adjacent to the third region 3ac is promoted, making it possible to improve the breakdown voltage and stability of the semiconductor device. Fifth embodiment<Konfigurationsbeispiel einer Halbleitervorrichtung>

[0059] Fig. 13 is a circuit diagram illustrating a potential detection circuit in a semiconductor device according to a fifth embodiment. Fig. 14 is a schematic plan view illustrating a part of a semiconductor device on which the Fig. 13 illustrated circuit is mounted. Fig. 15 is a schematic sectional view taken along a line XV-XV in Fig. 14. Fig. 16 is a schematic sectional view taken along a line XVI-XVI in Fig. 14. Fig. 17 is a schematic sectional view taken along a line XVII-XVII in Fig. 14. Fig. 18 is a schematic sectional view taken along a line XVIII-XVIII in Fig. 14.

[0060] The Fig. 13 to 18 has basically the same configuration as that shown in Fig. 1 and Fig. 2, except that it includes a determination circuit 80 for determining the potential of the first node 71 connected to the first electrode of the bootstrap capacitor 39. The determination circuit 80 mainly includes a first charging circuit 81, a second charging circuit 82, a first switching element 83, a second switching element 84, a third switching element 85, a comparator 62, and a gate control circuit 61. The first charging circuit 81 includes a first capacitor 81a, a first charging node 81b, a first resistor 81c, and a first diode 81d. The first capacitor 81a has two electrodes. One electrode of the first capacitor 81a is grounded, and the other electrode of the first capacitor 81a is electrically connected to the first charging node 81b. The first diode 81d is connected in parallel with the first capacitor 81a.

[0061] The second charging circuit 82 includes a second capacitor 82a, a second charging node 82b, a second resistor 82c, and a second diode 82d. The second capacitor 82a has two electrodes. One electrode of the second capacitor 82a is grounded, and the other electrode of the second capacitor 82a is electrically connected to the second charging node 82b. The second diode 82d is connected in parallel with the second capacitor 82a.

[0062] The source of the first switching element 83 is connected to the seventh node 77, from which the power supply voltage (Vcc) is provided. The drain of the first switching element 83 is connected to the first charging node 81b. The charging node 81b is connected to the comparator 62.

[0063] The source of the second switching element 84 is connected to the seventh node 77, from which the power supply voltage (Vcc) is provided. The drain of the second switching element 84 is connected to the second charging node 82b. The second charging node 82b is connected to the comparator 62. The second charging node 82b is also connected to the source of the third switching element 85. The drain of the third switching element 85 is connected to the first node 71. The drain of the transistor 30 is connected to the first node 71. The source of the transistor 30 is connected to the seventh node 77. The gate electrode of the transistor 30, the gate electrode of the first switching element 83, the gate electrode of the second switching element 84, and the gate electrode of the third switching element 85 are connected to the gate control circuit 61. The output of the comparator 62 is fed to the gate control circuit 61.

[0064] The power supply voltage (Vcc) is supplied to the first charging node 81b via the first switching element 83. The power supply voltage (Vcc) is supplied to the second charging node 82b via the second switching element 84. The first capacitor 81a and the second capacitor 82a have the same capacitance. The second charging node 82b is connected to the first node 71 via the third switching element 85. If the voltage of the second charging node 82b is greater than the voltage of the first charging node 81b, the determination circuit 80 determines that the voltage of the first node 71 is greater than the power supply voltage (Vcc).

[0065] Fig. 14 illustrates a planar layout of the semiconductor device in which the Fig. 13 illustrated circuit is mounted. Fig. Fig. 14 illustrates the planar shapes of an electrode layer serving as the gate electrode of the transistor 30, the first switching element 83, the second switching element 84 and the third switching element 85, and the diffusion regions 5a, 5f and 5g of the N + -type, which serve as the source region or the drain region. The transistor 30 and the like are arranged along a boundary between the N-type diffusion region 2 and the P-type diffusion region 3a. Specifically, an N-type diffusion region 5a is + -type is formed on the surface of the P-type diffusion region 3a so that it extends along the boundary. An N-type diffusion region 5f + -type is formed on the surface of the diffusion region 3a at a position separated from the diffusion region 5a of the N + -type along the boundary. The diffusion region 5f of the N +-type extends in a direction away from the boundary. A diffusion region 5g from the N + -type is formed on the surface of the P-type diffusion region 3a at a position separated from the N-type diffusion region 5f + -type is separated along the boundary. The diffusion region 5g from the N + -type extends in a direction away from the boundary. In other words, the diffusion region 5f of the N + -Type and the diffusion range 5g of N + -type so that they extend substantially parallel to each other. The diffusion region 5a of the N + -type is formed on the surface of the P-type diffusion region 3a at a position separated from the N diffusion region 5g + -type along the boundary. The diffusion region 5a of the N + -Type extends along the border.

[0066] A gate electrode 9g is formed such that it extends from a diffusion region 5a of the N + -type adjacent position extends across the surface of the P-type diffusion region 3a to the N-type diffusion region 2. An insulating film 15 is arranged below the gate electrode 9g as a gate insulating film. A first electrode layer 9e is formed so as to be separated from the gate electrode 9g along the boundary. An insulating film 15 is formed below the first electrode layer 9a as a gate insulating film. The first electrode layer 9e is arranged opposite the N-type diffusion region 5a. + -type are arranged adjacently and configured to separate part of the diffusion region 5f from the N + -type. The first electrode layer 9e extends from the P-type diffusion region 3a across the boundary to the N-type diffusion region 2.

[0067] A second electrode layer 9f is formed so as to be separated from the first electrode layer 9e along the boundary. An insulating film 15 is formed below the second electrode layer 9f as a gate insulating film. The second electrode layer 9f is connected to the other diffusion region 5a of the N + -type are arranged adjacently and configured to cover part of the diffusion region 5g from the N + -type. The second electrode layer 9f is formed only on the P-type diffusion region 3a. The second electrode layer 9f is arranged at a position separated from the boundary. A gate electrode 9h is formed so as to be separated from the other N-type diffusion region 5a. + -type adjacent position across the surface of the P-type diffusion region 3a to the N-type diffusion region 2. An insulating film 15 is arranged below the gate electrode 9h as a gate insulating film.

[0068] As in Fig. 14, the gate electrode 9g of the transistor 30 is between the diffusion region 5a of the N + -type and the N-type diffusion region 2. A portion of the first electrode layer 9e, which is located between the N-type diffusion region 5a + -type and the diffusion region 2 of the N-type serves as the gate electrode of the transistor 30. A portion of the first electrode layer 9e, which is located between the diffusion region 5a of the N + -type and the diffusion region 5f of the N + -type, serves as the gate electrode of the second switching element 84. A portion of the first electrode layer 9e, which is located between the diffusion region 5f of the N + -type and the N-type diffusion region 2 serves as the gate electrode of the third switching element 85. A portion of the second electrode layer 9f located between the other N-type diffusion region 5a + -Type and the diffusion range 5g of N +-type, serves as the gate electrode of the first switching element 83. The gate electrode 9g of the transistor 30 is between the other diffusion region 5a of the N + -type and the diffusion region 2 of N-type. <Effekt einer Halbleitervorrichtung>

[0069] The semiconductor device according to the present embodiment includes a determination circuit 80. The determination circuit 80 determines whether the voltage of the first node 71 on the current path between the first electrode of the bootstrap capacitor 39 and the first semiconductor region (the diffusion region 5b of the N +-type and the N-type diffusion region 2) is greater than the power supply voltage (Vcc) or not. The determination circuit 80 includes a first charging circuit 81, a second charging circuit 82, a first switching element 83, a second switching element 84, and a third switching element 85. The first charging circuit 81 includes a first capacitor 81a and a first charging node 81b. The first capacitor 81a has two electrodes. One electrode of the first capacitor 81a is grounded. The other electrode of the first capacitor 81a is electrically connected to the first charging node 81b.

[0070] The second charging circuit 82 includes a second capacitor 82a and a second charging node 82b. The second capacitor 82a has two electrodes. One electrode of the second capacitor 82a is grounded. The other electrode of the second capacitor 82a is electrically connected to the second charging node 82b. The first charging node 81b is supplied with the power supply voltage (Vcc) via the first switching element 83. The second charging node 82b is supplied with the power supply voltage (Vcc) via the second switching element 84. The first capacitor 81a and the second capacitor 82a have the same capacitance. The second charging node 82b is connected to the first node 71 via the third switching element 85. When the voltage of the second charging node 82b is greater than the voltage of the first charging node 81b, the determination circuit 80 determines that the voltage of the first node 71 is greater than the power supply voltage (Vcc).

[0071] Since the determination circuit 80 can determine whether the voltage of the first node 71 is greater than the power supply voltage or not, it is possible to perform or terminate the charging operation on the bootstrap capacitor 39 based on the determination result.

[0072] In the bootstrap charging system included in the semiconductor device according to each of the above-described embodiments, it is desirable to reliably terminate the charging operation on the bootstrap capacitor 39 when the potential (VB) of the first node 71 is greater than the potential (VS) of the third node 73 or the power supply voltage (Vcc). For this purpose, it is desirable that the potential (VB) of the first node 71 be indirectly monitored on the low-potential side.

[0073] In the Fig. In the determination circuit 80 illustrated in FIG. 13, two switching elements with the same characteristics are used as the first switching element 83 and the second switching element 84, respectively, two resistors with the same resistance value are used as the first resistor 81c and the second resistor 82c, two elements with the same capacitance value are used as the first capacitor 81a and the second capacitor 82a, respectively, and two diodes with the same characteristics as the first diode 81d and the second diode 82d are used to form two charging circuits. The first charging node 81b and the second charging node 82b are connected to the comparator 62 so as to monitor the voltage of the first charging node 81b and the voltage of the second charging node 82b. As shown in FIG. Fig. 13, the second charging node 82b is connected to the source of the third switching element 85, which is a high breakdown voltage MOS transistor similar to the transistor 30. The drain of the third switching element 85 is connected to the first node 71. On the other hand, in the first charging node 81b, as shown in the cross-sectional view of Fig. 17 illustrates a gap formed between the second electrode layer 9f and the first electrode layer 9e to prevent the surface layer of the P-type diffusion region 3a below the second electrode layer 9f, which serves as the gate electrode of the high breakdown voltage NchMOS transistor, from becoming a channel. The source of the first switching element 83 and the source of the second switching element 84 are supplied with the power supply voltage (Vcc) and controlled by the gate control circuit 61.

[0074] When the gate of the first switching element 83 and the gate of the second switching element 84 are turned on, currents flow through the first switching element 83 and the second switching element 84 and the first resistor 81c and the second resistor 82c to charge the first capacitor 81a and the second capacitor 82a, respectively. At this time, the third switching element 85 on the second switching element 84 side is also turned on. Therefore, if the potential (VB) of the first node 71 becomes lower than the power supply voltage (Vcc), part of the current of the second switching element 84 flows through the third switching element 85 to the first node 71. As a result, the current flowing through the second resistor 82c becomes smaller than the current flowing through the first resistor 81c, and thereby the potential (V1) of the first charging node 81b is greater than the potential (V2) of the second charging node 82b.

[0075] When the potential (VB) of the first node 71 is greater than the power supply voltage (Vcc) and the potential (V2) of the second charging node 82b is lower than the power supply voltage (Vcc), the currents from both the second switching element 84 and the third switching element 85 flow through the second resistor 82c. In this case, the potential (V1) of the first charging node 81b is smaller than the potential (V2) of the second charging node 82b. Since the potential (V1) of the first charging node 81b is equal to or lower than the power supply voltage (Vcc), even if the potential (V2) of the second charging node 82b becomes greater than the power supply voltage (Vcc), the potential (V1) of the first charging node 81b is lower than the potential (V2) of the second charging node 82b.

[0076] By comparing the potential (V1) of the first charging node 81b and the potential (V2) of the second charging node 82b using the comparator 62, it is possible to determine that the potential (VB) of the first node 71 becomes equal to or greater than the power supply voltage (Vcc). The determination result is fed back to the gate control circuit 61. The gate control circuit 61 turns off the gates of the first switching element 83, the second switching element 84, and the third switching element 85, thereby completing the charging operation on the bootstrap capacitor 39 via the first node 71. In the determination circuit 80, in order to further improve the determination accuracy, the power supply voltage (Vcc) may be input to the comparator 62 as a reference of the potential (V1) of the first charging node 81b and the potential (V2) of the second charging node 82b. Sixth embodiment<Konfiguration einer Halbleitervorrichtung>

[0077] Fig. 19 is a schematic plan view illustrating a part of a semiconductor device according to a sixth embodiment, Fig. 20 is a schematic sectional view taken along a line XX-XX of Fig. 19, Fig. 21 is a schematic sectional view taken along a line XXI-XXI in Fig. 19, and Fig. 22 is a schematic sectional view taken along a line XXII-XXII in Fig. 19.

[0078] The Fig. 19 to 22 have basically the same configuration as those shown in Fig. 13 to 18, except that the planar shapes of the diffusion regions 5h, 5i and 5j of the N + -type, the first electrode layer 9e and the second electrode layer 9f constituting each switching element and the like, from those in the Fig. 13 to 18 are different.

[0079] Similar Fig. 14 illustrates Fig. 19 the planar shapes of an electrode layer serving as the gate electrode of the transistor 30, the first switching element 83, the second switching element 84 and the third switching element 85, and the diffusion regions 5a, 5h, 5i, 5j and 5k of the N + -type, which serve as the source region or the drain region. Specifically, a diffusion region 5a of the N + -type diffusion region 3a is formed on the surface of the P-type diffusion region 3a so as to extend along a boundary between the N-type diffusion region 2 and the P-type diffusion region 3a. An N-type diffusion region 5h + -type is formed on the surface of the P-type diffusion region 3a at a position separated from the N-type diffusion region 5a. + -type along the boundary. The diffusion region 5h from the N +-type comprises a first sub-area 5ha, which extends along the boundary, and a second sub-area 5hb, which is connected to the first sub-area 5ha and extends in a direction away from the boundary. A diffusion area 5j from the N + -Type is formed in an area located on the other side of the first sub-area 5ha in relation to the border.

[0080] A diffusion region 5i of the N + -type is formed on the surface of the P-type diffusion region 3a at a position separated from the N diffusion region 5h + -type along the boundary. The diffusion region 5i from the N + -type comprises a first region 5ia extending along the boundary, and a second partial region 5ib connected to the first partial region 5ia and extending in a direction away from the boundary. A diffusion region 5k of the N +-type is formed in a region on the other side of the first partial region 5ia with respect to the boundary. The planar shape of the diffusion region 5h of the N + -type and the planar shape of the diffusion region 5j of the N + -type are line- or axisymmetric about a center line located between the second partial area 5hb and the second partial area 5ib and running parallel to the second partial area 5hb, and similarly, the planar shape of the diffusion area 5j of the N + -type and the planar shape of the diffusion region 5k of the N + -type axially symmetric around the center line. A diffusion region 5a of N + -type is formed on the surface of the P-type diffusion region 3a at a position separated from the N-type diffusion region 5i + -type along the boundary. The diffusion region 5a of the N + -Type extends along the border.

[0081] A gate electrode 9g is formed such that it extends from a diffusion region 5a of the N + -type adjacent position extends across the surface of the P-type diffusion region 3a to the N-type diffusion region 2. An insulating film 15 is arranged below the gate electrode 9g as a gate insulating film. A first electrode layer 9e is formed so as to be separated from the gate electrode 9g along the boundary. An insulating film 15 is formed below the first electrode layer 9e as a gate insulating film. The first electrode layer 9e is arranged opposite the N-type diffusion region 5j. + -type are arranged adjacently and configured to separate the first sub-area 5ha of the diffusion area 5h from the N + -type. The first electrode layer 9e extends from the P-type diffusion region 3a across the boundary to the N-type diffusion region 2. In plan view, the N +-type arranged so as to divide the first electrode layer 9e into a first electrode sub-region 9ea on the side of the diffusion region 5j of the N + -type and a second electrode portion 9eb on the side of the N-type diffusion region 2.

[0082] A second electrode layer 9f is formed so as to be separated from the first electrode layer 9e along the boundary. An insulating film 15 is formed below the second electrode layer 9f as a gate insulating film. The second electrode layer 9f is connected to the other diffusion region 5a of the N + -type are arranged adjacently and configured to separate part of the diffusion region 5i from the N +-type. The second electrode layer 9f is formed only on the P-type diffusion region 3a. The second electrode layer 9f is arranged at a position separated from the boundary. A gate electrode 9g is formed so as to be separated from one another by the other N-type diffusion region 5a. + -type adjacent position across the surface of the P-type diffusion region 3a to the N-type diffusion region 2. An insulating film 15 is formed below the gate electrode 9g as a gate insulating film.

[0083] As in Fig. 19, the gate electrode 9g of the transistor 30 is between the diffusion region 5a of the N + -type and the N-type diffusion region 2. A portion of the first electrode layer 9e, which is located between the N-type diffusion region 5j + -Type and the first sub-area 5ha of the diffusion area 5h from the N +-type, serves as the gate electrode of the second switching element 84. A portion of the first electrode layer 9e, which is located between the first portion 5ha of the diffusion region 5h of the N + -type and the N-type diffusion region 2 serves as the gate electrode of the third switching element 85. A portion of the second electrode layer 9f located between the N-type diffusion region 5k + -type and the first sub-area 5ia of the diffusion area 5i of the N + -type, serves as the gate electrode of the first switching element 83. The gate electrode 9g of the transistor 30 is between the other diffusion region 5a of the N + -type and the diffusion region 2 of N-type. <Effekt einer Halbleitervorrichtung>

[0084] The semiconductor device according to the present embodiment includes a fifth semiconductor region of the second conductivity type (the diffusion region 5j of N +-type), a sixth semiconductor region of the second conductivity type (the diffusion region 5h of the N + -type), a seventh semiconductor region of the second conductivity type (the diffusion region 5k from the N + -type) and an eighth semiconductor region of the second conductivity type (the diffusion region 5i of the N + -type). The fifth semiconductor region (the diffusion region 5j of the N + -type) is formed in the second semiconductor region (the P-type diffusion region 3a) and is separated from the third semiconductor region (the N-type diffusion region 5a). + -type). The sixth semiconductor region (the diffusion region 5h of the N + -type) is formed in the second semiconductor region (the P-type diffusion region 3a) and is separated from the fifth semiconductor region (the N-type diffusion region 5j) + -type). The seventh semiconductor region (the diffusion region 5k from the N +-type) is formed in the second semiconductor region (the P-type diffusion region 3a) and is separated from the fifth semiconductor region (the N-type diffusion region 5j) + -type). The eighth semiconductor region (the diffusion region 5i of the N + -type) is formed in the second semiconductor region (the P-type diffusion region 3a) and is separated from the seventh semiconductor region (the N-type diffusion region 5k) + -type). The sixth semiconductor region (the diffusion region 5h of the N + -type) comprises a first partial region 5ha which is closer to the first semiconductor region (the N-type diffusion region 2) than the fifth semiconductor region (the N-type diffusion region 5j). +-type) and is separated from the first semiconductor region (the N-type diffusion region 2). The semiconductor device further comprises a first electrode layer 9e and a second electrode layer 9f. The first electrode layer 9e is formed so as to extend from a position between the fifth semiconductor region (the N-type diffusion region 5j) + -type) and the first partial region 5ha, across the first partial region 5ha to the first semiconductor region (the N-type diffusion region 2). The first electrode layer 9e is arranged with the first insulating film (the insulating film 15) interposed therebetween. The second electrode layer 9f is formed such that it extends from a position between the seventh semiconductor region (the N-type diffusion region 5k) + -type) and the eighth semiconductor region (the diffusion region 5i of the N + -type) to the eighth semiconductor region (the diffusion region 5i of the N +-type). The second electrode layer 9f is arranged with the second insulating film (the insulating film 15) interposed therebetween. The second electrode layer 9f is arranged at a position separated from the boundary between the first semiconductor region (the N-type diffusion region 2) and the second semiconductor region (the P-type diffusion region 3a). In a plan view, the sixth semiconductor region (the N + -type) is formed so as to divide the first electrode layer 9e into a first electrode portion 9ea on the side of the fifth semiconductor region (the diffusion region 5j of the N + -type) and a second electrode portion 9eb on the side of the first semiconductor region (the N-type diffusion region 2). The fifth semiconductor region (the N-type diffusion region 5j) +-type) is a source region for the second switching element 84. The first partial region 5ha is a drain region for the second switching element 84 and a source region for the third switching element 85. The first semiconductor region (the N-type diffusion region 2) is a drain region for the third switching element 85. The first electrode partial region 9ea of ​​the first electrode layer 9e is a gate electrode of the second switching element 84. The second electrode partial region 9eb of the first electrode layer 9e is a gate electrode of the third switching element 85. The seventh semiconductor region (the N-type diffusion region 5k) is a drain region for the third switching element 85. + -type) is a source region for the first switching element 83. The eighth semiconductor region (the diffusion region 5i of the N + -type) is a drain region for the first switching element 83. The second electrode layer 9f is a gate electrode of the first switching element 83.

[0085] Since the diffusion area 5h from the N +-type is formed so as to insert the first electrode layer 9e into the first electrode portion 9ea on the side of the fifth semiconductor region (the diffusion region 5j of the N + -type) and the second electrode portion 9eb on the side of the first semiconductor region (the N-type diffusion region 2), it is possible to prevent the fifth semiconductor region (the N-type diffusion region 5j) from + -type) acts as the source region for the third switching element 85.

[0086] In other words, the diffusion region 5h of the N + -type configured to cover the diffusion area 5j of the N + -type. By adopting this configuration, the diffusion region 5j can be prevented as much as possible from being separated from the N + -Type, which serves as the source of the second switching element 84, acts as the source of the third switching element 85. Similar to the Fig. 14, the second electrode layer 9f is separated from the first electrode layer 9e so that the NchMOS transistor with high breakdown voltage is not sandwiched between the first partial region 5ia of the diffusion region 5i of the N + -type and the N-type diffusion region 2. By adopting this configuration, it is possible to prevent the current from being generated by the parasitic MOS structure not shown in the circuit diagram. As a result, the determination circuit 80 can stably output a signal voltage for detecting the potential (VB) of the first node 71, preventing the malfunction of the determination circuit 80. Seventh embodiment<Konfiguration einer Halbleitervorrichtung>

[0087] Fig. 23 is a circuit diagram illustrating a potential detection circuit in the semiconductor device according to the seventh embodiment. Fig. 23 has basically the same configuration as that shown in Fig. 13, except that the configuration of the first charging circuit 81 and the configuration of the second charging circuit 82 in the determination circuit 80 are different from those in the Fig. 13 illustrated semiconductor device. In other words, in the semiconductor device shown in Fig. In the semiconductor device illustrated in Figure 23, the first charging circuit 81 includes a fourth switching element 81e, and the second charging circuit 82 includes a fifth switching element 82e. The fourth switching element 81e is connected in parallel with the first capacitor 81a. The fifth switching element 82e is connected in parallel with the second capacitor 82a. <Effekt einer Halbleitervorrichtung>

[0088] The semiconductor device according to the present embodiment includes a fourth switching element 81e and a fifth switching element 82e. The fourth switching element 81e is connected in parallel with the first capacitor 81a. The fifth switching element 82e is connected in parallel with the second capacitor 82a. When the first switching element 83 and the second switching element 84 are turned off, the fourth switching element 81e and the fifth switching element 82e are turned on, and the first capacitor 81a and the second capacitor 82a are discharged.

[0089] Thus, by controlling the fourth switching element 81e and the fifth switching element 82e, it is possible to reliably discharge the first capacitor 81a of the first charging circuit 81 and the second capacitor 82a of the second charging circuit 82 and reset them to the initial state.

[0090] In the determination circuit 80 of the Fig. In the semiconductor device illustrated in Figure 13, the state of the first capacitor 81a and the state of the second capacitor 82a are subject to the influence of the discharge immediately after the completion of the previous charge or the subsequent discharge. Therefore, the initial state of the first capacitor 81a and the initial state of the second capacitor 82a may be different in each charging operation. In contrast to the state shown in Figure 13, Fig. Therefore, in the circuit operation assumed in the semiconductor device illustrated in Fig. 13, for example, when the potential (V2) of the second charging node 82b is greater than the potential (V1) of the first charging node 81b in the initial state, the potential (VB) of the first node 71 can be immediately determined to be greater than the power supply voltage (Vcc), which can terminate the charging operation.

[0091] If the first charging circuit 81 includes the fourth switching element 81e and the second charging circuit 82 includes the fifth switching element 82e as shown in Fig. 23, it is therefore possible to stabilize the voltage (VC1) of the first capacitor 81a and the voltage (VC2) of the second capacitor 82a in the determination circuit 80, making the operation of the determination circuit 80 stable. For example, while the gate of the first switching element 83 and the gate of the second switching element 84 are turned off to perform the charging operation, the gate of the fourth switching element 81e and the gate of the fifth switching element 82e are turned on. In this way, it is possible to dissipate the residual charges of the first capacitor 81a and the second capacitor 82a to reset the capacitors to the initial state, preventing the malfunction of the determination circuit 80.

Claims

[1] A semiconductor device providing a charging current to charge a target element (39), comprising: - a semiconductor layer (1) of a first conductivity type; - a first semiconductor region (2) of a second conductivity type formed on a main surface of the semiconductor layer (1) and electrically connected to a first electrode (71) of the target element (39); - a second semiconductor region (3a) of the first conductivity type formed on the main surface of the semiconductor layer (1) and arranged adjacent to the first semiconductor region (2); - a third semiconductor region (5a) of the second conductivity type formed on a surface of the second semiconductor region (3a) and supplied with a power supply voltage (VCC); - a source electrode (10b) connected to the third semiconductor region (5a) and supplied with the power supply voltage (VCC); - a drain electrode (10c) connected to the first semiconductor region (2) and electrically connected to the first electrode (71); - a back-gate electrode (10a) connected to and grounded by a region in the second semiconductor region (3a) separated from the third semiconductor region (5a); and - a gate electrode (9a) arranged to oppose a channel region located in the second semiconductor region (3a) between the third semiconductor region (5a) and the first semiconductor region (2), with a gate insulating film (15) interposed therebetween, wherein: - a breakdown voltage between the source electrode (10b) and the back-gate electrode (10a) is greater than the power supply voltage (VCC), - a fourth semiconductor region (21) of the second conductivity type is formed in the second semiconductor region (3a) and arranged to surround the periphery of the third semiconductor region (5a) and to insulate the third semiconductor region (5a) from the second semiconductor region (3a); - the fourth semiconductor region (21) extends from the periphery of the third semiconductor region (5a) to a region in the second semiconductor region (3a) which is opposite to the first semiconductor region (2) and separated from the first semiconductor region (2), and - the channel region is arranged in the second semiconductor region (3a) between the fourth semiconductor region (21) and the first semiconductor region (2). [2] A semiconductor device according to claim 1, further comprising a limit resistor (41) arranged on a current path from a power source providing the power supply voltage (VCC) to the channel region. [3] A semiconductor device according to claim 2, wherein the boundary resistor (41) is a portion of the fourth semiconductor region (21) located between the third semiconductor region (5a) and the channel region. [4] A semiconductor device providing a charging current to charge a target element (39), comprising: - a semiconductor layer (1) of a first conductivity type; - a first semiconductor region (2) of a second conductivity type formed on a main surface of the semiconductor layer (1) and electrically connected to a first electrode (71) of the target element (39); - a second semiconductor region (3a) of the first conductivity type formed on the main surface of the semiconductor layer (1) and arranged adjacent to the first semiconductor region (2); - a third semiconductor region (5a) of the second conductivity type formed on a surface of the second semiconductor region (3a) and supplied with a power supply voltage (VCC); - a source electrode (10b) connected to the third semiconductor region (5a) and supplied with the power supply voltage (VCC); - a drain electrode (10c) connected to the first semiconductor region (2) and electrically connected to the first electrode (71); - a back-gate electrode (10a) connected to and grounded by a region in the second semiconductor region (3a) separated from the third semiconductor region (5a); and - a gate electrode (9a) arranged to oppose a channel region located in the second semiconductor region (3a) between the third semiconductor region (5a) and the first semiconductor region (2), with a gate insulating film (15) interposed therebetween, wherein: - a breakdown voltage between the source electrode (10b) and the back-gate electrode (10a) is greater than the power supply voltage (VCC), - a main surface of the semiconductor layer (1) is formed with a trench (51), - a part of the trench (51) divides the channel region and the first semiconductor region (2), - the gate insulating film (15) is formed on a surface of an inner wall of the part of the trench (51) opposite the channel region, - the gate electrode (9a) is formed within the trench (51), - the trench (51) extends from the main surface of the semiconductor layer to a position deeper than the bottom of the second semiconductor region (3a), - the other part of the trench (51) is formed in a region between the back-gate electrode (10a) and the source electrode (10b), - the second semiconductor region (3a) comprises a first region (3aa) which is located closer to the back gate electrode (10a) than the other part of the trench (51), and a second region (3ab) which is located closer to the source electrode (10b) than the other part of the trench (51) and contains the channel region, - the first semiconductor region (2) extends over a region located below the part of the trench (51) so that it is in contact with the channel region, - the semiconductor region further includes an extended region (6) of the first conductivity type formed in the semiconductor layer (1) so as to be in contact with the first region (3aa) and the second region (3ab), and - the extended region (6) extends from the underside of the first region (3aa) via a region located below the other part of the trench (51) to the underside of the second region (3ab). [5] A semiconductor device according to claim 4, wherein the trench (51) is formed on the main surface of the semiconductor layer (1) and arranged to surround the third semiconductor region (5a). [6] A semiconductor device according to claim 5, wherein the second semiconductor region (3a) comprises a third region (3ac) located on the other side of the part of the trench (51) with respect to the second region (3ab), and a fourth region (3ad) located outside the trench (51) and continuous with the first region (3aa) and the third region (3ac). [7] Semiconductor device according to one of the preceding claims, further comprising a determination circuit (80) which determines whether a voltage of a first node (71) on a current path between the first electrode (71) and the first semiconductor region (2) is greater than the power supply voltage or not, where: - the determination circuit (80) contains a first charging circuit (81), a second charging circuit (82), a first switching element (83), a second switching element (84) and a third switching element (85), - the first charging circuit (81) includes a first capacitor (81a) and a first charging node (81b), - the first capacitor (81a) has two electrodes, - one electrode of the first capacitor (81a) is grounded and the other electrode of the first capacitor (81a) is electrically connected to the first charging node (81b), - the second charging circuit (82) includes a second capacitor (82a) and a second charging node (82b), - the second capacitor (82a) has two electrodes, - one electrode of the second capacitor (82a) is grounded and the other electrode of the second capacitor (82a) is electrically connected to the second charging node (82b), - the first charging node (81b) is supplied with the power supply voltage (VCC) via the first switching element (83), - the second charging node (82b) is supplied with the power supply voltage (VCC) via the second switching element (84), - the first capacitor (81a) and the second capacitor (82a) have the same capacitance, - the second charging node (82b) is connected to the first node (71) via the third switching element (85) and - the determination circuit (80) determines that the voltage of the first node (71) is greater than the power supply voltage (VCC) when the voltage of the second charging node (82b) is greater than the voltage of the first charging node (81b). [8] A semiconductor device according to claim 7, further comprising: - a fifth semiconductor region (5j) of the second conductivity type formed in the second semiconductor region (3a) and separated from the third semiconductor region (5a); - a sixth semiconductor region (5h) of the second conductivity type formed in the second semiconductor region (3a) and separated from the fifth semiconductor region (5j); - a seventh semiconductor region (5k) of the second conductivity type formed in the second semiconductor region (3a) and separated from the fifth semiconductor region (5j); and - an eighth semiconductor region (5i) of the second conductivity type formed in the second semiconductor region (3a) and separated from the seventh semiconductor region (5k), wherein: - the sixth semiconductor region (5h) contains a first partial region which is formed closer to the first semiconductor region (2) than the fifth semiconductor region (5j) and is separated from the first semiconductor region (2), - the semiconductor device further comprises: - a first electrode layer (9e) formed to extend from a position between the fifth semiconductor region (5j) and a first partial region across the first partial region to the first semiconductor region (2) and arranged with a first insulating film (15) arranged therebetween, and - a second electrode layer (9f) formed to extend from a position between the seventh semiconductor region (5k) and the eighth semiconductor region (5i) to the eighth semiconductor region (5i) and arranged with a second insulating film (15) arranged therebetween, - the second electrode layer (9f) is arranged at a position separated from a boundary between the first semiconductor region (2) and the second semiconductor region (3a), - in a plan view, the sixth semiconductor region (5h) is designed such that it divides the first electrode layer (9e) into a first electrode sub-region (9ea) on one side of the fifth semiconductor region (5j) and a second electrode sub-region (9eb) on the side of the first semiconductor region (2), - the fifth semiconductor region (5j) is a source region for the second switching element (84), - the first sub-region is a drain region for the second switching element (84) and a source region for the third switching element (85), - the first semiconductor region (2) is a drain region for the third switching element (85), - the first electrode portion (9ea) of the first electrode layer (9e) is a gate electrode of the second switching element (84), - the second electrode portion (9eb) of the first electrode layer (9e) is a gate electrode of the third switching element (85), - the seventh semiconductor region (5k) is a source region for the first switching element (83), - the eighth semiconductor region (5i) is a drain region for the first switching element (83) and - the second electrode layer (9f) is a gate electrode of the first switching element (83). [9] A semiconductor device according to claim 7 or 8, further comprising: - a fourth switching element (81e) connected in parallel with the first capacitor (81a); and - a fifth switching element (82e) connected in parallel with the second capacitor (82a), wherein, when the first switching element (83) and the second switching element (84) are turned off, the fourth switching element (81e) and the fifth switching element (82e) are turned on and the first capacitor (81a) and the second capacitor (82a) are discharged. [10] A semiconductor device according to any one of the preceding claims, wherein the breakdown voltage is 300 V or more.

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