Semiconductor structure with insulating element and method for forming the same

Abstract

Semiconductor structure (100), comprising: a substrate (102); a fin structure (104) which protrudes from the substrate (102); Nanostructures (108') which are formed above the fin structure (104); internal spacer elements (134) which are formed in notches (132) between the nanostructures (108'); and a gate structure (152) which surrounds the nanostructures (108'); a source / drain structure (142) connected to the nanostructures (108'), wherein the internal spacer elements (134) are configured to separate the source / drain structure (142) and the gate structure (152) from each other; and an insulating element (136) which is arranged between the fin structure (104) and the source / drain structure.

Description

BACKGROUND

[0001] The electronics industry faces a constantly increasing demand for smaller and faster electronic components capable of performing a greater number of increasingly complex and demanding functions. Consequently, there is a persistent trend in the semiconductor industry to produce cost-effective, high-performance, and energy-efficient integrated circuits (ICs). To date, these goals have largely been achieved by miniaturizing the dimensions of semiconductor ICs (e.g., the minimum feature size), thereby improving production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of the semiconductor manufacturing process. Thus, achieving continued progress in semiconductor ICs and components requires corresponding advancements in semiconductor manufacturing processes and related technologies.

[0002] Recently, multi-gate devices have been introduced with the intention of improving gate control by increasing gate-channel coupling, reducing turn-off current, and mitigating short-channel effects (SCEs). One such newly introduced multi-gate device is the wraparound gate transistor (GAA). The GAA device gets its name from its gate structure, which can extend around the channel area, providing access to the channel from two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for significant miniaturization while maintaining gate control and mitigating SCEs. However, integrating the fabrication features of the GAA can be challenging.

[0003] Document US 2017 / 0005195A1 describes a method for fabricating a semiconductor device that includes forming a fin extending from a substrate and having a source / drain region and a channel region. The fin comprises a first epitaxial layer with a first composition and a second epitaxial layer on top of the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source / drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source / drain element.

[0004] Publication US 2018 / 0151683A1 relates to a semiconductor device comprising a field-effect transistor (FET). The FET includes a first channel, a first source, and a first drain; a second channel, a second source, and a second drain; and a gate structure arranged over the first and second channels. The gate structure comprises a dielectric gate layer and a gate electrode layer. The first source comprises a first crystal-semiconductor layer, and the second source comprises a second crystal-semiconductor layer. The first and second sources are connected by an alloy layer consisting of one or more Group IV elements and one or more transition metal elements. The first crystal-semiconductor layer is not in direct contact with the second crystal-semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1A to 1E represent perspective views of intermediate stages in the fabrication of a semiconductor structure in accordance with some embodiments. The Fig. 2A-1 to 2K-1 represent cross-sectional views along line A - A' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. 2A-2 to 2K-2 represent cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 3A-1 to 3B-1 represent cross-sectional views along line A - A' of various stages in the production of a Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 3A-2 to 3B-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 4A-1 to 4C-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 4A-2 to 4C-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 5A-1 to 5B-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 5A-2 to 5B-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 6A-1 to 6B-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 6A-2 to 6B-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure shown in accordance with some embodiments. The Fig. Figures 7A-1 and 7A-2 represent cross-sectional views of a semiconductor structure in accordance with some embodiments. Fig. Figure 8 shows a cross-sectional view of a semiconductor structure in accordance with some embodiments. Fig. Figure 9 shows a cross-sectional representation of a semiconductor structure in accordance with some embodiments. Fig. Figure 10 shows a cross-sectional representation of a semiconductor structure in accordance with some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides numerous different embodiments, or examples, for realizing various elements of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements cannot be in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples.This repetition serves the purpose of simplification and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Several variations of the embodiments are described. In the different views and illustrative embodiments, similar reference numerals are used to identify similar elements. It is understood that additional operations may be provided before, during, and after the method(s), and some of the described operations may be substituted or omitted for other embodiments of the method.

[0008] The all-around gate transistor (GAA) structures described below can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. Typically, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing dimensions than those achievable using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed along with the structured sacrificial layer using a self-aligning process.Then the sacrificial layer is removed, and the remaining spacer elements can then be used to structure the GAA structure.

[0009] Embodiments of semiconductor structures and methods for forming them are provided. The semiconductor structures can be wrap-around gate transistors (GAA transistors). A wrap-around gate transistor can have semiconductor nanostructures and source / drain structures formed on opposite sides of the nanostructures. However, with the miniaturization of the device size, the source / drain structures can lead to an undesirable leakage current path in the off state if they are directly connected to the underlying substrate. Consequently, in some embodiments, an additional insulating element is formed before the source / drain structures are formed, so that the source / drain structures are separated from the substrate by the insulating element, and the leakage current can be avoided.

[0010] The Fig. Figures 1A to 1E represent perspective views of intermediate stages in the fabrication of a semiconductor structure 100 in accordance with some embodiments. As in Fig. As shown in Figure 1A, first semiconductor material layers 106 and second semiconductor material layers 108 are formed over a substrate 102 in accordance with some embodiments.

[0011] Substrate 102 can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate 102 can contain elemental semiconductor materials, composite semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials can include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Composite semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials can include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0012] In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are stacked alternately on the substrate 102. In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 can be made of different semiconductor materials. In some embodiments, the first semiconductor material layers 106 are made of SiGe, and the second semiconductor material layers 108 are made of silicon. Although three first semiconductor material layers 106 and three second semiconductor material layers 108 have been formed, it should be noted that the semiconductor structure can have a greater or lesser number of first semiconductor material layers 106 and second semiconductor material layers 108.For example, the semiconductor structure can have two to five of the first semiconductor material layers 106 and the second semiconductor material layers.

[0013] The first semiconductor material layers 106 and the second semiconductor material layers 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor-phase epitaxy (VPE).

[0014] After the first semiconductor material layers 106 and the second semiconductor material layers 108 have been formed as a semiconductor material stack over the substrate 102, the semiconductor material stack is structured to form a fin structure 104, as shown in Fig. 1B shown in accordance with some embodiments. In some embodiments, the fin structure 104 has a fin base structure 104B and the semiconductor material stack of the first semiconductor material layers 106 and the second semiconductor material layers 108.

[0015] In some embodiments, the structuring process comprises forming a mask structure 110 over the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure comprising a contact oxide layer 112 and a nitride layer 114 formed over the contact oxide layer 223. The contact oxide layer 112 can be made of silicon oxide formed by thermal oxidation or CVD, and the nitride layer 114 can be made of silicon nitride formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

[0016] After the fin structure 104 has been formed, an isolation structure 116 is formed around the fin structure 104, and the mask structure 110 is removed, as shown in Fig. 1C is shown in accordance with some embodiments. The isolation structure 116 is designed to electrically isolate active areas (for example, the fin structure 104) of the semiconductor structure 100 and is also referred to as a trench isolation feature (STI feature) in accordance with some embodiments.

[0017] The insulating structure 116 can be formed by applying an insulating layer over the substrate 102 and recessing the insulating layer such that the fin structure 104 protrudes from the insulating structure 116. In some embodiments, the insulating structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric lining (not shown) is formed before the insulating structure 116 is formed, and the dielectric lining is made of silicon nitride, while the insulating structure formed over the dielectric lining is made of silicon oxide.

[0018] After the isolation structure 114 has been formed, dummy gate structures 118 are formed across the fin structure 104 and extend over the isolation structure 116, as shown in Fig. Figure 1D shows in accordance with some embodiments. The dummy gate structures 118 can be used to define the source / drain regions and the channel regions of the resulting semiconductor structure 100.

[0019] In some embodiments, the dummy gate structures 118 comprise dielectric dummy gate layers 120 and dummy gate electrode layers 122. In some embodiments, the dielectric dummy gate layers 120 are made from one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO₂, HfZrO, HfSiO₂, HfTiO₂, HfAlO₂, or a combination thereof. In some embodiments, the dielectric dummy gate layers 120 are formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0020] In some embodiments, the dummy-gate electrode layers 122 are made of a conductive material. In some embodiments, the conductive material comprises polycrystalline silicon (poly-Si), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metals, or a combination thereof. In some embodiments, the dummy-gate electrode layers 122 are formed using CVD, PVD, or a combination thereof.

[0021] In some embodiments, hard mask layers 124 are formed over the dummy gate structures 118. In some embodiments, the hard mask layers 124 have several layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride.

[0022] The formation of the dummy gate structures 118 can include the conformal formation of a dielectric material as the dielectric dummy gate layers 120. Subsequently, a conductive material can be formed over the dielectric material as the dummy gate electrode layers 122, and the hard mask layer 124 can be formed over the conductive material. The dielectric material and the conductive material are then conformed by the hard mask layer 124 to form the dummy gate structures 118.

[0023] After the dummy gate structures 118 have been formed, gate spacer elements 126 are formed along opposite side walls of the dummy gate structure 118 and cover them, and fin spacer elements 128 are formed along opposite side walls of the source / drain regions of the fin structure 104 and cover them, as shown in Fig. 1E shown in accordance with some embodiments.

[0024] The gate spacer elements 126 can be configured to set off subsequently formed source / drain elements, to separate source / drain elements from the dummy gate structure 118 and to support the dummy gate structure 118, and the fin spacer elements 128 can be configured to restrict lateral growth of a subsequently formed source / drain structure and to support the fin structure 104.

[0025] In some embodiments, the gate spacer elements 126 and the fin spacer elements 128 are made from a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN) and / or a combination thereof. The formation of the gate spacer elements 126 and the fin spacer elements 128 can include the conformal application of a dielectric material covering the dummy gate structure 118, the fin structure 104 and the insulation structure 116 over the substrate 102, and performing an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer covering the top surfaces of the dummy gate structure 118, the fin structure 104 and sections of the insulation structure 116.

[0026] The Fig. 2A-1 to 2K-1 represent cross-sectional views along line A - A' of various stages of the production of the in Fig. Figure 1E shows a semiconductor structure 100 in accordance with some embodiments. Fig. 2A-2 to 2K-2 represent cross-sectional views along line B - B' of various stages of the production of the in Fig. 1E represents the semiconductor structure 100 shown in accordance with some embodiments. In particular, it represents Fig. 2A-1 shows the cross-sectional view along line AA', and Fig. 2A-2 represents the cross-sectional view shown along line BB' in Fig. 1E in accordance with some embodiments.

[0027] After the gate spacer elements 126 and the fin spacer elements 128 have been formed, the source / drain areas of the fin structure 104 are deepened to form source / drain depressions 130, as shown in the Fig. 2B-1 and 2B-2 are shown in accordance with some embodiments. In particular, the first semiconductor material layers 106 and the second semiconductor material layers 108, which are not covered by the dummy gate structures 118 and the gate spacer elements 126, are removed in accordance with some embodiments. In addition, some sections of the fin base structure 104B are also recessed to form curved upper surfaces, as shown in Fig. 2B-1 shown in accordance with some embodiments.

[0028] In some embodiments, the fin structure 104 is deepened by performing an etching process. The etching process can be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 118 and the gate spacer elements 126 are used as etching masks during the etching process.

[0029] In some embodiments, the lower surfaces of the source / drain depressions 130 are positioned lower than the upper surface of the insulation structure 116. Since the source / drain depressions 130 can be formed by performing an etching process, they cannot be too deep, as this could damage other sections of the semiconductor structures during the etching process. In some embodiments, the source / drain depression 130 has a depth in the range of approximately 10 nm to approximately 30 nm. The depth of the source / drain depression can be measured from the lowest section of the source / drain depression 130 to the plane of the original upper surface of the fin base structure 104B. In some embodiments, the fin spacer elements 128 are also recessed to form countersunk fin spacer elements 128'.

[0030] After the source / drain depressions 130 have been formed, the first semiconductor material layers 106 exposed by the source / drain depressions 130 are laterally recessed to form notches 132, as shown in the Fig. 2C-1 and 2C-2 shown in accordance with some embodiments.

[0031] In some embodiments, an etching process is performed on the semiconductor structure 100 to laterally deepen the first semiconductor material layers 106 of the fin structure 104 from the source / drain depressions 130. In some embodiments, during the etching process, the first semiconductor material layers 106 exhibit a higher etch rate (or a larger extent of etching) than the second semiconductor material layers 108, thereby forming notches 132 between adjacent second semiconductor material layers 108. In some embodiments, the etching process is an isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0032] Next, internal spacer elements 134 are formed in the notches 132 between the second semiconductor material layers 108, as shown in the Fig. 2D-1 and 2D-2 are shown in accordance with some embodiments. The inner spacers 134 are designed to separate the source / drain and gate structures formed in subsequent manufacturing processes in accordance with some embodiments. In some embodiments, the inner spacers 134 are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof.

[0033] After the inner spacer elements 134 have been formed, insulating elements 136 are formed in the lower section of the source / drain depressions 130, as shown in the Fig. 2E-1 and 2E-2 are shown in accordance with some embodiments. The insulating elements 136 are designed to separate the fin base structure 104B and the subsequently formed source / drain structure from each other in such a way that leakage currents can be reduced in accordance with some embodiments.

[0034] In some embodiments, the insulating element 136 has an upper section 138 and a lower section 140. The upper section 138 can be defined as a section of the insulating element 136 that is positioned higher than the lower surface of the lowest inner spacer element 134 and the lower surface of the first semiconductor material layer 106. The lower section 140 can be defined as a section of the insulating element 136 that is positioned lower than the lower surface of the lowest inner spacer element 134 and the lower surface of the first semiconductor material layer 106.

[0035] In some embodiments, the thickness H1 of the upper section 138 is less than the thickness H2 of the lower section 140. In some embodiments, the thickness H1 of the upper section 138 of the insulating element 136 is in the range of approximately 4 nm to approximately 8 nm. In some embodiments, the thickness H2 of the lower section 140 of the insulating element 136 is in the range of approximately 10 nm to approximately 30 nm. The size of the insulating element 136 can be adjusted so that it is thick enough to reduce or prevent leakage current. On the other hand, the insulating element cannot be too thick, as this would increase the resistance of the resulting transistor. It should be noted that the upper section 138 and the lower section 140 in Fig. Although 2E is divided into two sections, these two sections have only been drawn to illustrate the feature more clearly. That is to say, there is no actual boundary between the two sections.

[0036] In some embodiments, an uppermost section (for example, the upper surface) of the upper section 138 of the insulating element 136 is positioned higher than the upper surface of the fin base structure 104B and lower than the lowermost surface of the lowest of the second semiconductor material layers 108. In some embodiments, the ratio of the height H1 of the upper section 138 of the insulating element 136 to the distance D between the lowest of the second semiconductor material layer 108 (which will subsequently be used as a nanostructure) and the fin base structure 104B is in the range of approximately 1 / 3 to approximately 2 / 3. In some embodiments, the distance D between the lowest of the second semiconductor material layer 108 and the fin base structure 104B is in the range of approximately 8 nm to approximately 15 nm.

[0037] In some embodiments, the insulating elements 136 are arranged laterally between the inner spacer elements 134 and in direct contact with the inner spacer elements 134. In some embodiments, a lower section of the insulating elements 136 is arranged lower than the upper surface of the insulating structure 116.

[0038] In some embodiments, the insulating elements 136 are made from an undoped semiconductor material, such as undoped Si or undoped SiGe. The undoped semiconductor material can provide additional stress on the channel of the resulting transistor (for example, a PMOS transistor). In some embodiments, the insulating elements 136 are formed by performing an epitaxial growth process. The epitaxial growth process can be a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, a vapor phase epitaxy (VPE) process, or another applicable technique.

[0039] In some embodiments, the insulating elements 136 are made from an insulating material and are formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another applicable process. In some embodiments, the insulating elements 136 are made from metal oxide, silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluorine-doped silicate glass, or a combination thereof.

[0040] After the insulating elements 136 have been formed, source / drain structures 142 are formed above the insulating elements 136 in the source / drain depressions 130, as shown in the Fig. 2F-1 and 2F-2 shown in accordance with some embodiments.

[0041] In some embodiments, the source / drain structures 142 are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other applicable epitaxial growth processes, or a combination thereof. In some embodiments, the source / drain structures 142 are fabricated from any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.

[0042] In some embodiments, the source / drain structures 142 are doped in situ during the epitaxial growth process. For example, the source / drain structures 142 can be epitaxially grown SiGe doped with boron (B). Alternatively, the source / drain structures 142 can be epitaxially grown Si doped with carbon to form silicon:carbon source / drain elements (Si:C source / drain elements), with phosphorus to form silicon:phosphorus source / drain elements (Si:P source / drain elements), or with both carbon and phosphorus to form silicon-carbon-phosphorus source / drain features (SiCP source / drain elements). In some embodiments, the source / drain structures 142 are doped in one or more implantation processes after the epitaxial growth process.

[0043] In some embodiments, the source / drain structures 142 and the insulating elements 136 are made from the same semiconductor material, wherein the source / drain structures 142 are doped with dopants, but the insulating elements 136 are not. In some embodiments, the dopants in the source / drain structures 142 can diffuse into the insulating elements 136 during subsequent manufacturing processes, so that the source / drain structures 142 and the insulating elements 136 contain the same dopants, but the dopant concentration of the source / drain structures 142 is higher than the dopant concentration of the insulating elements 136.In some embodiments, the fin base structure 104B, the insulating elements 136 and the source / drain structures 142 are made from the same semiconductor material, wherein the dopant concentration of the source / drain structures 142 and the dopant concentration of the fin base structures 104B are both higher than the dopant concentration of the insulating elements 136.

[0044] In some embodiments, the source / drain structures 142 and the insulating elements 136 are made of different materials. In some embodiments, the source / drain structures 142 are made of a semiconductor material, and the insulating elements 136 are made of one or more dielectric materials.

[0045] After the source / drain structures 142 have been formed, a contact etch stop layer (CESL) 144 is conformally formed to cover the source / drain structures 142, and a dielectric intermediate layer (ILD layer) 146 is formed over the contact etch stop layers 144, as shown in the Fig. 2G-1 and 2G-2 shown in accordance with some embodiments.

[0046] In some embodiments, the contact etch stop layer 144 is made from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layers 144 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other deposition methods, or a combination thereof.

[0047] The dielectric interlayer 146 can have multiple layers made from several dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), and / or other applicable dielectric materials with a low k-value. The dielectric interlayer 146 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0048] After the contact etch stop layer 144 and the dielectric intermediate layer 146 have been applied, a planarization process, such as CMP or a back-etching process, can be carried out until the gate electrode layers 120 of the dummy gate structures 118 are exposed, as shown in Fig. 2G-1 shown in accordance with some embodiments.

[0049] Next, the dummy gate structures 118 are removed to form trenches 148, as shown in the Fig. 2H-1 and 2H-2 are shown in accordance with some embodiments. In particular, the dummy gate electrode layers 122 and dielectric dummy layers 120 are removed to form the trenches 148 between the gate spacer elements 126 in accordance with some embodiments. The removal process may include one or more etching processes. For example, if the dummy gate electrode layers 122 are polysilicon, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the dummy gate electrode layers 122. Subsequently, the dielectric dummy gate layers 120 may be removed using plasma dry etching, chemical dry etching, and / or wet etching.

[0050] After the dummy gate structures 118 have been removed, the first semiconductor material layers 106 are removed to form nanostructures 108', as shown in the Fig. 2I-1 and 2I-2 are shown in accordance with some embodiments. In particular, the second semiconductor material layers 108, which remain in the channel region, form the nanostructures 108', and gaps 150 are formed between the nanostructures 108' in accordance with some embodiments. The nanostructures 108' are configured to function as channel regions in the resulting semiconductor structure 100.

[0051] The first semiconductor material layers 106 can be removed by performing an etching process. The etching process can include a selective wet etching process, such as an APM etching process (for example, using an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the wet etching process uses etchants such as ammonium hydroxide solution (NH4OH), TMAH solution, ethylenediamine catechol solution (EDP), and / or potassium hydroxide solution (KOH).

[0052] After the nanostructures 108' have been formed, gate structures 152 are formed in the trenches 148 and the gaps 150 between the nanostructures 108', as shown in the Fig. 2J-1 and 2J-2 are shown in accordance with some embodiments. The gate structures 152 enclose the nanostructures 108' to form wrap-around gate transistor structures in accordance with some embodiments. In some embodiments, the gate structure 152 comprises an interface layer 154, a dielectric gate layer 156, and a gate electrode layer 166.

[0053] In some embodiments, the interface layers 154 are oxide layers formed around the nanostructures 108' and on the top surface of the fin base structure 104B. In some embodiments, the interface layers 154 are formed by performing a thermal process.

[0054] In some embodiments, the dielectric gate layers 156 are formed over the interface layers 154 such that the nanostructures 108' are surrounded (e.g., encased) by the dielectric gate layers 156. Furthermore, in some embodiments, the dielectric gate layers 156 also cover the side walls of the gate spacer elements 126 and the inner spacer elements 134. In some embodiments, the dielectric gate layers 156 are made from one or more layers of dielectric materials, such as HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), another suitable dielectric material with a high k-value, or a combination thereof. In some embodiments, the dielectric gate layers 156 are formed using CVD, ALD, another suitable method, or a combination thereof.

[0055] The gate electrode layers 158 are formed on the dielectric gate layer 156 and filled into the trenches 148 and the gaps 150 between the nanostructures 108' in such a way that the nanostructures 108' are enveloped by the gate structures 152 in accordance with some embodiments.

[0056] In some embodiments, the gate electrode layers 158 are made from one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layers 158 are formed using CVD, ALD, electroplating, another suitable process, or a combination thereof. Other conductive layers, such as exit work metal layers, can also be formed in the gate structures 52, but are not shown in the figures.After the interface layers 154, the dielectric gate layers 156 and the gate electrode layers 158 have been formed, a planarization process, such as CMP or a back-etching process, can be carried out until the dielectric intermediate layer 146 has been exposed.

[0057] After the gate structures 152 have been formed, silicide layers 160 and contacts 162 are formed over the source / drain structures 142, as shown in the Fig. 2K-1 and 2K-2 are shown in accordance with some embodiments. In particular, contact openings can be formed by the contact etch stop layer 144 and the dielectric intermediate layer 146 to expose the upper surfaces of the source / drain structures 142, and the silicide layers 160 and the contacts 162 can be formed in the contact openings. The contact openings can be formed using a photolithography process and an etching process. Furthermore, some sections of the source / drain structures 142 that have been exposed by the contact openings can also be etched during the etching process.

[0058] After the contact openings have been formed, the silicide layers 160 can be formed by depositing a metal layer over the upper surface of the source / drain structures 142 and annealing the metal layer such that it reacts with the source / drain structures 142 to form the silicide layers 160. The unreacted metal layer can be removed after the silicide layers 160 have been formed.

[0059] Subsequently, the contacts 162 are formed above the silicide layers 160 in the contact openings, as in the Fig. 2K-1 and 2K-2 are shown in accordance with some embodiments. In some embodiments, the contacts 162 are made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof.

[0060] The contacts 162 may further comprise a lining and / or a barrier layer. For example, a lining (not shown) may be formed on the side walls and bottom of the contact trench. The lining may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The lining may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical evaporation or a thermal process, may be used as an alternative. The barrier layer (not shown) may be formed over the lining (if present) and may cover the side walls and bottom of the opening.The barrier layer can be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process. The barrier layer can be made from tantalum nitride, although other materials such as tantalum, titanium, titanium nitride, or the like can also be used.

[0061] As described above, the semiconductor structure 100 features insulating elements 136 arranged between the source / drain structures 142 and the fin base structure 104B, in accordance with some embodiments. The formation of the insulating elements 136 can help block the current flow of the parasitic device, thereby interrupting the dominant creepage distance of the semiconductor structure 100. Consequently, the performance of the semiconductor structure 100 can be improved.

[0062] The Fig. Figures 3A-1 and 3B-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. Figure 1E shows the semiconductor structure 100a in accordance with some embodiments. Fig. Figures 3A-2 and 3B-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. Figure 1E represents the semiconductor structure 100a in accordance with some embodiments. The semiconductor structure 100a may be the same as the semiconductor structure 100 described above, except that the top surfaces of the insulating elements in the semiconductor structure 100a are not flat. Some processes and materials for forming the semiconductor structure 100a may be similar to or the same as those used for forming the semiconductor structure 100 and are not repeated here.

[0063] In particular, the processes which take place in the Fig. 1A to 1E, 2A-1 to 2D-1 and 2A-2 to 2D-2 are shown and previously described, carried out to form the fin structure 104 having the first semiconductor material layers 106 and the second semiconductor material layers 108 above the fin base structure 104B, the insulating structure 116, the dummy gate structures 118, the gate spacer elements 126, the fin spacer elements 128' and the inner spacer elements 134 in accordance with some embodiments. Next, insulating elements 136a are formed in the lower section of the source / drain recesses 130, as shown in the Fig. 3A-1 and 3A-2 shown in accordance with some embodiments.

[0064] In some embodiments, the insulating elements 136a are fabricated from an undoped semiconductor material (for example, undoped Si or undoped SiGe) by performing an epitaxial growth process. The epitaxial growth process can be a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, a vapor phase epitaxy (VPE) process, or another applicable technique. During the formation of the insulating element 136a, the growth rate of the central section of the insulating element 136a may be greater than that of the outer section, and therefore, in accordance with some embodiments, the central section of the emerging insulating element 136a has a greater thickness than the outer section. In some embodiments, the insulating element 136a has a curved (for example, convex) upper surface.

[0065] After the insulating elements 136a have been formed, processes which were previously described Fig. 2F-1 to 2K-1 and 2F-2 to 2K-2 are shown, implemented to form the semiconductor structure 100a, as shown in the Fig. 3B-1 and 3B-2 are shown in accordance with some embodiments. In some embodiments, the semiconductor structure 100a is a PMOS transistor, and the insulating elements 136a can provide additional stress for the nanostructures 108'. In some embodiments, the insulating elements 136a can be formed in both PMOS and NMOS transistors.

[0066] As in Fig. As shown in Figure 3B-1, the central section of the insulating elements 136a is relatively thicker than the edge section, but the upper surfaces of the insulating elements 136a are still positioned lower than the lowest surface of the nanostructures 108', so that the resistance of the semiconductor structure 100a is not too greatly affected in accordance with some embodiments.

[0067] The Fig. Figures 4A-1 to 4C-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. 1E shows the semiconductor structure 100b in accordance with some embodiments. Fig. Figures 4A-2 and 4C-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. Figure 1E shows the semiconductor structure 100b in accordance with some embodiments. The semiconductor structure 100b may be the same as the semiconductor structure 100 described above, except that the formation of the insulating elements of the semiconductor structure 100b differs from that of the semiconductor structure 100. Some processes and materials for forming the semiconductor structure 100b may be similar to or the same as those used for forming the semiconductor structure 100 and are not repeated here.

[0068] Similar to those used to form the semiconductor structure 100a, the ones in the Fig. The processes shown and previously described in Figures 1A to 1E, 2A-1 to 2D-1, and 2A-2 to 2D-2 are carried out in accordance with some embodiments. Next, insulating elements 136b are formed in the lower section of the source / drain recesses 130, as shown in the Fig. 4A-1 and 4A-2 shown in accordance with some embodiments.

[0069] In some embodiments, the insulating elements 136b are produced from an undoped semiconductor material (for example, undoped Si or undoped SiGe) by performing an epitaxial growth process. The formation of the insulating elements 136b can be similar to or the same as that of the insulating elements 136a, except that the thickness of the insulating element 136b can be greater than the thickness of the insulating element 136a. In some embodiments, the uppermost section of the insulating elements 136b is positioned higher than the lowermost section of the nanostructures 108'.

[0070] After the insulating elements 136b have been formed, an etching process can be carried out to form modified insulating elements 136b', as described in the Fig. Figures 4B-1 and 4B-2 are shown in accordance with some embodiments. In particular, the upper sections of the insulating elements 136b are removed such that the middle sections of the modified insulating elements 136b' become thinner than the edge sections of the modified insulating elements 136b' in accordance with some embodiments. This means that the upper surface of the middle section of the modified insulating elements 136b' is positioned lower than the upper surface of the edge section of the modified insulating elements 136b' in accordance with some embodiments. In some embodiments, the modified insulating element 136b' has a curved (for example, concave) upper surface.

[0071] Once the modified insulating elements 136b' have been formed, processes which were described previously will occur. Fig. 2F-1 to 2K-1 and 2F-2 to 2K-2 are shown, implemented to form the semiconductor structure 100b, as shown in the Fig. 4C-1 and 4C-2 are shown in accordance with some embodiments. Likewise, the semiconductor structure 100b is a PMOS transistor, and the modified insulating element 136b' can provide additional load for the nanostructures 108' in accordance with some embodiments. In some embodiments, the modified insulating element 136b' is formed in both PMOS and NMOS transistors.

[0072] Since an additional etching process is carried out, the upper surfaces of the modified insulating elements 136b' are positioned lower than the bottom surface of the nanostructures 108', so that the resistance of the semiconductor structure 100b is not too greatly affected in accordance with some embodiments.

[0073] The Fig. Figures 5A-1 and 5B-1 show cross-sectional views along line A - A' of various stages in the production of a Fig. Figure 1E shows the semiconductor structure 100c in accordance with some embodiments. Fig. Figures 5A-2 and 5B-2 show cross-sectional views along line B - B' of various stages of the production of the in Fig. Figure 1E shows the semiconductor structure 100c in accordance with some embodiments. The semiconductor structure 100c may be the same as the semiconductor structure 100 described above, except that the insulating elements in the semiconductor structure 100c are formed from multiple layers. Some processes and materials for forming the semiconductor structure 100c may be similar to or the same as those used for forming the semiconductor structure 100 and are not repeated here.

[0074] In particular, the ones in the Fig. The processes shown and previously described in sections 1A to 1E, 2A-1 to 2D-1, and 2A-2 to 2D-2 are carried out. Next, isolating elements 136c are formed in the lower section of the source / drain depressions 130, as shown in the Fig. 5A-1 and 5A-2 shown in accordance with some embodiments.

[0075] In some embodiments, the insulating element 136c comprises a first dielectric layer 136c-1, a second dielectric layer 136c-2, and a third dielectric layer 136c-3. In some embodiments, the dielectric constant of the first dielectric layer 136c-1 is higher than the dielectric constant of the second dielectric layer 136c-2 and the dielectric constant of the third dielectric layer 136c-3. The first dielectric layer 136c-1, with its relatively high dielectric constant, can help to reduce the parasitic capacitance of the resulting semiconductor structure 100c.

[0076] In some embodiments, the first dielectric layer 136c-1, the second dielectric layer 136c-2, and the third dielectric layer 136c-3 are made from different materials. In some embodiments, the first dielectric layer 136c-1 is made from HfO₂, HfSiO₂, HfSiON₂, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), or other suitable high-k dielectric materials. In some embodiments, the second dielectric layer 136c-2 is made from silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), and other applicable low-k dielectric materials.In some embodiments, the third dielectric layer 136c-3 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG) or other applicable dielectric materials with a low k-value.

[0077] The insulating element 136c can be formed by forming the first dielectric layer 136c-1, the second dielectric layer 136c-2 and the third dielectric layer 136c-3 such that they completely fill the source / drain recesses 130, and back-etching the first dielectric layer 136c-1, the second dielectric layer 136c-2 and the third dielectric layer 136c-3 to form the insulating element 136c in accordance with some embodiments.

[0078] Once the insulating elements 136c have been formed, processes which were described previously will occur. Fig. 2F-1 to 2K-1 and 2F-2 to 2K-2 are shown, implemented to form the semiconductor structure 100c, as shown in the Fig. 5B-1 and 5B-2 are shown in accordance with some embodiments. In some embodiments, the semiconductor structure 100c is an NMOS transistor. In some embodiments, the insulating elements 136c are formed in an NMOS transistor, and the insulating elements 136, 136a, and / or 136b are formed in a PMOS transistor. As shown in Fig. As shown in Figure 5B-1, the insulating elements 136c and the source / drain structures 142 essentially have flat interfaces arranged between them in accordance with some embodiments.

[0079] The Fig. Figures 6A-1 and 6B-1 show cross-sectional views of different stages in the fabrication of a 100d semiconductor structure, shown along the fin direction, and the Fig. Figures 6A-2 and 6B-2 show cross-sectional views of various stages in the fabrication of the semiconductor structure 100d along a gate direction, consistent with some embodiments. Some processes and materials for forming the semiconductor structure 100d may be similar to or the same as those previously described for forming the semiconductor structure 100 and are not repeated here.

[0080] In particular, the processes will be similar to those used in the Fig. Figures 1A to 1D and previously described are designed to form the fin structure 104, comprising the first semiconductor material layers 106 and the second semiconductor material layers 108 formed over the fin base structure 104B, the insulation structure 116 formed over the fin structure 104, and the dummy gate structures 118 formed over the fin structure 104, in accordance with some embodiments. Furthermore, the gate spacer elements 126 are formed on the side walls of the dummy gate structures 118, in accordance with some embodiments.

[0081] Next, the first semiconductor material layers 106 at the source / drain region are removed, as shown in the Fig. 6A-1 and 6A-2 are shown in accordance with some embodiments. In particular, the second semiconductor material layers 108 at the source / drain region are not removed, so that nanostructures 108' are formed in the source / drain region in accordance with some embodiments.

[0082] Subsequently, insulating elements 136d are formed in the lower sections of the source / drain trenches 130d, as shown in the Fig. Figures 6B-1 and 6B-2 are shown in accordance with some embodiments. The processes and materials for forming the insulating elements 136d may be similar to or the same as those previously described for forming the insulating elements 136.

[0083] In some embodiments, the insulating elements 136d are made from an insulating material. In some embodiments, the insulating elements 136d are made from metal oxide, silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluorine-doped silicate glass, or a combination thereof.

[0084] In some embodiments, the insulating elements 136d are formed by applying an insulating material by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other applicable processes, and partially etching the insulating material to form the insulating elements 136d such that they cover the fin base structure 104B.

[0085] In some embodiments, the upper surface of the insulating element 136d is positioned higher than the lower surface of the lowest nanostructures 108', but lower than the upper surface of the lowest nanostructures 108'. In some embodiments, the lowest nanostructures 108' are partially embedded in the insulating elements 136d in such a way that the leakage current can be reduced.

[0086] Next, source / drain structures 142d are formed over the insulating elements 136d in the source / drain trenches 130d, as shown in the Fig. Figures 6B-1 and 6B-2 are shown in accordance with some embodiments. Some processes and materials for forming the source / drain structures 142d may be similar to or the same as those previously described for forming the source / drain structures 142 and are not repeated here. As previously described, the nanostructures 108' are formed in the source / drain regions, and the subsequently formed source / drain structures 142d envelop the nanostructures 108', as shown in the Fig. 6B-1 and 6B-2 are shown in accordance with some embodiments. In some embodiments, the upper surfaces of the lowest nanostructures 108' are covered by the source / drain structures 142d, and the lower surfaces of the lowest nanostructures 108' are covered by the insulating elements 136d.

[0087] After the source / drain structures have been formed (142d), processes which were described previously will be carried out. Fig. 2G-1 to 2K-1 and 2G-2 to 2K-2 are shown, implemented to form the 100d semiconductor structure, as shown in the Fig. 6B-1 and 6B-2 are shown in accordance with some embodiments. In particular, the contact etch stop layer (CESL) (not shown) and an intermediate dielectric layer (ILD layer) 146 are formed, and the dummy gate structures 118 and the first semiconductor material layers 106 are removed to form the nanostructures 108d' in accordance with some embodiments. Subsequently, the gate structures 152 are formed to enclose the nanostructures 108d', and silicide layers 160 and the contact 162 are formed over the source / drain structure 142d, as shown in the Fig. 6B-1 and 6B-2 shown in accordance with some embodiments.

[0088] Since the semiconductor structure 100d, similar to those described above, features insulating elements 136d arranged between the source / drain structures 142d / nanostructures 108' and the fin base structure 104B, the leakage current of the transistor can be reduced. Therefore, the performance of the semiconductor structure 100d can be improved.

[0089] The Fig. Figures 7A-1 and 7A-2 represent cross-sectional views of a semiconductor structure 100e in accordance with some embodiments. The semiconductor structure 100e may be the same as the semiconductor structure 100d described above, except that the upper surfaces of the insulating elements in the semiconductor structure 100e are arranged essentially in the same plane as the bottommost nanostructure 108'. Some processes and materials for forming the semiconductor structure 100e may be similar to or the same as those for forming the semiconductor structure 100d and are not repeated here.

[0090] In particular, the nanostructures 108', which extend into the source / drain regions, are enveloped by the source / drain structures 142e, and insulating elements 136e are arranged between the source / drain structures 142e and the fin base structure 104B in accordance with some embodiments. The processes and materials for forming the source / drain structures 142e and the insulating elements 136e may be similar to or the same as those previously described for forming the source / drain structures 142 and the insulating elements 136, and are therefore not repeated here.

[0091] Fig. Figure 8 shows a cross-sectional view of a semiconductor structure 100f in accordance with some embodiments. The semiconductor structure 100f can be the same as the semiconductor structure 100d described above, except that the source / drain structures on two fin structures are fused into one in accordance with some embodiments. Processes and materials for forming the semiconductor structure 100f that are similar to or the same as those for forming the semiconductor structure 100d are not repeated here.

[0092] In particular, the ones in the Fig. The processes shown in 6A-1 and 6A-2, 6B-1 are carried out. Subsequently, the first semiconductor material layers 106 in the source / drain region of the fin structures are removed to form nanostructures 108f'-1 and 108f'-2 in accordance with some embodiments.

[0093] Next, an insulating element 136f is formed in the lower section of the source / drain region to cover both fin base structures 104B-1 and 104B-2, in accordance with some embodiments. The processes and materials for forming the insulating element 136f may be similar to or the same as those previously described for forming the insulating element 136d and are not repeated here.

[0094] After the insulating element 136f has been formed, a source / drain structure 142f is formed above the insulating element 136f, as shown in Fig. 8B is shown in accordance with some embodiments. The processes and materials for forming the source / drain structure 142f may be similar to or the same as those previously described for forming the source / drain structure 142 and are not repeated here.

[0095] After the source / drain structures 142f have been formed, processes which were described previously will be carried out. Fig. 2G-1 to 2J-1 and 2G-2 to 2J-2 are shown, carried out to form the semiconductor structure 100f, and a silicide layer 160f and a contact 162f are formed over the source-drain structures 142f, as shown in Fig. Figure 8 is shown in accordance with some embodiments. The processes and materials for forming the silicide layer 160f and the contact 162f may be similar to or the same as those previously described for forming the silicide layer 160 and the contact 162, and are not repeated here.

[0096] As in Fig. As shown in Figure 8, the nanostructures 108f'-1 and 108f'-2 are encased by the source / drain structure 142f in accordance with some embodiments. In some embodiments, the interface between the source / drain structure 142f and the insulating element 136f is located on a plane between the upper and lower surfaces of the lowest nanostructures 108f'-1 and 108f'-2. In some embodiments, the insulating element 136f is located between the source / drain structure 142f and the insulating structure 116.

[0097] Fig. Figure 9 shows a cross-sectional view of a semiconductor structure 100g in accordance with some embodiments. The semiconductor structure 100g can be the same as the semiconductor structure 100f described above, except that the upper surface of the insulating element 136g in the semiconductor structure 100g, in accordance with some embodiments, is arranged essentially in the same plane as the lowest nanostructures. Processes and materials for forming the semiconductor structure 100g that are similar to or the same as those for forming the semiconductor structure 100f are not repeated here.

[0098] In particular, the nanostructures 108g'-1 and 108g'-2 are enveloped by a source / drain structure 142g, and an insulating element 136g is arranged between the source / drain structures 142g and the fin base structures 104B-1 and 104B-2, in accordance with some embodiments. Next, a silicide layer 160g and a contact 162g are formed over the source / drain structures 142g, in accordance with some embodiments.

[0099] The processes and materials for forming the source / drain structure 142g, the insulating element 136g, the silicide layer 160g and the contact 162g may be similar or the same as those previously described for forming the source / drain structure 142, the insulating element 136, the silicide layer 160 and the contact 162, and are therefore not repeated here.

[0100] Fig. Figure 10 shows a cross-sectional view of a semiconductor structure 100h in accordance with several embodiments. The semiconductor structure 100h can be the same as the semiconductor structure 100g described above, except that the source / drain structures are not fused together at two fin structures. Processes and materials for forming the semiconductor structure 100h that are similar to or the same as those for forming the semiconductor structure 100g are not repeated here.

[0101] In particular, an insulating element 136h is formed in the lower section of the source / drain region of the fin base structures 104B-1 and 104B-2 in accordance with some embodiments. Subsequently, source / drain structures 142h-1 and 142h-2 are formed around the nanostructures 108h'-1 and 108h'-2 and separated from each other, as shown in Fig. 10 shown in accordance with some embodiments. In some embodiments, the lower surface of the source / drain trench 130h is completely covered by the insulating element 136h, and the insulating element 136h is completely covered by the source / drain structures 142h-1 and 142h-2.

[0102] After the source / drain structures 142h-1 and 142h-2 have been formed, processes which were described previously will be carried out. Fig. 2G-1 to 2J-1 and 2G-2 to 2J-2 are shown, carried out to form the semiconductor structure 100h, and silicide layers 160h-1 and 160h-2 and a contact 162h are formed over the source-drain structures 142h, as shown in Fig. 10 shown in accordance with some embodiments. The processes and materials for forming the silicide layers 160h-1 and 160h-2 and the contact 162h may be similar to or the same as those previously described for forming the silicide layer 160 and the contact 162, and are not repeated here.

[0103] In particular, the silicide layer 160h-1 is formed on the upper surface and side walls of the source / drain structure 142h-1, and the silicide layer 160h-2 is formed on the upper surface and side walls of the source / drain structure 142h-2 in accordance with some embodiments.

[0104] In some embodiments, a section of contact 162h is arranged between the silicide layers 160h-1 and 160h-2. In some embodiments, contact 162h is in direct contact with the insulating element 136h. Source / drain structures are typically formed on opposite sides of the nanostructure over a substrate. However, miniaturizing the device can lead to leakage currents at the bottom of the source / drain structures during the shutdown state. Consequently, in the embodiments described above, an additional insulating element (for example, the insulating elements 136, 136a, 136b', 136c, 136d, 136e, 136f, 136g and 136h) is formed before the source / drain structures (for example, the source / drain structures 142, 142d, 142e, 142f, 142g, 142h-1 and 142h-2) are formed, so that the source / drain structures are separated from the substrate 102 by the insulating element.Therefore, leakage current can be prevented, and the performance of semiconductor structures can be improved.

[0105] Furthermore, although the insulating elements 136, 136a, 136b', 136c, 136d, 136e, 136f, 136g, and 136h are shown in different figures, they can be formed in the same device. This means that a semiconductor structure can have more than one of the semiconductor structures described above and more than one of the insulating elements 136, 136a, 136b', 136c, 136d, 136e, 136f, 136g, and 136h. In some embodiments, a semiconductor structure includes a PMOS transistor as described in Fig. The structure shown in 3B-1 and 3B-2, and featuring an NMOS transistor, is shown in Fig. The structure shown in 5B-1 and 5B-2 is shown.

[0106] It should be noted that the same elements are found in the Fig. 1A to 10B may be marked with the same numbers, have similar materials, and be produced through similar processes; therefore, such redundant details have been omitted for the sake of brevity. Furthermore, the Fig. Although sections 1A to 10B are described with regard to a procedure, it is understood that the information contained in the Fig. The structures disclosed in sections 1A to 10B are not limited to the procedure, but can exist independently of the procedure. Likewise, the structures disclosed in the Fig. The methods shown in Figures 1A to 10B are not limited to the disclosed structures, but can stand on their own, independent of the structures. Furthermore, in accordance with some embodiments, the nanostructures described above may include nanowires, nanosheets, or other applicable nanostructures.

[0107] Although disclosed methods are further presented and described as a sequence of actions or events, it is understood that the presented sequence of these actions or events may be modified in some other embodiments. For example, some actions may occur in different sequences and / or simultaneously with other actions or events than those presented and / or described above. Furthermore, not all of the presented actions may be necessary to implement one or more aspects or embodiments of the above description. Additionally, one or more of the actions presented above may be performed in one or more separate actions and / or phases.

[0108] Furthermore, the terms "approximately," "essentially," "significantly / substantially," and "about" above account for minor deviations, and quantities described using these terms can vary across different technologies and fall within a range of acceptable deviations for experts. When used in connection with an event or circumstance, these terms can refer, for example, to cases where the event or circumstance occurs precisely, as well as cases where it occurs approximately.

[0109] Embodiments for forming semiconductor structures can be provided. These semiconductor structures can include nanostructures and source / drain structures connected to nanostructures formed on a substrate. Furthermore, an insulating element can be formed before the source / drain structures are formed, thus separating them from the substrate. Consequently, the risk of leakage currents from the underside of the source / drain structure can be reduced, and the performance of the semiconductor structure can be increased.

[0110] In some embodiments, a semiconductor structure is provided. The semiconductor structure comprises a substrate and a fin structure projecting from the substrate. The semiconductor structure also includes nanostructures formed over the fin structure and a gate structure surrounding the nanostructures. Furthermore, the semiconductor structure includes a source / drain structure for connecting to the nanostructures and an insulating element arranged between the fin structure and the source / drain structure.

[0111] In some embodiments, a semiconductor structure is provided. The semiconductor structure comprises a substrate and a first fin structure projecting from the substrate. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure that encloses the first nanostructures at a channel region. The semiconductor structure also includes an insulating element that covers an upper surface of the first fin structure at a source / drain region, and a first source / drain structure formed over the insulating element and connected to the first nanostructures.

[0112] In some embodiments, a method for fabricating a semiconductor structure is provided. This method comprises alternately stacking first and second semiconductor material layers over a substrate and structuring the first semiconductor material layers, the second semiconductor material layers, and the substrate to form a fin structure. The method also includes removing the first semiconductor material layers to form nanostructures from the second semiconductor material layers in a channel region and forming a gate structure surrounding the nanostructures. Furthermore, the method includes forming a source / drain depression in a source / drain region of the fin structure and forming an insulating element within the source / drain depression.The process for manufacturing the semiconductor structure also includes forming a source / drain structure that covers the insulating element.

[0113] The foregoing outlines features of various embodiments in such a way that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying further processes and structures to achieve the same purposes and / or to obtain the same advantages as the embodiments presented herein.

Claims

[1] Semiconductor structure (100), comprising: a substrate (102); a fin structure (104) which protrudes from the substrate (102); Nanostructures (108') which are formed above the fin structure (104); internal spacer elements (134) which are formed in notches (132) between the nanostructures (108'); and a gate structure (152) which surrounds the nanostructures (108'); a source / drain structure (142) connected to the nanostructures (108'), wherein the internal spacer elements (134) are configured to separate the source / drain structure (142) and the gate structure (152) from each other; and an insulating element (136) which is arranged between the fin structure (104) and the source / drain structure. [2] Semiconductor structure (100) according to claim 1, wherein an upper surface of the insulating element (136) is arranged lower than a lower surface of the nanostructures (108'). [3] Semiconductor structure (100) according to claim 1 or 2, wherein an upper surface of the insulating element (136) is arranged higher than a lower surface of the nanostructures (108'). [4] Semiconductor structure (100) according to one of the preceding claims, wherein the insulating element (136) is made of an undoped semiconductor material. [5] Semiconductor structure (100) according to one of the preceding claims, wherein the insulating element (136) is made of an insulating material. [6] Semiconductor structure (100) according to one of the preceding claims, wherein the insulating element (136) has a curved upper surface. [7] Semiconductor structure (100) according to one of the preceding claims, wherein the insulating element (136) has a lining layer in direct contact with the fin structure (104) and an insulating material layer above the lining and in direct contact with the source / drain structure (142). [8] Semiconductor structure (100), comprising: a substrate (102); a first fin structure which protrudes from the substrate (102); first nanostructures (108') which are formed above the first fin structure; wherein the nanostructures (108') are configured to function as channel regions in the semiconductor structure (100); a gate structure (152) which surrounds the first nanostructures in a channel region; an insulating element (136) which covers an upper surface of the first fin structure at a source / drain region, wherein the uppermost section of the insulating element (136) is positioned higher than the lowermost section of the nanostructures (108'); and a first source / drain structure which is formed above the insulating element (136) and is connected to the first nanostructures. [9] Semiconductor structure (100) according to claim 8, further comprising: first internal spacer elements formed between the first nanostructures, wherein the insulating element (136) and the gate structure (152) are separated by the first inner spacer elements. [10] Semiconductor structure (100) according to claim 8 or 9, wherein the first nanostructures extend from the channel region to the source / drain region and the first source / drain structure encloses the first nanostructures. [11] Semiconductor structure (100) according to one of claims 8 to 10, wherein the insulating element (136) is arranged in direct contact with the first nanostructures. [12] Semiconductor structure (100) according to any one of claims 8 to 11, further comprising: an insulation structure (116) formed around the first fin structure, wherein a lower surface of the insulating element (136) is positioned lower than an upper surface of the insulation structure (116). [13] Semiconductor structure (100) according to any one of claims 8 to 12, further comprising: a second fin structure which protrudes from the substrate (102); and second nanostructures (108') which are formed above the second fin structure, wherein the insulating element (136) also covers an upper surface of the second fin structure. [14] Method for producing a semiconductor structure (100), comprising: alternating stacking of first semiconductor material layers and second semiconductor material layers over a substrate (102); Structuring the first semiconductor material layers (106), the second semiconductor material layers (108) and the substrate (102) to form a fin structure (104); Removing the first semiconductor material layers (106) and the second semiconductor material layers (108) at a source / drain region of the fin structure (104) so ​​that a source / drain depression (130) is formed in the source / drain region, wherein the insulating element (136) is formed in a lower section of the source / drain depression (130); Forming an insulating element (136) in the source / drain depression (130); Forming a source / drain structure (142) which covers the insulating element (136); Removal of the first semiconductor material layers (106) to form nanostructures (108') from the second semiconductor material layers (108) in a channel region; and Forming a gate structure (152) which encloses the nanostructures (108'). [15] Method for producing the semiconductor structure (100) according to claim 14, wherein a central section of the insulating element (136) is arranged higher than an edge section of the insulating element (136). [16] Method for producing the semiconductor structure (100) according to claim 14, wherein a central section of the insulating element (136) is arranged lower than an edge section of the insulating element (136). [17] Method for producing the semiconductor structure (100) according to any one of claims 14 to 16, further comprising: Removal of the first semiconductor material layers (106) at the source / drain region, so that the nanostructures (108') which extend into the source / drain region are formed, wherein the nanostructures (108') are enveloped by the source / drain structure (142). [18] Method for producing the semiconductor structure (100) according to any one of claims 14 to 17, wherein the insulating element (136) is made either from undoped Si or undoped SiGe. [19] Method for producing the semiconductor structure (100) according to any one of claims 14 to 18, wherein the insulating element (136) has several dielectric layers.

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