METHOD FOR TUNING THRESHOLD VOLTAGES OF TRANSISTORS AND STRUCTURE WITH TRANSISTORS

Abstract

Procedure comprehensive: Forming a gate dielectric (68) which extends over a first semiconductor region and a second semiconductor region in a first device region (100B) and a second device region (100D); Deposition of a first exit work layer (120) extending into the first semiconductor region and the second semiconductor region and across the gate dielectric (68); Removing the first exit working layer (120) from the second device region (100D), leaving the first exit working layer (120) in the first device region (100B) to form a first part of a first gate stack of a first transistor; Deposition of a second exit working layer (126, 132), wherein the second exit working layer (126, 132) extends into the first device region (100B) and lies above the first exit working layer (120) and extends into the second device region (100D) and lies above the gate dielectric (68), wherein the first exit working layer (120) is formed of TiN and the second exit working layer (126, 132) is formed of WCN or TiSiN, and wherein both the first exit working layer (120) and the second exit working layer (126, 132) are of a first conductivity type; Removing the second exit working layer (126, 132) from the first device region (100B), leaving the second exit working layer (126, 132) in the second device region (100D) to form a second part of a second gate stack of a second transistor; Deposition of an adhesive layer (140), wherein the adhesive layer (140) extends into the first device region (100B) and lies above the first exit working layer (120) and extends into the second device region (100D) and lies above the second exit working layer (126, 132); and Deposition of a third output working layer (138) extending into the first device region (100B) and above the first output working layer (120) and into the second device region (100D) and above the second output working layer (126, 132), wherein the third output working layer (138) lies below the adhesive layer (140) and the third output working layer (138) has a second conductivity opposite to the first conductivity type.

Description

GENERAL STATE OF THE ART

[0001] Transistors are fundamental components in integrated circuits. Transistor formation may involve forming replacement gates, which include high-k gate dielectrics and metal gate electrodes over the high-k gate dielectrics. Forming a replacement gate typically involves depositing a high-k gate dielectric and metal layers over the high-k gate dielectric and then performing chemical mechanical polishing (CMP) to remove excess portions of the high-k gate dielectric and metal layers. The remaining portions of the metal layers form the metal gates.

[0002] In conventional MOS device manufacturing processes, the threshold voltages of transistors can be adjusted by stacking multiple work function layers. For example, for p-type transistors, multiple titanium nitride layers can be stacked to reduce the threshold voltages of the p-type transistors and create multiple threshold levels.

[0003] US 2020 / 0 105 623 A1 discloses a method for manufacturing integrated circuits. US 2018 / 0 151562 A1 relates generally to integrated circuits and, more particularly, to low-bias reference circuits.

[0004] The invention provides improvements for tuning threshold voltages of transistors according to claim 1 and claim 7. Further developments emerge from the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1-6, 7A, 7B, 8, 9A, 9B, 22 and 23 illustrate perspective and cross-sectional views of intermediate stages in forming fin field-effect transistors (FinFETs) according to some embodiments. The Fig. 10 to 21 illustrate perspective and cross-sectional views of intermediate stages in forming gate stacks of multiple transistors according to some embodiments. Fig. 24 illustrates a process flow for forming a FinFET according to some embodiments. Fig. 25 illustrates a process flow for forming gate stacks of FinFETs according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially related terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0008] Transistors having different threshold voltages and methods of forming them are provided according to various embodiments. The intermediate stages of forming the transistors are illustrated according to some embodiments. Some variations of some embodiments are explained. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. According to some embodiments, the formation of fin field-effect transistors (FinFETs) is used as an example to explain the concept of the present disclosure. Other types of transistors, such as planar transistors and gate-all-around (GAA) transistors, may also adopt the concept of the present disclosure.According to some embodiments of the present disclosure, when forming work function layers, multiple work function layers with different work functions may be deposited. An upper work function layer may be etched using the respective lower work function layer as an etch stop layer, so that the total thickness of the work function layers in a FinFET is limited while different threshold voltage levels can be achieved.

[0009] The Fig. 1-6, 7A, 7B, 8, 9A, 9B, 22, and 23 illustrate cross-sectional and perspective views of intermediate stages in the formation of fin field-effect transistors (FinFETs) according to some embodiments of the present disclosure. The processes shown in these figures are also schematically depicted in the process flow 200 shown in Fig. 24 is shown.

[0010] In Fig. 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be part of a wafer 10, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise silicon; germanium; a compound semiconductor including carbon-doped silicon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0011] Further with reference to Fig. 1, a well region 22 is formed in the substrate 20. The respective process is illustrated as process 202 in the process flow 200, which in Fig. 24. According to some embodiments of the present disclosure, the well region 22 is a p-well region formed by implanting a p-type impurity, which may be boron, indium, or the like, into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting an n-type impurity, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n- or p-type impurity concentration may be 1018 cm -3 , such as in the range between approximately 10 17 cm -3 and about 10 18 cm -3 , or less.

[0012] With reference to Fig. 2, isolation regions 24 are formed to extend from a top surface of the substrate 20 into the substrate 20. The isolation regions 24 are alternatively referred to below as shallow trench isolation regions (STI regions). The respective process is illustrated as process 204 in the process flow 200 shown in Fig. 24. The portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor stripes 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein a top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also act as an etch stop layer for etching the hard mask layer 30.According to some embodiments of the present disclosure, the hard mask layer 30 is formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitriding of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etch mask to form hard masks 30, as shown in FIG. Fig. 2 is shown.

[0013] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric materials, and the remaining portions of the dielectric material(s) are STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20.The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material over the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like. The dielectric material over the liner dielectric may comprise silicon oxide, according to some embodiments.

[0014] The top surfaces of the hard masks 30 and the top surfaces of the STI regions 24 may be substantially at the same height. The semiconductor stripes 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor stripes 26 are parts of the original substrate 20, and thus the material of the semiconductor stripes 26 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor stripes 26 are replacement stripes formed by etching the portions of the substrate 20 between the STI regions 24 to form recesses and performing epitaxy to re-grow a different semiconductor material in the recesses. Accordingly, the semiconductor stripes 26 are formed from a semiconductor material that is different from that of the substrate 20.According to some embodiments, the semiconductor stripes 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0015] With reference to Fig. 3, the STI regions 24 are recessed so that the upper portions of the semiconductor stripes 26 protrude higher than the upper surfaces 24A of the remaining portions of the STI regions 24 to form protruding fins 36. The respective process is illustrated as process 206 in the process flow 200 shown in Fig. 24. The etching may be performed using a dry etching process, using, for example, HF3 and NH3 as the etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI regions 24 is performed using a wet etching process. The etching may include, for example, HF.

[0016] In the previously illustrated embodiments, the fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, enabling the creation of patterns having, for example, pitches smaller than what can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0017] With reference to Fig. 4, the dummy gate stacks 38 are formed such that they extend on the top surfaces and side walls of the (protruding) fins 36. The respective process is illustrated as process 208 in the process flow 200 shown in Fig. 24. The dummy gate stacks 38 may include dummy gate dielectrics 40 ( Fig. 7B) and dummy gate electrodes 42 over the dummy gate dielectrics 40. The dummy gate electrodes 42 may be formed using polysilicon, for example, and other materials may also be used. Each of the dummy gate stacks 38 may also include one (or more) hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stacks 38 may traverse a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stacks 38 also have longitudinal directions perpendicular to the longitudinal directions of the protruding fins 36.

[0018] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stacks 38. The respective process is also shown as process 208 in the process flow 200 shown in Fig. 24. According to some embodiments of the present disclosure, the gate spacers 46 are formed from dielectric material(s), such as silicon nitride, silicon carbonitride, or the like, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0019] An etching process is then performed to etch the portions of the protruding fins 36 that are not covered by the dummy gate stacks 38 and the gate spacers 46, resulting in the Fig. 5. The respective process is illustrated as process 210 in the process flow 200, which is shown in Fig. 24. The recess may be anisotropic, and thus the portions of the fins 36 that lie directly beneath the dummy gate stacks 38 and the gate spacers 46 are protected and are not etched. The upper surfaces of the recessed semiconductor strips 26 may be lower than the upper surfaces 24A of the STI regions 24 according to some embodiments. The recesses 50 are formed accordingly. The recesses 50 include portions that lie on opposite sides of the dummy gate stacks 38 and portions between remaining portions of the protruding fins 36.

[0020] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) a semiconductor material in the recesses 50, resulting in the structure in Fig. 6. The respective process is illustrated as process 212 in the process flow 200, which is shown in Fig. 24. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or n-type impurity may be doped in situ as epitaxy progresses. For example, if the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) may be grown. Conversely, if the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) may be grown. According to alternative embodiments of the present disclosure, the epitaxial regions 54 comprise III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the recesses 50 are filled with the epitaxial regions 54, further epitaxial growth of the epitaxial regions 54 causes the epitaxial regions 54 to expand horizontally, and facets can be formed.Further growth of the epitaxial regions 54 may also cause adjacent epitaxial regions 54 to merge. Gaps (air gaps) 56 may be created.

[0021] After the epitaxial growth step, the epitaxial regions 54 may be further implanted with a p-type or n-type impurity to form source and drain regions, which are also designated using reference numeral 54. According to alternative embodiments of the present disclosure, the implantation step is skipped if the epitaxial regions 54 are doped in situ with the p-type or n-type impurity during epitaxial growth.

[0022] Fig. 7A illustrates a perspective view of the structure after forming the contact etch stop layer (CESL) 58 and the inter-layer dielectric (ILD) 60. The respective process is illustrated as process 214 in the process flow 200 shown in Fig. 24. The CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 60 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. The ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a low-k dielectric material, or the like. A planarization process, such as a CMP process or a mechanical grinding process, may be performed to align the top surfaces of the ILD 60, the dummy gate stacks 38, and the gate spacers 46. Fig. Figure 7B illustrates the reference cross section 7B-7B in Fig. 7A. The upper surfaces 24A and the lower surfaces 24B of the STI regions 24 are illustrated to show where the STI regions 24 are located and where the undersides of the projecting fins 36 are located.

[0023] Next, the dummy gate stacks 38 including the hard mask layers 44, the dummy gate electrodes 42 and the dummy gate dielectrics 40 are etched, forming trenches 62 between the gate spacers 46, as shown in Fig. 8. The respective process is illustrated as process 216 in the process flow 200, which is shown in Fig. 24. The upper surfaces and side walls of the projecting fins 36 are exposed to the trenches 62. As shown in the Fig. 9A and Fig. 9B, the replacement gate stacks 72 are next formed in the trenches 62 ( Fig. 8). The respective process is illustrated as process 218 in the process flow 200, which is shown in Fig. 24 is shown. Fig. Figure 9B illustrates the reference cross section 9B-9B in Fig. 9A. The replacement gate stacks 72 include the gate dielectrics 68 and the corresponding gate electrodes 70.

[0024] According to some embodiments of the present disclosure, a gate dielectric 68 has an interfacial layer (IL) 64 as its lower part, as shown in Fig. 9B. The IL 64 is formed on the exposed top and sidewall surfaces of the protruding fins 36. The IL 64 may include an oxide layer, such as a silicon oxide layer, formed by the thermal oxidation or chemical oxidation of the surface layers of the protruding fins 36 or by a deposition process. The gate dielectric 68 may also include a high-k dielectric layer 66 formed over the IL 64. The high-k dielectric layer 66 comprises a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like, or composite layers thereof. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than approximately 7.0.The high-k dielectric layer 66 is formed as a conformal layer and extends onto the top surfaces and sidewalls of the protruding fins 36 and the top surface and sidewalls of the gate spacers 46. According to some embodiments of the present disclosure, the high-k dielectric layer 66 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

[0025] Further with reference to Fig. 9B, the gate electrode 70 is formed on the gate dielectric 68. The gate electrode 70 may include a plurality of stacked layers 74, which may be formed as conformal layers, and fill metal regions 76 that fill the remainder of the trenches not filled by the plurality of stacked layers 74. The stacked layers 74 may include a barrier layer, one or more work function layers over the barrier layer, and possibly an adhesive layer over the work function layer(s). According to some embodiments, the high-k dielectric layer 66 and the stacked layers 74 are deposited layer by layer as conformal layers followed by the deposition of the fill metal regions 76 to completely fill the trenches 62 ( Fig. 8). The conformal layers may include first portions in the trenches 62 and second portions overlapping the ILD 60. A planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the deposited materials. This results in the structure shown in the Fig. 9A and Fig. 9B. The detailed structure and the formation method of the stacked layers 74 will be described with reference to Fig. 10 to 20 explained.

[0026] Fig. Figure 9B schematically illustrates the region 78 in which a portion of the fin 36, a portion of the gate dielectric 68, a portion of the stacked layers 74, and a portion of the fill metal region 76 are received. Fig. 10 to 20 illustrate the formation of features in region 78 according to some embodiments. The respective process is illustrated as process flow 300, as shown in Fig. 25. The process 218, as shown in Fig. 24 is achieved by the process flow 300.

[0027] The Fig. 10 to 20 illustrate the formation of the gate stacks of four FinFETs in device regions 100A, 100B, 100C, and 100D according to some embodiments. Each of device regions 100A, 100B, 100C, and 100D may be an n-type FinFET or a p-type FinFET in any combination. As explained below, in an exemplary embodiment, an n-type FinFET is formed in device region 100A, and the FinFETs formed in device regions 100B, 100C, and 100D are p-type FinFETs.

[0028] With reference to Fig. 10, the gate dielectric 68, which includes the IL 64 and the high-k dielectric layer 66, is formed simultaneously in the device regions 100A, 100B, 100C, and 100D. The respective process is illustrated as process 302 in the process flow 300, as shown in Fig. 25. The IL 64 is formed on the protruding fin 36. The high-k dielectric layer 66 is formed over the IL 64.

[0029] In subsequent processes, work function layers may be formed directly on the high-k dielectric layer 66 and patterned to expose the high-k dielectric layer 66. To reduce the loss of the high-k dielectric layer 66 during patterning of the work function layers, the high-k dielectric layer 66 may be reinforced by a thermal annealing process. According to some embodiments, the thermal annealing process is performed at a temperature in a range of between approximately 700°C and approximately 900°C, with an annealing peak having a duration shorter than approximately 1 second. The process gas for the thermal annealing process may include N2, NH3, and / or the like. During the annealing process, the high-k dielectric layer 66 is exposed to the process gases.

[0030] Further with reference to Fig. 10, a first work function layer 120 is deposited on the high-k dielectric layer 66 and extends into the device regions 100A, 100B, 100C, and 100D. The respective process is illustrated as process 304 in the process flow 300, as shown in Fig. 25. According to some embodiments, the work function layer 120 has a first p-type work function that is greater than a mid-band work function of the protruding fins 36. The mid-band work function is located in the middle of the valence band and the conduction band of the protruding fins 36. The material of the work function layer 120 may be made of a composite material, such as TiN, TaN, Ti x Al y N, Ti x Si y N, WC x N y , MoC x N yor the like or combinations thereof, according to the claim, it is made of TiN. The integers x and y indicate the atomic numbers. The material of the work function layer 120 may also be selected from an elemental material, such as Au, Pt, Pd, W or the like, or alloys thereof. The material of the work function layer 120 may also comprise the composite material doped with the elemental material, as previously mentioned. The first work function layer 120 may be deposited using ALD, CVD, or the like, and is deposited as a conformal layer that extends into the trenches 62 ( Fig. 8) and also includes sections on the ILD 60.

[0031] With reference to Fig. 11, an etch mask 122 is formed and patterned. The etch mask 122 may include a photoresist and may also include a metal hard mask, an anti-reflective coating, or the like. The respective process is illustrated as process 306 in the process flow 300, as shown in Fig. 25. The portions of the etch mask 122 in the device regions 100A, 100C, and 100D are removed, leaving a remaining portion in the device region 100B. The etch process 124 is then performed to remove the portions of the work function layer 120 in the device regions 100A, 100C, and 100D, exposing the respective portions of the high-k dielectric layer 66. The respective process is illustrated as process 308 in the process flow 300, as shown in Fig. 25. The portion of the work function layer 120 in the device region 100B remains after etching. During the etch process 124, the high-k dielectric layer 66 is used as an etch stop layer. When the etch rate of the work function layer 120 is represented as ER120 and the etch rate of the high-k dielectric layer 66 is represented as ER66, the etch selectivity ER120 / ER66 may be greater than about 100 and range between about 100 and about 150. According to some embodiments, the work function layer 120 comprises TiN, while the high-k dielectric layer 66 comprises HfO2, and H2O may be used as an etch gas. The etch mask 122 is then removed, and the resulting structure is shown in Fig. 12 shown.

[0032] To reduce damage to the high-k dielectric layer 66 during the etching process 124, a soft wet etching technique may be applied. According to some embodiments, the soft wet etching is performed using an etchant with a high etch selectivity greater than approximately 100. In subsequent processes, whenever a work function layer is patterned, the soft wet etching technique may be applied to reduce damage to the underlying work function layer and / or high-k dielectric layer 66.

[0033] With reference to Fig. 13, a second work function layer 126 is deposited. The respective process is illustrated as process 310 in the process flow 300, as in Fig. 25. According to some embodiments, the FinFETs in device regions 100B, 100C, and 100D are p-type FinFETs, and thus, work function layer 126 has a second p-type work function. According to some embodiments, the second work function is different from, and may be greater than, or less than, the first work function of work function layer 120. The difference between the first and second work functions may be greater than about 50 mV and may range between about 50 mV and about 150 mV, although larger or smaller differences may also be applied. The material of the work function layer 126 can be selected from the same (or a different) group of candidate materials for forming the work function layer 120; according to the claim, it is made of WCN or TiSiN, while the materials of the work function layers 120 and 126 are different from each other.The second work function layer 126 may be deposited using ALD, CVD, or the like, and is deposited as a conformal layer that extends into the trenches 62 (Fig. Fig. 8) and also includes sections on the ILD 60.

[0034] With reference to Fig. 14, an etch mask 128 is formed and patterned. The respective process is illustrated as process 312 in the process flow 300, as shown in Fig. 25. The portions of the etch mask 128 in the device regions 100A, 100B, and 100C are removed, leaving a portion in the device region 100D. The etch process 130 is then performed to remove the portions of the work function layer 126 in the device regions 100A, 100B, and 100C, exposing the underlying high-k dielectric layer 66 or work function layer 120, as shown in Fig. 15. The respective process is illustrated as process 314 in the process flow 300, as shown in Fig. 25. The portion of the work function layer 126 in the device region 100D remains after etching. In the etch process 130, in the device regions 100A and 100C, the high-k dielectric layer 66 is used as an etch stop layer. In the device region 100B, the work function layer 120 is used as the etch stop layer. Accordingly, the etch selectivity of the work function layer 126 and the work function layer 120 is high. For example, when the etch rates of the work function layers 120 and 126 are represented as ER120 and ER126, respectively, the etch selectivity ER126 / ER120 is greater than about 100 and may range between about 100 and about 150. According to some embodiments, the work function layer 120 is formed from TaN and the work function layer 126 is formed from TiN.Accordingly, the HCl solution can be used as an etching chemical to etch the work function layer 126, and the etching is stopped on the work function layer 120. Similarly, the etch selectivity ER126 / ER66 is also high. For example, the etch selectivity ER126 / ER66 is greater than about 100 and can range between about 100 and about 150. After etching, the etch mask 128 (Fig. Fig. 14) and the resulting structure is shown in Fig. 15 shown.

[0035] With reference to Fig. 16, a third work function layer 132 is deposited. The respective process is illustrated as process 316 in the process flow 300, as in Fig. 25. According to some embodiments, the work function layer 132 has a third p-type work function that is different from the first work function of the work function layer 120 and the second work function of the work function layer 126. According to some embodiments, the third work function is different from, and may be greater than, the first work function and the second work function. The difference between the third work function and each of the first and second work functions may be greater than about 50 mV and may range from about 50 mV to about 150 mV, although larger or smaller differences may be applied. The material of the work function layer 132 may be selected from the same or a different group of candidate materials of the work function layers 120 and 126.The materials of the work function layers 120, 126, and 130 differ from one another. For example, the work function layers 120, 126, and 132 may be formed from TiN, WCN, and TiSiN, respectively, which have work functions with a relatively large difference from one another. The work function layer 132 may be deposited using ALD, CVD, or the like and is deposited as a conformal layer that extends into the trenches 62 (Fig. Fig. 8) and also includes sections on the ILD 60.

[0036] With reference to Fig. 17, an etch mask 134 is formed and patterned. The respective process is illustrated as process 318 in the process flow 300, as shown in Fig. 25. The portions of the etch mask 134 in the device regions 100A and 100B are removed, leaving the portions in the device regions 100C and 100D. The etch process 136 is then performed to pattern and remove the portions of the work function layer 132 in the device regions 110A and 100B, exposing the underlying high-k dielectric layer 66 or work function layer 120. The respective process is illustrated as process 320 in the process flow 300, as shown in Fig. 25. The portions of the work function layer 132 in the device regions 100C and 100D remain after etching. In the etching process, the high-k dielectric layer 66 is used as an etch stop layer in the device region 100A. In the device region 100B, the work function layer 120 is used as an etch stop layer. Accordingly, the etch selectivity of the work function layer 132 and the work function layer 120 is high. For example, the etch selectivity ER132 / ER120 is greater than about 20 and may range between about 100 and about 150. Similarly, the etch selectivity ER132 / ER66 is also high. For example, the etch selectivity ER126 / ER66 is greater than about 20 and may range between about 100 and about 150. After etching, the etching mask 134 is removed and the resulting structure is in Fig. 18 shown.

[0037] Fig. 19 illustrates the deposition of the work function layer 138 extending into the device regions 100A, 100B, 100C, and 100D. The respective process is illustrated as process 322 in the process flow 300, as shown in Fig. 25. According to some embodiments, the FinFET in device region 100A is an n-type FinFET, and thus the work function layer 138 has an n-type work function that is less than the mid-band work function of the protruding fins 36. The material of the work function layer 138 may be selected from TiC, TaC, TiAlC, Ti, Al, or the like, or combinations thereof. The work function layer 138 may be deposited using ALD, CVD, or the like, and is deposited as a conformal layer that extends into the trenches 62 ( Fig. 8) and also includes sections on the ILD 60.

[0038] According to some embodiments, the work function layers 120, 126, 132, and 138 have thicknesses T1, T2, T3, and T4, respectively. Each of the thicknesses T1, T2, T3, and T4 may range between approximately 1 nm and approximately 3 nm. The total thicknesses of all work function layers in each of the device regions 100A, 100B, 100C, and 100D may be less than approximately 5 nm and range between approximately 3 nm and approximately 5 nm. According to some embodiments, additional work function layer(s) (not shown) may be deposited and patterned to be stacked over p-type work function layers 120, 126, and 132 in device regions 100B, 100C, and 100D, with the additional work function layers located between the top p-type work function layer and n-type work function layer 138. According to alternative embodiments, no additional work function layers are formed.

[0039] Fig. 20 illustrates the formation of the adhesive layer 140. The respective process is illustrated as process 324 in the process flow 300, as in Fig. 25. The adhesive layer 140 may be formed from a metal nitride, such as TiN, according to some embodiments, and other materials, such as TaN, may be used. According to some embodiments, the adhesive layer 140 is formed using ALD.

[0040] Fig. 20 further illustrates the deposition of a filler metal to form the filler metal region 76. The respective process is illustrated as process 326 in the process flow 300, as in Fig. 25. According to some embodiments, the fill metal region 76 is formed from tungsten or cobalt, which may be formed using chemical vapor deposition. For example, WF6 and SiH4 may be used as process gases for depositing tungsten. After forming the fill metal region 76, a planarization process is performed to remove excess portions of the deposited layers, as shown in Fig. 20, with the excess sections located on the ILD 60 ( Fig. 8). The respective planarization process is illustrated as process 328 in the process flow 300, as in Fig. 25. As shown in the Fig. 9A and Fig. 9B, the gate stacks 72 are thus formed.

[0041] Fig. 22 illustrates the formation of hard masks 80 according to some embodiments. The respective process is illustrated as process 220 in the process flow 200 shown in Fig. 24. Forming the hard masks 80 may include performing an etch process to recess the gate stacks 72 so that recesses are formed between the gate spacers 46, filling the recesses with a dielectric material, and then performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the dielectric material. The hard masks 80 may be formed from silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.

[0042] Fig. 23 illustrates the formation of source / drain contact plugs 82. The respective process is illustrated as process 222 in the process flow 200 shown in Fig. 24. Forming the source / drain contact plugs 82 includes etching the ILD 60 to expose the underlying portions of the CESL 58 and then etching the exposed portions of the CESL 58 to expose the source / drain regions 54. In a subsequent process, a metal layer (such as a titanium layer) is deposited and extends into the contact openings. A metal nitride cap layer may be formed. An annealing process is then performed to react the metal layer with the upper portion of the source / drain regions 54 to form silicide regions 84. A fill metal material, such as tungsten, cobalt, or the like, is then filled into the contact openings, followed by planarization to remove excess materials, resulting in the source / drain contact plugs 82.Gate contact plugs (not shown) are also formed to penetrate through a portion of each of the hard masks 80 to contact the gate electrodes 70. Thus, the FinFETs 86 are formed, which can be connected in parallel as one FinFET.

[0043] The previously explained processes result in four FinFETs 186, 286, 386 and 486 comprising the gate stacks as shown in the device regions 100A, 100B, 100C and 100D in Fig. 20. Each of the FinFETs 186, 286, 386 and 486 is also like the FinFET 86 in Fig. 23. FinFET 186 is located in device region 100A and may be an n-type FinFET whose work function is determined by work function layer 138. FinFET 286 is located in device region 100B and may be a p-type FinFET whose work function is determined by work function layer 120, with work function layer 138 having a lesser impact on the work function of FinFET 286. FinFET 386 is located in device region 100C and may be a p-type FinFET whose work function is determined by work function layer 132, with work function layer 138 having a lesser impact on the work function of FinFET 386.FinFET 486 is located in device region 100D and may be a p-type FinFET whose work function is determined by work function layer 126, with work function layers 132 and 138 having a smaller impact on the work function of FinFET 386. Accordingly, by selecting appropriate work function materials that differ from each other, some work function layers can be removed from some device regions, and the overall thicknesses of the work function layers are small. For example, in the illustrated example, at least three work function layers are present (in device region 100D), while at least four work functions and four threshold voltage levels are present.

[0044] Furthermore, using the same processes as previously explained, additional FinFETs with different work functions than the gate stacks used in Fig. 20 are formed in additional device regions, which are referred to as device regions 100E and 100F in Fig. 21. A first additional FinFET 586 may be formed in device region 100E, having work functions comprising layer 120 and layer 126 above layer 120. A second additional FinFET 686 may be formed in device region 100F, having work functions comprising layer 120 and layer 132 above layer 120. Accordingly, the additional FinFETs may have work functions (and corresponding threshold voltages) that differ from those of FinFETs 186, 286, 386, and 486. The formation of the additional FinFETs can be achieved by sharing the same processes as FinFETs 186, 286, 386, and 486, except that the patterns of the etch masks are modified to form the gate stacks in device regions 100E and 100F.

[0045] In the previously discussed examples, p-type work function layers are formed for different p-type FinFETs, resulting in different threshold voltages. An n-type work function layer is then deposited for an n-type FinFET and over the work function layers of the p-type FinFETs. According to alternative embodiments, multiple n-type work function layers can be formed and patterned for different n-type FinFETs, resulting in different threshold voltages. A p-type work function layer can then be deposited for a p-type FinFET, with the p-type work function layer located over the work function layers of the n-type FinFETs.

[0046] The embodiments of the present disclosure can be distinguished structurally. For example, transmission electron microscopy (TEM) can be used to distinguish the boundaries of different work function layers and their overlying and underlying layers. X-ray photoelectron spectroscopy (XPS) can be used to determine the compositions of the layers. Energy-dispersive X-ray spectroscopy (EDX) can be used to determine the elements in the work function layers.

[0047] The embodiments of the present disclosure have several advantageous features. By applying work function layers having different work functions, some work function layers can be removed from the same transistor regions to reduce the overall thickness of the work function layers. This overcomes the problems in conventional processes. For example, in conventional processes, to achieve more work function levels (and threshold voltage levels), more work function layers are stacked. For example, a single TiN layer, two TiN layers, and three TiN layers can be used to achieve three work function levels and corresponding three threshold voltage levels. However, stacking multiple layers to achieve lower work function levels results in an increase in the overall thickness of the work function layers, and this becomes prohibitive in more advanced technologies.Furthermore, the cap layer(s) and the barrier layer(s) conventionally formed between the high-k dielectric layer and the work function layer(s) are omitted in the embodiments of the present disclosure to reduce the thickness of the gate stacks.

Claims

[1] Procedure comprising: Forming a gate dielectric (68) extending across a first semiconductor region and a second semiconductor region in a first device region (100B) and a second device region (100D), respectively; depositing a first work function layer (120) extending into the first semiconductor region and the second semiconductor region and over the gate dielectric (68); Removing the first work function layer (120) from the second device region (100D), leaving the first work function layer (120) in the first device region (100B) to form a first portion of a first gate stack of a first transistor; Depositing a second work function layer (126, 132), wherein the second work function layer (126, 132) extends into the first device region (100B) and overlies the first work function layer (120) and extends into the second device region (100D) and overlies the gate dielectric (68), wherein the first work function layer (120) is formed of TiN and the second work function layer (126, 132) is formed of WCN or TiSiN, and wherein both the first work function layer (120) and the second work function layer (126, 132) are of a first conductivity type; Removing the second work function layer (126, 132) from the first device region (100B), leaving the second work function layer (126, 132) in the second device region (100D) to form a second portion of a second gate stack of a second transistor; Depositing an adhesive layer (140), wherein the adhesive layer (140) extends into the first device region (100B) and overlies the first work function layer (120) and extends into the second device region (100D) and overlies the second work function layer (126, 132); and Depositing a third work function layer (138) extending into the first device region (100B) and over the first work function layer (120) and extending into the second device region (100D) and over the second work function layer (126, 132), wherein the third work function layer (138) is below the adhesive layer (140) and the third work function layer (138) is of a second conductivity opposite to the first conductivity type. [2] The method of claim 1, wherein removing the first work function layer (120) from the second device region (100D) uses the gate dielectric (68) as an etch stop layer. [3] The method of any preceding claim, wherein removing the second work function layer (126) from the first device region (100B) comprises using the first work function layer (120) as an etch stop layer. [4] The method of any preceding claim, wherein the adhesive layer is located over and in physical contact with portions of the third work function layer (138) in both the first device region (100B) and the second device region (100D). [5] The method of any preceding claim, wherein both the first work function layer (120) and the second work function layer (126, 132) extend into a third device region (100E), and wherein, after the first work function layer (120) is removed from the second device region (100D) and after the second work function layer (126) is removed from the second device region (100D), both the first work function layer (120) and the second work function layer (126) remain in the third device region (100E) and form a third part of a third gate stack of a third transistor. [6] The method of any preceding claim, wherein the first work function layer (120) extends into the first device region (100B) to physically contact a first portion of a high-k dielectric layer of the gate dielectric (68), and the second work function layer (126) extends into the second device region (100D) to physically contact a second portion of the high-k dielectric layer. [7] Structure that has the following: a semiconductor substrate (20) having a first semiconductor region and a second semiconductor region; a first transistor comprising: a first gate dielectric over the first semiconductor region; a first work function layer (120) above and in contact with the first gate dielectric; and a first conductive region over the first work function layer (120); and a second transistor comprising: a second gate dielectric over the second semiconductor region; a second work function layer (132) above and in contact with the second gate dielectric, wherein the first work function layer (120) and the second work function layer (132) have different work functions, and wherein the first work function layer (120) is formed from TiN and the second work function layer (132) is formed from WCN or TiSiN, and wherein both the first work function layer (120) and the second work function layer (126) are of a first conductivity type; a second conductive region over the second work function layer (132); a third work function layer (138) over and in contact with the first work function layer (120); and a fourth work function layer (138) above and in contact with the second work function layer (132), wherein the third work function layer (138) and the fourth work function layer (138) are formed of a same material and are of a second conductivity type that is the opposite of the first conductivity type. [8] The structure of claim 7, wherein the first transistor further comprises a first adhesive layer (140) over and in physical contact with the third work function layer (132) and the second transistor further comprises a second adhesive layer over and in physical contact with the fourth work function layer (138), the first adhesive layer and the second adhesive layer being formed from a same additional material. [9] The structure of claim 8, wherein the first adhesive layer and the second adhesive layer are formed of titanium nitride. [10] Structure according to claim 8, wherein the semiconductor substrate (20) is a bulk semiconductor substrate; the first transistor is a first fin field effect transistor, FinFET, comprising: a first semiconductor fin that protrudes higher than the bulk semiconductor substrate wherein the first gate dielectric comprises a first high-k dielectric layer on first sidewalls and a first top surface of the first semiconductor fin; wherein the second transistor is a second FinFET comprising: a second semiconductor fin protruding higher than the bulk semiconductor substrate; wherein the second gate dielectric comprises a second high-k dielectric layer on second sidewalls and a second top surface of the second semiconductor fin. [11] The structure of claim 10, wherein both the first work function layer (120) and the second work function layer (132) are p-type work function layers. [12] A structure according to any one of claims 10 or 11, further comprising: a third FinFET which has the following: a third semiconductor fin protruding higher than the bulk semiconductor substrate; a third high-k dielectric layer on third sidewalls and a third top surface of the third semiconductor fin; a fifth work function layer over and in contact with the third high-k dielectric layer, wherein the second work function layer (132) and the fifth work function layer are formed of the same material of the second conductivity type; and a third adhesive layer above and in contact with the fifth work function layer.

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