Source / drain contacts and methods for their formation

Abstract

Device comprising: a device layer (115) comprising a first transistor and a second transistor; a first interconnect structure (120) on a front side of the device layer (115); and a second interconnect structure (136) on a back side of the device layer (115), the second interconnect structure (136) comprising: a first dielectric layer (162) on the back side of the device layer (115), wherein a semiconductor material (50) is arranged between the first dielectric layer (162) and a first source / drain region (92) of the first transistor; a contact (170) extending through the first dielectric layer (162) to a second source / drain region (92') of the second transistor; and a first line (134) which is electrically connected to the second source / drain region (92') of the second transistor via the contact (170).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material onto a semiconductor substrate. The various material layers are then structured using lithography to create circuit components and elements.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest possible feature size, thus enabling the integration of more components on a given area. However, as the smallest possible feature sizes are reduced, additional problems arise that must be solved. DE 11 2016 007 299 T5 describes an IC structure made of bonded wafers. During front-side processing of a transmission wafer with a component layer, a sacrificial source / drain (S / D) material and front-side wiring are formed. The transmission wafer is then flipped and bonded to a host wafer. After back-side exposure of the component layer by grinding, etching, and / or CMP processes, a back-side source / drain (S / D) exchange is performed.For this process, the sacrificial S / D material is removed by means of backside S / D contact grooves, using a seed layer as an etch stop, and relatively highly doped final S / D material is formed or grown from the seed layer. Finally, the backside wiring is formed. US 2008 / 0054313A1 describes an IC structure with backside contacts that are electrically connected from a backside surface of a substrate, through the substrate, to frontside semiconductor devices. For this purpose, backside contact openings are etched into the backside surface, which are aligned with the frontside semiconductor devices via alignment features in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as necessary for the sake of clarity in this discussion.

[0004] Fig. Figure 1 illustrates an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments.

[0005] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 12E, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28A, Fig. 28B, Fig. 28°C, Fig. 29A, Fig. 29B and Fig. Figure 29C shows cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments.

[0006] Fig. 30A, Fig. 30B, Fig. 30°C Fig. 31A, Fig. 31B, Fig. 31C, Fig. 32A, Fig. 32B, Fig. 32C, Fig. 33A, Fig. 33B, Fig. 33C, Fig. 33D, Fig. 33E, Fig. 34A, Fig. 34B, Fig. 34C, Fig. 34D, Fig. 34E, Fig. 35A, Fig. 35B, Fig. 35°C Fig. 35D, Fig. 35E, Fig. 36A, Fig. 36B, Fig. 36C, Fig. 36D and Fig. Figure 36E shows cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0009] Several embodiments provide a backside interconnect structure in which a large portion of a semiconductor substrate is etched away and removed, creating backside contacts to the source / drain regions of transistors formed on the semiconductor substrate. As part of the backside contact formation process, the etching of the semiconductor substrate includes leaving a portion of the semiconductor substrate such that at least the edge regions of the source / drain areas are covered. Consequently, the source / drain areas can be protected by the remaining semiconductor substrate during the backside contact formation process, and manufacturing defects can be reduced.

[0010] Some embodiments discussed here are described in connection with a die containing nanoFETs. However, various embodiments can be applied to dies containing other transistor types (for example, fin field-effect transistors (FinFETs), planar transistors, or the like), instead of the nanoFETs, or in combination with the nanoFETs.

[0011] Fig. Figure 1 illustrates an example of nanoFETs (for example, nanowire FETs, nanolayer FETs, or the like) in a three-dimensional view according to some embodiments. The nanoFETs comprise nanostructures 55 (for example, nanolayers, nanowires, or the like) over fins 66 on a substrate 50 (for example, a semiconductor substrate), the nanostructures 55 serving as channel regions for the nanoFETs. The nanostructure 55 can have p-nanostructures, n-nanostructures, or a combination thereof. Shallow trench isolation (STI) regions 68 are arranged between adjacent fins 66, which can project over and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, the term “substrate” in the context of this text can refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the STI regions.Furthermore, although the lower sections of the fins 66 are illustrated as single, continuous materials with the substrate 50, the lower sections of the fins 66 and / or the substrate 50 can also comprise a single material or multiple materials. In this context, the fins 66 refer to the section extending between the adjacent STI regions 68.

[0012] Gate dielectric layers 100 are located above the top surfaces of the fins 66 and along the top, side walls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are located above the gate dielectric layers 100. Epitaxial source / drain regions 93 are arranged on the fins 66 on opposite sides of the gate dielectric layers 100 and the gate electrodes 102.

[0013] Fig. Figure 1 further illustrates reference cross-sections used in subsequent figures. Cross-section AA' lies along a longitudinal axis of a gate electrode 102 and in a direction perpendicular, for example, to the direction of current flow between the epitaxial source / drain regions 93 of a nanoFET. Cross-section BB' runs parallel to cross-section AA' and extends through the epitaxial source / drain regions 93 of several nanoFETs. Cross-section CC' runs perpendicular to cross-section AA' and parallel to a longitudinal axis of a fin 66 of the nanoFET and, for example, in a direction of current flow between the epitaxial source / drain regions 93 of the nanoFET. The following figures refer to these reference cross-sections for clarification.

[0014] Some of the embodiments discussed in this text are discussed in the context of nanoFETs fabricated using a gate-load process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs).

[0015] Fig. Figures 2 to 21D are cross-sectional views of intermediate stages in the front-side fabrication of nano-FETs according to some embodiments. Fig. 2 to 5, 6A, 7A, 8A, 9A, 104, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A and 21A illustrate the in Fig. 1 illustrated reference cross-section A-A'. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 12D, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B and Fig. 21B illustrates the in Fig. 1 illustrated reference cross-section B-B'. Fig. 77C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 11D, Fig. 12C, Fig. 12E, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C and Fig. 21D illustrate the in Fig. 1 illustrated reference cross-section C-C'.

[0016] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is placed on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon, germanium, a composite semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide or combinations thereof.

[0017] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-devices, such as NMOS transistors, for example, n-nanoFETs, and the p-region 50P can be used to form p-devices, such as PMOS transistors, for example, p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (as illustrated by the divider 20), and any number of device features (for example, other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although a single n-region 50N and a single p-region 50P are illustrated, any number of n-regions 50N and p-regions 50P can be provided.

[0018] Furthermore, in Fig. 2 A multilayer stack 64 is formed on top of the substrate 50. The multilayer stack 64 has alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layers 51 are removed, and the second semiconductor layers 53 are structured to form channel regions of nano-FETs in the n-region 50N and the p-region 50P. However, in some embodiments the first semiconductor layers 51 can be removed, and the second semiconductor layers 53 can be structured to form channel regions of nano-FETs in the n-region 50N, and the second semiconductor layers 53 can be removed, and the first semiconductor layers 51 can be structured to form channel regions of nano-FETs in the p-region 50P.In some embodiments, the second semiconductor layers 53 can be removed, and the first semiconductor layers 51 can be structured to form channel regions of nanoFETs in the n-region 50N. In other embodiments, the first semiconductor layers 51 can be removed, and the second semiconductor layers 53 can be structured to form channel regions of nanoFETs in the p-region 50P. In some embodiments, the second semiconductor layers 53 can be removed, and the first semiconductor layers 51 can be structured to form channel regions of nanoFETs in both the n-region 50N and the p-region 50P. In such embodiments, the channel regions in both the n-region 50N and the p-region 50P can have the same material composition (for example, silicon or the like) and can be formed simultaneously.

[0019] For illustrative purposes, the multilayer stack 64 is shown to contain three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 can have any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 can be epitaxially grown by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.In various embodiments, the first semiconductor layers 51 can be formed from a first semiconductor material suitable for p-nanoFETs, such as silicon-germanium or the like, and the second semiconductor layers 53 can be formed from a second semiconductor material suitable for n-nanoFETs, such as silicon, silicon-carbon, or the like. For illustrative purposes, the multilayer stack 64 is shown with a bottom semiconductor layer suitable for p-nanoFETs. In some embodiments, the multilayer stack 64 can be formed such that the bottom layer is a semiconductor layer suitable for n-nanoFETs.

[0020] The first and second semiconductor materials can be materials that exhibit high etch selectivity relative to each other. Therefore, the first semiconductor layers 51 of the first semiconductor material can be removed without substantially removing the second semiconductor layers 53 of the second semiconductor material, thus enabling the structuring of the second semiconductor layers 53 to form channel regions of nano-FETs. Similarly, in embodiments where the second semiconductor layers 53 are removed and the first semiconductor layers 51 are structured for the purpose of forming channel regions, the second semiconductor layers 53 of the second semiconductor material can be removed without substantially removing the first semiconductor layers 51 of the first semiconductor material, thus enabling the structuring of the first semiconductor layers 51 for the purpose of forming channel regions of nano-FETs.

[0021] We now turn Fig. 3, where, according to some embodiments, fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 in the multilayer stack 64 and in the substrate 50, respectively, can be formed by etching trenches in the multilayer stack 64 and in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The formation of the nanostructures 55 by etching the multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as the first nanostructures 52) from the first semiconductor layers 51 and define second nanostructures 54A-54C (collectively referred to as the second nanostructures 54) from the second semiconductor layers 53.The first nanostructures 52 and the second nanostructures 54 can be referred to together as nanostructures 55.

[0022] The fins 66 and the nanostructures 55 can be structured by any suitable method. For example, the fins 66 and the nanostructures 55 can be structured by one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, spacings smaller than those obtainable by a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins 66.

[0023] Fig. Figure 3 illustrates, for illustrative purposes, that the fins 66 in the n-region 50N and the p-region 50P are essentially the same width. In some embodiments, the widths of the fins 66 in the n-region 50N may be greater or lesser than those of the fins 66 in the p-region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is illustrated to have a uniform width throughout, in other embodiments the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously towards the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal.

[0024] In Fig. 4. Shallow trench insulation regions (STI regions) 68 are formed adjacent to the fins 66. The STI regions 68 can be formed by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, as well as between adjacent fins 66. The insulating material can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be formed by high-density plasma deposition (HDP-CVD), flowable liquid deposition (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon dioxide formed by an FCVD process. An annealing process can be performed once the insulating material has been formed.In one embodiment, the insulating material is configured such that excess insulating material covers the nanostructures 55. Although the insulating material is illustrated as a single layer, some embodiments can also use multiple layers. For example, in some embodiments, a lining (not illustrated separately) can first be formed along a surface of the substrate 50, the fins 66, and the nanostructures 55. Subsequently, a filler material, such as those discussed above, can be formed over the lining.

[0025] A erosion process is then applied to the insulation material to remove excess insulation material covering the nanostructures 55. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 such that the top surfaces of the nanostructures 55 and the insulation material are flush after completion of the planarization process.

[0026] The insulating material is then recessed to form the STI regions 68. The insulating material is recessed such that upper portions of the fins 66 protrude between adjacent STI regions 68 in the n-region 50N and in the p-region 50P. Furthermore, the top surfaces of the STI regions 68 can have a flat surface, as illustrated, a convex surface, a concave surface (e.g., cup-shaped), or a combination thereof. The top surfaces of the STI regions 68 can be shaped flat, convex, and / or concave by suitable etching. The STI regions 68 can be recessed using an acceptable etching process, such as one that is selective for the insulating material (e.g., one that etches the insulating material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, oxide removal can be achieved using dilute hydrofluoric acid (dHF).

[0027] The above with reference to the Fig. The process described in sections 2 to 4 is only one example of how the fins 55 and the nanostructures 55 can be formed. In some embodiments, the fins 66 and / or the nanostructures 55 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures can comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby avoiding prior and subsequent implantations, although in-situ and implantation doping can also be used together.

[0028] Additionally, the first semiconductor layers 51 (and resulting first nanostructures 52) and the second semiconductor layers 53 (and resulting second nanostructures 54) are illustrated and discussed in this text – for illustrative purposes only – as comprising the same materials in the p-region 50P and the n-region 50N. Therefore, in some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be made of different materials or be arranged in a different order in the p-region 50P and the n-region 50N.

[0029] Furthermore, in Fig. Four suitable depressions (not shown separately) are formed in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different depression types, various implantation steps for the n-region 50N and the p-region 50P can be implemented using a photoresist or other masks (not shown separately). For example, a photoresist can be formed over the fins 66 and the STI regions 68 in the n-region 50N and the p-region 50P. The photoresist is structured such that the p-region 50P is exposed. The photoresist can be formed using a spin-depositing technique and can be structured using suitable photolithography techniques. Once the photoresist is structured, an implantation of n-perturbation atoms is performed in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-perturbation atoms from being implanted into the n-region 50N.The n-interfering atoms can be phosphorus, arsenic, antimony, or the like, which are introduced into the region at a concentration in the range of about 10. 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3 The photoresist is implanted. After implantation, it is removed, for example by an acceptable asching process.

[0030] Prior to or following the implantation of the p-region 50P, a photoresist or other masks (not shown separately) are formed over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and the n-region 50N. The photoresist is structured to leave the n-region 50N exposed. The photoresist can be formed using a spin-casting technique and can be structured using suitable photolithography techniques. Once the photoresist is structured, p-interfering atoms can be implanted into the n-region 50N, and the photoresist can act as a mask to essentially prevent the implantation of p-interfering atoms into the p-region 50P. The p-interfering atoms can be boron, boron fluoride, indium, or the like, introduced into the region to a concentration in the range of approximately 10¹³ atoms / cm². 3 up to about 1014 atoms / cm³ 3It can be implanted. After implantation, the photoresist can be removed, for example through an acceptable asching process.

[0031] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair implantation damage and activate the implanted p- and / or n-interfering atoms. In some embodiments, the grown materials can be doped in situ by epitaxial fins during growth, which can eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0032] In Fig. A dielectric dummy layer 70 is formed on the fins 66 and / or the nanostructures 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and then planarized, for example, by a CMP. The mask layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 72 can be made from other materials exhibiting high etch selectivity from etching insulating regions. The mask layer 74, for example, can contain silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-region 50N and the p-region 50P, respectively. It should be noted that the dummy dielectric layer 70 is shown for illustrative purposes only, covering just the fins 66 and the nanostructures 55.In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI regions 68 such that the dielectric dummy layer 70 extends between the dummy gate layer 72 and the STI regions 68.

[0033] Fig. Figures 6A to 21C illustrate various additional steps in the manufacture of devices of the embodiments. Fig. 6A to 21C illustrate features in one of the n-regions (50N) and the p-region (50P). In the Fig. 6A to 6C can use mask layer 74 (see Fig. 5) are structured using acceptable photolithography and etching techniques to form masks 78. The structure of the masks 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The structure of the masks 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 66.

[0034] In the Fig. 7A to 7C have a first spacer layer 80 and a second spacer layer 82 applied over the in the Fig. Structures illustrated in Figures 6A to 6C are formed. The first spacer layer 80 and the second spacer layer 82 are then structured to serve as spacers for forming self-adjusting source / drain regions. In the Fig. In steps 7A to 7C, the first spacer layer 80 is formed on the top surfaces of the STI regions 68, on the top surfaces and side walls of the fins 66, the nanostructures 55, and the masks 78, as well as on the side walls of the dummy gates 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposition by CVD, ALD, or the like. The second spacer layer 82 can be formed from a material with a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and can be deposited by CVD, ALD, or the like.

[0035] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantations for weakly doped source / drain regions (LDD regions) (not illustrated separately) can be performed. In embodiments with different device types, similar to those shown above in Fig. Following the implantation procedure discussed above, a mask, such as a photoresist, can be formed over the n-region 50N while the p-region 50P remains exposed, and interfering atoms of a suitable type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-region 50P. The mask can then be removed. The n-type interfering atoms can be any of the previously discussed n-type interfering atoms, and the p-type interfering atoms can be any of the previously discussed p-type interfering atoms. The weakly doped source / drain regions can have a concentration of impurity atoms in a range of about 1x10' % atoms / cm² 3up to about 1×10 19 atoms / cm² 3 exhibiting [unclear]. Tempering can be used to repair implantation damage and to activate the implanted disruptive atoms.

[0036] In the Fig. In steps 8A to 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and second spacer 83. As discussed in more detail below, the first spacer 81 and the second spacer 83 serve to align subsequently formed source / drain regions and to protect the sidewalls of the fins 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and such that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 can be etched using an anisotropic etching process in which the first spacer layer 80 acts as an etch stop layer, with remaining sections of the second spacer layer 82 forming second spacer layers 83, as shown in [reference]. Fig. Figure 8B illustrates this. The second spacers 83 then act as a mask, while exposed sections of the first spacer layer 80 are etched, forming first spacers 81, as shown in the Fig. 8B and Fig. 8C illustrates.

[0037] As in Fig. As illustrated in Figure 8B, the first spacers 81 and the second spacers 83 are arranged on side walls of the fins 66 and / or nanostructures 55. Fig. As illustrated in Figure 8C, in some embodiments the second spacer layer 82 above the first spacer layer 80 can be removed next to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71, and the first spacers 81 are arranged on side walls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 60. In other embodiments, a portion of the second spacer layer 82 above the first spacer layer 80 next to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can remain.

[0038] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can also be used. For example, fewer or additional spacers can be used, a different sequence of steps can be employed (for example, the first spacers 81 can be structured before the deposition of the second spacer layer 82), additional spacers can be formed and removed, and / or the like. Furthermore, the n- and p-devices can be formed using other structures and steps.

[0039] In the Fig. In some embodiments, 9A to 9C, first recesses 86 and second recesses 87 are formed in the fins 66, the nanostructures 55, and the substrate 50. Epitaxial source / drain regions are subsequently formed in the first recesses 86 and the second recess 87, and epitaxial materials and epitaxial source / drain regions are subsequently formed in the second recesses 87. The first recesses 86 and the second recesses 87 can extend through the first nanostructures 52 and the second nanostructures 54 and into underlying fins 66 of the substrate 50. As in Fig. As illustrated in Figure 9B, the upper surfaces of the STI regions 58 can be higher than the lower surfaces of the first recesses 86. In various embodiments, the fins 66 can be etched such that the lower surfaces of the first recesses 86 are at the same level as the upper surfaces of the STI regions 68, or the like. The lower surfaces of the second recesses 87 can be positioned below the lower surfaces of the first recesses 86 and the upper surfaces of the STI regions 68.

[0040] The first recesses 86 and the second recesses 87 can be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask sections of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to form the first recesses 86 and the second recesses 87. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55 and / or the fins 66. Timed etching processes can be used to stop the etching after the first recesses 86 and the second recesses 87 have reached the desired depths.The second recesses 87 can be etched using the same processes as those used to etch the first recesses 86, as well as with an additional etching process before or after etching the first recesses 86. In some embodiments, regions corresponding to the first recesses 86 can be masked while the additional etching process for the second recesses 87 is performed.

[0041] In the Fig. In steps 10A to 10C, sections of the sidewalls of the layers of the multilayer stack 64, formed from the first semiconductor materials (for example, the first nanostructures 52) exposed by the first recesses 86 and the second recesses 87, are etched to form sidewall recesses 88. Although sidewalls of the first nanostructures 52 are located next to the sidewall recesses 88 in Fig. While the sidewalls are illustrated as straight lines, they can also be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching or the like. In an embodiment where the first nanostructures 52 contain, for example, SiGe and the second nanostructures 54 contain, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructures 52.

[0042] In the Fig. At 11A to 11D, the first inner spacers 89 are formed in the side wall recess 88. The first inner spacers 89 can be formed by depositing an inner spacer layer (not shown separately) over the area in the Fig. The structures illustrated in Figures 10A to 10C are formed. The first internal spacers 89 act as insulating features between subsequently formed source / drain regions and a gate structure. As will be discussed in more detail below, source / drain regions and epitaxial materials are formed in the first recesses 86 and the second recesses 87, while the first nanostructures 52 are replaced by corresponding gate structures.

[0043] The inner spacer layer can be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer can comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (low k-value) with a k-value of less than approximately 3.5, can be used. The inner spacer layer can then be anisotropically etched to form the first inner spacers 89. Although the outer sidewalls of the first inner spacers 89 are illustrated as being flush with the sidewalls of the second nanostructures 54, the outer sidewalls of the first inner spacers 89 can extend beyond or be indented from the sidewalls of the second nanostructures 54A-54C.

[0044] Furthermore, the outer side walls of the first inner spacers 89 are indeed in Fig. Figure 11C is illustrated as straight, but the outer side walls of the first inner spacers 89 can also be concave or convex. As an example, it is illustrated... Fig. Figure 11D is an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 89 are concave, and the first inner spacers 89 are indented from the sidewalls of the second nanostructures 54. The inner spacer layer can be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers 89 can be used to prevent damage to subsequently formed source / drain regions (such as the epitaxial source / drain regions 93, which are described below with respect to the Fig. (discussed in sections 12A to 12E) to prevent subsequent etching processes, such as etching processes to form gate structures.

[0045] In the Fig. In 12A to 12D, first epitaxial materials 91 are formed in the second recesses 87, second epitaxial materials 89 are formed in the first recesses 86 and are formed over the first epitaxial materials 91 in the second recesses 87, and epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87 over the second epitaxial materials 89. In some embodiments, the first epitaxial materials 91 can be sacrificial materials that are subsequently removed to form backside vias (such as the backside vias 170 shown below in relation to the Fig. 27A to 27C will be discussed). As in the Fig. As illustrated in Figures 12B to 12C, the top surfaces of the first epitaxial materials 91 can be at the same level as the bottom surfaces of the first recesses 86. However, in some embodiments, the top surfaces of the first epitaxial materials 91 can also be arranged below or above the bottom surfaces of the first recesses 86. The first epitaxial materials 91 can be epitaxially grown in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial materials 91 can comprise any acceptable material, such as silicon germanium or the like.The first epitaxial materials 91 can be formed from materials with high etch selectivity relative to the materials of the epitaxial source / drain regions 92, the substrate 50, and the dielectric layers (such as the STI regions 68 and the second dielectric layers 125). Therefore, the first epitaxial materials 91 can be removed and replaced by the backside vias without substantially removing the epitaxial source / drain regions 92 and the dielectric layers.

[0046] The second epitaxial materials 89 are then formed in the first recesses 86 and in the second recesses 87 over the first epitaxial materials 91. In some embodiments, sections of the second epitaxial materials 89 in the first epitaxial materials 91 can be sacrificial materials that are subsequently removed to form backside vias (such as the backside vias 130 shown below in relation to the Fig. 30A to 30C). Other sections of the second epitaxial materials 89 (which are formed, for example, in the first recesses 86) can be used as a mask to protect the third epitaxial materials 89 during subsequent etching steps to remove sections of the substrate 50 and the first epitaxial materials 91. As discussed in the Fig. As illustrated in Figures 12B to 12C, the top surfaces of the second epitaxial materials 89 can be at the same level as the top surfaces of the STI regions 68. However, in some embodiments, the top surfaces of the second epitaxial materials 89 can be located below or above the top surfaces of the STI regions 68. The second epitaxial materials 89 can be epitaxially grown in the first recesses 86 and in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The second epitaxial materials 89 can contain any acceptable material, such as silicon germanium or the like.In some embodiments, the second epitaxial materials 89 can be similar materials to the first epitaxial materials 91 (for example, silicon-germanium); however, the germanium concentration in the second epitaxial materials 89 can differ from the germanium concentration in the first epitaxial materials 91. As a result, the first epitaxial materials 91 can be selectively etched without significantly etching the second epitaxial materials 89. The second epitaxial materials 89 can be formed from materials with high etch selectivity relative to the materials of the epitaxial source / drain regions 92, the substrate 50, and the dielectric layers (such as the STI regions 68 and the dielectric layer 162, as discussed below).Therefore, the second epitaxial materials 89 can be removed and replaced by the backside vias without substantially removing the epitaxial source / drain regions 92 and the dielectric layers.

[0047] The epitaxial source / drain regions 92 are then formed over the second epitaxial materials 89 in the first recesses 86 and in the second recesses 87. In some embodiments, the epitaxial source / drain regions 92 can exert a strain on the second nanostructures 54, thereby improving performance. As shown in Fig. As illustrated in Figure 12C, the epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87 such that each dummy gate 76 is arranged between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by a suitable lateral distance, so that the epitaxial source / drain regions 92 are not short-circuited with the subsequently formed gates of the resulting nano-FETs.

[0048] The epitaxial source / drain regions 92 in the n-region 50N, for example the NMOS region, can be formed by masking the p-region 50P, for example the PMOS region. Then, the epitaxial source / drain regions 92 are grown epitaxially in the first recesses 86, and the second recesses 87 are grown epitaxially in the n-region 50N. The epitaxial source / drain regions 92 can contain any acceptable material suitable for n-nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 can contain materials that exert a tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces that are raised from the respective top surfaces of the nanostructures 55 and may have facets.

[0049] The epitaxial source / drain regions 92 in the p-region 50P, for example the PMOS region, can be formed by masking the n-region 50N, for example the NMOS region. Then, the epitaxial source / drain regions 92 are grown epitaxially in the first recesses 86, and the second recesses 87 are grown epitaxially in the p-region 50P. The epitaxial source / drain regions 92 can contain any acceptable material suitable for p-nanoFETs. For example, if the first nanostructures 52 are silicon-germanium, the epitaxial source / drain regions 92 can comprise materials that exert a compressive stress on the first nanostructures 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have surfaces that are raised from the respective surfaces of the multilayer stack 56 and may have facets.

[0050] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 can be implanted with dopants to form source / drain regions, similar to the process previously discussed for the formation of lightly doped source / drain regions, followed by annealing. The source / drain regions can contain an impurity atom concentration of approximately 1 × 10 19 atoms / cm² 3 and about 1×10 21 atoms / cm² 3 exhibit. The n-type and / or p-type interfering atoms for source / drain regions can be any of the previously discussed interfering atoms. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0051] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the n-region 50N and the p-region 50P, the top surfaces of the epitaxial source / drain regions 92 exhibit facets that extend laterally outward beyond the side walls of the nanostructures 55. In some embodiments, adjacent source / drain regions 92 remain separated after the epitaxial process is complete, as described by Fig. 12B illustrates this. In the Fig. In the embodiments illustrated in Figure 12B, first spacers 81 can be formed to a top surface of the STI regions 68, thereby blocking epitaxial growth. In some other embodiments, the first spacers 81 can cover sections of sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacers 81 can be adjusted to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 68. In other embodiments, the extension of the epitaxial source / drain regions 92 can cause adjacent epitaxial source / drain regions 92 to merge, as described in the embodiment of Fig. Illustrated in 12D.

[0052] The epitaxial source / drain regions 92 can comprise one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C can be formed from different semiconductor materials and can be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 92A can have a doping concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer 92A can be deposited, the second semiconductor material layer 92B can be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C can be deposited over the second semiconductor material layer 92B.

[0053] In the Fig. 13A to 13C a first interlayer dielectric (ILD) 96 is applied over the layer in the Fig. The structure illustrated in Figures 12A to 12D is deposited. The first ILD 96 can be formed from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can also be used. In some embodiments, a contact etch stop layer (CESL) 94 is arranged between the first ILD 96 and the epitaxial source / drain regions 93, the mask 78, and the first spacers 81.The CESL 94 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride or the like, which has a lower etch rate than the material of the overlying first ILD 96.

[0054] In the Fig. In embodiments 14A to 14C, a planarization process, such as a CMP, can be performed to make the top surface of the first ILD 96 flush with the top surfaces of the dummy gates 76 or the masks 78. The planarization process can also remove the masks 78 on the dummy gates 76 and sections of the first spacers 81 along the side walls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are flush within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 may remain; in this case, the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the masks 78 and the first spacers 81.

[0055] In the Fig. In steps 15A to 15C, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps, resulting in third recesses 98. Sections of the dummy gate dielectrics 60 in the third recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gates 76 at a faster rate than the first ILD 96 or the first spacers 81. Each of the third recesses 98 exposes and / or overlays sections of the nanostructures 55, which function as channel regions in subsequently completed nanoFETs. Sections of the nanostructures 55, which serve as the channel regions, are arranged between adjacent pairs of the epitaxial source / drain regions 93.During removal, the dummy gate dielectrics 60 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 60 can then be removed after the dummy gates 76 have been removed.

[0056] In the Fig. In 16A to 16C, the first nanostructures 52 are removed, thereby extending the third recesses 98. The first nanostructures 52 can be removed by performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 58 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 contain, for example, SiGe and the second nanostructures 54A-54C contain, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructures 52.

[0057] In the Fig. At 17A to 17C, the gate dielectric layers 100 and gate electrodes 102 are formed as replacement gates. The gate dielectric layers 100 are conformally deposited in the third recesses 98. The gate dielectric layers 100 can be formed on the top and side walls of the substrate 50 and on the top, side walls, and bottom surfaces of the second nanostructures 54. The gate dielectric layers 100 can also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI regions 68, as well as on the side walls of the first spacers 81 and the first inner spacers 89.

[0058] According to some embodiments, the gate dielectric layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, or the like, or combinations thereof. In some embodiments, the gate dielectrics may, for example, comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 contain a dielectric material with a high k-value, and in these embodiments, the gate dielectric layers 100 may have a k-value greater than approximately 7.0 and may contain a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-region 50N and the p-region 50P.The formation processes of the gate dielectric layers 100 can include molecular beam deposition (MBD), ALD, PECVD and the like.

[0059] The gate electrodes 102 are deposited over the gate dielectric layers 100 and fill the remaining sections of the third recesses 98. The gate electrodes 102 can contain a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although, for example, in the Fig. 17A and Fig. As illustrated in Figure 17C, single-layer gate electrodes 102 can comprise any number of lining layers, any number of work function tuning layers, and a filler material. Any combination of the layers comprising the gate electrodes 102 can be deposited in the n-region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and in the p-region 50P between adjacent first nanostructures 52.

[0060] The formation of the gate dielectric layers 100 in the n-region 50N and in the p-region 50P can occur simultaneously, so that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 can also occur simultaneously, so that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region can be formed by separate processes, so that the gate dielectric layers 100 can be made of different materials and / or have a different number of layers, and / or the gate electrodes 102 in each region can be formed by separate processes, so that the gate electrodes 102 can be made of different materials and / or have a different number of layers.Different masking steps can be used to mask and expose appropriate regions when using standalone processes.

[0061] After filling the third recess 98, a planarization process, such as CMP, can be performed to remove the excess sections of the gate dielectric layers 100 and the material of the gate electrodes 102, with these excess sections lying above the top surface of the first ILD 96. The remaining material sections of the gate electrodes 102 and the gate dielectric layers 100 thus form substitute gate structures of the resulting nanoFETs. The gate electrodes 102 and the gate dielectric layers 100 can be collectively referred to as the “gate structures”.

[0062] In the Fig. In 18A to 18C, the gate structures (which include the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) are recessed such that recesses are formed directly above the gate structures and between opposing sections of the first spacers 81. Gate masks 104, comprising one or more layers of dielectric material, such as SiO₂, HfSi, SiOC₂, AlO₂, ZrSi, AlON₂, ZrO₂, HfO₂, TiO₂, ZrAlO₂, ZnO₂, TaO₂, LaO₂, YO₂, TaCN, SiN₂, SiOCN₂, Si, SiOCN₂, ZrN₂, SiCN₂, combinations thereof, or the like, are filled into the recesses, followed by a planarization process to remove excess sections of material extending over the first ILD 96. Subsequently formed gate contacts (such as the gate contacts 114 shown below with respect to the Fig. (discussed in sections 20A to 20C) penetrate the gate masks 104 to contact the top surfaces of the recessed gate electrodes 102. In some embodiments, the thickness of the gate masks 104 (for example, measured between the top and bottom surfaces) can be 50 nm or less, and the width of the gate masks 104 (for example, measured between opposite side walls) can be in a range of about 5 nm to about 30 nm. In other embodiments, the gate masks 104 can have different dimensions.

[0063] As through the Fig. As further illustrated in Figures 18A to 18C, a second ILD 106 is deposited over the first ILD 96 and over the gate masks 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In other embodiments, the second ILD 106 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0064] In the Fig. In processes 19A to 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to create fourth recesses 108 that expose the surfaces of the epitaxial source / drain regions 93 and / or the gate structures. The fourth recesses 108 can be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the fourth recesses 108 can be etched through the second ILD 106 and the first ILD 96 by a first etching process; they can be etched through the gate masks 104 by a second etching process; and they can then be etched through the CESL 94 by a third etching process. A mask, such as a photoresist, can be formed and structured over the second ILD 106 to mask sections of the second ILD 106 against the first etching process and the second etching process.In some embodiments, the etching process can over-etch, which is why the fourth recesses 108 can extend into the epitaxial source / drain regions 93 and / or the gate structures, and the bottom of the fourth recesses 108 can be flush (for example, at the same level as, or at the same distance from, the substrate 50) with the epitaxial source / drain regions 93 and / or the gate structures, or it can be lower (for example, closer to the substrate 50) than the epitaxial source / drain regions 93 and / or the gate structures. Although... Fig. 19C the fourth recesses 108 illustrated such that the epitaxial source / drain regions 93 and the gate structures are exposed in the same cross-section, in different embodiments the epitaxial source / drain regions 93 and the gate structures can be exposed in different cross-sections, thereby reducing the risk of a short circuit of subsequently formed contacts.

[0065] After the fourth recesses 108 have been formed, the first silicide regions 110 are formed over the epitaxial source / drain regions 93. In some embodiments, the first silicide regions 110 are formed by first depositing a metal (not shown separately) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 93 (for example, silicon, silicon-germanium, germanium) for the purpose of forming silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare-earth metals, or their alloys, over the exposed portions of the epitaxial source / drain regions 93, and then performing a thermal tempering process to form the first silicide regions 110. The unreacted portions of the deposited metal are then removed, for example, by an etching process.Although the first silicide regions 110 are referred to as silicide regions, they can also be germanide regions or silicon germanide regions (for example, regions comprising both silicide and germanide). In one embodiment, the first silicide regions 110 comprise TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or the like in the n-region 50N, and the first silicide regions 110 comprise NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or the like in the p-region 50P. In some embodiments, the first silicide regions 110 have a thickness in the range of about 1 nm to about 10 nm.

[0066] In the Fig. In embodiments 20A to 20C, the source / drain contacts 112 and the gate contacts 114 (also referred to as contact plugs) are formed in the fourth recess 108. The source / drain contacts 112 and the gate contacts 114 can each comprise one or more layers, such as barrier layers, diffusion layers, and filler materials. In some embodiments, for example, the source / drain contacts 112 and the gate contacts 114 each contain a barrier layer and a conductive material and are each electrically coupled to an underlying conductive feature (for example, a gate electrode 102 and / or a first silicide region 110). The gate contacts 114 are electrically coupled to the gate electrodes 102, and the source / drain contacts 112 are electrically coupled to the first silicide regions 110. The barrier layer may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like.The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, ruthenium, aluminum, nickel, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from surfaces of the second ILD 106. The epitaxial source / drain regions 93, the second nanostructures 54, and the gate structures (which include the gate dielectric layers 100 and the gate electrodes 102) can collectively be referred to as a transistor structure. The transistor structures can be formed in a device layer 115, with a first interconnect structure (such as the front interconnect structure 120, shown below with respect to the Fig. 21A to 21C) is formed across its front side and a second interconnect structure (such as the rear interconnect structure 136, which is discussed below in relation to the Fig. (discussed in sections 28A to 28C) is formed on the back side. Although the device layer 115 is described as being equipped with nano-FETs, other embodiments may have a device layer 115 with different types of transistors (for example, planar FETs, FinFETs, thin-film transistors (TFTs), or the like).

[0067] Although the Fig. To illustrate a source / drain contact 112 extending to each of the epitaxial source / drain regions 92, as shown in Figures 20A to 20C, the source / drain contacts 112 of certain epitaxial source / drain regions 92 (referred to as source / drain regions 92') can be omitted. The source / drain regions 92' can correspond to source / drain regions formed directly above the first epitaxial regions 91. For example, as explained in more detail below, conductive features (such as backside vias or busbars) can be subsequently added through the backside of one or more of the epitaxial source / drain regions 92.For these special epitaxial source / drain regions 92, the source / drain contacts 112 can be omitted or replaced by dummy contacts that are not electrically connected to overlying conductors (such as the first conductive features 122 shown below in relation to the . Fig. 22A to 22C will be discussed).

[0068] Fig. 20D illustrates a cross-sectional view along cross-section CC' of Fig. 1 of a device according to some other embodiments. The embodiment of Fig. 20D may resemble the embodiments described above in relation to the Fig. Sections 20A to 20C were described, where the same reference numbers denote the same elements that were formed using the same processes. Fig. In 20D, the source / drain contacts 112 can have a composite structure and can each contain a first contact 112A in the first ILD 96 and a second contact 112B in the second ILD 106. In various embodiments, the first contacts 112A in the first ILD 96 can be formed before the second ILD 106 is deposited, and the first contacts 112A can be recessed from a top surface of the first ILD 96. After the first contacts 112A have been recessed, insulating masks 117 can be deposited to cover the first contacts 112A. The first contacts 112A can comprise W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, combinations thereof, or the like, and can have a thickness (measured, for example, between opposing sidewalls) in a range of about 1 nm to about 50 nm.The insulating masks 117 can comprise SiO₂, HfSi, SiOC₂, AlO₂, ZrSi, AlON, ZrO₂, HfO₂, TiO₂, ZrAlO₂, ZnO₂, TaO₂, LaO₂, YO₂, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, combinations thereof, or the like. In some embodiments, the material of the insulating masks 117 can differ from the material of the gate masks 104, such that the insulating mask 117 and the gate masks 104 can be selectively etched to each other. In this way, the second contacts 112B and the gate contacts 114 can be formed independently of each other.

[0069] The second ILD 106 is then deposited over the insulating masks 117 and the first contacts 112A as described above. After the deposition of the second ILD 106, second contacts 112B can be formed such that they extend through the second ILD 106, through the insulating masks 117, and are electrically connected to the first contacts 112A. The second contacts 112B can further extend partially into and be embedded within the first contacts 112A. The second contacts 112B can comprise W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, combinations thereof, or the like, and can have a thickness (measured, for example, between opposing sidewalls) in the range of about 1 nm to about 50 nm.The thickness of the second contacts 112B can be the same as, or different from, the thickness of the first contacts 112A, and the material of the second contacts 112B can be the same as, or different from, the material of the first contacts 112A. In this way, composite source / drain contacts 112 can be formed, comprising the first contacts 112A and the second contacts 112B. The following process steps are provided for easier illustration regarding the embodiment of the [component / design]. Fig. described in sections 20A to 20C, but it is understood that they also apply to the embodiment of the Fig. 20D are applicable. In other embodiments, other configurations of the source / drain contact 112 are also possible.

[0070] The Fig. Figures 21A to 29C illustrate intermediate steps in the formation of front-side and back-side interconnect structures on the device layer 115. The front-side and back-side interconnect structures can each include conductive features that are electrically connected to the nano-FETs formed on the substrate 50. Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A and Fig. 29A illustrates the in Fig. 1 illustrated reference cross-section A-A'. Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B and Fig. 29B illustrate the in Fig. 1 illustrated reference cross-section B-B'. Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25°C, Fig. 26C, Fig. 27C, Fig. 28C and Fig. 29C illustrate the in Fig. 1 illustrated reference cross-section C-C'. The in the Fig. The process steps described in sections 21A to 29C can be applied to one or both of the n-region 50N and the p-region 50P. As mentioned above, a backside conductive feature (for example, a backside via) can be connected to one or more of the epitaxial source / drain regions 92'. Therefore, the source / drain contacts 112 can optionally be omitted from the epitaxial source / drain regions 92'.

[0071] In the Fig.At 21A to 21C, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 can be described as a front-side interconnect structure because it is formed on a front side of the device layer 115 (for example, a side of the device layer 115 where the gate electrodes 102 are located).

[0072] The front-side interconnect structure 120 can comprise one or more layers with first conductive features 122, formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 can comprise a dielectric material, such as a low k-value dielectric material, an extra-low k-value (ELK) dielectric material, or the like. The first dielectric layers 124 can be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, or the like.

[0073] The first conductive features 122 can include conductors and conductive vias that connect the conductor layers. The conductive vias can extend through each of the first dielectric layers 124 to create vertical connections between conductor layers. The first conductive features 122 can be formed by any acceptable process, such as a damascus process, a dual damascus process, or the like.

[0074] In some embodiments, the first conductive features 122 can be formed using a damascening process in which a first dielectric layer 124 is structured using a combination of photolithography and etching techniques to form trenches corresponding to the desired structure of the first conductive features 122. An optional diffusion barrier and / or adhesive layer can be deposited, and the trenches can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like.In one embodiment, the first conductive features 122 can be formed by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. A chemical-mechanical planarization (CMP) process or the like can be used to remove excess conductive material from a surface of the respective first dielectric layer 124 and to planarize the surfaces of the first dielectric layer 124 and the first conductive features 122 for subsequent processing.

[0075] The Fig. Figures 21A to 21C illustrate five layers of the first conductive features 122 and the first dielectric layers 124 in the front interconnect structure 120. It should be noted, however, that the front interconnect structure 120 can have any number of first conductive features 122 arranged in any number of first dielectric layers 124. The front interconnect structure 120 can be electrically connected to the gate contacts 114 and the source / drain contacts 112 to form functional circuits. In some embodiments, the functional circuits formed by the front interconnect structure 120 may include logic circuits, memory circuits, image sensor circuits, or the like.

[0076] In the Fig. In steps 22A to 22C, a support substrate 150 is bonded to a top surface of the front interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as a bonding layer 152). The support substrate 150 can be a glass support substrate, a ceramic support substrate, a wafer (for example, a silicon wafer), or the like. The support substrate 150 can provide structural support during subsequent processing steps and in the finished device.

[0077] In various embodiments, the support substrate 150 can be bonded to the front interconnect structure 120 using a suitable technique, such as dielectric-to-dielectric bonding or the like. The dielectric-to-dielectric bonding can include the deposition of the first bonding layer 152A on the front interconnect structure 120. In some embodiments, the first bonding layer 152A comprises silicon oxide (for example, a high-density plasma oxide (HDP oxide) or the like) deposited by CVD, ALD, PVD, or the like. The second bonding layer 152B can likewise be an oxide layer formed on a surface of the support substrate 150 prior to bonding, for example, by CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can also be used for the first bonding layer 152A and the second bonding layer 152B.

[0078] The dielectric-to-dielectric bonding process can further include the application of a surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (for example, rinsing with deionized water or the like) that can be applied to one or more of the bonding layers 152. The support substrate 150 is then aligned with the front interconnect structure 120, and the two are pressed together to initiate pre-bonding of the support substrate 150 to the front interconnect structure 120. The pre-bonding can be performed at room temperature (for example, between approximately 21°C and approximately 25°C).After pre-bonding, a tempering process can be applied by, for example, heating the front interconnect structure 120 and the support substrate 150 to a temperature of about 170°C to about 500°C.

[0079] Furthermore, in the Fig. 22A to 22C, the device, after the support substrate 150 has been bonded to the front interconnect structure 120, is rotated so that a back side of the transistor structures 109 faces upwards. The back side of the transistor structures 109 can refer to a side opposite the front side of the device layer 105, on which gate electrodes 102 of the active devices are formed.

[0080] A thinning process can then be applied to the back side of the substrate 50. The thinning process can include a planarization process (for example, mechanical grinding, CMP, or the like), a back-etching process, or a combination thereof. In some embodiments, the thinning process includes a combination of planarization to remove a large portion of the substrate 50, followed by a back-etching process to further recess the substrate 50. The thinning process can expose surfaces of the first epitaxial material 91 opposite the front-side interconnect structure 120. For example, the thinning process can back-etch the substrate 50 and the STI regions 68 below the top surfaces of the first epitaxial regions 91. In some embodiments, the back-etching process can be a plasma etching process using O2, Cl2, HCl, HBr, combinations thereof, or the like to etch the substrate 60.Furthermore, the etching process can include an etchant flow rate in the range of approximately 5 sccm to approximately 100 sccm, a chamber pressure in the range of approximately 0.133322 Pa (1 mTorr) to approximately 13.3322 Pa (100 mTorr), and a bias voltage in the range of approximately 300 V to approximately 1000 V. Other embodiments may employ different etching conditions.

[0081] Furthermore, a portion of the substrate 50 remains over the epitaxial source / drain regions 92 (including the epitaxial source / drain regions 92'), the gate structures (for example, the gate electrodes 102 and the gate dielectric layers 100), and the second epitaxial material 89 after the thinning process. For example, the remaining portion of the substrate 50 can extend over and cover the second epitaxial material 89 and the gate electrodes 102. In some embodiments, the thickness T1 of the remaining portion of the substrate 50 can be in a range of approximately 5 nm to approximately 40 nm.It was found that by leaving a sufficiently thick section (for example, in the thickness range mentioned above) of the substrate 50 over the epitaxial source / drain regions 92, the epitaxial source / drain regions 92 can be fully protected during subsequent processes for removing the first epitaxial material 91 and the second epitaxial material 89 over the epitaxial source / drain regions 92'.

[0082] In the Fig. 23A to 23C then have one or more insulating materials (for example, a dielectric layer 162) applied to the surface in the Fig. The structure illustrated in Figures 22A to 22C is deposited. The dielectric layer 162 can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric layer 162 can comprise phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can also be used. In some embodiments, a dielectric lining 160 is arranged between the dielectric layer 162 and the STI regions 68, the semiconductor substrate 50, and the first epitaxial material 91. The dielectric lining 160 can comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride or the like and can be deposited by a similar process to the dielectric layer 162.In some embodiments, the dielectric lining 160 can be a conformal layer extending along sidewalls of the first epitaxial material 91, and the dielectric lining 160 can prevent or reduce diffusion between the dielectric layer 162 and the semiconductor substrate 50, the second epitaxial material 89, and / or the source / drain regions 92. In the embodiment of the . Fig. 23A to 23C, the semiconductor substrate 150 can completely separate the dielectric lining 160 from the second epitaxial material 89 and the epitaxial source / drain regions 92, such that the dielectric lining 160 does not touch either the second epitaxial material 89 or the epitaxial source / drain regions 92.

[0083] In the Fig. In steps 24A to 24C, a planarization process, such as CMP, can be performed to level the top surface of the dielectric layer 162 with the top surfaces of the first epitaxial material 91. After the planarization process, the top surfaces of the dielectric layer 162, the first epitaxial material 91, and the dielectric lining 160 are flush, depending on the process variation. Accordingly, the top surface of the first epitaxial material 91 is exposed through the oxide layer 162.

[0084] In the Fig. In processes 25A to 25C, the first epitaxial material 91 and sections of the second epitaxial material 89 covering the epitaxial source / drain regions 92' are removed, creating recesses 164. These recesses 164 can expose selected epitaxial source / drain regions 92 (referred to as epitaxial source / drain regions 92') through the dielectric layer 162, the dielectric lining 160, the STI regions 68, and the semiconductor substrate 50. In some embodiments, the first epitaxial material 91 and the sections of the second epitaxial material 89 are removed by an anisotropic dry etching process or the like.For example, the etching process can include a dry etching process in which one or more reactive gases are used that selectively etch the first epitaxial material 91 and sections of the second epitaxial material 89 at a faster rate than the dielectric lining 160 and the dielectric layer 162. During the etching processes to remove the first epitaxial material 91 and the sections of the second epitaxial material 89, the semiconductor substrate 50 and the remaining sections of the second epitaxial material 89 can mask other epitaxial source / drain regions 92 and protect them from unintended etching. In particular, by leaving a section of the semiconductor substrate 50 untouched, corner regions 92C of the epitaxial source / drain regions can be protected from lateral etching by the second epitaxial material 89.As a result, manufacturing defects (for example, etching damage to the source / drain regions 92) can be reduced and production yield increased.

[0085] In the Fig. In steps 26A to 26C, insulating spacers 166 are deposited on the sidewalls of the recesses 164. The spacers 166 can comprise a dielectric material deposited by CVD, ALD, PVD, PECVD, or the like. After deposition, an etching process, such as a dry or wet etching process, can be performed to remove lateral sections of the dielectric material, leaving the dielectric material on the sidewalls of the recesses 164, thus forming the spacers 166. The etching process can be anisotropic, and the dielectric material can be chosen to be different from the dielectric layer 162. Therefore, the etching process can selectively etch the dielectric material without substantially etching the dielectric layer 162. For example, the dielectric material can be silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like.

[0086] In the Fig. In 27A to 27C, second silicide regions 168 are formed in the recesses 164 on the back sides of the epitaxial source / drain regions 92'. The second silicide regions 168 can be formed by a similar process to the first silicide regions 110. Furthermore, the second silicide regions 168 can comprise TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, and YbSi in the n-region 50N, and the second silicide regions 168 can comprise NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, and OsSi in the p-region 50P. The material composition of the second silicide regions 168 can be the same as, or different from, that of the first silicide regions 110. In some embodiments, the second silicide regions 168 have a thickness in the range of 1 nm to 10 nm.

[0087] As in the Fig. As further illustrated in Figures 27A to 27C, backside vias 170 are formed in the recesses 164. The backside vias 170 can extend through the dielectric layer 162, the dielectric lining 160, the STI regions 168, and the semiconductor substrate 50. The backside vias 170 can be electrically coupled to the epitaxial source / drain regions 92' through the second silicide regions 168. The backside vias 170 can resemble the source / drain contacts 112 described above in relation to the Fig. 20A to 20C are described. For example, the backside contacts 170 can be formed from a similar material and using the same process as the source / drain contacts 112. In some embodiments, the backside contacts 170 can have a thickness (for example, measured between the top and bottom surfaces of the backside contacts 170) in the range of about 10 nm to about 50 nm. The thickness of the backside vias 170 can be greater than the thickness of the semiconductor substrate 50. The material composition of the backside contacts 170 can be the same as, or different from, that of the source / drain contacts 112.

[0088] In the Fig. In components 28A to 28C, conductors 134 and a dielectric layer 132 are formed over the dielectric layer 162, the STI regions 68, and the backside vias 170. The dielectric layer 132 can be similar to the dielectric layer 162. For example, the dielectric layer 132 can be formed from a similar material and using the same process as the dielectric layer 162.

[0089] The conductors 134 are formed in the dielectric layer 132. Forming the conductors 134 can, for example, involve structuring recesses in the dielectric layer 132 using a combination of photolithography and etching processes. A structure of the recesses in the dielectric layer 132 can correspond to a structure of the conductors 134. The conductors 134 are then formed by depositing a conductive material in the recesses. In some embodiments, the conductors 134 comprise a metal layer, which can be a single layer or a composite layer comprising several sublayers that can be made of different materials. In some embodiments, the conductors 134 comprise copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like.An optional diffusion barrier and / or adhesive layer can be deposited before filling the recesses with the conductive material. Suitable materials for the barrier / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. The conductors 134 can be formed, for example, by CVD, ALD, PVD, plating, or the like. The conductors 134 are physically and electrically coupled to the epitaxial source / drain regions 92' through the back-side vias 170 and the second silicide regions 168. A planarization process (for example, CMP, looping, back-etching, or the like) can be performed to remove excess sections of the conductors 134 formed above the dielectric layer 132.

[0090] In some embodiments, the conductors 134 are busbars, that is, conductors that electrically connect the epitaxial source / drain regions 92' to a reference voltage, a supply voltage, or the like. Advantages can be realized by arranging busbars on a back side of the resulting semiconductor die instead of on a front side. For example, the gate density of the nanoFETs and / or the interconnect density of the front-side interconnect structure 120 can be increased. Furthermore, the back side of the semiconductor die can accommodate wider busbars, thereby reducing resistance and increasing the efficiency of the current supply to the nanoFETs. For example, the width of the conductors 134 can be at least twice the width of conductors of a first level (for example, first conductive features 122) of the front-side interconnect structure 120.

[0091] In the Fig. Sections 29A to 29C form the remaining sections of a backside interconnect structure 136 above the dielectric layer 132 and the traces 134. The backside interconnect structure 136 can be described as a backside interconnect structure because it is formed on the back side of the device layer 115 (for example, on one side of the transistor structures opposite the gate electrodes 102). The backside interconnect structure 136 can include the second dielectric layer 125, the third dielectric layer 132, the backside vias 130, and the traces 134.

[0092] The remaining sections of the rear interconnect structure 136 can comprise materials and be formed using processes that are the same as or similar to those used for the front interconnect structure 120 and described above with respect to the Fig. 21A to 21D were discussed. In particular, the backside interconnect structure 136 can comprise stacked layers of secondary conductive features 140 formed in dielectric layers 138. The secondary conductive features 140 can include routing lines (for example, for routing to and from subsequently formed contact pads and external connectors). The secondary conductive features 140 can further be structured to include one or more embedded passive devices such as resistors, capacitors, inductors, or the like. The embedded passive devices can be integrated with the lines 134 (for example, the busbar) to form circuits (for example, power circuits) on the backside of the nanoFETs.

[0093] As in the Fig. As further illustrated in Figures 29A to 29C, a passivation layer 144, UBMs 146, and external connections 148 are formed over the rear interconnect structure 136. The passivation layer 144 can comprise polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 144 can contain inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 144 can be deposited, for example, by CVD, PVD, ALD, or the like.

[0094] The UBMs 146 are formed by the passivation layer 144 to the second conductive features 140 in the rear interconnect structure 136, and the external connections 148 are formed on the UBMs 146. The UBMs 146 may comprise one or more layers of copper, nickel, gold, or the like, formed by a plating process or the like. The external connectors 148 (for example, solder beads) are formed on the UBMs 146. Forming the external connectors 148 may involve placing solder beads on exposed portions of the UBMs 146 and melting the solder beads. In some embodiments, forming the external connectors 148 includes performing a plating step to form solder regions over the uppermost second conductive features 140 and subsequently melting the solder regions.The UBMs 146 and the external connectors 148 can be used to establish input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), mainboards, or the like. The UBMs 146 and the external connectors 148 can also be referred to as rear-side input / output pads that can provide signal, supply voltage, and / or ground connections to the nanoFETs described above. In this way, semiconductor dies 200 are formed, comprising a device layer 115, a front-side interconnect structure 120, and a rear-side interconnect structure 136.

[0095] The Fig. Figures 30A to 36E illustrate intermediate steps of a rear-side interconnect structure according to some other embodiments. Fig. 30A, Fig. 31A, Fig. 32A, Fig. 33A, Fig. 34A, Fig. 35A and Fig. 36A illustrates the in Fig. 1 illustrated reference cross-section A-A'. Fig. 30B, Fig. 31B, Fig. 32B, Fig. 33B, Fig. 34B, Fig. 35B and Fig. 36B illustrates the in Fig. 1 illustrated reference cross-section B-B'. Fig. 30°C Fig. 31C, Fig. 32C, Fig. 33C, Fig. 33D, Fig. 33E, Fig. 34C, Fig. 34D, Fig. 34E, Fig. 35°C Fig. 35D, Fig. 35E, Fig. 36C, Fig. 36D and Fig. 36E illustrate the in Fig. 1 illustrated reference cross-section C-C'. In the Fig. Semiconductor dies 250 are formed from 30A to 36E. Semiconductor dies 250 may resemble the semiconductor dies 200 described above, where the same reference numbers denote identical elements formed using the same process, unless otherwise specified.

[0096] The Fig. 30A to 30C illustrate a structure similar to that found in the Fig. The structure illustrated in sections 22A to 22C is similar, and the same process steps as above can be used with regard to the Fig. The steps described in sections 1 to 21C are carried out to create the structure in the Fig. to reach 30A to 30C. As in the Fig. As further illustrated in Figures 30A to 30C, a rear side of the semiconductor substrate 50 is structured to expose the first epitaxial material 91. The structuring process may include a planarization process (for example, mechanical grinding, CMP, or the like), a back-etching process, or a combination thereof. In some embodiments, the structuring process includes a combination of planarization to remove a large portion of the substrate 50, followed by back-etching to remove further sections of the substrate 50. The structuring process may expose surfaces of the first epitaxial material 91 and the second epitaxial material 89 opposite the front-side interconnect structure 120. Surfaces of the STI regions 68 and the gate electrodes (including the gate dielectric 100 and the gate electrodes 102) may also be exposed.For example, the structuring process can back-etch the substrate 50 and the STI regions 68 below the top surfaces of the first epitaxial regions 91. In some embodiments, the back-etch process can be a plasma etching process using O₂, Cl₂, HCl, HBr, combinations thereof, or the like to etch the substrate 50. Furthermore, the back-etch process can include an etchant flow rate in the range of about 5 sccm to about 100 sccm, a chamber pressure in the range of about 0.133322 Pa (1 mTorr) to about 13.3322 Pa (100 mTorr), and a bias voltage in the range of about 300 V to about 1000 V. In other embodiments, other process conditions can be used.

[0097] As a result of the structuring of the substrate 50, a substantial portion of the substrate 50 is removed, leaving only sections of the substrate 50 at corners of the epitaxial source / drain regions 92. In some embodiments, the remaining sections of the substrate 50 can form an area along the crystalline <111> -level. By removing a substantial portion of the substrate 50, leakage current and capacitance in the resulting device can be reduced. Furthermore, by leaving sections of the substrate 50 to cover corner regions of the epitaxial source / drain regions 92, the epitaxial source / drain regions 92 can continue to be protected during subsequent etching processes. In this way, manufacturing defects can be reduced.In some embodiments, each of the remaining sections of the substrate 50 can have a width W1 in a range of approximately 1 nm to approximately 5 nm and a height H1 in a range of approximately 1 nm to approximately 15 nm. It has been found that by ensuring that the remaining sections of the substrate 50 fall within the dimensions mentioned above, leakage current and capacitance can be reduced, while the epitaxial source / drain regions 92 remain protected in subsequent process steps.

[0098] In the Fig. 31A to 31C, the dielectric layer 162 and the dielectric lining 160 are then made from a similar material and in a similar process as above with regard to the Fig. 23A to 23C describe how the dielectric lining 160 and the dielectric layer 162 can be deposited over the STI regions 68, the first epitaxial material 91, the second epitaxial material 89, and the gate stacks (including the gate dielectric 100 and the gate electrode 102). Because a considerable portion of the substrate 50 is removed, an insulating material (for example, the dielectric lining 160) can directly contact the STI regions 68, the first epitaxial material 91, the second epitaxial material 92, and the gate stacks (for example, the gate dielectric 100) of the active devices. For example, the dielectric layer 162 and the dielectric lining 160 can extend through the remaining regions 50 to contact the gate stack (see Figure 23A to 23C). Fig. 31C).

[0099] In the Fig. 32A to 32C, a thinning process can be applied to the dielectric layer 162 and the dielectric lining 160, using a similar process to the one described above with respect to the Fig. 24A to 24C are used as described. As a result, the first epitaxial material 91 can be exposed.

[0100] In the Fig. 33A to 33C, an etching process can be applied to obtain the first epitaxial material 91 as above in relation to the Fig. Sections of the second epitaxial material 89 covering the epitaxial source / drain regions 92', as described in sections 25A to 25C, can also be removed. As a result, the recesses 164 are formed, extending through the dielectric layer 162, the dielectric material 160, and the STI regions 68 to expose the epitaxial source / drain regions 92'. Because sections of the substrate 50 remain in the recesses 164 during the structuring process, the epitaxial source / drain regions 92 can be covered and protected, thereby reducing manufacturing defects.

[0101] In some embodiments (such as through Fig. (As illustrated in Figure 33D), sections of substrate 50 in the recesses 164 can optionally be removed after the recesses 164 have been etched using a suitable etching process, such as wet etching, dry etching, or the like. The etching process can use a chemical etchant that selectively etches substrate 50 without significantly etching the epitaxial source / drain regions 92 (including regions 92'). As a result, substrate 50 can be removed from the recesses 164 without significantly damaging or etching the epitaxial source / drain regions 92.

[0102] In some embodiments, an insulating material 172 can optionally be deposited in the recesses 164, as shown in Fig. Figure 33E illustrates this. In some embodiments, the insulating material 172 can be deposited after the substrate 50 has been removed from the recesses 164, and the insulating material 172 can comprise a dielectric material such as silicon oxide, silicon nitride, an oxynitride, combinations thereof, or the like. The deposition of the insulating material 172 can include any suitable process, such as CVD, ALD, PVD, PECVD, or the like. After the insulating material 172 has been deposited, etching can be performed to remove excess sections of the insulating material 172 from the recesses 164. The etching can be anisotropic in some embodiments.In some embodiments, the insulating material 172 can be produced by performing an oxidation process (for example, thermal oxidation) on the semiconductor substrate 50 in the recesses 164 to convert the semiconductor substrate 50 in the recesses 164 into silicon oxide or the like. The resulting insulating material 172 can have a similar shape and dimensions to the substrate 50 in the recesses 164. For example, the insulating material 172 can have a width in the range of about 1 nm to about 5 nm and a height in the range of about 1 nm to about 15 nm. Fig. The steps illustrated in 33D and / or 33E are optional, and one or the other may be omitted in other embodiments.

[0103] In the Fig. 34A to 34C, insulating spacers 166 are attached to the side walls of the recesses 164 according to the embodiments of the Fig. 33A to 33C formed. Fig. Figure 34D illustrates the insulating spacers 166, which are attached to the side walls of the recesses 164 according to the embodiments in Fig. 33D are formed (for example, where the substrate 50 is removed from the recesses 164). As a result of removing the substrate 50, cavities 174 can be defined between the insulating spacers 166 and the dielectric lining 160. In some embodiments, the cavities 174 can be sealed by a material of the insulating spacers 166, and the cavities 174 can be sealed by adjusting process conditions (for example, chamber pressure, gas flow, and the like) during the deposition of the spacers 166 such that the spacers 166 seal the cavities 174 without filling them. The cavities 174 can have a similar shape and dimensions to the substrate 50 that was previously removed from the recesses 164. For example, the cavities 174 can have a width in a range of about 1 nm to about 5 nm and a height in a range of about 1 nm to about 15 nm. Fig. Figure 34E illustrates the insulating spacers 166 formed on the side walls of the recesses 164 and the insulating material 172 according to the embodiments in Fig. 33E (for example, where the substrate 50 in the recesses 164 is replaced by the insulating material 172). The insulating spacers 166 can be formed using a similar process and the same material as described above in relation to the Fig. 26A to 26C was described.

[0104] In the Fig. 35A to 35C, the rear vias 170 and the second silicide regions 110 are located in the recesses 164 according to the embodiment of Fig. 33A to 33C formed. Fig. Figure 34D illustrates the backside vias 170 and the second silicide regions 110 formed in the recesses 164, according to the embodiments in Fig. 33D (for example, where the substrate 50 is removed from the recesses 164). Fig. Figure 34E illustrates the backside vias 170 and the second silicide regions 110 formed in the recesses 164, according to the embodiment in Fig. 33E (for example, where the substrate 50 in the recesses 164 is replaced by the insulating material 172). The backside vias 170 and the second silicide regions 110 can be produced using a similar process and the same material as described above. Fig. 27A to 27C are described and formed.

[0105] Additional processing (for example, similar to the above in relation to the Fig. (described in sections 28A to 29C) can be seen in the structures of the Fig. 35A to 35E are carried out to form the remaining sections of the rear interconnect structure 136, the passivation layer 144, the UBMs 146 and the external connectors 148. Fig. 36A to 36C correspond to the embodiments of the Fig. 35A to 35C; Fig. 36D corresponds to the embodiments of Fig. 35D; and Fig. 36E corresponds to the embodiments of Fig. 36E. The device 250 is now complete. In the device 250, the substrate 50 is essentially removed, leaving only sections along the crystalline <111> -plane remain and corner regions of the epitaxial source / drain regions 92 are covered. Optionally, the substrate 50 can remain around the lower sections of the backside vias 170, or the substrate 50 can be covered by cavities 174 (see Fig. 36D) or insulation materials 172 (see Fig. 36E) will be replaced.

[0106] Several embodiments can realize advantages. Various embodiments provide a backside interconnect structure in which a large portion of a semiconductor substrate is etched away and removed, creating backside contacts to the source / drain regions of transistors formed on the semiconductor substrate. As part of the backside contact formation, the etching of the semiconductor substrate includes leaving a portion of the substrate such that at least the edge regions of the source / drain areas are covered. As a result, the source / drain areas can be better protected during the backside contact formation process, and manufacturing defects can be reduced. Additional portions of the substrate can be removed to further reduce leakage current and capacitance.

[0107] According to one embodiment, a device comprises: a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front side of the device layer; and a second interconnect structure on a back side of the device layer. The second interconnect structure comprises: a first dielectric layer on the back side of the device layer, wherein a semiconductor material is arranged between the first dielectric layer and a first source / drain region of the first transistor; a contact extending through the first dielectric layer to a second source / drain region of the second transistor; and a first conductor electrically connected to the second source / drain region of the second transistor through the contact. Optionally, in some embodiments, the first conductor is a power supply line or an electrical ground line.Optionally, in some embodiments, the device further comprises a dielectric lining between the first dielectric layer and the device layer, with the contact extending through the dielectric lining. Optionally, in some embodiments, the dielectric lining contacts a gate stack of the first transistor. Optionally, in some embodiments, the device also comprises an insulating spacer on a side wall of the contact. Optionally, in some embodiments, the insulating spacer contacts the semiconductor material. Optionally, in some embodiments, the device also comprises a cavity between the insulating spacer and the semiconductor material. Optionally, in some embodiments, the device further comprises an insulating material between the insulating spacer and the semiconductor material.

[0108] According to another embodiment, a device layer comprises: several transistors; a front-side interconnect structure on a front face of the device layer; and a back-side interconnect structure on a rear face of the device layer. The back-side interconnect structure comprises: a semiconductor material on the rear face of the device layer; a first insulating material on the rear face of the device layer, wherein the first insulating material contacts a gate stack in the device layer, and wherein the semiconductor material separates the first insulating material from a corner region of a first source / drain region in the device layer; a contact extending through the first insulating material to a second source / drain region in the device layer; and a conductor electrically connected to the second source / drain region through the contact.Optionally, in some embodiments, the semiconductor material has an area in a crystalline structure. <111> -level. Optionally, in some embodiments, the device also has a cavity between the contact and the first insulating material. Optionally, in some embodiments, the device further has a second insulating material between the contact and the first insulating material. Optionally, in some embodiments, the device further has an insulating spacer on side walls of the contact, wherein the insulating spacer separates the contact from the first insulating material. Optionally, in some embodiments, the device further has an epitaxial material between the first source / drain region and the first insulating material, wherein the semiconductor material is arranged on a side wall of the epitaxial material.

[0109] According to a further embodiment, a method comprises: forming a device layer on a semiconductor substrate, wherein the device layer comprises multiple transistors, the formation of the device layer comprising: etching a first recess and a second recess in the semiconductor substrate; epitaxially growing a first semiconductor material in the first recess; epitaxially growing a second semiconductor material over the first semiconductor material in the first recess; and epitaxially growing a third semiconductor material in the second recess; forming a first interconnect structure over a back side of the device layer, the formation of the first interconnect structure comprising: removing a section of the semiconductor substrate,to expose the first semiconductor material; depositing a first dielectric layer over remaining portions of the semiconductor substrate and around the first semiconductor material; removing the first semiconductor material to define a third recess, wherein the remaining portions of the semiconductor substrate mask at least one corner region of the third semiconductor material while the first semiconductor material is removed, and wherein the third recess exposes the second semiconductor material; and forming a contact in the second recess and in electrical connection with the second semiconductor material. Optionally, in some embodiments, removing the portion of the semiconductor substrate further exposes a gate stack of the device layer. Optionally, in some embodiments, forming the device layer further comprises: epitaxially growing a fourth semiconductor material in the second recess,wherein the third semiconductor material is located above the fourth semiconductor material, and wherein the remaining portions of the semiconductor substrate contact a side wall of the fourth semiconductor material. Optionally, in some embodiments, the method further comprises removing the semiconductor substrate from the third recess before the contact is formed. Optionally, in some embodiments, the method further comprises oxidizing the semiconductor substrate in the third recess to form an insulating material. Optionally, in some embodiments, the method further comprises replacing the semiconductor substrate in the third recess with an insulating material.

[0110] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence of the present disclosure and that they can make various changes, substitutions, and modifications to the present invention without deviating from the essence of the present disclosure.

Claims

[1] Device comprising: a device layer (115) comprising a first transistor and a second transistor; a first interconnect structure (120) on a front side of the device layer (115); and a second interconnect structure (136) on a back side of the device layer (115), the second interconnect structure (136) comprising: a first dielectric layer (162) on the back side of the device layer (115), wherein a semiconductor material (50) is arranged between the first dielectric layer (162) and a first source / drain region (92) of the first transistor; a contact (170) extending through the first dielectric layer (162) to a second source / drain region (92') of the second transistor; and a first line (134) which is electrically connected to the second source / drain region (92') of the second transistor via the contact (170). [2] Device according to claim 1, wherein the first line (134) is a power supply line or an electrical earthing line. [3] Device according to claim 1, which further comprises a dielectric lining (160) between the first dielectric layer (162) and the device layer (115), wherein the contact (170) extends through the dielectric lining (160). [4] Device according to claim 3, wherein the dielectric lining (160) contacts a gate stack (100, 102) of the first transistor. [5] Device according to claim 1, which further comprises an insulating spacer (166) on a side wall of the contact (170). [6] Device according to claim 5, wherein the insulating spacer (166) contacts the semiconductor material (50). [7] Device according to claim 5, which further comprises a cavity (174) between the insulating spacer (166) and the semiconductor material (50). [8] Device according to claim 5, which further comprises an insulating material (172) between the insulating spacer (166) and the semiconductor material (50). [9] Device comprising: a device layer (115) comprising several transistors; a front-side interconnect structure (120) on a front side of the device layer (115); and a rear interconnect structure (136) on a rear side of the device layer (115), wherein the rear interconnect structure (136) comprises: a semiconductor material (50) on the back side of the device layer (115); a first insulating material (160) on the back side of the device layer (115), wherein the first insulating material (160) contacts a gate stack (100, 102) in the device layer (115), and wherein the semiconductor material (50) separates the first insulating material (160) from a corner region (92C) of a first source / drain region (92) in the device layer (115); a contact (170) extending through the first insulating material (160) to a second source / drain region (92') in the device layer (115); and a line (134) which is electrically connected to the second source / drain region (92') via the contact (170). [10] Device according to claim 9, wherein the semiconductor material (50) forms an area in a crystalline <111> -level. [11] Device according to claim 9, which further comprises a cavity (174) between the contact (170) and the first insulating material (160). [12] Device according to claim 9, which further comprises a second insulating material (172) between the contact (170) and the first insulating material (160). [13] Device according to claim 9, which further comprises an insulating spacer (166) on side walls of the contact (170), wherein the insulating spacer (166) separates the contact (170) from the first insulating material (160). [14] Device according to claim 13, which further comprises an epitaxial material (89) between the first source / drain region (92) and the first insulation material (160), wherein the semiconductor material (50) is arranged on a side wall of the epitaxial material (89). [15] Procedure that includes: Forming a device layer (115) on a semiconductor substrate (50), wherein the device layer (115) comprises several transistors, wherein the formation of the device layer (115) comprises: Etching a first recess (87) and a second recess (86) in the semiconductor substrate (50); epitaxial growth of a first semiconductor material (91) in the first recess (87); epitaxial growth of a second semiconductor material (89) over the first semiconductor material (91) in the first recess (87); and epitaxial growth of a third semiconductor material (92) in the second recess (86); Forming a first interconnect structure (120) over a back side of the device layer (115), wherein forming the first interconnect structure (120) comprises: Removing a section of the semiconductor substrate (50) to expose the first semiconductor material (91); Deposition of a first dielectric layer (160) over remaining sections of the semiconductor substrate (50) and around the first semiconductor material (91); Removing the first semiconductor material (91) to define a third recess (164), wherein the remaining sections of the semiconductor substrate (50) mask at least one corner region (92C) of the third semiconductor material (92) while the first semiconductor material (91) is removed, and wherein the third recess (164) exposes the second semiconductor material (89); and Forming a contact (170) in the second recess (86) and in electrical connection with the second semiconductor material (89). [16] Method according to claim 15, wherein by removing the section of the semiconductor substrate (50) further exposes a gate stack (100, 102) of the device layer (115). [17] Method according to claim 16, wherein forming the device layer (115) further comprises: epitaxial growth of a fourth semiconductor material in the second recess (86), wherein the third semiconductor material (92) is located above the fourth semiconductor material, and wherein the remaining sections of the semiconductor substrate (50) contact a side wall of the fourth semiconductor material. [18] Method according to claim 17, further comprising removing the semiconductor substrate (50) from the third recess (164) prior to forming the contact (170). [19] Method according to claim 17, further comprising oxidizing the semiconductor substrate (50) in the third recess (164) to form an insulating material (172). [20] Method according to claim 17, further comprising replacing the semiconductor substrate (50) in the third recess (164) with an insulating material (172).

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