Semiconductor device and method for manufacturing the same

Abstract

Device comprising: a device layer comprising a first transistor (109); a first interconnect structure (110, 112, 114, 120, 152) on a front side of the device layer; and a second interconnect structure (129, 130, 134, 136, 146, 148) on a backside of the device layer, the second interconnect structure (129, 130, 134, 136, 146, 148) comprising: a first dielectric material (68) on the backside of the device layer; a contact (129, 130) extending through the first dielectric material (68) to a first source / drain region (92) of the first transistor (109), wherein a first width (W1) of the contact (129, 130) is greater than a second width (W2) of the first source / drain region (92), wherein the first width (W1) of the contact (129, 130) is measured at a level of the first dielectric material (68) and the second width (W2) of the first source / drain region (92) is measured from a first nanostructure (54, 54A-54C) of the first transistor (109) to a second nanostructure (54, 54A-54C); and a first conductive layer comprising a first conductive trace (134) electrically connected to the first source / drain region (92) through the contact (129, 130); wherein the device further comprises an insulating spacer (206, 214) on a sidewall of the contact (129, 130), the spacer (206, 214) separating the contact (129, 130) from the first dielectric material (68).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated in a given area. However, as the minimum feature sizes are reduced, additional problems arise that should be addressed. DE 11 2016 007 299 T5 describes a backside source / drain exchange for semiconductor devices with metallization on both sides, which enables a low contact resistance value. DE 10 2017 127 206 A1 describes a method for manufacturing a semiconductor device, wherein the method creates a concave top side of a first conductive region, which enables a larger contact area and thus a reduced contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. Indeed, the dimensions of various features may be exaggerated or reduced as desired for clarity. Fig. 1 illustrates an example of a nanostructure field effect transistor (nano-FET) in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 12E, Fig. 12F, Fig. 12G, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 27D, Fig. 28A, Fig. 28B, Fig. 28C, Fig. 28D, Fig. 28E, Fig. 28F, Fig. 28G, Fig. 28I, Fig. 29A, Fig. 29B, Fig. 29C, Fig. 30A, Fig. 30B, Fig. 30C, Fig. 31A, Fig. 31B, Fig. 31C, Fig. 32A, Fig. 32B, Fig. 32C, Fig. 33A, Fig. 33B, Fig. 33C, Fig. 34A, Fig. 34B, Fig. 34C, Fig. 34D, Fig. 34E, Fig. 34F, Fig. 35A, Fig. 35B, Fig. 35C, Fig. 35D and Fig. 35E are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples of implementing different features of the invention. Specific examples of the components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The formation of a first feature over or on top of a second feature in the following description may, for example, include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "deeper," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0006] Various embodiments provide methods for forming nano-FETs in semiconductor devices and semiconductor devices incorporating them. By forming backside vias before removing substrates, the size of the backside vias can be expanded. Subsequent liner deposition and etch processes can be applied to the outer surfaces of the already formed backside vias, such that the liner formation and subsequent etching processes do not reduce the width of the backside vias. The larger backside vias can be useful for silicide formation and for a larger contact area to obtain better contact resistance and resulting device performance.

[0007] Some embodiments discussed herein are described in the context of a die comprising nano-FETs. However, instead of or in combination with the nano-FETs, various embodiments may be applied to dies, including other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like).

[0008] Fig. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view according to some embodiments. The nano-FETs include nanostructures 55 (e.g., nanosheets, nanowires, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructures 55 serve as channel regions for the nano-FETs. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, the term “substrate” as used herein may refer only to the semiconductor substrate or a combination of the semiconductor substrate and the STI regions.Furthermore, although bottom portions of fins 66 are illustrated as individual, continuous materials with substrate 50, the bottom portions of fins 66, and / or substrate 50 may comprise a single material or a plurality of materials. In this context, fins 66 refer to the portion extending between adjacent STI regions 68.

[0009] Dielectric gate layers 100 are located above top surfaces of the fins 66 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are located above the dielectric gate layers 100. Epitaxial source / drain regions 92 are arranged on the fins 66 on opposite sides of the dielectric gate layers 100 and the gate electrodes 102.

[0010] Fig. 1 further illustrates reference cross-sections used in later figures. Cross-section AA' extends in a YZ plane along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of a nano-FET. Cross-section BB' extends in a YZ plane parallel to cross-section AA' and extends through epitaxial source / drain regions 92 of multiple nano-FETs. Cross-section CC' extends in an XZ plane perpendicular to cross-section AA' and parallel to a longitudinal axis of a fin 66 of the nano-FET and, for example, in a direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Subsequent figures refer to these reference cross-sections for clarity.

[0011] Some of the embodiments discussed herein are explained in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Some embodiments also contemplate aspects used in planar devices, such as planar FETs, or fin field-effect transistors (FinFETs).

[0012] Fig. 2 to 34H are cross-sectional views of the intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2 to 5, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, 31A, 32A, 33A, 34A and 35A illustrate the Fig. 1 illustrated cross section A-A'. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 12D, Fig. 12F, Fig. 12G, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B, Fig. 31B, Fig. 32B, Fig. 33B, Fig. 34B, Fig. 34E, Fig. 34F, Fig. 35B, Fig. 35D and Fig. 35E illustrate the Fig. 1 illustrated reference cross section B-B'. Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 11D, Fig. 12C, Fig. 12E, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25C, Fig. 26C, Fig. 27C, Fig. 28C, Fig. 29C, Fig. 30C, Fig. 31C, Fig. 32C, Fig. 33C, Fig. 34C, Fig. 34D and Fig. 35C illustrate the Fig. 1 illustrated reference cross section C-C'.

[0013] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a composite semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0014] The substrate 50 includes an n-type region 50N and a p-type region 50P. The n-type region 50N may be used to form n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region 50P may be used to form p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region 50N may be physically separated from the p-type region 50P (as illustrated by divider 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P may be provided.

[0015] Furthermore, Fig. 2, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as explained in more detail below, the first semiconductor layers 51 are removed and the second semiconductor layers 53 are patterned to form channel regions of nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of the nano-FETs in the n-type region 50N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of the nano-FETs in the p-type region 50P.In some embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of the nano-FETs in the n-type region 50N, and the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of the nano-FETs in the p-type region 50P. In some embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of the nano-FETs in both the n-type region 50N and the p-type region 50P.

[0016] The multilayer stack 64 is illustrated for illustrative purposes as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.In various embodiments, the first semiconductor layers 51 may be formed from a first semiconductor material suitable for p-type nanoFETs, such as silicon germanium or the like, and the second semiconductor layers 53 may be formed from a second semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbon, or the like. The multilayer stack 64 is illustrated for illustrative purposes as having a bottommost semiconductor layer suitable for p-type nanoFETs. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nanoFETs.

[0017] The first semiconductor materials and the second semiconductor materials may be materials that have a high etch selectivity to each other. Thus, the first semiconductor layers 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layers 53 of the second semiconductor material, thereby enabling the second semiconductor layers 53 to be patterned to form channel regions of the nano-FETs. Similarly, in embodiments in which the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to form channel regions, the second semiconductor layers 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layers 51 of the first semiconductor material, thereby enabling the first semiconductor layers 51 to be patterned to form channel regions of the nano-FETs.

[0018] Now with reference to Fig. 3, according to some embodiments, fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 may be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching may be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 may define first nanostructures 52A-52C (collectively referred to as the first nanostructures 52) from the first semiconductor layers 51 and second nanostructures 54A-54C (collectively referred to as the second nanostructures 54) from the second semiconductor layers 53.The first nanostructures 52 and the second nanostructures 54 may together be referred to as nanostructures 55.

[0019] The fins 66 and the nanostructures 55 can be patterned using any suitable method. The fins 66 and the nanostructures 55 can be patterned, for example, using one or more photolithographic processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, which makes it possible to create structures that have, for example, smaller pitches than what can otherwise be achieved using a single, direct photolithography process. In one embodiment, for example, a mask is formed and patterned over a substrate using a photolithography process. Spacers are formed along the patterned mask using a self-aligned process.The mask is then removed and the remaining spacers can then be used to structure the fins 66.

[0020] Fig. 3 illustrates the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths for illustrative purposes. In some embodiments, the widths of the fins 66 in the n-type region 50N may be larger or thinner than the fins 66 in the p-type region 50P. Furthermore, although each of the fins 66 and the nanostructures 55 is illustrated as having a uniform width throughout, in other embodiments the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that a width of each of the fins 66 and / or the nanostructures 55 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0021] In Fig. 4, shallow trench isolation (STI) regions 68 are formed adjacent to fins 66. STI regions 68 may be formed by depositing an isolation material over substrate 50, fins 66, and nanostructures 55, and between adjacent fins 66. The isolation material may be a dielectric material, such as an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other isolation materials formed by an acceptable process may also be used. In the illustrated embodiment, the isolation material is silicon oxide formed by an FCVD process. After the isolation material is formed, an annealing process may be performed.In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately illustrated) may first be formed along a surface of the substrate 50, the fins 66, and the nanostructures 55. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0022] A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 such that the upper surfaces of the nanostructures 55 and the insulation material are flush after completion of the planarization process.

[0023] The insulation material is then recessed to form the STI regions 68. The insulation material is recessed such that upper portions of the fins 66 in the n-type region 50N and in the p-type region 50P protrude from between adjacent STI regions 68. Further, the upper surfaces of the STI regions 68 may have a flat surface, as illustrated, a convex surface, a concave surface (such as domed), or a combination thereof. The upper surfaces of the STI regions 68 may be formed flat, convex, and / or concave by a suitable etch. The STI regions 68 may be recessed using any acceptable etching process, such as one that is selective for the insulation material material (e.g., etching the insulation material material at a faster rate than the material of the fins 66 and the nanostructures 55).For example, oxide removal can be carried out using dilute hydrofluoric acid (dHF).

[0024] The one with reference to Fig. The process described in Figures 2 to 4 above is just one example of how the fins 66 and the nanostructures 55 may be formed. In some embodiments, the fins 66 and / or the nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth, which may preempt prior and / or subsequent implantations, although in situ and implantation doping may also be used together.

[0025] Furthermore, for illustrative purposes only, the first semiconductor layers 51 (and resulting first nanostructures 52) and the second semiconductor layers 53 (and resulting second nanostructures 54) are illustrated and discussed herein as comprising the same materials in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0026] Furthermore, Fig. 4, corresponding sources (not separately illustrated) may be formed in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different source types, the different implantation steps for the n-type region 50N and the p-type region 50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins 66 and the STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin-on technique and may be patterned using acceptable photolithography techniques.After the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, which can be introduced into the region to a concentration in the range of about 10%. 13 atoms / cm 3 up to about 10 14 atoms / cm 3 implanted. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0027] After or before the implantation of the p-type region 50P, a photoresist or other masks (not separately illustrated) are formed over the fins 66, the nanostructures 55, and the STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, a p-type impurity implantation is performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium or the like, ranging up to a concentration in the range of about 1013 atoms / cm 3 up to about 1014 atoms / cm 3implanted. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0028] After the implantation of the n-type region 50N and the p-type region 50P, an annealing process is performed to repair implantation damage and to activate the implanted p-type and / or n-type impurities. In some embodiments, the grown materials of the epitaxial fins can be doped in situ during growth, which can preempt the implantations, although in situ and implantation doping can be used together.

[0029] In Fig. 5, a dummy dielectric layer 70 is formed on the fins 66 and / or the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy gate dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by a CMP process. The mask layer 74 may be deposited over the dummy gate layer 72.The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other known techniques for depositing the selected material. The dummy gate layer 72 may be formed from other materials that have high etch selectivity by etching the isolation regions. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region 50N and the p-type region 50P.Note that for illustrative purposes, the dummy dielectric layer 70 is shown covering only the fins 66 and the nanostructures 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions 68 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI regions 68.

[0030] Fig. 6A to 18C illustrate various additional steps in the manufacture of embodiment devices. Fig. 6A to 18C illustrate features in either the n-type region 50N or the p-type region 50P. In Fig. 6A to 6C, the mask layer 74 (see Fig. 5) patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The pattern of the masks 78 can be used to separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction substantially perpendicular to the longitudinal direction of the respective fins 66.

[0031] In Fig. 7A to 7C, a first spacer layer 80 and a second spacer layer 82 are deposited over the Fig. 6A to 6C. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. In Fig. 7A to 7C, the first spacer layer 80 is formed on top surfaces of the STI regions 68; top surfaces and sidewalls of the fins 66, the nanostructures 55, and the masks 78; and sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation or by CVD, ALD deposition, or the like. The second spacer layer 82 may be formed from a material with a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0032] After the first spacer layer 80 has been formed and before the second spacer layer 82 is formed, implantations for lightly doped source / drain (LDD) regions (not separately illustrated) may be formed. In embodiments with different device types, similar to the steps described above for Fig. 4, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and appropriate type impurities (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities discussed above, and the p-type impurities may be any of the p-type impurities discussed above.The lightly doped source / drain regions can have an impurity concentration in the range of about 1×10. 15 atoms / cm 3 up to about 1×10 19 atoms / cm 3 An annealing process can be used to repair implantation damage and to activate the implanted impurities.

[0033] In Fig. 8A to 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. As will be explained in more detail below, the first spacers 81 and the second spacers 83 act to self-align subsequently formed source-drain regions, as well as to protect sidewalls of the fins 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer during patterning of the second spacer layer 82, and such that the second spacer layer 82 can act as a mask during patterning of the first spacer layer 80. The second spacer layer 82 can be etched, for example, using an anisotropic etch process, wherein the first spacer layer 80 acts as an etch stop layer, with remaining portions of the second spacer layer 82 forming second spacers 83, as shown in FIG. Fig. 8B. Thereafter, the second spacers 83 act as a mask during the etching of exposed portions of the first spacer layer 80, thereby forming first spacers 81, as shown in Fig. 8B and Fig. 8C illustrates.

[0034] As in Fig. 8B, the first spacers 81 and the second spacers 83 are arranged on sidewalls of the fins 66 and / or nanostructures 55. As shown in Fig. 8C, in some embodiments, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71, and the first spacers 81 are disposed on sidewalls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71.

[0035] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, a different step sequence may be used (e.g., the first spacers 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps.

[0036] In Fig. 9A to 9C, according to some embodiments, first recesses 86 and second recesses 87 are formed in the fins 66, the nanostructures 55, and the substrate 50. Subsequently, epitaxial source / drain regions are formed in the first recesses 86 and in the second recesses 87. The first recesses 86 and the second recesses 87 may extend through the first nanostructures 52 and the second nanostructures 54 and into the substrate 50. As shown in Fig. 9B, the fins 66 may be etched such that bottom surfaces of the first recesses 86 are disposed below the top surfaces of the STI regions 68. In other embodiments, top surfaces of the STI regions 68 may be flush with or higher than bottom surfaces of the first recesses 86. Bottom surfaces of the second recesses 87 may be disposed below the bottom surfaces of the first recesses 86 and the top surfaces of the STI regions 68. The first recesses 86 and the second recesses 87 may be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask portions of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to form the first recesses 86 and the second recesses 87.A single etch process or multiple etch processes may be used to etch each layer of the nanostructures 55 and / or the fins 66. Timed etch processes may be used to stop the etching after the first recesses 86 and the second recesses 87 have reached a desired depth. The second recesses 87 may be etched using the same processes used to etch the first recesses 86, plus an additional etch process before or after etching the first recesses 86. In some embodiments, regions corresponding to the first recesses 86 may be masked while the additional etch process for the second recesses 87 is performed.

[0037] In Fig. 10A to 10C, portions of the sidewalls of the layers of the multilayer stack 64 formed from the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86 and the second recesses 87 are etched to form sidewall recesses 88. Although sidewalls of the first nanostructures 52 are formed adjacent to the sidewall recesses 88 in Fig. 10C as being straight, the sidewalls may also be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In an embodiment where the first nanostructures 52 include, for example, SiGe and the second nanostructures 54 include, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures 52.

[0038] In Fig. 11A to 11D, inner spacers 90 are formed in the sidewall recess 88. The inner spacers 90 can be formed by depositing an inner spacer layer (not separately illustrated) over the Fig. 10A to 10C. The inner spacers 90 serve as isolation features between later-formed source / drain regions and a gate structure. As discussed in more detail below, source / drain regions and epitaxial materials are formed in the first recesses 86 and the second recesses 87, while the first nanostructures 52 are replaced with corresponding gate structures.

[0039] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may be a material such as silicon nitride (SiN) or silicon oxynitride (SiO x Ny ), although any suitable material may be used, such as low dielectric constant (low-k) materials with a k value less than about 3.5. The inner spacer layer may, for example, be SiN, SiO x N y, SiOCN, ZrN, TaCN, SiCN, SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, the like, or a combination thereof. The inner spacer layer may then be anisotropically etched to form the inner spacers 90. Although outer sidewalls of the inner spacers 90 are illustrated as being flush with the sidewalls of the second nanostructures, the outer sidewalls of the inner spacers 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54. In some embodiments, the inner spacers 90 have widths in a range of about 1 nm to about 10 nm, which may be useful for isolating subsequently formed source / drain regions and / or subsequently formed backside vias (see Fig. 29A-29C) from the subsequently formed gate structure may be advantageous. Internal spacers 90 with a thickness less than about 1 nm may be disadvantageous because they may allow short circuits between the subsequent gate structure and the source / drain regions and / or the backside vias. Internal spacers 90 with a thickness greater than about 10 nm may be disadvantageous because they may reduce the widths of the gate structure and / or the source / drain regions, reducing device performance.

[0040] In addition, the outer side walls of the first inner spacers 90, although the outer side walls of the first inner spacers 90 in Fig. 11C are illustrated as straight, may be concave or convex. Fig. 11D exemplifies an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the inner spacers 90 are concave, and the inner spacers 90 are recessed from sidewalls of the second nanostructures 54. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The inner spacers 90 may be used to prevent damage to later formed source / drain regions (such as the epitaxial source / drain regions 92 described below with reference to Fig. 12A to 12E) by subsequent etching processes, such as etching processes used to form gate structures.

[0041] In Fig. 12A to 12D, first epitaxial materials 91 are formed in the second recesses 87, second epitaxial materials 89 are formed in the first recesses 86 and over the first epitaxial materials 91 in the second recesses 87, and epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87 over the second epitaxial materials 89. The first epitaxial materials 91 and the second epitaxial materials 89 formed in the second recesses 87 may also be referred to as dummy semiconductor regions 95. In some embodiments, the dummy semiconductor regions 95 (e.g., comprising the first and second epitaxial materials 89 and 91) may be sacrificial materials that may later be used to form backside vias (such as the backside vias 130 described below with reference to Fig. 30A to 30C). As explained in Fig. 12B to 12D, upper surfaces of the first epitaxial materials 91 may be flush with bottom surfaces of the first recesses 86. However, in some embodiments, upper surfaces of the first epitaxial materials 91 may be disposed below or above bottom surfaces of the first recesses 86.

[0042] The first epitaxial materials 91 may be grown in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial materials 91 may include any acceptable material, such as silicon germanium or the like. The first epitaxial materials 91 may be formed from materials with high etch selectivity to materials of the epitaxial source / drain regions 92, the substrate 50, and dielectric layers (such as the STI regions 68). Thus, the first epitaxial materials 91 may be removed and replaced with the backside vias without substantially removing the epitaxial source / drain regions 92 and the dielectric layers.In some embodiments, the first recesses 86 may be masked while the first epitaxial materials 91 are grown in the second recesses 87, such that the first epitaxial materials 91 are not formed in the first recesses 86. This may be useful for subsequently filling the first recesses with second epitaxial materials 89 (see below), which may be different from the first epitaxial materials 91. After the first epitaxial materials 91 have been formed, the masks in the first recesses 87 may then be removed.

[0043] Then, the second epitaxial materials 89 are formed in the first recesses 86 and in the second recesses 87 over the first epitaxial materials 91. As in Fig. 12B to 12C, top surfaces of the second epitaxial materials 89 may be flush with bottom surfaces of the STI regions 68. However, in some embodiments, top surfaces of the second epitaxial materials 89 may be disposed below or above bottom surfaces of the STI regions 68. The second epitaxial materials 89 may be epitaxially grown in the first recesses 87 and in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The second epitaxial materials 89 may include any acceptable material, such as silicon germanium or the like. In some embodiments, the second epitaxial materials 89 may be substantially the same material as the first epitaxial materials 91.In other embodiments, the second epitaxial materials 89 may differ from the first epitaxial materials 91. The second epitaxial materials 89 and the first epitaxial materials 91 may, for example, each comprise silicon-germanium. However, a germanium concentration of the second epitaxial materials 89 may differ from a germanium concentration of the first epitaxial materials 91. First epitaxial materials 91 that differ from the second epitaxial materials 89 may be useful as dummy material for the subsequent formation of fifth recesses 128 (see FIG. Fig. 24A-C below). The second epitaxial materials 89 may be formed from materials with high etch selectivity to materials of the epitaxial source / drain regions 92, the substrate 50, and the dielectric layers (such as the STI regions 68). Thus, the second epitaxial materials 89 may be removed and replaced with the backside vias without substantially removing the epitaxial source / drain regions 92 and the dielectric layers.

[0044] Then, the epitaxial source / drain regions 92 are formed over the second epitaxial materials 89 in the first recesses 86 and in the second recesses 87. In some embodiments, the epitaxial source / drain regions 92 may exert stress on the second nanostructures 54, thereby improving performance. As shown in Fig. 12C, the epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87 such that each dummy gate 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by an appropriate lateral distance so that the epitaxial source / drain regions 92 are not short-circuited to subsequently formed gates of the resulting nano-FETs.

[0045] The epitaxial source / drain regions 92 in the n-type region 50N, e.g., the NMOS region, can be formed by masking the p-type region 50P, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for N-type nano-FETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 can include materials that exert a tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces that are raised from the respective upper surfaces of the nanostructures 55 and they may have facets.

[0046] The epitaxial source / drain regions 92 in the p-type region 50P, e.g., the PMOS region, can be formed by masking the n-type region 50N, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the p-type region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for p-type nano-FETs. For example, if the first nanostructures 52 are silicon germanium, the epitaxial source / drain regions 92 can comprise materials that exert compressive stress on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have surfaces that are raised from respective surfaces of the multilayer stack 56 and may have facets.

[0047] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process discussed above for forming lightly doped source / drain regions, followed by an annealing process. The source / drain regions may have an impurity concentration of between about 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3 The n-type and / or p-type impurities for source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0048] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, upper surfaces of the epitaxial source / drain regions 92 have facets that extend laterally outward beyond sidewalls of the nanostructures 55. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is complete, as shown in Fig. 12B. In other embodiments, these facets cause adjacent epitaxial source / drain regions 92 of a same nano-FET to merge, as in Fig. 12D. In the Fig. 12B and Fig. In the embodiments illustrated in FIG. 12D, the first spacers 81 may be formed on a top surface of the STI regions 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adapted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 68.

[0049] The epitaxial source / drain regions 92 may include one or more semiconductor material layers. The epitaxial source / drain regions 92 may, for example, include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed from different semiconductor materials and doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B and a higher dopant concentration than the third semiconductor material layer 92C.In embodiments where the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0050] Fig. 12E illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the inner spacers 90 are concave, and the inner spacers 90 are recessed from sidewalls of the second nanostructures 54. As in Fig. 12E, the epitaxial source / drain regions 92 may be formed in contact with the inner spacers 90 and extend beyond the sidewalls of the second nanostructures 54.

[0051] Fig. 12F and Fig. 12G illustrate detailed views of area 85 as shown in Fig. 12B. In some embodiments according to Fig. 12B and Fig. 12F, the widths of the first epitaxial materials 91 and the second epitaxial materials 89 are substantially the same, and the first epitaxial materials 91 have substantially straight sidewalls. In other embodiments according to Fig. 12G, the first epitaxial materials 91 have rounded sidewalls. The first epitaxial materials 91 may have a maximum width, measured between opposing rounded sidewalls, that is greater than a width measured between opposing sidewalls of the second epitaxial materials 89. The rounded sidewalls of the first epitaxial materials 91 may, for example, result from overetching the second recesses 87 into the material of the STI regions 68. Subsequent figures are based on the embodiments in order to simplify the illustration. Fig. 12F. However, it is understood that subsequent processing also applies to the embodiments in Fig. 12G can be applied.

[0052] In Fig. 13A to 13C, a first interlayer dielectric (ILD) layer 96 is formed over the Fig. 12A to 12C. The first ILD 96 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by an acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the masks 78, and the first spacers 81. The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying first ILD 96.

[0053] In Fig. 14A to 14C, a planarization process, such as CMP, may be performed to level the top surface of the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78. The planarization process may also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along sidewalls of the masks 78. After the planarization process, top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are flush, subject to process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 may remain. In this case, the planarization process levels the top surface of the first ILD 96 with top surfaces of the masks 78 and the first spacers 81.

[0054] In Fig. 15A to 15C, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps to form third recesses 98. Portions of the dummy gate dielectrics 60 in the third recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 60 are removed by an anisotropic dry etching process. The etching process may, for example, comprise a dry etching process using one or more reactant gases that selectively etches the dummy gates 76 faster than the first ILD 96 or the first spacers 81. Each of the third recesses 98 exposes and / or overlies portions of nanostructures 55 that serve as channel regions in later completed nano-FETs. Portions of the nanostructures 55 serving as the channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 60 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 60 can then be removed after the dummy gates 76 are removed.

[0055] In Fig. 16A to 16C, the first nanostructures 52 are removed along the third recesses 98. The first nanostructures 52 may be removed by performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 contain, for example, SiGe, and the second nanostructures 54A-54C contain, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructures 52.

[0056] In Fig. 17A to 17C, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. The gate dielectric layers 100 are conformally deposited in the third recesses 98. The gate dielectric layers 100 may be formed on top surfaces and sidewalls of the substrate 50 and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures 54. The gate dielectric layers 100 may also be deposited on top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI regions 68, and on sidewalls of the first spacers 81 and the inner spacers 90.

[0057] According to some embodiments, the gate dielectric layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. In some embodiments, the gate dielectrics may, for example, comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 include a high-k dielectric material, and in these embodiments, the gate dielectric layers 100 may have a k value greater than about 7.0 and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-type region 50N and the p-type region 50P.The formation methods of the gate dielectric layers 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0058] The gate electrodes 102 are each deposited over the gate dielectric layers 100 and fill the remaining portions of the third recesses 98. The gate electrodes 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in Fig. 17A and Fig. 17C, single-layer gate electrodes 102 are illustrated by way of example. The gate electrodes 102 may include any number of liner layers, any number of work-function matching layers, and a fill material. Any combination of the layers forming the gate electrodes 102 may be deposited in the n-type region 50N between adjacent ones of the second nanostructures 54 and between the second nanostructures 54A and the substrate 50, and they may be deposited in the p-type region 50P between adjacent ones of the first nanostructures 52.

[0059] The formation of the gate dielectric layers 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 may occur simultaneously, such that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes, such that the gate dielectric layers 100 are made of different materials and / or have a different number of layers, and / or the gate electrodes 102 in each region may be formed by different processes, such that the gate electrodes 102 may be made of different materials and / or have a different number of layers.When using different processes, different masking steps can be used to mask and expose suitable areas.

[0060] After filling the third recesses 98, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102, the excess portions of which are located above the top surface of the first ILD 96. The remaining material portions of the gate electrodes 102 and the gate dielectric layers 100 thus form replacement gate structures of the resulting nano-FETs. The gate electrodes 102 and the gate dielectric layers 100 may be collectively referred to as "gate structures."

[0061] In Fig. 18A to 18C, the gate structures (including the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) are recessed such that a recess is formed directly above the gate structures and between opposing portions of the first spacers 81. Gate masks 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled into the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts (such as the gate contacts 114 described below with reference to Fig. 20A to 20C) penetrate through the gate masks 104 to come into contact with the upper surfaces of the recessed gate electrodes 102.

[0062] As in Fig.18A to 18C, a second ILD 106 is deposited over the first ILD 96 and over the gate masks 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.

[0063] In Fig. 19A to 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to form fourth recesses 108, thereby exposing areas of the epitaxial source / drain regions 92 and / or the gate structures. The fourth recesses 108 may be formed by etching using an anisotropic etch process, such as RIE, NBE, or the like. In some embodiments, the fourth recesses 108 may be etched through the second ILD 106 and the first ILD 96 using a first etch process; they may be etched through the gate masks 104 using a second etch process; and they may then be etched through the CESL 94 using a third etch process. A mask, such as a photoresist, may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etch process and the second etch process.In some embodiments, the etch process may overetch, and therefore the fourth recesses 108 may extend into the epitaxial source / drain regions 92 and / or the gate structures, and a bottom of the fourth recesses 108 may be flush with (e.g., at the same level or at the same distance from the substrate 50) or lower than (e.g., closer to the substrate 50) the epitaxial source / drain regions 92 and / or the gate structures. Although . Fig. 19C illustrates the fourth recesses 108 as exposing the epitaxial source / drain regions 92 and the gate structures in a same cross-section, in other embodiments the epitaxial source / drain regions 92 and the gate structures may also be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently formed contacts.

[0064] After the fourth recesses 108 are formed, silicide regions 110, also referred to as first silicides 110, are formed over the epitaxial source / drain regions 92. In some embodiments, the first silicide regions 110 are first formed by depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon-germanium, germanium) to form silicide or germanide regions over the exposed portions of the epitaxial source / drain regions 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, and then performing a thermal annealing process to form the first silicide regions 110.The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide regions 110 are referred to as silicide regions, the first silicide regions 110 may also be germanide regions or silicon germanide regions (e.g., regions comprising silicide and germanide). In some embodiments, the first silicide regions 110 comprise TiSi and have a thickness in a range between about 2 nm and about 10 nm.

[0065] In Fig. 20A to 20C, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recesses 108. The source / drain contacts 112 and the gate contacts 114 may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. In some embodiments, for example, the source / drain contacts 112 and the gate contacts 114 each comprise a barrier layer and a conductive material and are each electrically coupled to an underlying conductive feature (e.g., a gate electrode 102 and / or a first silicide region 110). The gate contacts 114 are electrically coupled to the gate electrodes 102, and the source / drain contacts 112 are electrically coupled to the first silicide regions 110. The barrier layer may contain titanium, titanium nitride, tantalum, tantalum nitride or the like.The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from surfaces of the second ILD 106. The epitaxial source / drain regions 92, the second nanostructures 54, and the gate structures (including the gate dielectric layers 100 and the gate electrodes 102) may be collectively referred to as transistor structures 109. The transistor structures 109 may be formed in a device layer, wherein a first interconnect structure (such as the front-side interconnect structure 120 described below with reference to FIG. Fig. 21A to 21C) is formed over a front side thereof and a second connection structure (such as the rear connection structure 136 described below with reference to Fig. 28A to 28I) is formed over a back surface thereof. Although the device layer is described as comprising nano-FETs, other embodiments may include a device layer with other types of transistors (e.g., planar FETs, FinFETs, thin-film transistors (TFTs), or the like).

[0066] Although Fig. 20A to 20C illustrate a source / drain contact 112 extending to each of the epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted from certain one of the epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., backside vias or power rails) may be later applied through a backside of one or more of the epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted or they may be dummy contacts that are not electrically connected to overlying conductive traces (such as the first conductive features 122 described below with reference to Fig. 21A to 21C are explained).

[0067] Fig. 21A to 29C illustrate intermediate steps of forming front-side interconnect structures and back-side interconnect structures on the transistor structures 109. The front-side interconnect structures and the back-side interconnect structures may each include conductive features electrically connected to the nano-FETs formed on the substrate 50. Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A and Fig. 29A illustrate the Fig. 1 illustrated reference cross section A-A'. Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B and Fig. 29B illustrate the Fig. 1 illustrated reference cross section B-B'. Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25C, Fig. 26C, Fig. 27C, Fig. 27D, Fig. 28C, Fig. 28E, Fig. 28F, Fig. 28G, Fig. 28I and Fig. 29C illustrate the Fig. 1 illustrated reference cross-section C-C'. Fig. The process steps illustrated in Figures 21A to 29C can be applied to both the n-type region 50N and the p-type region 50P. As mentioned above, a backside conductive feature (e.g., a backside via or a power rail) can be connected to one or more of the epitaxial source / drain regions 92. Thus, the source / drain regions 112 can optionally be omitted from the epitaxial source / drain regions 92.

[0068] In Fig. 21A to 21C, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on a front side of the transistor structures 109 (e.g., a side of the transistor structures 109 on which active devices are formed).

[0069] The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed within one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material, such as a low-k dielectric material, an extra-low-k (ELK) dielectric material, or the like. The first dielectric layers 124 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, or the like.

[0070] The first conductive features 122 may include conductive traces and conductive vias that interconnect the layers of the conductive traces. The conductive vias may extend through corresponding ones of the first dielectric layers 124 to provide vertical connections between layers of the conductive traces. The first conductive features 122 may be formed using any acceptable process, such as a damascene process, a double damascene process, or the like.

[0071] In some embodiments, the first conductive features 122 may be formed using a damascene process in which a respective first dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired structure of the first conductive features 122. An optional diffusion barrier and / or optional adhesion layer may be deposited, and then the trenches may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like.In one embodiment, the first conductive features 122 may be formed by depositing a growth layer of copper or a copper alloy and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process may be used to remove excess conductive material from a surface of the respective first dielectric layer 124 and to planarize surfaces of the first dielectric layer 124 and the first conductive features 122 for subsequent processing.

[0072] Fig. 21A to 21C illustrate five layers of conductive features 122 and the first dielectric layers 124 in the front-side interconnect structure 120. However, it should be appreciated that the front-side interconnect structure 120 may include any number of first conductive features 122 disposed within any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to the gate contacts 114 and the source / drain contacts 112 to form functional circuits. In some embodiments, the functional circuits formed by the front-side interconnect structure 120 may include logic circuits, memory circuits, image sensor circuits, or the like.

[0073] In Fig. 22A to 22C, a support substrate 150 is bonded to a top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as a bonding layer 152). The support substrate 150 may be a glass support substrate, a ceramic support substrate, a wafer (e.g., a silicon wafer), or the like. The support substrate 150 may provide structural support during subsequent processing steps and in the finished device.

[0074] In various embodiments, the carrier substrate 150 may be bonded to the front-side interconnect structure 120 using a suitable technique, such as dielectric-to-dielectric bonding or the like. The dielectric-to-dielectric bonding may include depositing the first bonding layer 152A on the front-side interconnect structure 120. In some embodiments, the first bonding layer 152A comprises silicon oxide (e.g., a high-density plasma (HDP) oxide or the like) deposited by CVD, ALD, PVD, or the like. The second bonding layer 152B may also be an oxide layer formed on a surface of the carrier substrate 150 prior to bonding, for example, using CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may also be used for the first bonding layer 152A and the second bonding layer 152B.

[0075] The dielectric-to-dielectric bonding process may further include applying a surface treatment to the first bonding layer 152A and / or the second bonding layer 152B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a deionized water rinse or the like) that may be applied to one or more of the bonding layers 152. The carrier substrate 150 is then aligned with the front-side interconnect structure 120, and the two are pressed against each other to initiate pre-bonding of the carrier substrate 150 to the front-side interconnect structure 120. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C).After pre-bonding, an annealing process may be applied, for example by heating the front-side interconnect structure 120 and the carrier substrate 150 to a temperature, for example, between about 170 °C and about 500 °C.

[0076] Furthermore, the device is Fig. 22A to 22C, after the carrier substrate 150 has been bonded to the front-side interconnect structure 120, the carrier substrate 150 is rotated such that a backside of the transistor structures 109 faces upward. The backside of the transistor structures 109 may refer to a side opposite the frontside of the transistor structures 109 on which the active devices are formed.

[0077] In Fig. 23A to 23C, a thinning process may be applied to the backside of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, or the like), an etch-back process, a combination thereof, or the like. The thinning process may expose surfaces of the first epitaxial materials 91 opposite the front-side interconnect structure 120. Furthermore, a portion of the substrate 50 may remain above the gate structures (e.g., the gate electrodes 102 and the gate dielectric layers 100) and the nanostructures 55 after the thinning process. As shown in Fig. 23A to 23C, back surfaces of the substrate 50, the first epitaxial materials 91, the STI regions 68, and the fins 66 may be flush with each other after the thinning process.

[0078] In Fig. 24A to 24C, the first epitaxial materials 91 and first portions of the second epitaxial materials 89 located between the first epitaxial materials 91 and the source / drain regions 92 are removed to form fifth recesses 128. Subsequently, in the fifth recesses 128 (see Fig. 29A-29C below), prior to removing remaining portions of the fins 66 and the substrate 50, back vias may be formed, which may be useful for achieving wider back vias, thereby enabling larger contact areas for obtaining better contact resistance and improved device performance. The first epitaxial materials 91 and the first portions of the second epitaxial materials 89 may be removed by a suitable etching process, which may be an isotropic etching process, such as a wet etching process. In some embodiments, the etching process may remove portions of the epitaxial source / drain regions 92, producing convex bottoms of the fifth recesses 128.In other embodiments, the etching process may have a high etch selectivity toward materials of the first epitaxial materials 91 and the first portions of the second epitaxial materials 89, such that the first epitaxial materials 91 and the first portions of the second epitaxial materials 89 may be removed without substantially removing materials of the STI regions 68 or the epitaxial source / drain regions 92. The fifth recesses 128 may expose sidewalls of the STI regions 68, back surfaces of the epitaxial source / drain regions 92, sidewalls of the first spacers 81, and sidewalls of the inner spacers 90.

[0079] In Fig. 25A to 25C, a mask 204 is formed in the fifth recesses 128. In some embodiments, mask 204 may be formed, for example, from a dielectric, an organic material, a bottom anti-reflective coating (BARC) material, or the like, and deposited, for example, by spin coating, PECVD, CVD, or the like. After deposition, an etch-back process may be performed to remove the material from outside the fifth recesses 128 and partially expose sidewalls of the fifth recesses 128, thereby forming the mask 204. The etch-back process may recess the mask below upper surfaces of the substrate 50 and further below upper surfaces of the STI regions 68 such that upper sidewalls of the fifth recesses 128 are exposed. The mask 204 may be formed to a thickness in the range of about 20 nm to about 40 nm.The mask 204 may be used in a subsequent process to widen the fifth recesses 128, as described below with reference to FIG. Fig. 26A to 26C, and it may be deposited to a desired thickness to control the shape of the fifth recess 128 after the widening process. The mask 204 may further protect underlying source / drain regions 92 during subsequent etch processes.

[0080] In Fig. 26A to 26C, the fifth recesses 128 are widened and the mask 204 is removed. Widening the fifth recesses 128 may further round sidewalls of the fifth recesses 128. The fifth recesses 128 may be widened by a suitable etching process, such as a dry etching process or the like. The dry etching may use an etching gas suitable for etching silicon, such as O2, Cl2, HCl, HBr, the like, or a combination thereof. The etching process may etch sidewalls of the substrate 50 and the STI regions 68 exposed by the fifth recesses 128 (e.g., not covered by the mask 204). As shown in Fig. 26B and Fig. 26C, the fifth recesses 128 may have tapered profiles after the etch process, tapering toward the front side of the device. A ratio of the maximum width RW1 of the fifth recesses 128 to a minimum width RW2 of the fifth recesses 128 may be from about 1.1 to about 1.8. Widening the fifth recesses 128 may allow for subsequent formation of larger backside vias, which advantageously reduces contact resistance and reduces the likelihood of contacts to the backside vias being misaligned. After widening the fifth recesses 128, the mask 204 may then be removed using a suitable process, such as a BARC-selective etch, an ashing process, or the like.

[0081] In Fig. 27A to 27C, a first liner 206, also referred to as a first dielectric liner 206, is formed on sidewalls of the fifth recesses 128. The first liner 206 may be formed by depositing a first liner layer (not separately illustrated) over the Fig. 26A to 26C. The first liner layer may be deposited by CVD, ALD, or the like. The first inner liner may be formed of silicon nitride (SiN), silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multilayers thereof, or the like.

[0082] The first liner layer is then etched to form the first liner 206. The first liner layer may be etched using suitable etching processes, wet etching, a dry etching, combinations thereof, or the like. The etching process may be anisotropic in some embodiments. The etching process removes lateral portions of the first liner layer and leaves the first liner 206 on sidewalls of the fifth recesses 128. In some embodiments, the etching process may further remove the first liner 206 from upper portions of the fifth recesses 128 (see, e.g., Fig. 34D). The first liner 206 may have a thickness in a range of about 1 nm to about 5 nm, which may be advantageous because it facilitates subsequent formation of second silicide regions 129 (see Fig. 28A-C below) on sidewalls of substrate 50. A thickness of the first liner 206 of less than about 1 nm may be disadvantageous because it may lead to increased formation of second silicide regions 129 on sidewalls of substrate 50. A thickness of the first liner 206 greater than about 5 nm may be disadvantageous because it may lead to a narrowing of the width of subsequently formed backside vias 130 (see Fig. 29A-C below), which may degrade device performance.

[0083] In Fig. 28A to 28C, second silicide regions 129, also referred to as second silicides 129, are formed in the fifth recesses 128 on backsides of the epitaxial source / drain regions 92. Forming the second silicide regions 129 before removing the remaining portions of the fins 66 and the substrate 50 may be useful for improving silicide formation by allowing a larger surface area of ​​the second silicide regions 129. This may reduce the contact resistance of the later formed backside vias (see Fig. 29A-29C below). In some embodiments, the second silicide regions 129 are first formed by depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying backsides of the epitaxial source / drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions over the exposed portions of the backsides of the epitaxial source / drain regions 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, and then performing a thermal annealing process to form the second silicide regions 129. The unreacted portions of the deposited metal are then removed, for example, by an etching process.Although the second silicide regions 129 are referred to as silicide regions, the second silicide regions 129 may also be germanide regions or silicon germanide regions (e.g., regions comprising silicide and germanide). In some embodiments, the second silicide regions 129 in the n-type region 50N comprise TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, the like, or a combination thereof, and the second silicide regions 129 in the p-type region 50P comprise NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, the like, or a combination thereof.

[0084] In some embodiments, the second silicide regions 129 have a thickness in a range between about 1 nm and about 10 nm, which may be advantageous for reducing contact resistance and improving device performance. A thickness of the second silicide regions 129 less than about 1 nm may be disadvantageous because the silicide may be too thin, resulting in increased contact resistance due to ineffective silicide thickness. A thickness of the second silicide regions 129 greater than about 10 nm may be disadvantageous because it may lead to higher resistance, degrading device performance.

[0085] In Fig. 29A to 29C, backside vias 130, also referred to as contacts or conductive contacts 130, are formed in the fifth recesses 128. Forming the backside vias 130 before removing remaining portions of the fins 66 and the substrate 50 may be useful for achieving larger widths of the backside vias 130. This may result in larger contact areas with the underlying source / drain regions 92, which may reduce contact resistance and achieve better device performance. The backside vias 130 may include one or more layers, such as barrier layers, diffusion layers, and fill materials. The backside vias 130 may be electrically coupled to the epitaxial source / drain regions 92 through the second silicide regions 120.The backside vias 130 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), combinations thereof, or the like. A planarization process, such as CMP, may be performed to remove excess material from surfaces of the substrate 50 and the STI regions 68.

[0086] In some embodiments, the rear vias 130 extend as shown in Fig. 29C, to a depth D1 measured from a level of a top surface of the gate electrode 102 to a bottom vertex of the backside vias 130, and the depth D1 may range from about 0.5 nm to about 10 nm. In other embodiments, the bottom vertices of the backside vias 130 are level with the top surface of the gate electrode 102 (not illustrated).

[0087] In Fig. 30A to 30C, remaining portions of the fins 66 and the substrate 50 are removed. The fins 66 and the substrate 50 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The etching process may be selective to the material of the fins 66 and the substrate 50 (e.g., the material of the fins 66 and the substrate 50 may etch faster than the material of the backside vias 130, the first liner 206, the STI regions 68, the gate dielectric layers 100, the inner spacers 90, and the epitaxial source / drain regions 92). After etching the fins 66 and the substrate 50, areas of the STI regions 68, the dielectric gate layers 100, the inner spacers 90 and the epitaxial source / drain regions 92 can be exposed.Removing the remaining portions of the fins 66 may form sixth recesses 210 exposing back surfaces of the gate dielectric layers 100 and epitaxial source / drain regions 92. In some embodiments, the etching process may remove exposed back portions of the epitaxial source / drain regions 92, creating concave back surfaces of the epitaxial source / drain regions 92. The sixth recesses 210 may extend to the same or a different depth than the previously discussed fifth recesses 128 (see FIG. Fig. 24A to 24C) and the corresponding rear vias 130 formed in the fifth recesses 128.

[0088] In Fig. 31A to 31C is in the sixth recesses 210 and over exposed surfaces of the Fig. 30A to 30C, an insulating plug 212 is filled. In some embodiments, the insulating plug 212 includes a convex bottom profile that is in physical contact with an epitaxial source / drain region 92. In some embodiments, the insulating plug 212 includes a second liner 214, also referred to as a second dielectric liner 214, and a second dielectric layer 125. Forming the second liner 214 and the second dielectric layer 125 on the outer sidewalls of the back vias 130 may allow the back vias 130 to be formed with larger widths, which may improve contact resistance and device performance.In some embodiments, the second liner 214 is formed over the first liner 206, the STI regions 68, the gate dielectric layers 100, the epitaxial source / drain regions 92, and the inner spacers 90. The second liner may comprise a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multilayers thereof, or the like.

[0089] The second liner 214 may have a thickness in a range of about 1 nm to about 10 nm, which may be advantageous for protecting the underlying epitaxial source / drain regions 92 from a subsequent annealing process performed on the second dielectric layer 125 (see below). A second liner 214 with a thickness less than about 1 nm may be disadvantageous because it may not be thick enough to protect the underlying epitaxial source / drain regions 92 from the subsequent annealing process. A second liner 214 with a thickness greater than about 10 nm may be disadvantageous because its relatively high k-value may lead to an undesirably high parasitic capacitance.

[0090] The second dielectric layer 125 is formed over the second liner 214. In some embodiments, the second dielectric layer 125 is a flowable film formed by FCVD or the like. In some embodiments, the second dielectric layer 125 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.In some embodiments, the second dielectric layer 125 comprises silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multilayers thereof, or the like. In some embodiments, the second dielectric layer 125 and the second liner 214 may comprise substantially the same material. In other embodiments, the second dielectric layer 125 may comprise a different material than the second liner 214. For example, the second dielectric layer 125 may have a lower k-value than the second liner 214.

[0091] In some embodiments, an annealing process is performed after the second dielectric layer 125 is formed to prevent oxidation of the second dielectric layer 125 and improve its dielectric properties. A CMP process or the like may be used to remove material from the second dielectric layer 125 and the second liner 214 so that upper surfaces of the second dielectric layer 125 and the second liner 214 are flush with upper surfaces of the STI regions 68 and the backside vias 130.

[0092] In Fig. 32A to 32C, conductive lines 134 and a third dielectric layer 132 are formed over the second dielectric layer 125, the STI regions 68, and the backside vias 130. The third dielectric layer 132 may be similar to the second dielectric layer 125. For example, the third dielectric layer 132 may be formed from a similar material and using similar processes as the second dielectric layer 125.

[0093] The conductive traces 134 are formed in the third dielectric layer 132. Forming the conductive traces 134 may, for example, comprise patterning recesses in the third dielectric layer 132 using a combination of photolithography and etching processes. A pattern of the recesses in the third dielectric layer 132 may correspond to a pattern of the conductive traces 134. The conductive traces 134 are then formed by depositing a conductive material in the recesses. In some embodiments, the conductive traces 134 comprise a metal layer, which may be a single layer or a composite layer consisting of a plurality of sublayers formed from different materials. In some embodiments, the conductive traces 134 comprise copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like.An optional diffusion barrier and / or optional adhesion layer may be deposited before filling the recesses with the conductive material. Suitable materials for the barrier layer / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. The conductive lines 134 may be formed, for example, using CVD, ALD, PVD, plating, or the like. The conductive lines 134 are physically and electrically coupled to the epitaxial source / drain regions 92 via the backside vias 130 and the second silicide regions 129. A planarization process (e.g., CMP, grinding, etching back, or the like) may be performed to remove excess portions of the conductive lines 134 formed above the third dielectric layer 132.

[0094] In some embodiments, the conductive traces 134 are power rails, which are conductive traces that electrically connect the epitaxial source / drain regions 92 to a reference voltage, a supply voltage, or the like. Advantages can be achieved by placing power rails on a backside of the resulting semiconductor die rather than on a frontside of the semiconductor die. For example, a gate density of the nano-FETs and / or connection density of the front-side interconnect structure 120 can be increased. Furthermore, the backside of the semiconductor die can accommodate wider power rails, which reduces resistance and increases the efficiency of power delivery to the nano-FETs. A width of the conductive traces 134 can, for example, be at least twice a width of the conductive traces (e.g., first conductive features 122) of the front-side interconnect structure 120.

[0095] In Fig. 33A to 34C, remaining portions of a backside interconnect structure 136 are formed over the third dielectric layer 132 and the conductive lines 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on a backside of the transistor structures 109 (e.g., a side of the transistor structures 109 opposite the side of the transistor structure 109 on which active devices are formed). The backside interconnect structure 136 may include the second dielectric layer 125, the third dielectric layer 132, the backside vias 130, and the conductive lines 134.

[0096] The remaining portions of the rear connection structure 136 may comprise materials and be formed using processes that are the same or similar to those used for the front connection structure 120 described above with reference to Fig. 21A to 21D. In particular, the backside interconnect structure 136 may include stacked layers of second conductive features 140 formed in fourth dielectric layers 138. The second conductive features 140 may include routing lines (e.g., for routing to and from subsequently formed contact pads and external connectors). The second conductive features 140 may be further patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, or the like. The embedded passive devices may be integrated into the conductive traces 134 (e.g., the power rail) to provide circuitry (e.g., power circuitry) on the backside of the Nano-FETs.

[0097] In Fig. 34A to 34C, a passivation layer 144, UBMs 146, and external connectors 148 are formed over the backside interconnect structure 136. The passivation layer 144 may comprise a polymer, such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 144 may contain non-organic dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 144 may be deposited, for example, by CVD, PVD, ALD, or the like.

[0098] The UBMs 146 are formed through the passivation layer 144 to the second conductive features 140 in the backside interconnect structure 136, and the external connectors 148 are formed on the UBMs 146. The UBMs 146 may include one or more layers of copper, nickel, gold, or the like formed by a plating process or the like. The external connectors 148 (e.g., solder balls) are formed on the UBMs 146. Forming the external connectors 148 may include placing solder balls on exposed portions of the UBMs 146 and reflowing the solder balls. In some embodiments, forming the external connectors 148 includes performing a plating step to form solder regions over the topmost second conductive features 140 and then reflowing the solder regions.The UBMs 146 and external connectors 148 can be used to provide input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs 146 and external connectors 148 can also be referred to as rear input / output pads, which can provide signal, supply voltage, and / or ground connections to the nano-FETs described above.

[0099] Fig. 34D to 34F illustrate detailed views of the areas in Fig. 34B and Fig. 34C. Fig. Figure 34D illustrates a detailed view of the Fig. 34C according to some embodiments. The backside vias 130 may have a minimum first width W1 measured between opposite sidewalls at the level of the second dielectric layer 125 above the inner spacers 90 along cross section CC' in Fig. 1, in a range of about 25 nm to about 50 nm, which may be advantageous because it may enable lower contact resistance, which may improve device performance. A first width W1 less than about 25 nm may be disadvantageous because it may lead to higher contact resistance, which may degrade device performance. A first width W1 greater than about 50 nm may be disadvantageous because it may increase the risk of leakage to adjacent backside vias 130. The backside vias 130 may have a minimum first height H1, measured from a top surface of the backside vias 130 to a bottom vertex of the backside vias 130, in a range of about 15 nm to about 50 nm, which may be important for achieving a good connection between the device and later formed conductive lines 134 (see Fig. 32A-C below) may be advantageous. A first height H1 less than about 15 nm may be disadvantageous because it may result in a high risk of leakage between the device and the subsequently formed conductive lines 134. A first height H1 greater than about 50 nm may be disadvantageous because it may result in higher resistance for the backside vias 130.

[0100] The epitaxial source / drain regions 92 may have a minimum second width W2, measured between opposite sidewalls of the second nanostructures 54 along cross section CC' in Fig. 1, in a range of about 15 nm to about 25 nm, which may be advantageous because it may lower the source / drain resistance, which may improve device performance. A second width W2 less than about 15 nm may be disadvantageous because a narrower W2 may increase the source / drain resistance and degrade device performance. A second width W2 greater than about 25 nm may be disadvantageous because it may lead to degradation of device performance due to the reduction in gate length and spacer width. In some embodiments, the first width W1 is greater than the second width W2, which may be useful for lowering contact resistance and improving device performance.

[0101] Fig. 34E and Fig. 34F each illustrate detailed views of the Fig. 34B according to some embodiments. The backside vias 130 may have a minimum third width W3 measured between opposite sidewalls of the first liner 206 along cross section BB' in Fig. 1, in a range of about 5 nm to about 50 nm, which may be advantageous because it may lower the resistance for backside vias 130, which may improve device performance. A first width W3 less than about 5 nm may be disadvantageous because it may result in higher resistance for backside vias 130, which may reduce device performance. A third width W3 greater than about 50 nm may be disadvantageous because it may increase the risk of leaks to adjacent backside vias 130. The insulating plugs 212 may have a minimum fourth width W4, measured between opposite sidewalls of the STI regions 68 along cross section CC' in Fig. 1, in a range of about 10 nm to about 30 nm. In some embodiments, the third width W3 of the backside vias 130 is greater than the fourth width W4 of the insulating plugs 212. In some embodiments, the first width W1 of the backside vias 130 is greater than the fourth width W4 of the insulating plugs 212.

[0102] Fig. 35A to 35E illustrate other embodiments in which the epitaxial source / drain regions 92 are separated by insulating fins 280. Fig. 35A is illustrated along cross section AA' and shows a similar structure to Fig. 34A, but with insulating fins 280 adjacent to the gate electrode 102, and the gate dielectric 100 covers the insulating fins 280. Fig. Figure 35B is illustrated along cross section BB' and shows a similar structure to Fig. 35B, but with the epitaxial source / drain regions 92 disposed between the insulating fins 280, and the CESL 94 covering the insulating fins 280. Fig. Figure 35C is illustrated along cross section CC' and shows a substantially similar structure to Fig. 34C. The insulating fins 280 can be formed after the fins 66 have been formed by etching (see Fig. 4) and before formation of the dummy gates 76 (see Fig. 5). The insulating fins 280 may be formed by depositing a sacrificial layer (not explicitly illustrated) on sidewalls of the fins 66 using a conformal deposition process, such as CVD, ALD, PECVD, or the like. In some embodiments, the sacrificial material is a semiconductor material (e.g., SiGe, Si, or the like) having a same material composition as the first semiconductor material 51 or the second semiconductor material 53. The sacrificial material may define recesses between the fins 66 above the sacrificial material and between sidewalls of the sacrificial material. One or more insulating materials may be deposited in the recesses to form the insulating fins 280. For example, a liner 281 and a fill material 283 may be deposited in the recesses by CVD, ALD, PECVD, or the like. The liner 281 may, for example, be a nitride (e.g.,Silicon nitride) or the like, and the fill material 283 may comprise, for example, an oxide (e.g., silicon oxide) or the like. In embodiments, a portion of the liner 281 and the fill material 283 may be partially etched, and a high-k material 285, such as HfO, ZrO, or the like, may be deposited into the recess over the liner 281 and the fill material 283.

[0103] The insulating fins 280 provide an insulating boundary between adjacent epitaxial source / drain regions 92, which may have different conductivity types. After the insulating fins 280 have been formed, the sacrificial material may be removed along with the removal of the first semiconductor material 51 and / or the second semiconductor material 53 to define the nanostructures 52.

[0104] Fig. 35D and Fig. 35E illustrate detailed views of the Fig. 35B shown area 600 or in Fig. 35B, according to some embodiments. In some embodiments, the epitaxial source / drain regions 92 may contact sidewalls of the insulating fins 280, and a portion of the first ILD 96 may be deposited between the insulating fins 280, the STI regions 68, and the first liner 206 or the second liner 214. The portions of the first ILD 96 may result in the backside vias 130 and the insulating plugs 212 forming bottleneck profiles where an upper width is smaller than a lower width. Fig. 35D illustrates a minimum fifth width W5 of the back vias 130 at a level with a bottom surface of the STI regions 68 and a sixth width W6 of the back vias 130 measured across the widest portion of the back vias 130 below the STI regions 68. The fifth width W5 is less than the sixth width W6, thereby forming a bottleneck profile of the back vias 130. Fig. 35E illustrates a minimum seventh width W7 of the insulating plug 212 at a level with a bottom surface of the STI regions 68 and an eighth width W8 of the insulating plug 212 measured across the widest portion of the insulating plug 212 below the STI regions 68. The seventh width W7 is smaller than the eighth width W8, thereby forming a bottleneck profile of the backside vias 130.

[0105] Embodiments can achieve advantages. Backside vias can be widened by forming the backside vias before removing remaining portions of the fins and substrates. Liner formation and subsequent etching processes do not need to reduce the width of the backside vias because they are applied to the outside of the backside vias. By forming the wider backside vias before fin and substrate removal, better contact resistance, silicide formation, and resulting device performance can be achieved.

[0106] According to some embodiments, a device comprises: a device layer comprising a first transistor; a first interconnect structure on a front side of the device layer; and a second interconnect structure on a back side of the device layer.The second interconnect structure comprises: a first dielectric material on the backside of the device layer; a contact extending through the first dielectric material to a first source / drain region of the first transistor, wherein a first width of the contact is greater than a second width of the first source / drain region, wherein the first width of the contact is measured at a level of the first dielectric material and the second width of the first source / drain region is measured from a first nanostructure of the first transistor to a second nanostructure; and a first conductive layer including a first conductive line electrically connected to the first source / drain region through the contact. In one embodiment, the first width is in a range of 25 nm to 50 nm, the second width is in a range of 15 nm to 25 nm, and the contact has a height in a range of 15 nm to 50 nm.In one embodiment, the device further comprises an insulating spacer on a sidewall of the first contact, the spacer separating the contact from the first dielectric material. In one embodiment, the insulating spacer extends closer to the first interconnect structure than the first dielectric material.

[0107] According to some embodiments, a device comprises: a first transistor in a device layer, the first transistor comprising a first source / drain region and a second source / drain region; a first dielectric material on the backside of the device layer; a first conductive contact extending through the first dielectric material to the first source / drain region; and an insulating plug extending through the first dielectric material to the second source / drain region, wherein a first width of the first conductive contact is greater than a second width of the insulating plug, the first width and the second width each being measured at a level of the first dielectric material.In one embodiment, the insulating plug comprises: a dielectric liner on sidewalls of the first dielectric material; and a second dielectric material, wherein the dielectric liner separates the second dielectric material from the first dielectric material, and wherein the dielectric liner separates the second dielectric material from the second source / drain region. In one embodiment, the first dielectric material is a shallow trench isolation (STI) region. In one embodiment, the insulating plug comprises a convex bottom profile that physically contacts the second source / drain region. In one embodiment, the insulating plug comprises a bottleneck profile.

[0108] According to some embodiments, a method comprises: forming a first transistor on a semiconductor substrate, the first transistor comprising a first source / drain region; planarizing the semiconductor substrate to expose a dummy semiconductor region; removing the dummy semiconductor region to define a first opening exposing a backside of the first source / drain region; widening the first opening, wherein widening the first opening comprises etching the semiconductor substrate; after widening the first opening, forming a contact in the first opening, the contact electrically coupled to the first source / drain region; and after forming the contact in the first opening, removing remaining portions of the semiconductor substrate.In one embodiment, removing remaining portions of the semiconductor substrate defines a second opening extending through a shallow trench isolation region, the method further comprising forming an insulating plug in the second opening, and wherein the insulating plug extends to a second source / drain region of the first transistor. In one embodiment, forming the insulating plug comprises: depositing a first dielectric liner on sidewalls and a bottom surface of the second opening; and depositing a first dielectric material in the second opening over the first dielectric liner. In one embodiment, the method further comprises: prior to forming the contact in the first opening, depositing a second dielectric liner on sidewalls of the first opening.In one embodiment, the method further comprises: prior to forming the contact in the first opening, forming a silicide on the backside of the first source / drain region. In one embodiment, the method further comprises: depositing a mask in the first opening, wherein the mask covers the first source / drain region during widening of the first opening; and removing the mask prior to forming the contact in the first opening. In one embodiment, the mask comprises a bottom anti-reflection coating (BARC) material. In one embodiment, the first opening has a maximum width and a minimum width after widening of the first opening, wherein a ratio of the maximum width to the minimum width is in a range of 1.1 to 1.8. In one embodiment, etching the semiconductor substrate comprises performing a dry etching process using O2, Cl2, HCl, or HBr.In one embodiment, a first width of the contact is greater than a second width of the first source / drain region, wherein the first width of the contact is measured at a shallow trench isolation (STI) region level, the contact extending through the STI region, and the second width of the first source / drain region is measured from a first nanostructure of the first transistor to a second nanostructure. In one embodiment, the first width is in a range of 25 nm to 50 nm, and the second width is in a range of 15 nm to 25 nm.

[0109] The foregoing provides an overview of the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same benefits of the embodiments presented herein.

Claims

[1] Device comprising: a device layer comprising a first transistor (109); a first interconnect structure (110, 112, 114, 120, 152) on a front side of the device layer; and a second interconnect structure (129, 130, 134, 136, 146, 148) on a backside of the device layer, the second interconnect structure (129, 130, 134, 136, 146, 148) comprising: a first dielectric material (68) on the backside of the device layer; a contact (129, 130) extending through the first dielectric material (68) to a first source / drain region (92) of the first transistor (109), wherein a first width (W1) of the contact (129, 130) is greater than a second width (W2) of the first source / drain region (92), wherein the first width (W1) of the contact (129, 130) is measured at a level of the first dielectric material (68) and the second width (W2) of the first source / drain region (92) is measured from a first nanostructure (54, 54A-54C) of the first transistor (109) to a second nanostructure (54, 54A-54C); and a first conductive layer comprising a first conductive trace (134) electrically connected to the first source / drain region (92) through the contact (129, 130); wherein the device further comprises an insulating spacer (206, 214) on a sidewall of the contact (129, 130), the spacer (206, 214) separating the contact (129, 130) from the first dielectric material (68). [2] The device of claim 1, wherein the first width (W1) is in a range of 25 nm to 50 nm, the second width (W2) is in a range of 15 nm to 25 nm, and the contact (129, 130) has a height (H1) in a range of 15 nm to 50 nm. [3] The device of claim 1, wherein the insulating spacer (206, 214) extends closer to the first interconnect structure (110, 112, 114, 120, 152) than the first dielectric material (68). [4] Device comprising: a first transistor (109) in a device layer, the first transistor (109) comprising a first source / drain region (92) and a second source / drain region (92); a first dielectric material (68) on the backside of the device layer; a first conductive contact (129, 130) extending through the first dielectric material (68) to the first source / drain region (92); and an insulating plug (212) extending through the first dielectric material (68) to the second source / drain region (92), wherein a first width (W3) of the first conductive contact (129, 130) is greater than a second width (W4) of the insulating plug (212), wherein the first width (W3) and the second width (W4) are each measured at a level of the first dielectric material (68). [5] The device of claim 4, wherein the insulating plug (212) comprises: a dielectric liner (214) on sidewalls of the first dielectric material (68); and a second dielectric material (125), wherein the dielectric liner (214) separates the second dielectric material (125) from the first dielectric material (68), and wherein the dielectric liner (214) separates the second dielectric material (125) from the second source / drain region (92). [6] The device of claim 4, wherein the first dielectric material (68) is a shallow trench isolation (STI) region. [7] The device of claim 4, wherein the insulating plug (212) comprises a convex bottom profile that physically contacts the second source / drain region (92). [8] The device of claim 4, wherein the insulating plug (212) comprises a bottleneck profile. [9] Method comprising: Forming a first transistor (109) on a semiconductor substrate (50), the first transistor (109) comprising a first source / drain region (92); Planarizing the semiconductor substrate (50) to expose a dummy semiconductor region (95, 91, 89); Removing the dummy semiconductor region (95, 91, 89) to define a first opening (128) exposing a backside of the first source / drain region (92); Widening the first opening (128), wherein widening the first opening (128) comprises etching the semiconductor substrate (50); after widening the first opening (128), forming a contact (129, 130) in the first opening (128), the contact (129, 130) being electrically coupled to the first source / drain region (92); and after forming the contact (129, 130) in the first opening (128), removing remaining portions of the semiconductor substrate (50). [10] The method of claim 9, wherein removing remaining portions of the semiconductor substrate (50) defines a second opening (210) extending through a shallow trench isolation region (68), the method further comprising forming an insulating plug (212) in the second opening (210), and wherein the insulating plug (212) extends to a second source / drain region (92) of the first transistor (109). [11] The method of claim 10, wherein forming the insulating plug (212) comprises: Depositing a first dielectric lining (214) on sidewalls and a bottom surface of the second opening (210); and Depositing a first dielectric material (125) in the second opening (210) over the first dielectric liner (214). [12] The method of claim 9, further comprising depositing a second dielectric liner (206) on sidewalls of the first opening (128) prior to forming the contact (129, 130) in the first opening (128). [13] The method of claim 9, further comprising forming a silicide (129) on the backside of the first source / drain region (92) prior to forming the contact (129, 130) in the first opening (128). [14] The method of claim 9, further comprising: Depositing a mask (204) in the first opening (128), the mask covering the first source / drain region (92) during the widening of the first opening (128); and Removing the mask (204) before forming the contact (129, 130) in the first opening (129, 130). [15] The method of claim 14, wherein the mask (204) comprises a bottom anti-reflection coating (BARC) material. [16] The method of claim 9, wherein the first opening (128) comprises a maximum width (RW1) and a minimum width (RW2) after widening the first opening (128), the ratio of the maximum width (RW1) to the minimum width (RW2) being in a range of 1.1 to 1.

8. [17] The method of claim 9, wherein etching the semiconductor substrate (50) comprises performing a dry etching process using O2, Cl2, HCl or HBr. [18] The method of claim 9, wherein a first width (W1) of the contact (129, 130) is greater than a second width (W2) of the first source / drain region (92), the first width (W1) of the contact (129, 130) being measured at a level of a shallow trench isolation (STI) region (68), the contact (129, 130) extending through the STI region (68), and the second width (W2) of the first source / drain region (92) being measured from a first nanostructure (54, 54A-54C) of the first transistor (109) to a second nanostructure (54, 54A-54C). [19] The method of claim 18, wherein the first width (W1) is in a range of 25 nm to 50 nm and the second width (W2) is in a range of 15 nm to 25 nm.

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