Chip package, semiconductor device, method of forming a chip package, and method of forming a semiconductor device

Abstract

A chip package (200) comprising: a semiconductor chip (102); a packaging material (106) at least partially surrounding the semiconductor chip (102) and in physical contact with the semiconductor chip (102), having an opening (220) extending from a top surface of the packaging material (106) to the chip (102) and / or to an electrical contact structure contacting the chip (102); a thermally conductive material (222) in the opening (220), the thermally conductive material (222) being configured to conduct heat from the chip (102) to an outside; wherein the thermally conductive material (222) was in a viscous state when arranged in the opening (220), completely fills the opening and extends laterally, at least partially, over the upper surface (106T) of the packaging material (106).

Description

Technical field

[0001] Various embodiments generally relate to a chip package, a semiconductor device, a method of forming a chip package, and a method of forming a semiconductor device. background

[0002] It is well known to mount a cooling structure on one side of a chip package to dissipate heat from the chip and protect it from overheating. The need for effective heat dissipation is particularly important for devices such as power semiconductor chips, which operate under high power and voltage conditions. However, in some cases, the increasing demand for higher computing power and / or higher voltage has led to increased heat dissipation requirements, which are difficult to achieve with a single-sided cooling solution.

[0003] As a result, two-sided cooling devices, in which cooling structures are provided on opposite sides of a chip package, have emerged as a solution to meet the increased demands for more efficient heat dissipation. Fig. 1A to 1C are cross-sectional views illustrating known methods for manufacturing a chip package 100 with a double-sided cooling structure. Fig. 6A and Fig. 6B are corresponding schematic diagrams showing how chip packages 100 resulting from manufacturing processes Fig. 1A to 1C, in some implementations may look like this. Referring back to Fig. 1A, the method may include attaching a first side of a chip 102 to a lead frame 104 and attaching a clamp 108 to a second opposite side of the chip 102. In the example Fig. 1A-1C, the clamp includes a heat spreader portion 108A positioned over and thermally coupled to the chip 102 to conduct heat away from the chip 102. The heat spreader portion 108A comprises a metallic material such as copper or aluminum. The clamp 108 further includes a connection portion 108B whose function is to electrically connect one or more contact pads on the chip 102 to a conductor 110 on the lead frame 104. The heat spreader portion 108A may be replaced by a heat slug attached to a clamp rather than being an integral part of the clamp. A packaging material 106, such as a molding compound, may be formed to enclose the chip 102, the lead frame 104, and partially the clamp 108. An upper surface of the heat spreader section is exposed by grinding the packaging material 106.Subsequent process steps such as curing the mold material 106, removing unwanted parts of the mold material 106 by a deburring process, separating into individual chip packages 100, as well as coating, labeling and cutting of lines can then be carried out.

[0004] As in Fig. 1B, a thermal transition material 112 may be formed on the exposed surface of the clamp 108, and a cooling structure 114 may be attached to the thermal transition material.

[0005] In this arrangement, heat is dissipated from the chip 102 primarily through the heat spreader portion 108A of the clamp 108, through the thermal transition material 112, and through the cooling structure 114. Typically, the cooling structure 114 is mounted over a heat transferring surface, such as the exposed clamp 108 (in Fig. 1 visible on the surface of the package 100) on a user page.

[0006] However, exposing the surface of the heat spreader portion 108A by grinding involves a plurality of steps, which significantly increase the production cost of a chip package 100.

[0007] For example, the associated process steps may include mounting the bottom surface of the package 100 on abrasive tape and abrading the top surface of the package 100 until a surface of the heat spreader portion 108A of the clamp 108 is exposed. A rinsing process is then performed to flush away dust from the abrading process, followed by removing the abrasive tape from the package 100, for example, by irradiating the abrasive tape with ultraviolet light. The aforementioned four processes are a significant cost driver. In particular, large packages 100, where the additional cost is shared by a smaller number of individual chip packages 100 compared to smaller chip packages 100, may suffer from increased costs.

[0008] DE 10 2008 027 703 A1 discloses a module comprising a first carrier having a first mounting surface and a second mounting surface, a first semiconductor chip mounted on the first mounting surface of the first carrier having a first surface facing away from the first carrier, a first connecting element connected to the first surface of the first semiconductor chip, a second semiconductor chip having a first surface facing away from the first carrier, a second connecting element connected to the first surface of the second semiconductor chip, and a molding material only partially covering the first connecting element and the second connecting element.

[0009] DE 10 2014 118 080 A1 discloses an electronic module comprising a semiconductor package, a heat spreader attached to the semiconductor package, and an electrically insulating layer arranged on the heat spreader remote from the semiconductor package.

[0010] DE 10 2015 108 700 A1 discloses a semiconductor power package comprising a preformed chip housing and an electrically conductive chip carrier molded in place in the preformed chip housing. The semiconductor power package further comprises a power semiconductor chip bonded to the electrically conductive chip carrier. A cover material is provided to embed the power semiconductor chip, wherein the cover material has a modulus of elasticity that is smaller than the modulus of elasticity of the material of the preformed chip housing, and / or has a thermal conductivity that is greater than the thermal conductivity of the material of the preformed chip housing, and / or has a temperature stability that is greater than the temperature stability of the preformed chip housing.

[0011] US 2004 / 0 169 289 A1 discloses a semiconductor device comprising a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, wherein the first conductive member is exposed from a first main surface of the resin sealing member and the second conductive member is exposed from a second main surface of the resin sealing member and also from side surfaces of the resin sealing member.

[0012] US 2004 / 0 232 545 A1 discloses a semiconductor device that can be mounted on a printed circuit board with the bottom surface facing the printed circuit board. The semiconductor device comprises: a semiconductor chip, a molding resin encapsulating the semiconductor chip, a first heat spreader connected to the semiconductor chip on the bottom surface side and extending nearly parallel to the bottom surface, with both ends thereof protruding from an edge of the molding resin, the first heat spreader being connectable to the printed circuit board at both ends thereof; and a second heat spreader connected to the semiconductor chip on a top surface side and extending nearly parallel to the bottom surface to cross the first heat spreader, with both ends thereof protruding from the edge of the molding resin, the second heat spreader being connectable to the printed circuit board at both ends.

[0013] US 2014 / 0 213 018 A1 discloses a method comprising providing an IC chip assembly comprising a substrate and an IC chip mounted on a portion of a major surface of the substrate, distributing an interface material on the IC chip, positioning a portion of a heat spreader in contact with the interface material, and applying an adhesive between a side of the heat spreader facing the IC chip assembly and exposed portions of a major surface of an encapsulation material on the substrate.

[0014] US 6,146,921 A discloses an integrated circuit package containing a thermocouple extending into a cavity of an injection-molded housing. The cavity exposes at least a portion of an integrated circuit mounted on a substrate. The package contains an adhesive that secures the thermocouple to the housing and / or the integrated circuit. The thermocouple is installed in the housing after the housing is molded onto the substrate and the integrated circuit. overview

[0015] A chip package according to claim 1, a semiconductor device according to claim 7, a method of forming a chip package according to claim 10, and a method of forming a semiconductor device are provided. Further embodiments are described in the dependent claims.

[0016] A chip package comprising a semiconductor chip is provided. The chip package may comprise a packaging material at least partially surrounding the semiconductor chip, with an opening extending from a top surface of the packaging material toward the chip and / or toward an electrical contact structure contacting the chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to conduct heat from the chip to an exterior surface, wherein the thermally conductive material extends laterally, at least partially, beyond the top surface of the packaging material. Brief description of the drawings

[0017] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which: Fig. 1A to 1C are schematic cross-sectional views illustrating a method of forming a semiconductor device according to the prior art; Fig. 2A to 2D illustrate, as a series of cross-sectional views, a method of forming a chip package according to various embodiments; Fig. 3A to 3J illustrate, as a series of cross-sectional views, a method of forming a semiconductor device including a chip package, according to various embodiments; Fig. 4A to 4C illustrate, as a series of cross-sectional views, a method of forming a semiconductor device according to various embodiments; Fig. 5A and Fig. 5B illustrate, as a series of cross-sectional views, a method of forming a semiconductor device according to various embodiments; Each of the Fig. 6A and Fig. 6B shows a schematic top view of a chip package according to the prior art; Each of the Fig. 7A to 7G show a schematic top view of a chip package in accordance with various embodiments; Each of the Fig. 8A to 8C show a schematic cross-sectional view of a chip package according to various embodiments; Fig. 9 shows a flowchart of a method for forming a chip package in accordance with various embodiments; and Fig. 10 shows a flowchart of a method of forming a semiconductor device in accordance with various embodiments. Description

[0018] The following detailed description refers to the accompanying drawings which show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0019] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0020] The word "over," as used in reference to a deposited material formed "over" a side or surface, may be used herein to mean that the deposited material may be formed "directly on," e.g., in direct contact with the indicated side or surface. The word "over," as used in reference to a deposited material formed "over" a side or surface, may be used herein to mean that the deposited material may be formed "indirectly on" the indicated side or surface, with one or more additional layers disposed between the indicated side or surface and the deposited material.

[0021] The terms "thermally conductive material," "thermally conductive path," and the like, may be used herein, unless otherwise specified, to refer to a material, path, etc., with a relatively high thermal conductivity, for example, a thermal conductivity higher than the thermal conductivity of a packaging material used in the package (e.g., a molding compound). Exemplary materials (e.g., forming the path) may include so-called thermal interface materials, also referred to as gap fillers, composite materials including a base material with low(er) thermal conductivity and an additional material, e.g., filler particles, with high / higher thermal conductivity to collectively form a thermally conductive material, metals, and other suitable materials used in the art for the purpose of heat transfer.

[0022] Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It should be understood that basic characteristics of devices also apply to the methods, and vice versa. Therefore, for the sake of brevity, duplicate descriptions of such characteristics may be omitted.

[0023] In various embodiments, a chip package with a cooling structure and a corresponding method for forming a chip package are provided. The chip package may have a thermally conductive material partially disposed over a top surface of a packaging material exposed to an exterior of the chip package. The thermally conductive material may be part of a thermal path from the chip to the exterior of the chip package and may be configured to conduct heat from the chip to the exterior of the chip package.

[0024] The thermally conductive material partially disposed over a top surface of a packaging material may be indicative of a lightweight manufacturing process, which may include forming the packaging material with an opening over the chip and filling the opening with the thermally conductive material until it overflows. This means that the exposed thermally conductive material can be provided without the costly grinding process.

[0025] In addition, the overflow can serve to ensure that no voids—i.e., regions free of the thermally conductive material—remain in the opening. This can easily ensure high thermal conductivity between the chip and the outside.

[0026] In addition, the thermally conductive material, partially disposed above an upper surface of the packaging material, may protrude sufficiently to allow easy attachment of the cooling structure.

[0027] Furthermore, the thermally conductive material, partially disposed over a top surface of the packaging material, can allow the thermally conductive material to be easily defined in a (lateral) shape as desired. In particular, a (lateral) area of ​​the thermally conductive material can be larger than a (lateral) surface of the chip, or a (lateral) surface of the clamp that may be attached to the chip.

[0028] In various embodiments, if an electrically insulating thermally conductive material is used, the thermally conductive material, partially disposed over a top surface of the packaging material, may serve to increase a creepage distance to the chip package.

[0029] The thermally conductive material may be provided in addition to metal leads having electronic contact with the chip, at least some of which, e.g., a lead frame, may serve as an additional cooling structure, e.g., for double-sided cooling (DSC), e.g., heterogeneous double-sided cooling.

[0030] Fig. 2A to 2D and Fig. 3A to 3I illustrate, as a series of schematic cross-sectional views, a method of forming a chip package 200 according to various embodiments. Fig. 3J illustrates, as a schematic cross-sectional view, a method of forming a semiconductor device using a chip package 200 according to various embodiments, as in context with, for example, Fig. 3A to 3I.

[0031] Fig. 4A to 4C respectively Fig. 5A and Fig. 5B illustrate, as a series of schematic cross-sectional views, a method of forming a semiconductor device 400 according to various embodiments.

[0032] Each of the Fig. 7A to 7G shows a schematic top view of a chip package 200 in accordance with various embodiments, and each of the Fig. 8A to 8C shows a schematic cross-sectional view of a chip package 200 according to various embodiments.

[0033] In various embodiments, the chip package 200 may include a semiconductor chip 102 (shortly referred to as “chip”), for example a transistor, a diode or the like, for example a power chip, e.g. a power transistor or a power diode or the like.

[0034] In various embodiments, the chip 102 may be attached to a carrier 104, for example, a lead frame. The carrier 104, e.g., the lead frame, may be configured in various embodiments to mechanically support the chip 102 and / or to provide electrical conductors from the outside of the chip package 200 to chip contacts. Additionally, the carrier 104 may be configured as a cooling structure.

[0035] In various embodiments, the chip package 200 may include a packaging material 106 at least partially surrounding the semiconductor chip 102, with an opening 220 extending from a top surface 106T of the packaging material 106 toward the chip 102 and / or to an electrical contact structure 108, 808 contacting the chip 102.

[0036] The electrical contact structure 108, 808 may, in principle, comprise any type of electrical contact structure typically used to contact the chip 102 and suitable for being at least partially encapsulated by the packaging material 106, for example, bond wires 808, bond ribbons, clamps 108, and the like. However, at least in some embodiments, a clamp 108 may differ from bond wires and the like in that the clamp may be sufficiently large to cover the entire chip 102, such that only a surface of the clamp may be exposed through the opening 220, whereas in the case of bond wire 808, the ribbon, a small / narrow clamp, or the like, at least a portion of the chip 102, together with at least a portion of the electrical contact structure 108, 808, may be exposed through the opening 220.

[0037] The opening 220 in the packaging material 106 can be formed in various embodiments, as in the context of the exemplary visualization of the Fig. 3B to 3D: A mold 330 (in this case, a two-part mold 330 including an upper mold 330T and a lower mold 330B) is arranged around the chip 102 (and the carrier 104). The upper mold 330T may be provided with a projection 330P, which may be arranged above the chip 102, e.g., in direct or indirect contact with the chip 102, e.g., on the clamp 108, e.g., in direct physical contact with the clamp 108. A cavity 331 formed by the mold 330 may be filled with the packaging material 106 (which may be in a viscous state), essentially as known in the art, e.g., by compression molding and curing.

[0038] Removing the mold 330 may leave the opening 220 where the protrusion 330P was located. The mold 330 may be formed from a single material or a combination of materials, for example, by using a different, e.g., softer, material for the protrusion 330P or for portions of the protrusion 330P.

[0039] In various embodiments, the opening 220 may be a blind hole that is open only at the top surface 106T of the packaging material 106, with the packaging material 106 forming the sidewall and the electrical contact structure 108 closing the bottom of the opening 220. In various embodiments, the packaging material 106 may be formed completely around the semiconductor chip 102.

[0040] In various embodiments, the chip package 200 may include a thermally conductive material 222 in the opening 220. The thermally conductive material 222 may be configured to conduct heat from the chip 102 to an outside. For example, the thermally conductive material 222 may be made of or include a material having a thermal conductivity of at least 1 W / m K, for example, at least 5 W / m K, for example, at least 10 W / m K. The thermal conductivity of the thermally conductive material 222 may be higher than the thermal conductivity of the packaging material 106.

[0041] In various embodiments, the thermally conductive material 222 may be disposed in the opening 220 in a viscous state (see Fig. 3F and Fig. 3G for illustrative examples), for example, by utilizing a nozzle 334 and / or compression molding. The thermally conductive material 222 may be cured later in various embodiments. Therefore, a shape of the opening 220, with a closed bottom and sidewalls as described above, may be particularly suitable for filling the opening 220 with the thermally conductive material 222 without risking the thermally conductive material 222 from flowing out of the opening 220, except when the opening 220 is completely filled and the thermally conductive material 222 flows over the top surface 106T of the packaging material 106 as desired.

[0042] By forming the opening 220 during the encapsulation process (when placing the packaging material 106) and filling the opening 220 with the thermally conductive material 222, the prior art grinding process for exposing the thermally conductive material (in this case, the clamp 108) can be avoided.

[0043] The thermally conductive material 222 which overflows onto the upper surface 106T of the packaging material 106 may cause the thermally conductive material 222 to extend laterally at least on the upper surface 106T of the packaging material 106.

[0044] The overflowing thermally conductive material 222 can be shaped using a second mold 338. Using the second mold 338 with a preformed recess can enable a consistent and easily controllable shape of the thermally conductive material 222.

[0045] A lateral extension of the thermally conductive material 222 over the upper surface 106T of the packaging material 106 may be shaped in various embodiments as required for the application. Fig. 7A to 7G show exemplary embodiments. As can be seen in particular from a comparison with the chip packages 100 according to the prior art on Fig. 6A and Fig. 6B, a creepage distance D can be increased by using an electrically insulated thermally conductive material 222. Furthermore, a lateral extension of the thermally conductive material 222 over the opening 220 and onto the upper surface 106T of the packaging material 106 also results in a larger heat dissipation area, compared to the exposed upper surface of the terminal 108 in the Fig. 1A known structure.

[0046] Of the embodiments shown in Fig. 7A to Fig. 7G, the thermally conductive material 222 of Fig. 7A have the largest exposed surface to the outside of the package 220 and can therefore be advantageous compared to the embodiments in Fig. 7B to 7G in terms of heat dissipation. However, the configurations of the thermally conductive material 222 of Fig. 7B to Fig. 7G may have other application-specific advantages, for example for mounting a cooling structure 114, as alignment marks, or for other purposes.

[0047] In various embodiments, the thermally conductive material 222 may completely cover the upper surface 106T of the packaging material 106 and may optionally also cover at least one other outer side, optionally all outer sides, of the chip package 200. An illustrative example is shown in Fig. 4B, where the thermally conductive material 222 is applied to encapsulate the chip package 200 from five sides, so that only a bottom side of the chip package 200, on which the carrier 104 is arranged, remains free of the thermally conductive material 222.

[0048] The thermally conductive material 222 may be electrically insulating in various embodiments, for example in the chip package 200 of Fig. 4B (which parts of a semiconductor device 400 of Fig. 4C), because otherwise the lead frame 104 and the terminal 108 could be shorted, or in one of the other embodiments shown in the figures.

[0049] The thermally conductive material 222 may be electrically conductive in various embodiments, for example, an embodiment shown in the figures with the exception of Fig. 4B, Fig. 4C and Fig. 7A to 7G because there the thermally conductive material 222 is placed in direct contact with and / or near more than one metal contact, which could cause an electrical short circuit or reduce a creepage distance. In the exemplary embodiment in Fig. 8C, the thermally conductive material 222 may be configured, for example, as an electrically conductive material for electrically contacting the backside of the chip 102 exposed in the opening 220.

[0050] In various embodiments, an electrically conductive thermally conductive material 222 may be chosen, for example, because of its high thermal conductivity.

[0051] In various embodiments, the thermally conductive material 222 may comprise or consist of a thermal transition material, for example, silicone with filler particles that have a higher thermal conductivity than the silicone, for example, aluminum oxide particles or the like, or an electrically conductive adhesive. Silicone is a stable material with good electrical insulation properties, but may not have the desired thermal conductivity.

[0052] In various embodiments, the chip package 200 may be completed, specifically the thermally conductive material 222 may be applied, before the chip package 200 is delivered to a customer.

[0053] In various embodiments, the chip package 200 may be delivered to a customer before the thermally conductive material 222 is applied. This may allow the customer to use the thermally conductive material 222 of their choice and optionally, e.g., if the thermally conductive material 222 has adhesive properties, to use it as an attachment material for the cooling structure 114. In various embodiments, the cooling structure 114 may serve as the molding compound. In other words, the cooling structure 114 may have the bottom surface shaped to define the lateral shape of the thermally conductive material on the top surface 106T of the packaging material 106, and at the same time be attached to the chip package 200 to form the semiconductor device 400.

[0054] The cooling structure is not limited to the shapes depicted in the figures. For example, in various embodiments, as an alternative to mounting the cooling structure, or as a supplement thereto, a water cooling device may be attached to the chip package 200, e.g., the thermally conductive material 222. The cooling structure may also be a single block of material, rather than a multi-fin-like structure as in the figures.

[0055] In various embodiments, the semiconductor device 400 may include at least one chip package 200 according to various embodiments, for example, as described above, and at least one cooling structure 114 attached to the thermally conductive material 222. An exemplary embodiment of a single semiconductor device 400 is shown in Fig. 3J shown.

[0056] Exemplary embodiments of semiconductor devices 400 comprising a plurality of chip packages 200 combined with a single cooling structure 114 attached to the plurality of chip packages 200 (in particular to the thermally conductive material 222 of each of the chip packages 200) are shown in Fig. 4C and Fig. 5B.

[0057] In various embodiments, a plurality of cooling structures 114 may be provided, each attached to one or more chip packages 200, ie, to their associated exposed thermally conductive material 222.

[0058] In various embodiments, the thermally conductive material 222 of at least two of the plurality of chip packages 200 may form an integral structure. An exemplary embodiment is shown in Fig. 4B and Fig. 4C, wherein the thermally conductive material 222 additionally extends between the at least two chip packages 200.

[0059] In various embodiments, the chip package 200 may be soldered (e.g., using a soldering iron 446) to a circuit board 444, e.g., a printed circuit board. Mounting the chip package 200 (or rather, the chip package 200 without the thermally conductive material 222) before the thermally conductive material 222 is applied avoids exposing the thermally conductive material 222 to the high heat reflow associated with the assembly process.

[0060] By distributing the thermally conductive material 222 across the plurality of chip packages, assembly costs can be reduced.

[0061] In various embodiments, the five processes mentioned above according to the prior art for exposing the thermally conductive material, i.e., gluing, grinding, rinsing, irradiating with ultraviolet light, and stripping, may be replaced by a fewer number of processes. The replacement processes may include securing the thermally conductive material 222 in the opening, e.g., by coating and / or casting, e.g., compression molding. Optionally, the thermally conductive material 222 may require curing. By reducing the number of process steps and additionally avoiding the more expensive grinding process, the thermal conduction path between the exterior of the chip package 200 and the chip 102 may be provided at a significantly lower cost than the prior art.

[0062] The cooling structure 114 may be configured as a prior art cooling structure, for example comprising or consisting of a material, e.g., metal, with a high thermal conductivity, and may be structured, for example, with fins, channels, or the like to increase the area exposed to a cooling medium, e.g., air.

[0063] Fig. 9 shows a flowchart 900 of a method of forming a chip package in accordance with various embodiments.

[0064] The method may comprise arranging a packaging material, at least partially around the semiconductor chip, with an opening extending from a top surface of the packaging material to the chip and / or to an electrical contact structure contacting the chip (in 910), arranging a thermally conductive material in the opening so that it extends laterally, at least partially, over the top surface of the packaging material, wherein the thermally conductive material is configured to conduct heat from the chip to an outside (in 920).

[0065] Fig. 10 shows a flowchart 1000 of a method of forming a semiconductor device in accordance with various embodiments.

[0066] The method may comprise arranging a packaging material, at least partially around the semiconductor chip, with an opening extending from a top surface of the packaging material to the chip and / or to an electrical contact structure contacting the chip (in 1010), arranging a thermally conductive material in the opening so that it extends laterally, at least partially, over the top surface of the packaging material, wherein the thermally conductive material is configured to conduct heat from the chip to an outside (in 100), and attaching a cooling structure to the thermally conductive material (in 1030).

[0067] Various examples are explained below:

[0068] Example 1 is a chip package comprising a semiconductor chip, a packaging material at least partially surrounding the semiconductor chip and having an opening extending from a top surface of the packaging material toward the chip and / or toward an electrical contact structure contacting the chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to conduct heat outward from the chip, wherein the thermally conductive material extends laterally, at least partially, over the top surface of the packaging material.

[0069] In Example 2, the subject matter of Example 1 may optionally additionally comprise the packaging material being completely molded around the semiconductor chip.

[0070] In Example 3, the article of Example 1 or 2 may optionally additionally comprise the thermally conductive material completely filling the opening.

[0071] In Example 4, the article of Examples 1 to 3 can optionally additionally comprise that the thermally conductive material only partially covers the upper surface.

[0072] In Example 5, the article of Examples 1 to 3 may optionally additionally comprise that the thermally conductive material completely covers the upper surface.

[0073] In Example 6, the subject matter of Example 5 can optionally additionally comprise that the thermally conductive material further covers at least one further outer side, optionally all outer sides of the chip package.

[0074] In Example 7, the subject matter of Examples 1 to 6 can optionally further comprise a clamp mounted on the chip, wherein the thermally conductive material is disposed in direct physical contact with the clamp.

[0075] In Example 8, the subject matter of Examples 1 to 7 can optionally additionally comprise that the thermally conductive material is arranged in direct physical contact with the chip.

[0076] In Example 9, the article of Examples 1 to 7 can optionally additionally comprise that the thermally conductive material is electrically insulating.

[0077] In Example 10, the article of Examples 1 to 9 can optionally additionally comprise that the thermally conductive material is electrically conductive.

[0078] In Example 11, the article of Examples 1 to 10 can optionally additionally comprise that the thermally conductive material is a cured material.

[0079] In Example 12, the article of Examples 1 to 11 can optionally additionally comprise that the thermally conductive material comprises or consists of a material with a higher thermal conductivity than the packaging material, optionally a thermal conductivity of at least 1 W / m K.

[0080] In Example 13, the article of Examples 1 to 12 may optionally additionally comprise that the thermally conductive material comprises or consists of silicone with filler particles which have a higher thermal conductivity than the silicone, for example, aluminum oxide particles.

[0081] Example 14 is a semiconductor device including at least one chip package according to any one of Examples 1 to 13 and at least one cooling structure attached to the thermally conductive material.

[0082] In Example 15, the subject matter of Example 14 can optionally additionally comprise that the at least one chip package includes a plurality of chip packages, wherein at least one cooling structure is attached to the respective thermally conductive material of at least two of the plurality of chip packages.

[0083] In Example 16, the subject matter of Examples 14 to 15 can optionally additionally comprise that the at least one chip package includes a plurality of chip packages and that the thermally conductive material of at least two of the plurality of chip packages form an integral structure.

[0084] In Example 17, the subject matter of Example 16 can optionally further comprise the thermally conductive material further extending between the at least two chip packages.

[0085] Example 18 is a method of forming a chip package, the method including disposing the packaging material at least partially around the semiconductor chip having an opening extending from a top surface of the packaging material to the chip and / or to an electrical contact structure contacting the chip, disposing a thermally conductive material in the opening to extend laterally at least partially over the top surface of the packaging material, the thermally conductive material being configured to conduct heat from the chip to an exterior.

[0086] In Example 19, the subject matter of Example 18 can optionally additionally comprise that the packaging material is completely molded around the semiconductor chip.

[0087] In Example 20, the article of Example 18 or 19 can optionally additionally comprise the thermally conductive material completely filling the opening.

[0088] In Example 21, the subject matter of Examples 18 to 20 can optionally additionally comprise that disposing the thermally conductive material in the opening includes filling the opening with the thermally conductive material in a viscous state until the thermally conductive material flows over the top surface of the packaging material.

[0089] In Example 22, the article of Examples 18 to 21 can optionally further comprise: curing the thermally conductive material.

[0090] In Example 23, the article of Examples 18 to 22 can optionally additionally comprise that the thermally conductive material only partially covers the upper surface.

[0091] In Example 24, the article of Examples 18 to 22 can optionally additionally comprise the thermally conductive material completely covering the upper surface.

[0092] In Example 25, the subject matter of Example 24 can optionally additionally comprise that the thermally conductive material further covers at least one outer side, optionally all outer sides of the chip package.

[0093] In Example 26, the subject matter of Examples 18 to 25 can optionally further comprise the packaging material being completely molded around the semiconductor chip.

[0094] In Example 27, the subject matter of Examples 18 to 26 can optionally additionally comprise the thermally conductive material being disposed in direct physical contact with the chip.

[0095] In Example 28, the subject matter of Examples 18 to 26 can optionally additionally comprise mounting a clamp on the chip, wherein the thermally conductive material is disposed in direct physical contact with the clamp.

[0096] In Example 29, the article of Examples 18 to 28 can optionally additionally comprise that the thermally conductive material is electrically insulating.

[0097] In Example 30, the article of Examples 18 to 28 can optionally additionally comprise that the thermally conductive material is electrically conductive.

[0098] In Example 31, the article of Examples 18 to 30 can optionally additionally comprise that the thermally conductive material comprises or consists of a material with higher thermal conductivity than the packaging material, optionally a thermal conductivity of at least 1 W / m K.

[0099] In Example 32, the article of Examples 18 to 31 can optionally additionally comprise that the thermally conductive material comprises or consists of silicone with filler particles that have a higher thermal conductivity than the silicone, for example, aluminum oxide particles.

[0100] Example 33 is a method of forming a semiconductor device, including forming a chip package according to any of the methods of any of Examples 18 to 32, and attaching a cooling structure to the thermally conductive material.

[0101] In Example 34, the subject matter of Example 33 can optionally additionally comprise that the at least one chip package includes a plurality of chip packages, and that the at least one cooling structure is attached to the respective thermally conductive material of at least two of the plurality of chip packages.

[0102] In Example 35, the subject matter of Examples 33 to 34 can optionally additionally comprise that the at least one chip package includes a plurality of chip packages and that the thermally conductive material of at least two of the plurality of chip packages form an integral structure.

[0103] In Example 36, the subject matter of Example 35 can optionally further comprise the thermally conductive material further extending between the at least two chip packages.

[0104] Although the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

[1] A chip package (200) comprising: a semiconductor chip (102); a packaging material (106) at least partially surrounding the semiconductor chip (102) and in physical contact with the semiconductor chip (102), having an opening (220) extending from a top surface of the packaging material (106) to the chip (102) and / or to an electrical contact structure contacting the chip (102); a thermally conductive material (222) in the opening (220), the thermally conductive material (222) being configured to conduct heat from the chip (102) to an outside; wherein the thermally conductive material (222) was in a viscous state when arranged in the opening (220), completely fills the opening and extends laterally, at least partially, over the upper surface (106T) of the packaging material (106). [2] The chip package (200) of claim 1, wherein the thermally conductive material (222) only partially covers the upper surface (106T). [3] The chip package (200) according to one of claims 1 or 2, further comprising: a terminal (108) mounted on the chip (102), wherein the thermally conductive material (222) is arranged in direct physical contact with the terminal (108). [4] The chip package (200) of claim 1 or 2, wherein the thermally conductive material (222) is arranged in direct physical contact with the chip (102). [5] The chip package (200) according to any one of claims 1 to 4, wherein the thermally conductive material (222) includes or consists of a material having a higher thermal conductivity than the packaging material (106). [6] The chip package (200) according to any one of claims 1 to 5, wherein the thermally conductive material (222) includes or consists of silicone with filler particles having a higher thermal conductivity than the silicone, for example aluminum oxide particles. [7] A semiconductor device (400) comprising: at least one chip package (200) according to one of claims 1 to 6; and at least one cooling structure (114) attached to the thermally conductive material (222). [8] The semiconductor device (400) according to claim 7, comprising a plurality of chip packages (200) in accordance with any one of claims 1 to 6; wherein the at least one cooling structure (114) is attached to the corresponding thermally conductive material (222) of at least two of the plurality of chip packages (200). [9] The semiconductor device according to claims 7 or 8, comprising a plurality of chip packages (200) in accordance with any one of claims 1 to 6; wherein the thermally conductive material (222) of at least two of the plurality of chip packages (200) form an integral structure. [10] A method of forming a chip package, the method comprising: Arranging a packaging material at least partially around the semiconductor chip and in physical contact with the semiconductor chip, having an opening extending from a top surface of the packaging material to the chip and / or to an electrical contact structure (910) contacting the chip; Disposing a thermally conductive material in the opening, which material is in a viscous state when disposed in the opening so that it completely fills the opening and extends laterally, at least partially, over the upper surface of the packaging material, wherein the thermally conductive material is configured to conduct heat from the chip to an outside (920). [11] The method of claim 10, wherein disposing a thermally conductive material in the opening comprises filling the opening with thermally conductive material in a viscous state until the thermally conductive material flows over the top surface of the packaging material. [12] The method according to claim 10 or 11, further comprising: Curing of the thermally conductive material [13] The method according to any one of claims 10 to 12, wherein the thermally conductive material only partially covers the upper surface. [14] The method according to any one of claims 10 to 13, wherein the thermally conductive material completely covers the upper surface. [15] The method according to any one of claims 10 to 14, wherein the thermally conductive material is arranged in direct physical contact with the chip. [16] The method according to any one of claims 10 to 15, further comprising: Mounting a clamp on the chip, wherein the thermally conductive material is arranged in direct physical contact with the terminal. [17] A method of forming a semiconductor device, the method comprising: Forming a chip package according to the method of any one of claims 10 to 16; and attaching a cooling structure to the thermally conductive material. [18] The method of claim 17, wherein the at least one chip package includes a plurality of chip packages; and wherein the at least one cooling structure is attached to the respective thermally conductive material of at least two of the plurality of chip packages.

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