Electroluminescent display device

Abstract

An electroluminescent display device comprising a plurality of pixels (PXL), each pixel (PXL) comprising: a drive transistor (DT) having a gate connected to a first node (N1), a source connected to a third node (N3), and a drain connected to a fourth node (N4), wherein the drive transistor (DT) is configured to generate a pixel current corresponding to a data voltage (Vdata) when a high-level source voltage (ELVDD) is applied to the third node (N3); an internal compensator comprising a first capacitor (Cst1) connected between the first node (N1) and a second node (N2), and a second capacitor (Cst2) connected between the second node (N2) and a high-level source voltage input terminal (ELVSS), wherein the internal compensator is configured to control a threshold voltage of the drive transistor (DT) with reference to a first sampling signal (SN(n-2)), a second sampling signal (SP(n-2)) that is in antiphase with the first sampling signal (SN(n-2)), a third sampling signal (SN(n)) that lags the first sampling signal (SN(n-2)) in phase, a fourth sampling signal (SN(n-3)) that leads the first sampling signal (SN(n-2)) in phase, and an emission signal (EM); and a light-emitting element (EL) connected between a fifth node (N5) and a low-level source voltage input terminal (ELVSS), wherein the internal compensator further comprises: a first switching transistor (T1) configured to apply the second initialization voltage (V2) to the fourth node (N4) in accordance with the fourth sensing signal (SN(n-3)) having an ON level in an aging period (P3); a second switching transistor (T2) configured to connect the second node (N2) and the third node (N3) in accordance with the first sensing signal SN(n-2) having an ON level in an initialization period (P4), whereby a first voltage obtained by subtracting the threshold voltage of the drive transistor (DT) from the initialization voltage (V1) is applied to the second and third nodes (N2, N3); a third switching transistor (T3) configured to apply the first initialization voltage (V1) to the first node (N1) in accordance with the first sensing signal SN(n-2) having an ON level in the initialization period (P4); a fourth switching transistor (T4) configured to apply the first initialization voltage (V1) to the fifth node (N5) in accordance with the second strobe signal SP(n-2) having an ON level in the initialization period (P4); a fifth switching transistor (T5) configured to apply the data voltage (Vdata) to the second node (N2) in accordance with the third strobe signal having an ON level in the data write period (P5); a sixth switching transistor (T6) configured to electrically connect the high-level source voltage input terminal and the third node (N3) in accordance with the emission signal (EM) having an ON level in the emission period (P6); and a seventh switching transistor (T7) configured to electrically connect the fourth node (N4) and the fifth node (N5) in accordance with the emission signal (EM) having an ON level in the emission period (P6).

Description

[0001] The application claims priority from KR patent application No. 10-2019-0178616, filed on December 30, 2019. BACKGROUNDArea of ​​Revelation

[0002] The present disclosure relates to an electroluminescent display device. Description of the background

[0003] Electroluminescent display devices are classified into inorganic light-emitting display devices and electroluminescent display devices according to the materials of their emission layers. Each pixel of such an electroluminescent display device includes a light-emitting element configured to emit light in a self-luminous manner and adjusts the luminance by controlling an emission amount of the light-emitting element in accordance with a gray level of image data. The pixel circuit of each pixel may include a drive transistor configured to supply a pixel current to the light-emitting element, and at least one switching transistor and one capacitor configured to program a gate / source voltage of the drive transistor. The switching transistor, the capacitor, etc.may be designed to have an interconnection structure capable of compensating for a threshold voltage variation of the drive transistor and may therefore act as a compensating circuit.

[0004] A pixel current generated in the drive transistor is determined in accordance with the threshold voltage and the gate-source voltage in the drive transistor. To achieve a desired luminance in such an electroluminescent display device, it is necessary, first, to reduce the influence of hysteresis characteristics of the drive transistor on the gate-source voltage of the drive transistor when programming the gate-source voltage of the drive transistor. Second, the compensation circuit should be optimally designed to prevent a threshold voltage fluctuation of the drive transistor from affecting the pixel current. Third, the gate voltage of the drive transistor should be continuously maintained at a programmed voltage even during light emission from the light-emitting element. US 2018 / 0374425 A1 concerns an all-round display device. KR 10 2012 043 301 A relates to a display device with organic light-emitting diodes. The display device is configured to compensate for a change in the first control voltage in real time. SUMMARY

[0005] Accordingly, the present disclosure is directed to an electroluminescent display device that substantially obviates one or more problems due to limitations and disadvantages of the prior art.

[0006] Aspects of the present disclosure provide an electroluminescent display device that can mitigate hysteresis characteristics of a drive transistor before programming a gate / source voltage of the drive transistor, thereby optimally compensating for a threshold voltage variation of the drive transistor.

[0007] Additionally, aspects of the present disclosure provide an electroluminescent display device that can continuously maintain a gate voltage of a driving transistor at a programmed voltage even during light emission of a light-emitting element.

[0008] Additional advantages, objects, and features of the present disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and claims as well as the accompanying drawings.

[0009] The object is achieved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0010] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, an electroluminescent display device comprises a plurality of pixels. Each pixel includes a drive transistor having a gate connected to a first node, a source connected to a third node, and a drain connected to a fourth node, the drive transistor generating a pixel current corresponding to a data voltage when a high-level source voltage is applied to the third node, an internal compensator comprising a first capacitor connected between the first node and a second node, and a second capacitor connected between the second node and an input terminal for the high-level source voltage.wherein the internal compensator controls a threshold voltage of the drive transistor with reference to a first sensing signal, a second sensing signal in phase opposition to the first sensing signal, a third sensing signal lagging the first sensing signal in phase, a fourth sensing signal leading the first sensing signal in phase, and an emission signal, and a light-emitting element connected between a fifth node to be connected to the fourth node and a low-level source voltage input terminal.

[0011] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate one or more aspects of the present disclosure and, together with the description, serve to explain the principle of the present disclosure.

[0013] The drawings show: Fig. 1 is a block diagram of an electroluminescent display device of an example of a disclosure; Fig. 2 a condition under which the electroluminescent display device of Fig. 1 performs low refresh rate (LRR) driving (or low speed driving); Fig. 3 is an equivalent circuit diagram of a pixel from the electroluminescent display device of Fig. 1; Fig. 4 is a drive waveform diagram of a pixel circuit shown in Fig. 3 is shown; Fig. 5A, Fig. 5B Diagrams showing the operation of each pixel in the period P1 of Fig. 4 are assigned; Fig. 6A, Fig. 6B Diagrams showing the operation of each pixel in the period P2 of Fig. 4 are assigned; Fig. 7A, Fig. 7B Diagrams showing the operation of each pixel in the period P3 of Fig. 4 are assigned; Fig. 8A, 8B Diagrams showing the operation of each pixel in the period P4 of Fig. 4 are assigned; Fig. 9A, Fig. 9B Diagrams showing the operation of each pixel in the period P5 from Fig. 4 are assigned; Fig. 10A and Fig. 10B Diagrams illustrating the operation of each pixel in P6 of Fig. 4 are assigned. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Throughout the disclosure, the same reference numerals denote substantially the same components. In describing the present disclosure, a detailed description will be omitted if a specific description of publicly known techniques related to the contents of the present disclosure is judged to obscure the understanding of the contents of the present disclosure.

[0015] Each of a pixel circuit and a gate drive circuit in an electroluminescent display device may include an N-channel transistor (NMOS) and / or a P-channel transistor (PMOS). Such a transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying charge carriers to the transistor. In the transistor, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers migrate from the transistor to the outside. In the transistor, charge carriers flow from the source to the drain. In an N-channel transistor, charge carriers are electrons, and thus, a source voltage is lower than a drain voltage to allow electrons to flow from the source to the drain. In an N-channel transistor, current flows from the drain to the source.On the other hand, in a P-channel transistor, charge carriers are holes, and thus, a source voltage is higher than a drain voltage to allow holes to flow from the source to the drain. In the P-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted here that the source and drain of such a transistor are not fixed. For example, the source and drain can be interchanged with each other in accordance with voltages applied to them. Therefore, the present disclosure is not limited to the source and drain of a transistor. Accordingly, in the following description, the source and drain of a transistor are referred to as a "first electrode" and a "second electrode."

[0016] A sensing signal (or a gate signal) applied to each pixel oscillates between a turn-on gate voltage and a turn-off gate voltage. The turn-on gate voltage is set to a voltage higher than a threshold voltage of a transistor in the pixel, and the turn-off gate voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the turn-on gate voltage and turns off in response to the turn-off gate voltage. In an N-channel transistor, the turn-on gate voltage may be a high gate voltage VGH, and the turn-off gate voltage may be a low gate voltage VGL. In a P-channel transistor, the turn-on gate voltage may be the low gate voltage VGL, and the turn-off gate voltage may be the high gate voltage VGH.

[0017] Each pixel of an electroluminescent display device includes a light-emitting element and a driving element configured to generate a pixel current in accordance with its gate / source voltage, thereby driving the light-emitting element. The light-emitting element includes an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The organic compound layer includes, but is not limited to, a hole-injection layer (HIL), a hole-transportation layer (HTL), an emission layer (EML), an electron-transportation layer (ETL), and an electron-injection layer (EIL). When a pixel current flows in the light-emitting element, holes passing through the hole-transportation layer (HTL) and electrons passing through the electron-transportation layer (ETL) migrate to the emission layer (EML), and excitons are generated. As a result, the emission layer (EML) generates visible light.

[0018] The driving element may be embodied as a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Electrical characteristics (e.g., threshold voltages) of driving transistors in pixels should be uniform across pixels. However, such electrical characteristics may vary across pixels due to process variation and variation in element characteristics. Furthermore, such electrical characteristics may vary over the course of the driving time of the display device, and their degree of variation may vary across pixels. To compensate for such variation in the electrical characteristics of the driving transistors, an internal compensation method may be applied to the electroluminescent display device.In accordance with the internal compensation method, a compensator is included in the pixel circuit to prevent a fluctuation in electrical characteristics of the driving transistor from affecting the pixel current.

[0019] Recently, attempts have increased to embody some of the transistors included in a pixel circuit in an electroluminescent display device as oxide transistors. In such an oxide transistor, oxide—that is, an oxide formed by a combination of indium (In), gallium (Ga), zinc (Zn), and oxygen (O), referred to as "IGZO," is used instead of polysilicon.

[0020] Such an oxide transistor has the advantage that, although the oxide transistor has a lower electron mobility than a low-temperature polysilicon transistor (hereinafter referred to as an "LTPS transistor"), the oxide transistor has a 10-fold or more higher electron mobility than an amorphous silicon transistor. In addition, the oxide transistor has the advantage that its manufacturing cost is significantly lower than that of the LTPS transistor, although its manufacturing cost is higher than that of the amorphous silicon transistor. Furthermore, since the manufacturing process for the oxide transistor is similar to that of the amorphous silicon transistor, existing equipment can be used, and therefore the oxide transistor has the advantage of high efficiency.In particular, since the leakage current of the oxide transistor is low, the oxide transistor has an advantage in that high drive stability and high reliability can be achieved when the oxide transistor is driven at a low speed such that its off-time is relatively long. Accordingly, such an oxide transistor can be applied to a large liquid crystal display device requiring high resolution and low-power driving, or an organic light-emitting diode (OLED) TV, where obtaining a desired screen size using an LTPS process is impossible.

[0021] Fig. 1 is a block diagram illustrating an electroluminescent display device according to an exemplary aspect of the present disclosure. Fig. Fig. 2 illustrates a condition wherein the electroluminescent display device of Fig. 1 performs low refresh rate (LRR) driving (or low speed driving).

[0022] With reference to Fig. 1, the electroluminescent display device according to the exemplary aspect may include a display panel 10, a timing controller 11, a data drive circuit 12, a gate drive circuit 13, and a power circuit 16. The timing controller 11, the data drive circuit 12, and the power circuit 16 may be fully or partially integrated into an integrated driver circuit.

[0023] A plurality of data lines 14 extending in a column direction (or a vertical direction) and a plurality of gate lines 15 extending in a row direction (or a horizontal direction) intersect each other on a screen of the display panel 10, which displays an input image. Pixels PXL are arranged in a matrix at respective intersection areas, thus forming a pixel array.

[0024] Each gate line 15 may include two or more scanning lines for supplying two or more scanning signals configured to apply a data voltage supplied to each data line 14 and an initialization voltage supplied to an initialization voltage line, respectively, to corresponding pixels PXL, an emission line for supplying an emission signal configured to enable light emission from the corresponding pixels PXL, etc.

[0025] The display panel 10 may further include a first power line for supplying a high-level source voltage ELVDD to the pixels PXL, a second power line for supplying a low-level source voltage ELVSS to the pixels PXL, and the initialization voltage line supplying an initialization voltage Vint configured to initialize the pixel circuits of the pixel PXL. The first and second power lines and the initialization voltage line are connected to the power circuit 16. The second power line may be formed in the form of a transparent electrode covering a plurality of pixels PXL.

[0026] Touch sensors may be arranged on the pixel array of the display panel 10. A touch input may be detected using individual touch sensors or may be detected by the pixels PXL. The touch sensors may be embodied as touch sensors arranged on the screen of the display panel 10 in an in-cell type or a supplementary type, or as touch sensors built into the pixel array in an in-cell type.

[0027] Each pixel PXL arranged in the same horizontal string in the pixel array is connected to a data line 14 and one or at least two gate lines 15, and therefore, the pixels PXL form a pixel string. Each pixel PXL is electrically connected to the corresponding data line 14 and the initialization voltage line in response to a scanning signal and an emission signal applied to it through the corresponding gate line 15, thereby receiving a data voltage or an initialization voltage Vint. Accordingly, each pixel PXL drives a light-emitting element to emit light by a pixel current corresponding to the data voltage. The pixels PXL arranged in the same pixel string operate simultaneously in accordance with a scanning signal and an emission signal applied through the same gate line 15.

[0028] A pixel unit may be formed by, but is not limited to, three sub-pixels including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or four sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Each sub-pixel may be embodied as a pixel circuit including a compensator. In the following description, "pixel" means "sub-pixel."

[0029] Each pixel PXL may receive a high-level source voltage ELVDD, an initialization voltage Vint, and a low-level source voltage ELVSS from the power circuit 16, and may include a drive transistor, a light-emitting element, and an internal compensator. The internal compensator may, as in the case of Fig. 3, which will be described later, may be formed by several switching transistors and at least one capacitor.

[0030] The timing controller 11 supplies image data DATA sent from an external host system (not shown) to the data drive circuit 12. The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a pixel clock DCLK from the host system and therefore generates control signals configured to control the actuation timing of the data drive circuit 12 and the gate drive circuit 13. The control signals include a gate timing signal GCS configured to control the actuation timing of the gate drive circuit 13 and a data timing signal DCS configured to control the actuation timing of the data drive circuit 12.

[0031] The data drive circuit 12 samples and latches digital image data DATA input thereto from the timing controller 11 based on the data timing signal DCS, thereby changing the digital image data DATA into parallel data. The data drive circuit 12 then converts the parallel data into analog data voltages using a digital-to-analog converter (hereinafter referred to as a "DAC") in accordance with a gamma reference voltage and supplies the data voltages to the pixels PXL via output channels and the data lines 14, respectively. Each data voltage may be a value corresponding to a gray level to be expressed by a corresponding pixel PXL. The data drive circuit 12 may be constituted by a plurality of drive integrated circuits.

[0032] The data drive circuit 12 may include a shift register, a latch, a level shifter, a DAC, and a buffer. The shift register shifts a clock input to it from the timing controller 11, thereby sequentially outputting clocks for sampling. The latch samples and latches digital image data at the timing of the sampling clocks sequentially input to it from the shift register, and simultaneously outputs all sampled pixel data. The level shifter shifts the voltages of pixel data input to it from the latch so that they are within an input voltage range of the DAC. The DAC converts the pixel data received from the level shifter into data voltages and then supplies the data voltages to the data lines 14 via the buffer.

[0033] The gate drive circuit 13 generates a scanning signal and an emission signal based on the gate control signal GCS. In this case, the gate drive circuit 13 generates the scanning signal and the emission signal in a row-sequential manner during an active period and then sequentially applies the scanning signal and the emission signal to the gate lines 15 connected to the respective pixel lines. A specific scanning signal of each gate line 15 is synchronized with the timing of the data voltage supply to the data lines 14. The scanning signal and the emission signal oscillate between a turn-on gate voltage and a turn-off gate voltage.

[0034] The gate drive circuit 13 may be constituted by a plurality of gate drive integrated circuits, each including a shift register, a level shifter for converting an output signal from the shift register into a signal having a swing width suitable for driving pixels using thin-film transistors (TFT driving), an output buffer, etc. Alternatively, the gate drive circuit 13 may be directly formed in a lower substrate of the display panel 10 in the manner of an in-panel gate drive IC (GIP). If the gate drive circuit 13 is of a GIP type, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed in the lower substrate of the display panel 10.

[0035] The power circuit 16 adjusts a DC input voltage supplied from the host system using a DC-DC converter, thereby generating a turn-on gate voltage VGH, a turn-off gate voltage VGL, etc., required to operate the data drive circuit 12 and the gate drive circuit 13. The power circuit 16 also generates a high-level source voltage ELVDD, an initialization voltage Vint, and a low-level source voltage ELVSS required to drive the pixel array. The initialization voltage Vint may include a first initialization voltage and a second initialization voltage higher than the first initialization voltage. The second initialization voltage is required for the aging operation to mitigate hysteresis characteristics of the drive transistor.

[0036] The host system may be an application processor (AP) in a mobile terminal, a wearable terminal, a virtual / augmented reality terminal, or the like. Otherwise, the host system may be a motherboard in a television system, a set-top box, a navigation system, a personal computer, a home theater system, or the like. Of course, aspects of the present disclosure are not limited to the conditions described above.

[0037] Fig. Fig. 2 illustrates a condition wherein the electroluminescent display device of Fig. 1 performs low refresh rate (LRR) driving (or low speed driving).

[0038] With reference to Fig. 2, the electroluminescent display device according to the exemplary aspect may employ LRR driving to reduce power consumption. The LRR driving described in Fig. 2(B) reduces the number of image frames into which data voltages are written, compared to driving at 60 Hz, which is shown in Fig. 2(A). In 60 Hz driving, 60 frames are reproduced per second. A data voltage write operation is performed for every 60 frames. On the other hand, in LRR driving, a data voltage write operation is performed only for a part of the 60 frames. In LRR driving, in each remaining frame, data voltages written in a previous frame are maintained (held). In other words, output operations of the data drive circuit 12 and the gate drive circuit 13 are stopped for the remaining frames, and therefore, an effect of reducing power consumption is present. LRR driving can be applied to a still image or a moving image having image fluctuation, and a data voltage update period can be longer than that of 60 Hz driving.Accordingly, in a pixel circuit, the time for which the gate / source voltage of a driving transistor is maintained is longer in LRR driving than in 60 Hz driving. In LRR driving, it is necessary to maintain the gate / source voltage of the driving transistor for a desired time. For this purpose, switching transistors directly / indirectly connected to the gate of the driving transistor can be embodied as oxide transistors that have excellent off-state characteristics. Meanwhile, 60 Hz driving and LRR driving can be selectively applied to the exemplary aspect in accordance with the characteristics of an input image.When there are a first image frame and a second image frame in which the data voltage is written into the pixels, a plurality of third image frames in which the data voltage written into the first image frame is maintained are arranged between the first image frame and the second image frame.

[0039] Fig. 3 is an equivalent circuit diagram of a pixel used in the electroluminescent display device of Fig. 1 is included. Fig. 4 is a driving waveform diagram of a pixel circuit shown in Fig. 3. In the following description, a first electrode of a transistor may be a source or a drain, and a second electrode of the transistor may be the other of the source and the drain.

[0040] With reference to Fig. 3, a pixel circuit of the pixel is connected to a data line 14, a first scanning line A, a second scanning line B, a third scanning line C, a fourth scanning line D, and an emission line E. The pixel circuit receives a data voltage Vdata from the data line 14, receives a first scanning signal SN(n-2) from the first scanning line A, receives a second scanning signal SP(n-2) from the second scanning line B, receives a third scanning signal SN(n) from the third scanning line C, receives a fourth scanning signal SN(n-3) from the fourth scanning line D, and receives an emission signal EM from the emission line E. The first scanning signal SN(n-2) and the second scanning signal SP(n-2) have opposite phases. The third scanning signal SN(n) has a phase that lags the phase of the first scanning signal SN(n-2). The fourth scanning signal SN(n-3) has a phase that leads the phase of the first scanning signal SN(n-2).

[0041] With reference to Fig. 3 and Fig. 4, the pixel circuit may include a drive transistor DT, a light-emitting element EL and an internal compensator.

[0042] The drive transistor DT generates a pixel current that allows the light-emitting element EL to emit light in accordance with a data voltage Vdata. The drive transistor DT is connected at its first electrode to a third node N3, while its second electrode is connected to a fourth node N4. The gate of the drive transistor DT is connected to a first node N1.

[0043] The light-emitting element EL includes an anode connected to the fifth node N5, a cathode connected to a low-level source voltage ELVSS input terminal, and an emission layer disposed between the anode and the cathode. The light-emitting element EL can be embodied as an organic light-emitting diode including an organic emission layer or an inorganic light-emitting diode including an inorganic emission layer.

[0044] The internal compensator is designed not only to compensate for the threshold voltage of the drive transistor DT, but also to mitigate the hysteresis characteristics of the drive transistor DT. The internal compensator can be formed by seven switching transistors T1 to T7 and two capacitors Cst1 and Cst2. In this case, at least a portion of the switching transistors T1 to T7 can be formed by an oxide transistor.

[0045] The internal compensator includes a first capacitor Cst1 connected between the first node N1 and a second node N2, and a second capacitor Cst2 connected between the second node N2 and a high level source voltage ELVDD input terminal.The internal compensator acts to reflect the threshold voltage of the drive transistor DT in an aging period P6 following a programming period P4-P5 in the gate / source voltage of the drive transistor DT by controlling voltages of the first to fifth nodes N1, N2, N3, N4 and N5 in accordance with the operation of a plurality of transistors in an aging period P3 and the programming period P4-P5, which are set with reference to the first scanning signal SN(n-2), the second scanning signal SP(n-2) which is in antiphase with the first scanning signal SN(n-2), the third scanning signal SN(n) which is lagging in phase with the first scanning signal SN(n-2), the fourth scanning signal SN(n-3) which is leading in phase with the first scanning signal SN(n-2), and the emission signal EM.When the threshold voltage of the driving transistor DT is reflected in the gate / source voltage of the driving transistor DT during the emission period P6, a pixel current flowing through the driving transistor DT is not significantly affected by a fluctuation in the threshold voltage of the driving transistor DT. Therefore, a threshold voltage fluctuation of the driving transistor DT is compensated for in the pixel.

[0046] The programming period P4-P5 includes an initialization period P4 and a data write period P5 following the initialization period P4. The internal compensator can control the operation of the switching transistors during the initialization period P4 such that a first initialization voltage V1 is applied to the first, fourth, and fifth nodes N1, N4, and N5, and can control the operation of the switching transistors during the data write period P5 such that the data voltage Vdata is applied to the second node N2.

[0047] The first switching transistor T1 is configured to apply an initialization voltage Vint to the fourth node N4. One of the first and second electrodes in the first switching transistor T1 is connected to an input terminal for the initialization voltage Vint, and the other of the first and second electrodes is connected to the fourth node N4. The gate of the first switching transistor T1 is connected to the fourth scanning line D to receive the fourth scanning signal SN(n-3).

[0048] The second switching transistor T2 is configured to apply a threshold voltage of the drive transistor DT to the second node N2. One of the first and second electrodes in the second switching transistor T2 is connected to the second node N2, and the other of the first and second electrodes is connected to the third node N3. The gate of the second switching transistor T2 is connected to the first scanning line A to receive the first scanning signal SN(n-2).

[0049] The third switching transistor T3 is configured to supply the data voltage Vdata of the data line 14 to the second node N2. One of the first and second electrodes in the third switching transistor T3 is connected to the data line 14, and the other of the first and second electrodes is connected to the second node N2. The gate of the third switching transistor T3 is connected to the third scanning line C to receive the third scanning signal SN(n).

[0050] The fourth switching transistor T4 is configured to supply the initialization voltage Vint to the gate electrode of the drive transistor DT, i.e., the first node N1. One of the first and second electrodes in the fourth switching transistor T4 is connected to the fourth node N4, and the other of the first and second electrodes is connected to the first node N1. The gate of the fourth switching transistor T4 is connected to the first scanning line A to receive the first scanning signal SN(n-2).

[0051] Each of the fifth switching transistor T5 and the sixth switching transistor T6 is configured to control the light emission of the light-emitting element EL. One of the first and second electrodes in the fifth switching transistor T5 is connected to an input terminal for the high-level source voltage ELVDD, and the other of the first and second electrodes is connected to the third node N3. The gate of the fifth switching transistor T5 is connected to the emission line E to receive an emission signal EM. One of the first and second electrodes in the sixth switching transistor T6 is connected to the fourth node N4, and the other of the first and second electrodes is connected to the fifth node N5. The gate of the sixth switching transistor T6 is connected to the emission line E to receive the emission signal EM.

[0052] The seventh switching transistor T7 is configured to supply the initialization voltage Vint to the anode of the light-emitting element EL. One of the first and second electrodes in the seventh switching transistor T7 is connected to the anode of the light-emitting element EL, and the other of the first and second electrodes is connected to the input terminal for the initialization voltage Vint. The gate of the seventh switching transistor T7 is connected to the second scanning line B to receive the second scanning signal SP(n-2).

[0053] The first storage capacitor Cst1 is connected between the first node N1 and the second node N2 to store the threshold voltage of the drive transistor DT in the initialization period P4.

[0054] The second storage capacitor Cst2 acts to store the data voltage Vdata during the data write period P5. One of the first and second electrodes in the second storage capacitor Cst2 is connected to the second node N2, and the other of the first and second electrodes is connected to the high-level source voltage input terminal ELVDD.

[0055] The pixel current flowing through the drive transistor DT is determined by the gate-source voltage of the drive transistor DT, i.e., the voltages of the first and third nodes N1 and N3, in a radiation period. In the radiation period P6, the voltage of the third node N3 is fixed at the high-level source voltage ELVDD, but the voltage of the first node N1 is influenced by the off-state characteristics of the first and fourth switching transistors T1 and T4. This is because the first node N1 is in a floating state due to the off-states of the first and fourth switching transistors T1 and T4 in the radiation period P6. Accordingly, the first and fourth switching transistors T1 and T4 can be embodied as N-type oxide transistors, which have excellent off-state characteristics (i.e., low leakage current).In addition, the second and third switching transistors T2 and T3, which are maintained in an OFF state during the irradiation period P6, may be embodied as N-type oxide transistors having excellent off-state characteristics (i.e., low leakage current) because the second and third switching transistors T2 and T3 may have an influence on the voltage of the first node N1 due to their coupling actions through the first storage capacitor Cst1. Meanwhile, the driving transistor DT may be embodied as a P-type low-temperature polysilicon (LTPS) transistor having excellent electron mobility because the driving transistor DT generates a pixel current. Accordingly, the fifth to seventh switching transistors T5 to T7 may be embodied as P-type LTPS transistors.In a P-channel transistor, the turn-on gate voltage that turns the transistor on is a low gate voltage VGL, and the turn-off gate voltage that turns the transistor off is a high gate voltage VGH. In an N-channel transistor, the turn-on gate voltage that turns the transistor on is a high gate voltage VGH, and the turn-off gate voltage that turns the transistor off is a low gate voltage VGL.

[0056] The pixel current flowing through the drive transistor DT during the irradiation period P6 is determined by the gate / source voltage of the drive transistor DT, which is set in the programming period P4-P5, i.e., the voltages of the first and third nodes N1 and N3. Since the threshold voltage of the drive transistor DT has been reflected in the gate / source voltage of the drive transistor DT, it may be possible to obtain the desired pixel current regardless of a fluctuation in the threshold voltage of the drive transistor DT. To this end, the gate / source voltage of the drive transistor DT should be correctly set in the programming step to achieve a desired threshold voltage compensation effect.

[0057] Since the gate / source voltage of the drive transistor DT is affected by hysteresis characteristics of the drive transistor DT, the internal compensator applies a relatively strong on-bias to the drive transistor DT using the aging period P3 preceding the programming period P4-P5, thereby weakening hysteresis characteristics of the drive transistor DT before programming.

[0058] This will be described in detail. The internal compensator controls the drive transistor DT based on a first initialization voltage V1 and a data voltage Vdata to be a first level including a threshold voltage in the programming period P4-P5. Specifically, the internal compensator controls the gate / source voltage of the drive transistor DT based on a second initialization voltage V2 (VGH) higher than the first initialization voltage V1 to be a second level higher than the first level in the aging period P3 preceding the programming period P4-P5, thereby mitigating hysteresis characteristics of the drive transistor DT before programming. In this case, the drive transistor DT achieves an on-bias state in which its gate / source voltage has the first or second level. The on-bias (ie,The gate / source voltage of the drive transistor DT is higher during the aging period P3 than during the programming period P4-P5. In other words, the single-channel resistance of the drive transistor DT is lower during the aging period P3 than during the programming period P4-P5.

[0059] In the case of Fig. 4, the hysteresis attenuation period may be embodied to include only the aging period P3. In this case, the on-bias voltage (i.e., the gate / source voltage) of the drive transistor DT in the aging period P3 may be a voltage obtained by subtracting a programming voltage of the previous frame from the second initialization voltage V2 (V2 - programming voltage of the previous frame).

[0060] Meanwhile, in the case of Fig. 4, the hysteresis attenuation can be embodied such that it includes both a pre-initialization period P1-P2 and the aging period P3. For this purpose, the internal compensator can further set the pre-initialization period P1-P2 preceding the aging period P3 and can further control the operation of the switching transistors such that the first initialization voltage V1 is applied to the first, fourth, and fifth nodes N1, N4, and N5 in the pre-initialization period P1-P2. An aging effect is improved in proportion to the on-bias (i.e., the gate / source voltage) of the drive transistor DT. When the gate voltage of the drive transistor DT (i.e., the voltage of the first node N1) is previously lowered by the pre-initialization period P1-P2 to the first initialization voltage V1, the on-bias (i.e.,The gate / source voltage of the drive transistor DT is lower than when the aging period P3 is entered immediately without the pre-initialization period P1-P2. That is, a voltage "V2 - Vth - V1" is higher than the voltage "V2 - programming voltage of the previous frame." Accordingly, when the pre-initialization period P1-P2 is further set to precede the aging period P3, there is an advantage in maximizing the aging effect.

[0061] Of course, to further set the pre-initialization period P1-P2 preceding the aging period P3, each of the first sampling signal SN(n-2), the second sampling signal SP(n-2), and the fourth sampling signal SN(n-3) may be input at a primary ON level in the pre-initialization period P1-P2 and may then be input at a secondary ON level in the programming period P4-P5.

[0062] Of course, since the pixel circuit can be driven even without the pre-initialization period P1-P2, each of the first scanning signal SN(n-2), the second scanning signal SP(n-2), and the fourth scanning signal SN(n-3) can be inputted only once at an ON level.

[0063] Fig. 5A to Fig. 10B are diagrams corresponding to the operation of the pixel in the periods P1 to P6 of Fig. 4 are assigned. In Fig. 5A to Fig. 10B, P1 and P2 represent a pre-initialization period, P3 represents an aging period, P4 represents an initialization period, P5 is a data write period, and P6 is a radiation period.

[0064] With reference to Fig. 5A and Fig. 5B, in the first period P1, each of the first to third scanning signals SN(n-2), SN(n), and SP(n-2) and the emission signal EM is an off-gate voltage, whereas the fourth scanning signal SN(n-3) is an on-gate voltage. The first switching transistor T1 turns on, thereby applying the first initialization voltage V1 to the fourth node N4. On the other hand, the second to seventh switching transistors T2 to T7 turn off, and therefore each of the first, second, third, and fifth nodes N1, N2, N3, and N5 is held in a previous voltage state thereof, or its voltage state cannot be determined.

[0065] With reference to Fig. 6A and Fig. 6B, in the second period P2, each of the first, second, and fourth scanning signals SN(n-2), SP(n-2), and SN(n-3) is a turn-on gate voltage, whereas each of the third scanning signal SN(n) and the emission signal EM is a turn-off gate voltage. The first, second, fourth, and seventh switching transistors T1, T2, T4, and T7 turn on by the first, second, and fourth scanning signals SN(n-2), SP(n-2), and SN(n-3) having the turn-on gate voltage. Accordingly, the first initialization voltage V1 is supplied to the first node N1 via the first and fourth switching transistors T1 and T4, and current flows through the second to fourth nodes N2, N3, and N4 via the first switching transistor T1 and the drive transistor DT. That is, current flows in one direction of the first switching transistor T1 → the drive transistor DT → the second switching transistor T2 or in an opposite direction.Accordingly, each voltage of the second node N2 and the third node N3 is lowered from the first initialization voltage V1 by the threshold voltage Vth of the driving transistor DT, and therefore each potential of the second node N2 and the third node N3 rises (or falls) until the driving transistor DT turns off. Accordingly, when the second period P2 ends, the voltage of the first node N1 becomes the first initialization voltage V1, and each voltage of the second and third nodes N2 and N3 becomes a voltage V1-Vth, which is lower than the initialization voltage Vint, that is, the first initialization voltage V1, by the threshold voltage Vth of the driving transistor DT or the vicinity thereof.

[0066] As in Fig. 7A and Fig. As shown in Figure 7B, in the third period P3, the fourth strobe signal SN(n-3) is a turn-on gate voltage, whereas each of the first to third strobe signals SN(n-2), SN(n), and SP(n-20), and the emission signal EM is a turn-off gate voltage. The drive transistor DT is maintained in an ON state, and the first switching transistor T1 turns on by the fourth strobe signal SN(n-3) having the turn-on gate voltage. Accordingly, the second initialization voltage V2, which is higher than the first initialization voltage V1, is charged to the fourth node N4, and an initialization voltage V2 - Vth, which is higher than the first initialization voltage V1, is charged to the third node N3. The on-bias voltage (gate / source voltage) of the drive transistor DT reaches "V2 - Vth - V1." The on-bias weakens the hysteresis properties of the control transistor DT.Meanwhile, all of the second to seventh switching transistors T2 to T7 turn off.

[0067] With reference to Fig. 8A and Fig. 8B, in the fourth period P4, each of the first, second, and fourth scanning signals SN(n-2), SP(n-2), and SN(n-3) is a turn-on gate voltage, whereas each of the third scanning signal SN(n) and the emission signal EM is a turn-off gate voltage. The first, second, fourth, and seventh switching transistors T1, T2, T4, and T7 turn on by the first, second, and fourth scanning signals SN(n-2), SP(n-2), and SN(n-3) having the turn-on gate voltage. Accordingly, the first initialization voltage V1 is supplied to the first node N1 via the first and fourth switching transistors T1 and T4, and current flows through the second to fourth nodes N2, N3, and N4 via the first switching transistor T1 and the driving transistor DT. That is, current flows in one direction of the first switching transistor T1 → the drive transistor DT → the second switching transistor T2 or in an opposite direction.Accordingly, each voltage of the second node N2 and the third node N3 is lowered from the first initialization voltage V1 by the threshold voltage Vth of the driving transistor DT, and therefore each potential of the second node N2 and the third node N3 rises (or falls) until the driving transistor DT turns off. Accordingly, when the fourth period P4 ends, the voltage of the first node N1 reaches the first initialization voltage V1, and each voltage of the second and third nodes N2 and N3 reaches a voltage V1-Vth, which is lower than the initialization voltage Vint, that is, the first initialization voltage V1, by the threshold voltage Vth of the driving transistor DT or the vicinity thereof. The threshold voltage Vth of the driving transistor DT is stored in the first storage capacitor Cst1.

[0068] In the fourth period P4, the potential of the first node N1 immediately reaches the first initialization voltage V1, and the potential difference between the first initialization voltage V1 of the first node N1 and the high-level source voltage ELVDD is divided by the first and second storage capacitors Cst1 and Cst2. The divided potential is immediately formed at the second node N2. Subsequently, the potential of the second node N2 reaches a voltage V1 - Vth by reflecting the first initialization voltage V1 and the threshold voltage Vth by current according to the first initialization voltage V1. Accordingly, the time required for the potential of the second node N2 to become solid is not long.

[0069] With reference to Fig. 9A and Fig. 9B, in the fifth period P5, the third strobe signal SN(n) is an on-gate voltage, and each of the remaining strobe signals SN(n-3), SN(n-2), and SP(n-2) and the emission signal EM is an off-gate voltage. The third switching transistor T3 turns on by the third strobe signal SN(n), which is an on-gate voltage, and therefore the data voltage Vdata is supplied from the data line 13 to the second node N2.

[0070] In the fifth period P5, the voltage of the first node N1 has a value α(Vdata + Vth), which is obtained by adding the threshold voltage Vth of the drive transistor DT to the data voltage Vdata, because the second node N2 has the data voltage Vdata under the condition where the potential difference between opposite electrodes of the first storage capacitor Cst1 is still maintained. Here, "α" represents a value obtained by dividing the capacitance of the first storage capacitor Cst1 by a sum of the capacitance of the first storage capacitor Cst1 and a sum of parasitic capacitances connected to the first node N1. Since the capacitance of the first storage capacitor Cst1 is significantly larger than the sum of the parasitic capacitances connected to the first node N1, "α" approaches 1 and can therefore be neglected.

[0071] In the fifth period P5, the amount of charge accumulated in the first storage capacitor Cst1 does not vary, and only the potentials at opposite electrodes of the first storage capacitor Cst1 vary at the same rate. Accordingly, in the fifth period P5, the time required for the potential of the first node N1 to be set to the data voltage Vdata (exactly a data voltage reflecting the threshold voltage) is reduced.

[0072] In the fifth period P5, the voltage of the first node N1 is “α(Vdata + Vth)”, the voltage of the second node N2 is the data voltage Vdata, the voltage of the third node N3 is “Vint - Vth”, and the voltage of the fourth node N4 is the first initialization voltage V1.

[0073] With reference to Fig. 10A and Fig.10B, in the sixth period P6, each of the first to fourth scanning signals SN(n-3), SN(n-2), SN(n), and SP(n-2) is an off-gate voltage, and the emission signal EM is an on-gate voltage. All of the first to fourth switching transistors T1 to T4 and the seventh switching transistor T7 turn on, but the fifth and sixth switching transistors T5 and T6 turn on by the emission signal EM. In addition, the high-level source voltage ELVDD is input to the third node N3, and the voltage of the first node N1 is maintained at a voltage value α(Vdata + Vth) lower than the high-level source voltage ELVDD. Accordingly, the driving transistor DT turns on, resulting in the flow of a pixel current. Such a pixel current is applied to the light-emitting element EL, which in turn emits light.

[0074] The pixel current I ELis proportional to a square of a value obtained by subtracting the threshold voltage Vth of the drive transistor DT from the gate / source voltage Vgs of the drive transistor DT, and can be expressed by the following expression 1: IEL∝(Vgs−Vth)2=(a(Vdata+Vth)−ELVDD−Vth)2=(aVdata−ELVDD)2

[0075] As shown in Expression 1, components of the threshold voltage Vth of the driving transistor DT in the comparison expression of the pixel current I EL deleted and therefore the pixel current I EL regardless of a fluctuation in the threshold voltage of the drive transistor DT. The pixel current I EL is a value corresponding to the difference between the data voltage Vdata and the high-level source voltage ELVDD and can enable the light-emitting element EL to emit light. The anode potential of the light-emitting element EL increases due to the pixel current IEL to a turn-on voltage ELVSS + Vel. From the potential rise time, the light-emitting element EL can begin to emit light.

[0076] In accordance with each aspect of the present disclosure, it may be possible to mitigate hysteresis characteristics of a drive transistor before programming a gate / source voltage of the drive transistor by applying a relatively strong on-bias to the drive transistor using an aging period preceding a programming period. Accordingly, it may be possible to optimally compensate for a threshold voltage fluctuation of the drive transistor.

[0077] In accordance with each aspect of the present disclosure, an internal compensator is included in each pixel circuit to prevent a threshold voltage fluctuation of the drive transistor from being reflected in the pixel current. Accordingly, an improvement in image quality can be achieved.

[0078] In each aspect of the present disclosure, switching transistors directly / indirectly connected to the gate of the drive transistor are embodied as oxide transistors that exhibit excellent off-state characteristics. Accordingly, the gate voltage of the drive transistor can be continuously maintained at a programmed voltage even during light emission of a light-emitting element, and therefore, an improvement in image quality can be achieved.

[0079] It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the scope of the disclosure. Thus, it is intended that the present disclosure cover the changes and modifications of the disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

[1] An electroluminescent display device comprising a plurality of pixels (PXL), each pixel (PXL) comprising: a drive transistor (DT) having a gate connected to a first node (N1), a source connected to a third node (N3), and a drain connected to a fourth node (N4), wherein the drive transistor (DT) is configured to generate a pixel current corresponding to a data voltage (Vdata) when a high-level source voltage (ELVDD) is applied to the third node (N3); an internal compensator comprising a first capacitor (Cst1) connected between the first node (N1) and a second node (N2), and a second capacitor (Cst2) connected between the second node (N2) and a high-level source voltage input terminal (ELVSS), wherein the internal compensator is configured to control a threshold voltage of the drive transistor (DT) with reference to a first sampling signal (SN(n-2)), a second sampling signal (SP(n-2)) that is in antiphase with the first sampling signal (SN(n-2)), a third sampling signal (SN(n)) that lags the first sampling signal (SN(n-2)) in phase, a fourth sampling signal (SN(n-3)) that leads the first sampling signal (SN(n-2)) in phase, and an emission signal (EM); and a light-emitting element (EL) connected between a fifth node (N5) and a low-level source voltage input terminal (ELVSS), wherein the internal compensator further comprises: a first switching transistor (T1) configured to apply the second initialization voltage (V2) to the fourth node (N4) in accordance with the fourth sensing signal (SN(n-3)) having an ON level in an aging period (P3); a second switching transistor (T2) configured to connect the second node (N2) and the third node (N3) in accordance with the first sensing signal SN(n-2) having an ON level in an initialization period (P4), whereby a first voltage obtained by subtracting the threshold voltage of the drive transistor (DT) from the initialization voltage (V1) is applied to the second and third nodes (N2, N3); a third switching transistor (T3) configured to apply the first initialization voltage (V1) to the first node (N1) in accordance with the first sensing signal SN(n-2) having an ON level in the initialization period (P4); a fourth switching transistor (T4) configured to apply the first initialization voltage (V1) to the fifth node (N5) in accordance with the second strobe signal SP(n-2) having an ON level in the initialization period (P4); a fifth switching transistor (T5) configured to apply the data voltage (Vdata) to the second node (N2) in accordance with the third strobe signal having an ON level in the data write period (P5); a sixth switching transistor (T6) configured to electrically connect the high-level source voltage input terminal and the third node (N3) in accordance with the emission signal (EM) having an ON level in the emission period (P6); and a seventh switching transistor (T7) configured to electrically connect the fourth node (N4) and the fifth node (N5) in accordance with the emission signal (EM) having an ON level in the emission period (P6). [2] The electroluminescent display device according to claim 1, wherein the internal compensator is configured to control voltages of the first to fifth nodes (N1-N5) in accordance with operations of a plurality of switching transistors (T1-T7) in the aging period (P3) and in a programming period (P4, P5) set with reference to the first to fourth scanning signals (SN(n-2), SP(n-2), SN(n), SN(n-3)) and the emission signal (EM) such that the threshold voltage of the driving transistor (DT) in an emission period (P6) following the programming period (P4, P5) is reflected in a gate / source voltage of the driving transistor (DT). [3] An electroluminescent display device having a plurality of pixels (PXL), each pixel (PXL) comprising: a drive transistor (DT) having a gate connected to a first node (N1), a source connected to a third node (N3), and a drain connected to a fourth node (N4), wherein the drive transistor (DT) is configured to generate a pixel current corresponding to a data voltage (Vdata) when a high-level source voltage (ELVDD) is applied to the third node (N3); a light-emitting element (EL) connected between a fifth node (N5) and a low-level source voltage input terminal (ELVSS), and an internal compensator comprising a second node (N2) coupled to the first node (N1), wherein the internal compensator is configured to control a threshold voltage of the drive transistor (DT) with reference to a first sensing signal (SN(n-2)), a second sensing signal (SP(n-2)) in antiphase with the first sensing signal SN(n-2), a third sensing signal (SN(n)) lagging in phase with the first sensing signal (SN(n-2)), a fourth sensing signal (SN(n-3)) leading in phase with the first sensing signal SN(n-2), and an emission signal (EM), and to control voltages of the first to fifth nodes (N1-N5) in accordance with operations of a plurality of switching transistors (T1-T7) during an aging period (P3) and a programming period (P4, P5) determined with reference to the first to fourth sensing signals (SN(n-2), SP(n-2), SN(n), SN(n-3)) and the emission signal (EM) were set in such a way,that the threshold voltage of the drive transistor (DT) is reflected in a gate / source voltage of the drive transistor (DT) in a radiation period (EM) following the programming period (P4, P5), wherein the internal compensator further comprises: a first switching transistor (T1) configured to apply the second initialization voltage (V2) to the fourth node (N4) in accordance with the fourth sensing signal (SN(n-3)) having an ON level in the aging period (P3); a second switching transistor (T2) configured to connect the second node (N2) and the third node (N3) in accordance with the first sensing signal SN(n-2) having an ON level in the initialization period (P4), whereby a first voltage obtained by subtracting the threshold voltage of the drive transistor (DT) from the initialization voltage (V1) is applied to the second and third nodes (N2, N3); a third switching transistor (T3) configured to apply the first initialization voltage (V1) to the first node (N1) in accordance with the first sensing signal SN(n-2) having an ON level in the initialization period (P4); a fourth switching transistor (T4) configured to apply the first initialization voltage (V1) to the fifth node (N5) in accordance with the second strobe signal SP(n-2) having an ON level in the initialization period (P4); a fifth switching transistor (T5) configured to apply the data voltage (Vdata) to the second node (N2) in accordance with the third strobe signal having an ON level in the data write period (P5); a sixth switching transistor (T6) configured to electrically connect the high-level source voltage input terminal and the third node (N3) in accordance with the emission signal (EM) having an ON level in the emission period (P6); and a seventh switching transistor (T7) configured to electrically connect the fourth node (N4) and the fifth node (N5) in accordance with the emission signal (EM) having an ON level in the emission period (P6). [4] The electroluminescent display device according to claim 2 or 3, wherein the internal compensator is configured to control the gate / source voltage of the drive transistor (DT) based on a first initialization voltage (V1) and the data voltage (Vdata) to have a first level including the threshold voltage in the programming period (P4, P5), and wherein the internal compensator is configured to control the gate / source voltage of the drive transistor (DT) based on a second initialization voltage (V2) higher than the first initialization voltage (V1) such that it has a second level higher than the first level in the aging period (P3) preceding the programming period (P4, P5). [5] Electroluminescent display device according to one of the preceding claims 2-4, wherein the drive transistor (DT) is configured to be turned on by the gate / source voltage having the first level or the second level, wherein the gate / source voltage of the drive transistor (DT) is preferably higher in the aging period (P3) than in the programming period (P4, P5). [6] An electroluminescent display device according to any one of the preceding claims 2-5, wherein the programming period (P4, P5) comprises an initialization period (P4) and a data writing period (P5) following the initialization period (P4). [7] Electroluminescent display device according to the preceding claim 6, wherein the internal compensator is configured to control operations of the switching transistors (T1-T7) such that the first initialization voltage (V1) is applied to the first, fourth and fifth nodes (N1, N4, N5) in the initialization period (P4), and wherein the internal compensator is configured to control the operation of the switching transistors (T1-T7) such that the data voltage (Vdata) is applied to the second node (N2) in the data write period (P5). [8] An electroluminescent display device according to any one of the preceding claims, wherein the internal compensator is further configured to control the operation of the switching transistors (T1-T7) such that the first initialization voltage (V1) is pre-applied to the first node (N1) in a pre-initialization period (P1, P2) before the aging period (P3). [9] An electroluminescent display device according to any one of the preceding claims 2-8, wherein each of the first, second and fourth scanning signals (SN(n-2), SP(n-2), SN(n-3)) is input at a primary ON level in the pre-initialization period (P1, P2), and each of the first, second and fourth scanning signals (SN(n-2), SP(n-2), SN(n-3)) is input at a secondary ON level in the programming period (P4, P5). [10] An electroluminescent display device according to claim 2, 3, 8 or 9, wherein the first switching transistor (T1) and the third switching transistor (T3) each comprise an N-channel oxide transistor having an oxide semiconductor layer, or the second switching transistor (T2) and the fourth switching transistor (T4) each comprise an N-channel oxide transistor having an oxide semiconductor layer, or the drive transistor (DT), the fifth switching transistor (T5), the sixth switching transistor (T6) and the seventh switching transistor (T7) each comprise a P-channel low-temperature polysilicon transistor LTPS transistor having an LTPS semiconductor layer. [11] An electroluminescent display device according to any one of the preceding claims, wherein the first capacitor (Cst1) is configured to store the threshold voltage of the drive transistor (DT) in the initialization period (P4) and / or the second capacitor (Cst2) is configured to store the data voltage (Vdata) in the data write period (P5). [12] An electroluminescent display device according to any one of the preceding claims, wherein, when a first image frame and a second image frame in which the data voltage (Vdata) is written into the pixels (PXL) are present, a plurality of third image frames in which the data voltage (Vdata) written into the first image frame is obtained are arranged between the first image frame and the second image frame.

Images