Ferroelectric random access memory (FERAM) with stacked ferroelectric film and method for forming the same

Abstract

Method comprising: Forming a lower electrode layer (42); Depositing a first ferroelectric layer (44A-1) on the lower electrode layer (42), wherein the first ferroelectric layer (44A-1) is amorphous; Depositing a second ferroelectric layer (44P-1) on the first ferroelectric layer (44A-1), the second ferroelectric layer (44P-1) having a polycrystalline structure; Depositing a third ferroelectric layer (44A-2) on the second ferroelectric layer (44P-1), wherein the third ferroelectric layer (44A-2) is amorphous; Depositing a fourth ferroelectric layer (44P-2) on the third ferroelectric layer (44A-2), the fourth ferroelectric layer (44P-2) having an additional polycrystalline structure; Depositing an upper electrode layer (46) on the fourth ferroelectric layer (44P-2); and Patterning the upper electrode layer (46), the fourth ferroelectric layer (44P-2), the third ferroelectric layer (44A-2), the second ferroelectric layer (44P-1), the first ferroelectric layer (44A-1), and the lower electrode layer (42) to form a ferroelectric random access memory cell (50).

Description

BACKGROUNDA ferroelectric random access memory (FeRAM) is a memory device in which a ferroelectric layer is used for storing a state ("0" or "1"). Binary "0" and "1" are stored as one of two possible electrical polarizations in each of the data storage cells.The writing of an FeRAM cell is accomplished by applying a field to the ferroelectric layer to charge the electrodes on each side of the ferroelectric layer, thereby forcing the atoms inside the ferroelectric layer (depending on the polarity of the charge) to an "up" or "down" orientation, thereby storing a "1" or "0".In a read operation of an FeRAM cell, the FeRAM cell is forced to a selected state, e.g., "0". If the cell has already included a "0", no pulse is generated. If the FeRAM cell has contained a "1", the realignment of the atoms in the ferroelectric layer will cause a short current pulse. The presence of this pulse means that the cell has included a "1.". Since the cell is overwritten by this process, reading the FeRAM is a destructive process and requires rewriting the cell.An FeRAM is known from KR 10 1999 0 005 439 A. An electronic device having a ferroelectric layer is known from U.S. Pat. No. 2020 / 0 176 610 A1. A method for forming a ferroelectric hafnium oxide layer is known from US 2019 / 0 057 860 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with common industry practice. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-6 illustrate cross-sectional views of intermediate phase in the formation of an FeRAM (ferroelectric random access memory) cell comprising a stacked ferroelectric layer, in accordance with some embodiments. FIGS. 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B illustrate cross-sectional views of intermediate phase in the formation of a stacked ferroelectric layer including two alternating layers, in accordance with some embodiments. FIG. 11 illustrates the core in the low crystallization temperature material according to some embodiments. FIG. 12 illustrates a stacked ferroelectric layer with three alternating layers, in accordance with some embodiments. FIG. 13 illustrates the intensity of the O-phase of a ferroelectric layer as a function of the number of cycles of atomic layer deposition (ALD), in accordance with some embodiments. FIGS. 14 and 15 illustrate the comparison of CV curves for a uniform ferroelectric layer and a stacked ferroelectric layer, in accordance with some embodiments. FIG. 16 illustrates a process flow for forming an FeRAM cell including a stacked ferroelectric layer, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "underlying", "below", "lower / r / s", "overlying", "upper / r / s", and the like may be used herein to simplify the description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly.A ferroelectric random access memory (FeRAM) cell including a stacked ferroelectric layer and a method of forming the same are provided. According to some embodiments of the present disclosure, the stacked ferroelectric layer includes a first ferroelectric layer having a first crystallization temperature and a second ferroelectric layer having a second crystallization temperature lower than the first crystallization temperature. The first ferroelectric layer and the second ferroelectric layer may be repeatedly formed. The second ferroelectric layer may have a polycrystalline structure, and a grain size of the second ferroelectric layer is limited by the thickness of the second ferroelectric layer. Thus, the performance of the FeRAM cell is improved. Embodiments discussed herein are used to provide examples to enable making or using the subject matter of this disclosure, and those of ordinary skill in the art will readily understand modifications that may be made without departing from the contemplated scope of various embodiments. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other embodiments of the method may be performed in any logical order.FIGS. 1-6 illustrate cross-sectional views of intermediate phase in the formation of an FeRAM cell, in accordance with some embodiments of the present disclosure. The illustrated FeRAM cell may be part of an FeRAM array that includes a plurality of FeRAM cells arranged as a plurality of rows and columns. The corresponding process is also schematically reflected in the process sequence illustrated in FIG. 16.Referring to FIG. 1, a wafer 10 is formed. The wafer 10 may include a plurality of identical device chips. According to some embodiments of the present disclosure, the wafer 10 includes a semiconductor substrate 20 and the features formed on a surface of the semiconductor substrate 20. The semiconductor substrate 20 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon doped silicon, or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. The semiconductor substrate 20 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions 22 may be formed in semiconductor substrate 20 to isolate various regions and devices in semiconductor substrate 20.According to some embodiments of the present disclosure, the wafer 10 includes integrated circuit devices formed on the upper surface of the semiconductor substrate 20. The integrated circuit devices may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like, in accordance with some embodiments.The integrated circuit devices may include a transistor 26 including source / drain regions 28A and 28B. A gate dielectric 30 is formed on a substrate 24. In accordance with some embodiments, the gate dielectric 30 includes silicon oxide, a high-k dielectric material such as HfO 2, La 2 O 3 or the like, or composite layers thereof. A gate electrode 32 is formed on the gate dielectric 30. The gate electrode 32 may be formed of polysilicon, a metal, a metal alloy, or the like. A gate contact plug 34 and source / drain contact plugs 36A and 36B are formed to be electrically connected to the gate electrode 32 and the source / drain regions 28A and 28B. The gate dielectric 30, the gate electrode 32, the gate contact plug 34, and the source / drain contact plugs 36A and 36B are disposed in an interlayer dielectric 38. In some embodiments, the interlayer dielectric 38 includes silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phospho-fused silica (BPSG), fluorine doped fused silica (FSG), or the like. An etch stop layer 40 may be formed, if desired. The etch stop layer 40 may be used for patterning the FeRAM layers to form FeRAMs. The etch stop layer 40 is illustrated with a dashed line to indicate that it may or may not be formed. In accordance with some embodiments, the etch stop layer 40 is formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.FIGS. 2-5 illustrate intermediate stages in the formation of an FeRAM cell 50 (FIG. 5 ), in accordance with some embodiments. It should be appreciated that while the following drawings illustrate the formed FeRAM cell 50 directly on the interlayer dielectric 38, the FeRAM cell 50 may be formed in any layer above or below the interlayer dielectric 38. For example, the FeRAM cell 50 may be formed in an inter-metal dielectric (IMD) in an interconnect structure on the interlayer dielectric 38. Metal lines and vias may be formed in the interconnect structure, and some of the metal lines and vias may be formed in the same dielectric layer in which the FeRAM cells 50 are formed. The IMD may be formed of a low-k dielectric material. The FeRAM cell 50 may also be formed on the interconnect structure and in a passivation layer formed of a non-low-k dielectric layer.Referring to FIG. 2, a lower electrode layer 42 is deposited. The respective process is illustrated as process 202 in process flow 200 as shown in FIG. 16. The bottom electrode layer 42 comprises a conductive material including, but not limited to, W, TaN, TiN, Ti, Ru, Pt, Ir, or the like, alloys thereof, and / or composite layers thereof. The thickness T1 of the bottom electrode layer 42 may be in the range between about 10 nm (about 100 Å) and about 50 nm (about 500 Å).Referring to FIG. 3, a stacked ferroelectric layer 44 is deposited on the lower electrode layer 42. The respective process is illustrated as process 204 in process flow 200 as shown in FIG. 16. In FIG. 3, the stacked ferroelectric layer 44 is schematically illustrated, and the details of forming the stacked ferroelectric layer 44 are illustrated in FIGS. 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B.Referring to FIGS. 7A and 7B, a ferroelectric layer 44A- 1 is deposited, in accordance with some embodiments. The respective process is illustrated as process 206 in process flow 200 as shown in FIG. 16. In accordance with alternative embodiments of the present disclosure, the deposition of the ferroelectric layer 44A- 1 is omitted and a ferroelectric layer 44P- 1 (FIG. 8A ) is deposited directly on the bottom electrode layer 42 (FIG. 3 ). Process 206 is therefore shown in FIG. 16 as a dashed box to indicate that the process may or may not be performed. FIG. 7A schematically illustrates the atomic positions of the ferroelectric layer 44A- 1, where a series of circuits represents a series of molecules in the ferroelectric layer 44A- 1. It should be understood that the arrangement of the circuits does not mean that lattice structures are present in the ferroelectric layer 44A- 1. Rather, this arrangement is intended to represent the atomic layer(s) of the ferroelectric layer 44A-1. FIG. 7B shows the absence of a crystal structure and grains in the ferroelectric layer 44A-1. In accordance with some embodiments of the present disclosure, ferroelectric layer 44A- 1 is formed of or comprises a high-k dielectric material, which may also be a ferroelectric material. The deposition may be performed using atomic layer deposition (ALD), which may accurately control the number of atomic layers forming the ferroelectric layer, and thus may accurately control the thickness of the ferroelectric layer 44A- 1. According to alternative embodiments, other deposition methods are used, such as chemical vapor deposition (CVD). The process of the embodiments is controlled to achieve a desired thickness.According to some embodiments, the temperature of the wafer 10 (FIG. 3 ) is adjusted to a desired wafer temperature, which may be in a range between about 250° C. and about 300° C., before the ferroelectric layer 44A- 1 deposition process begins. The material of the ferroelectric layer 44A- 1 is selected to have a first crystallization temperature CTemp 1 that is higher than the wafer temperature. For example, a hafnium oxide-based material, such as HfOx(hafnium oxide (HfO 2) or HfO), may be used to form the ferroelectric layer 44A- 1, and other ferroelectric materials having crystallization temperatures above the wafer temperature may also be used. For example, ferroelectric materials such as silicon oxide (SiOx), aluminum oxide (AlOx), yttrium oxide (Y 2 O) or the like may also be used.In some embodiments where ALD is used to deposit HfO 2 as the ferroelectric layer 44A- 1, the precursor may include an Hf-containing precursor such as Tetrakis(ethylmethylamino)hafnium (TEMAH), and an oxidizing agent such as ozone (O 3), oxygen (O 2), water vapor (H 2 O), or the like. The deposition may include one or more ALD cycles, wherein an HfO 2- atomic layer is deposited in each ALD cycle. To obtain good isolation capability to prevent growth of grains (if present) in the underlying bottom electrode layer 42 into the overlying layers, about three or more atomic layers of the ferroelectric layer 44A-1 may be formed, as will be discussed in subsequent paragraphs. In some embodiments, each ALD cycle includes pulsing TEMAH into a reaction chamber in a production tool, purging TEMAH with, for example, nitrogen (N 2) or an inert gas, pulsing the oxidant, and purging the oxidant. The resulting ferroelectric layer 44A- 1 may therefore comprise about 3 atomic layers and possibly a plurality (e.g., 4, 5, 6, or more) atomic layers. The thickness T2 of the ferroelectric layer 44A- 1 may range between about 0.5 nm (about 5 Å) and about 3 nm (about 30 Å).Since the wafer temperature is lower than the crystallization temperature of the ferroelectric layer 44A-1, the ferroelectric layer 44A-1 is formed as an amorphous layer, and no grains or substantially no grains are formed in the ferroelectric layer 44A-1. To ensure that no grains form in the ferroelectric layer 44A- 1, the wafer temperature may be lower than the crystallization temperature of the ferroelectric layer 44A- 1 by a difference of more than, e.g., about 25° C. or 50° C.Referring to FIGS. 8A and 8B, a polycrystalline ferroelectric layer 44P- 1 is deposited. The respective process is illustrated as process 208 in process flow 200 as shown in FIG. 16. FIG. 8A schematically illustrates the atomic positions of the ferroelectric layer 44A- 1. Figure 8B shows grains 43-1 in ferroelectric layer 44A-1. According to some embodiments of the present disclosure, the ferroelectric layer 44P- 1 is formed of or includes a high-k dielectric material, which is a ferroelectric material. The deposition may also be performed using ALD, but other deposition methods such as CVD may also be used.In accordance with some embodiments, the deposition of a ferroelectric layer 44P- 1 is performed at the same wafer temperature as for the deposition of the ferroelectric layer 44A- 1, which may be in a range between about 250° C. and about 300° C., for example. The material of the ferroelectric layer 44P- 1 is selected to have a second crystallization temperature CTemp2which is lower than the wafer temperature. For example, zirconium oxide (ZrO 2) having a crystallization temperature in a range between about 200° C. and about 250° C. may be used to form the ferroelectric layer 44P- 1, and other ferroelectric materials having crystallization temperatures below the wafer temperature may also be used. For example, ferroelectric materials such as ZrOx, SiOx, TaOx, AlOx, TiOx, YOx, GdOx, LaOx, SrOx, or the like, and combinations thereof may be used.In alternative embodiments, wafer temperature increases as ferroelectric layer 44A- 1 is transferred from deposition to deposition of ferroelectric layer 44P- 1, such that ferroelectric layer 44P- 1 is deposited at a higher temperature than the deposition of layer 44A- 1. This can ensure the formation of the grains in the ferroelectric layer 44P-1.In some embodiments where ALD is used to deposit ZrOxfor ferroelectric layer 44P- 1, the precursor may include a Zr-containing precursor such as tetrakis(dimethylamido)zirconium (Zr(NMe 2)4), tetrakis(ethylmethylamido)zirconium Zr(NMeEt) 4 or tetrakis(dimethylamido)zirconium Zr(NEt 2)4, and an oxidizing agent such as ozone (O 3), oxygen (O 2), water vapor (H 2 O), or the like. The deposition comprises a plurality of ALD cycles, in which an atomic layer of the ferroelectric layer 44P- 1 is deposited in each case. In some embodiments, each ALD cycle includes pulsing a Zr-containing precursor into the reaction chamber, flushing the Zr-containing precursor, pulsing the oxidant, and flushing the oxidant. Thus, the resulting ferroelectric layer 44P-1 comprises a plurality of atomic layers. The total number of atomic layers and the corresponding thickness of the ferroelectric layer 44P-1 are discussed in the following paragraphs. In some embodiments, the total number of ALD cycles for the ferroelectric layer 44 p- 1 is greater than the total number of ALD cycles for the ferroelectric layer 44A- 1. In alternative embodiments, the total number of ALD cycles for the ferroelectric layer 44P- 1 is equal to or less than the total number of ALD cycles for the ferroelectric layer 44A- 1.When the wafer temperature is higher than the crystallization temperature of the ferroelectric layer 44P-1, the ferroelectric layer 44P-1 is formed to have a polycrystalline structure having a plurality of grains 43-1. To ensure the formation of grains in the ferroelectric layer 44P- 1, the crystallization temperature of the ferroelectric layer 44P- 1 may be lower than the wafer temperature, for example, by a difference of more than about 20° C.FIG. 8B schematically illustrates the grains 43- 1 formed in the ferroelectric layer 44P- 1. In some embodiments, some of the grains 43- 1 have a height H 1 equal to the thickness T 3 of the ferroelectric layer 44P- 1, meaning that these grains expand throughout the growth of the ferroelectric layer 44P- 1. Some of the grains 43- 1 may also have a grain height that is less than the thickness T 3.In some embodiments, the selection and formation of the ferroelectric layer 44A- 1 and the ferroelectric layer 44P- 1 includes selecting two ferroelectric materials having crystallization temperatures CTemp1and CTemp2, respectively, wherein the crystallization temperature CTemp1is higher than the crystallization temperature CTemp2. Further, the materials of the ferroelectric layer 44A- 1 and the ferroelectric layer 44P- 1 are selected such that the difference (CTemp1-CTemp2) between their crystallization temperatures is sufficiently large, for example, greater than about 50 degrees, or in the range between about 50° C. and about 300° C. The wafer temperature used to deposit the ferroelectric layer 44A- 1 and the ferroelectric layer 44P- 1 is selected to be lower than the crystallization temperature CTemp1and higher than the crystallization temperature CTemp2with a sufficient margin of both temperatures CTemp1and CTemp2such that the ferroelectric layer 44A- 1does not have grains while the ferroelectric layer 44P- 1has the grains.Fig. 13 illustrates the intensity of the orthorhombic phase (O phase) of a polycrystalline ferroelectric layer depending on the number of atomic layers therein. The Y axis represents the intensity of the O phase, and the X axis represents the total number of atomic layers (which corresponds to the thickness of the ferroelectric layer). It is understood that as the number of atomic layers increases, the grain size also increases, as the grains can extend across the entire thickness of the ferroelectric layer, as shown in FIG. 8B. Fig. 13 shows that as the number of atomic layers increases, for example, as the number increases from 1 to 7, the peak intensity of the O phase (the peak position of the orthorhombic phase (ferroelectric phase) measured at 30.4 degrees) correspondingly increases, meaning that larger currents can be induced by switching the ferroelectric dipoles. As illustrated in FIGS. 14 and 15, the performance of the resulting FeRAM improves with the increase in the number of atomic layers due to the increase in the currents. For example, the peak intensity of the O phase of a ferroelectric layer having 7 atomic layers is 59% higher than the peak intensity of the O phase of a ferroelectric layer having one atomic layer.FIGS. 14 and 15 illustrate the comparison of the CV curves of two FeRAM types. The CV curve shown in Fig. 14 was obtained from a sample having a single atomic layer of the ferroelectric material. The capacitance of the FeRAM in FIG. 14 is about 0.3E-11 farads. The CV curve shown in Fig. 15 was obtained from a sample having five atomic layers of the ferroelectric material. The capacitance of the FeRAM in FIG. 15 is about 0.6E-11 farads, which is improved by nearly 100% compared to the sample shown in FIG. 15. This shows that increasing the thickness of the ferroelectric material from one atomic layer to five atomic layers significantly affects the improvement of the FeRAM performance.Referring again to FIG. 13, the peak intensity of the O phase decreases as the number of atomic layers increases to a certain level, e.g., about 10 (or a certain number between 7 and 10). This shows that the grain size must not be too large. Throughout the specification, the thickness of the ferroelectric layer having the peak maximized intensity of the O phase is referred to as a threshold thickness, and if the thickness of the ferroelectric layer exceeds the threshold thickness, the intensity of the O phases will decrease disadvantageously. Accordingly, the number of atomic layers corresponding to the threshold thickness is referred to as a threshold number of atomic layers, and when the number of atomic layers exceeds the threshold number, the intensity of the O phase also disadvantageously decreases. Therefore, according to embodiments of the present disclosure, measures are taken to limit the grain size by limiting the number of atomic layers and the thickness of the ferroelectric layer 44P- 1 to be equal to or less than a corresponding threshold number and a corresponding threshold thickness. In some embodiments, the number of atomic layers in the ferroelectric layer 44P- 1 is equal to or less than 10 and may be less than about 7, depending on the material, and may be in a range between about 5 and about 7. With respect to thickness (rather than number of atomic layers), the thickness T3 (Fig. 8B) of the ferroelectric layer 44P-1 may be selected to be less than about 2 nm (about 20 Å), and may be in the range between about 0.1 nm (about 1 Å) and about 1.5 nm (about 15) Å. In some embodiments, the grain size constraint 43- 1 is achieved by depositing an amorphous ferroelectric layer on the ferroelectric layer 44P- 1 to complete grain growth, as shown in FIGS. 9A and 9B.Referring to FIGS. 9A and 9B, ferroelectric layer 44A- 2 is deposited. The respective process is illustrated as process 210 in process flow 200 as shown in FIG. 16. In some embodiments, a ferroelectric layer 44A- 2 is formed of a material that is identical to or different from the material of the ferroelectric layer 44A- 1. In some embodiments, the ferroelectric layer 44A- 2 is formed of HfOxor comprises HfOx. Further, the wafer temperature for depositing the ferroelectric layer 44A- 2 may be the same as or different from the wafer temperatures for depositing the ferroelectric layers 44A- 1 and 44P- 1. The wafer temperature for depositing the ferroelectric layer 44A- 2 is lower than the crystallization temperature of the material of the ferroelectric layer 44A- 2. Thus, the ferroelectric layer 44A-2 is deposited as an amorphous layer, and the grains in the ferroelectric layer 44P-1 do not grow into the ferroelectric layer 44A-2. The deposition of the ferroelectric layer 44A- 2 may be performed using ALD, CVD, or the like. Throughout the specification, reference to a grain as "growing" from a first layer to a second layer means that the lattice arrangement in the first layer is incorporated into the second layer, although the first layer and the second layer are formed of different materials.Since ferroelectric layer 44A-2 is amorphous, grains 43-1 (Fig. 9B) terminate where ferroelectric layer 44P-1 meets ferroelectric layer 44A-2. Thus, the grain size of the grain 43-1 is limited. In order to effectively prevent grain growth from extending into the ferroelectric layer 44P-2 to be deposited on the ferroelectric layer 44A-2, the ferroelectric layer 44A-2 needs to have a certain thickness, e.g., about three atomic layers or more. The ferroelectric layer 44A-2, on the other hand, tends to form a monoclinic phase and does not tend to promote the induction of current for the FeRAM. The thickness T4 of the ferroelectric layer 44A-2 may therefore not be too large and may be less than about 5 atomic layers, as more additional atomic layers than are required to stop grain growth would be functionally wasted. It should be appreciated that one or sometimes two atomic layers of the ferroelectric layer 44A- 2 may not be sufficient to stop grain growth. Therefore, the thickness T4 of the ferroelectric layer 44A- 2 may be equal to or greater than about 3 atomic layers (about 0.2 nm (about 2 Å)) and may be in a range between about 3 atomic layers (about 0.2 nm (about 2 Å)) and about 18 atomic layers (about 1.3 nm (about 13 Å)).After the deposition of the ferroelectric layer 44A-2, the ferroelectric layer 44P-2 is deposited. The respective process is illustrated as process 212 in process flow 200 as shown in FIG. 16. In some embodiments, a ferroelectric layer 44P- 2 is formed of an identical material to the ferroelectric layer 44P- 1. For example, the ferroelectric layer 44P- 2 may be formed of or include a material selected from the same group of candidate materials used to deposit the ferroelectric layer 44P- 1, and the material may include ZrOx, SiOx, TaOx, AlOx, TiOx, Yox, GdOx, LaOx, SrOx, or the like, or a combination thereof.Further, the wafer temperature for depositing the ferroelectric layer 44P- 2 may be the same as or different from the wafer temperature for depositing the ferroelectric layers 44A- 1, 44P- 1, and 44A- 2. The wafer temperature for depositing the ferroelectric layer 44P- 2 is also higher than the crystallization temperature of the material of the ferroelectric layer 44P- 2. Thus, the ferroelectric layer 44P-2 is deposited as a polycrystalline layer. The grains 43- 2 in the ferroelectric layer 44P- 2 are schematically illustrated in FIG. 9B. Grains 43-2 are physically separated from grains 43-1 by amorphous ferroelectric layer 44A-2.The deposition of the ferroelectric layer 44P- 2 may be performed using ALD, CVD, or the like. When ALD is used, the total number of ALD cycles may be close to and equal to or less than the corresponding threshold number. For example, the number of ALD cycles may be equal to about 7 or less, and may be in the range of between about 5 and about 7, for example. The thickness of the ferroelectric layer 44P-2 is controlled to be equal to or less than the threshold thickness. For example, when CVD is used that does not involve cycles, the threshold thickness serves as a criterion for controlling the deposition process.It should be appreciated that the formation of the ferroelectric layer 44A- 2 to separate the ferroelectric layer 44P- 2 from the ferroelectric layer 44P- 1 effectively controls grain growth in the ferroelectric layer 44P- 1 to a desired size, where the height of the grains is less than or equal to the thickness T 3 of the ferroelectric layer 44P- 1. In other words, the grains of the ferroelectric layer 44P-2 are restarted instead of expanding from the grains of the ferroelectric layer 44P-1. This also enables the grain size of the ferroelectric layer 44P-2 to be controlled.Throughout the specification of the present disclosure, an amorphous ferroelectric layer and a polycrystalline ferroelectric layer are collectively referred to as a composite ferroelectric layer. The formation of the ferroelectric composite layer is referred to as a composite deposition cycle. FIG. 9A illustrates two ferroelectric compound layers, wherein the first ferroelectric compound layer comprises ferroelectric layers 44A- 1 and 44P- 1 and the second ferroelectric compound layer comprises ferroelectric layers 44A- 2 and 44P- 2. The first and second ferroelectric compound layers are further stacked with more ferroelectric compound layers, so that the resulting stacked ferroelectric layer has a larger thickness. As shown in FIG. 3, the resulting stacked ferroelectric composite layer is referred to as a ferroelectric layer 44.Figures 10A and 10B illustrate the formation of more ferroelectric compound layer(s). The upper ferroelectric composite layer includes ferroelectric layers 44A-n and 44P-n, where n is an atomic number equal to or greater than 3. The process is shown as a loop back to process 210 in process flow 200 as shown in FIG. 16. The ferroelectric layers 44A- 1 to 44A- n are also referred to individually and collectively as ferroelectric layers 44A throughout the specification, and the ferroelectric layers 44P- 1 to 44P- n are also referred to individually and collectively as ferroelectric layers 44P. In some embodiments, the number n may be in the range between about 3 and about 6. It is also understood that the total number of the ferroelectric compound layers may be 2 or 1, which means that the formation of the stacked ferroelectric layer 44 (FIG. 3 ) may be completed when the process shown in FIG. 8A or 9A is completed, or when the process shown in FIG. 10A is completed. The details such as the materials, the formation methods, and the thicknesses of the ferroelectric layers 44A-n and the underlying layers 44A may be found with reference to those of the ferroelectric layers 44A-1 and 44A-2. The details of the ferroelectric layers 44P-n and the underlying layers 44P may also be found with reference to those of the ferroelectric layers 44P-1 and 44P-2.It should be appreciated that generally, an increase in the thickness of the ferroelectric layer 44 may result in an increase in the current of the resulting FeRAM. However, if the entire ferroelectric layer 44 is formed of a homogeneous material, as the ferroelectric layer 44 increases, the grains in the ferroelectric layer 44 also increase and eventually exceed the threshold thickness. Therefore, the effect in FIG. 13 is produced. This means that the thickness of the ferroelectric layer 44 is limited, as is the increase in the current of the FeRAM by increasing the thickness. In the embodiments of the present disclosure, the thickness of the ferroelectric layer 44 is increased by increasing the number of composite ferroelectric layers, while the grain size is limited by the thickness of the single stacked ferroelectric layer. Accordingly, in the example shown in FIGS. 10A and 10B, there are n ferroelectric layers 44P, and the induced current in each of the FeRAMs is determined by the total thickness of the n ferroelectric layers 44P.According to some embodiments, the temperature of the wafer 10 remains constant during the formation of the entire ferroelectric layer 44, and the material of 44A (including 44A- 1 to 44A-n) and 44P (including 44P- 1 to 44P-n) alternate. The ferroelectric layers 44A- 1 to 44A- nmay be formed of the same material, such as HfOx, and may have the same thickness (the number of ALD cycles). The ferroelectric layers 44P- 1 to 44P- nmay be formed of the identical material, for example, ZrOx, and may have the same thickness (number of ALD cycles). According to alternative embodiments, the wafer temperatures, the materials, and / or the number of ALD cycles (and the thicknesses) in the formation of the amorphous ferroelectric layers 44A- 1 to 44A- nmay be different from each other in any combination, and / or the wafer temperatures, the materials, and / or the number of ALD cycles in the formation of the polycrystalline ferroelectric layers 44P- 1 to 44P- nmay be different from each other in any combination.In the embodiments shown, the amorphous ferroelectric layer 44A- 1 is depicted as the bottom layer of the ferroelectric layer 44 and the polycrystalline ferroelectric layer 44P-n is the top layer. According to alternative embodiments, each of the lower layer and the upper layer may be an amorphous ferroelectric layer 44A or a polycrystalline ferroelectric layer 44P in any combination as long as the amorphous ferroelectric layers and the polycrystalline ferroelectric layers are alternating. The thickness ratio T 3 / T 4 may be in the range between about 1:1 and about 1:4, depending on the material.It should also be understood that the amorphous layers 44A may be formed of a high-k dielectric material or, alternatively, a non-high-k material, in accordance with some embodiments, and may be formed of a ferroelectric material or a non-ferroelectric material, in accordance with some embodiments, as long as grain growth is stopped in the polycrystalline ferroelectric layer 44P.FIGS. 11A and 11B also illustrate the stacked ferroelectric layer 44. FIG. 11A is similar to FIG. 10A, except that the core 45 shown in FIG. 11 illustrates the growth of grains based on the core 45 in the ferroelectric layers 44P. Also illustrated schematically are atoms 47 that diffuse from ferroelectric layers 44P into their adjacent ferroelectric layers 44A.FIG. 12 illustrates ferroelectric layer 44 according to alternative embodiments of the present disclosure. In some embodiments, the ferroelectric layers 44A- 1 to 44A- nare substantially the same as the corresponding layers shown in FIGS. 10A and 10B and are therefore not repeated here. Each of the ferroelectric layers 44P may further include a lower layer (denoted by the letter "L") and an upper layer (denoted by the letter "U"). The ferroelectric layer 44P- 1 includes, for example, lower layers 44P- 1L and 44P- 1U. The ferroelectric layers 44P-1L and 44P-1U are discussed herein as an example, and the details of other layers, such as 44P-2L and 44P-2U to 44P-nL and 44P-nU, may also be inferred from the discussion of the ferroelectric layers 44P-1L and 44P-1U.The crystallization temperatures of the ferroelectric layers 44P- 1L and 44P- 1U are lower than the temperature of the wafer 10 (FIG. 3 ). Thus, both ferroelectric layers 44P-1L and 44P-1U have polycrystalline structures with grains formed therein. The materials of the ferroelectric layers 44P-1L and 44P-1U are different from each other, and each of the ferroelectric layers 44P-1L and 44P-1U may be formed of or include a material selected from ZrOx, SiOx, TaOx, AlOx, TiOx, YOx, GdOx, LaOx, SrOx, or the like, or a combination thereof, and other materials may be used. The grains formed in the ferroelectric layer 44P-1L may optionally extend into the ferroelectric layer 44P-1U. Accordingly, as shown in FIG. 12, some grains may extend from the bottom of the ferroelectric layer 44P-1L to the top of the ferroelectric layer 44P-1U. Some of the other grains may be confined to the ferroelectric layer 44P-1L and the ferroelectric layer 44P-1U. For example, some of the grains may extend from and terminate at the top of the ferroelectric layer 44P-1L, while some other grains may extend from and terminate at the bottom of the ferroelectric layer 44P-1U. The total number of atomic layers in the ferroelectric layer 44P- 1L and the ferroelectric layer 44P- 1U may be equal to or less than the threshold number, and may be in a range between about 5 and 7. According to some embodiments, the ferroelectric layer 44P- 1L has a lower crystallization temperature than the ferroelectric layer 44P- 1U, so that grains in the ferroelectric layer 44P- 1L can well establish, resulting in better grain growth in the ferroelectric layer 44P- 1U having a higher crystallization temperature. According to some embodiments, the ferroelectric layer 44P- 1L has a crystallization temperature equal to or higher than the ferroelectric layer 44P- 1U.Referring to Figure 4, as explained in the previous paragraphs, after the formation of the ferroelectric layer 44, an upper electrode layer 46 is deposited on the lower electrode layer 42. The respective process is illustrated as process 214 in process flow 200 as shown in FIG. 16. The upper electrode layer 46 comprises a conductive material including, but not limited to, W, TaN, TiN, Ti, Ru, Pt, Ir, or the like, alloys thereof, and / or composite layers thereof. The thickness T 5 of the upper electrode layer 46 may be in a range between about 10 nm (about 100 Å) and about 50 nm (about 500 Å).A patterning process is then performed to pattern the top electrode layer 46, stack the ferroelectric layer 44, and pattern the bottom electrode layer 42. The respective process is illustrated as process 216 in process flow 200 as shown in FIG. 16. In accordance with some embodiments, as shown in FIG. 5, an etch mask 48, which may include a photoresist, is deposited and patterned. The upper electrode layer 46, the ferroelectric layer 44, and the lower electrode layer 42 are then etched using the etching mask 48. The etching may be performed using the layer 40 as an etch stop layer or, if the layer 40 is not formed, using the dielectric layer 38 as an etch stop layer. After the etching process, the etching mask 48 is removed. The remaining portions of the upper electrode layer 46, the stacked ferroelectric layer 44, and the lower electrode layer 42 are referred to as upper electrode 46', stacked ferroelectric layer 44', and lower electrode 42', which are collectively referred to as FeRAM cell 50. While forming the FeRAM cell 50, an array of FeRAM cells arranged in a plurality of rows and columns may be formed with the same structure as the FeRAM cell 50.FIG. 6 shows the formation of a dielectric layer 54 surrounding the FeRAM cell 50, and further includes a portion covering the FeRAM. The respective process is illustrated as process 218 in process flow 200 as shown in FIG. 16. In some embodiments, the dielectric layer 54 is formed of or comprises silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric layer, or the like. A contact plug 56 is formed over and contacts the top electrode 46'. The respective process is illustrated as process 220 in process flow 200 as shown in FIG. 16. The contact plug 56 may be formed of or comprise titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, or the like, and composite layers thereof.FIG. 6 further includes a control circuit 58 electrically connected to the FeRAM cell 50. The control circuit 58 includes circuits for applying appropriate voltages and currents for operating the FeRAM cell 50 and performing the read and write operations for the FeRAM cell 50 For a write operation, the control circuit 58 charges the stacked ferroelectric layer 44 by applying an electric field, thereby forcing the atoms (depending on the polarity of the charge) inside the ferroelectric layer 44 in an "up" or "down" orientation, thereby storing a "1" or "0". In a read operation of the FeRAM cell 50, the control circuit 58 forces the FeRAM cell 50 to a selected state, e.g., "0". If the FeRAM cell 50 has already included a "0", no pulse is generated. If the FeRAM cell 50 has included a "1", the realignment of the atoms in the ferroelectric layer 44 will cause a short current pulse. The control circuit 58 reads the state of the FeRAM cell 50 by determining whether or not this pulse exists, and when the pulse is detected, it means that the FeRAM cell 50 contains "1". Since this process will override the FeRAM cell 50, reading the FeRAM cell 50 is a destructive process and the control circuit 58 writes the FeRAM cell 50 back to "1.".The embodiments of the present disclosure show improved device performance. A first sample FeRAM cell having a uniform ferroelectric layer and a second sample FeRAM cell having a stacked ferroelectric layer are each formed with a cell size of 0.135 μm. The storage window (MW) of the first sample FeRAM cell is about 0.1 V, while the MW of the second sample FeRAM cell is improved to about 0.5 V. The common window of the first sample FeRAM cell is about 0 V, while the common window of the second sample FeRAM cell is improved to about 0.1 V. Moreover, 9 (30 percent) out of 31 samples comprising the sample FeRAM cells with the uniform ferroelectric layers overlap between erasing and programming and are defective. In comparison, none of the 31 sample FeRAM cells were defective with stacked ferroelectric layers.The embodiments of the present disclosure have some advantageous features. The performance of the resulting FeRAM is improved by increasing the total thickness of the ferroelectric layers having the orthorhombic phase (having the polycrystalline structure). However, increasing the thickness of the ferroelectric layers may result in increasing the grain size to a threshold thickness at which the intensity of the orthorhombic phase undesirably decreases. According to some embodiments of the present disclosure, amorphous ferroelectric layers are formed (by applying a material having a high crystallization temperature) to disturb the increase of the grain size, thereby enabling the improvement of the FeRAM performance by increasing the thickness of the ferroelectric material.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A method comprising: forming a bottom electrode layer (42); depositing a first ferroelectric layer (44A-1) on the bottom electrode layer (42), wherein the first ferroelectric layer (44A-1) is amorphous; depositing a second ferroelectric layer (44P-1) on the first ferroelectric layer (44A-1), wherein the second ferroelectric layer (44P-1) has a polycrystalline structure; depositing a third ferroelectric layer (44A-2) on the second ferroelectric layer (44P-1), wherein the third ferroelectric layer (44A-2) is amorphous; depositing a fourth ferroelectric layer (44P-2) on the third ferroelectric layer (44A-2), wherein the fourth ferroelectric layer (44P-2) has an additional polycrystalline structure; depositing an upper electrode layer (46) on the fourth ferroelectric layer (44P-2); and patterning the upper electrode layer (46), the fourth ferroelectric layer (44P-2), the third ferroelectric layer (44A-2), the second ferroelectric layer (44P-1), the first ferroelectric layer (44A-1), and the lower electrode layer (42) to form a ferroelectric random access memory cell (50).The method of claim 1, wherein the first ferroelectric layer (44A-1) and the second ferroelectric layer (44P-1) are deposited at the same wafer temperature.The method of any preceding claim, wherein the first ferroelectric layer (44A-1) has a first crystallization temperature and the second ferroelectric layer (44P-1) has a second crystallization temperature that is lower than the first crystallization temperature.The method of any preceding claim, wherein the second ferroelectric layer (44P-1) comprises a grain (43-1) extending from the top to the bottom of the second ferroelectric layer (44P-1).The method of any preceding claim, wherein depositing the first ferroelectric layer (44A-1) and depositing the second ferroelectric layer (44P-1) comprises depositing different materials.The method of any preceding claim, wherein depositing the first ferroelectric layer (44A-1) and depositing the third ferroelectric layer (44A-2) comprises depositing an identical material.The method of any preceding claim, wherein the first ferroelectric layer (44A-1) is deposited using ALD, and wherein depositing the first ferroelectric layer (44A-1) comprises more than about 3 ALD cycles.The method of any preceding claim, wherein the second ferroelectric layer (44P-1) is deposited using ALD, and wherein depositing the second ferroelectric layer (44P-1) comprises less than about 7 ALD cycles.A device comprising: a ferroelectric random access memory cell (50) comprising: a bottom electrode (42'); a stacked ferroelectric layer (44') comprising: a first amorphous ferroelectric layer (44A-1) on the bottom electrode (42); a first polycrystalline ferroelectric layer (44P-1) on the first amorphous ferroelectric layer (44A-1); a second amorphous ferroelectric layer (44A-2) on the first polycrystalline ferroelectric layer (44P-1); and a second polycrystalline ferroelectric layer (44P-2) on the second amorphous ferroelectric layer (44A-2); and a top electrode (46') on the second polycrystalline ferroelectric layer (44P-2).The device of claim 9, wherein the first amorphous ferroelectric layer (44A-1), the first polycrystalline ferroelectric layer (44P-1), the second amorphous ferroelectric layer (44A-2), and the second polycrystalline ferroelectric layer (44P-2) are high-k dielectric layers.The device of claim 9 or 10, wherein the first amorphous ferroelectric layer (44A-1) and the first polycrystalline ferroelectric layer (44P-1) comprise different materials.The device of any of claims 10 to 11, wherein the first amorphous ferroelectric layer (44A-1) and the second amorphous ferroelectric layer (44A-2) comprise an identical material.The device of any of claims 9 to 12, wherein each of the first polycrystalline ferroelectric layer (44P-1) and the second polycrystalline ferroelectric layer (44P-2) comprises less than about 7 atomic layers.The device of any of claims 9 to 13, wherein the second amorphous ferroelectric layer (44A-2) comprises more than about 3 atomic layers.The device of any of claims 9 to 11, wherein the first amorphous ferroelectric layer (44A-1) comprises hafnium oxide and the second amorphous ferroelectric layer (44A-2) comprises zirconium oxide.A device comprising: a bottom electrode (42'); a first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) over the bottom electrode (42), the first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) being formed from first materials having first crystallization temperatures; a second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) on the lower electrode (42), wherein the first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) and the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) are alternately stacked, and wherein the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) are formed of second materials having second crystallization temperatures, and the second crystallization temperatures are lower than the first crystallization temperatures; and an upper electrode (46') on the first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) and the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n).The device of claim 16, wherein the first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) are formed of an identical first material and the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) are formed of an identical second material.The device of claim 16 or 17, wherein the first plurality of ferroelectric layers (44A-1, 44A-2, 44A-n) are amorphous layers and the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) are polycrystalline layers.The device of any of claims 16 to 18, wherein grains (43-1, 43-2) in each of the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n) are completely separated from additional grains (43-1, 43-2) in other of the second plurality of ferroelectric layers (44P-1, 44P-2, 44P-n).

Images