INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

Procedure, comprehensive: Connecting a first IC component and a second IC component with an interposer using dielectric-to-dielectric bonds and metal-to-metal bonds; Forming a stress-reducing material around the first IC component and the second IC component, wherein the stress-reducing material has a first Young's modulus; Encapsulating the stress-reducing material, the first IC component, and the second IC component with a molding material, wherein the molding material has a second Young's modulus, the first Young's modulus being smaller than the second Young's modulus; and Thinning the molding material to expose the first IC component and the second IC component, wherein the stress reduction material has first filler materials with a first average filler particle size and the molding material has second filler materials with a second average filler particle size, wherein the first average filler particle size is smaller than the second average filler particle size.

Description

BACKGROUND

[0001] Since the development of the integrated circuit (IC), the semiconductor industry has experienced sustained rapid growth due to the continuous improvement in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have resulted from repeated reductions in spacer features, allowing more components to be integrated into a given area.

[0002] These integration improvements are essentially two-dimensional (2D) in nature, meaning the area occupied by the integrated components is essentially confined to the area of ​​the semiconductor wafer. The increased density and the associated reduction in the area of ​​the integrated circuit have generally rendered the ability to directly bond an integrated circuit chip to a substrate obsolete. Interposers have been used to redistribute the spherical contact areas from those of the chip to a larger area of ​​the interposer. Furthermore, interposers have enabled three-dimensional packages that incorporate multiple chips. Other packages incorporating three-dimensional aspects have also been developed.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2013 / 0187258 A1, US 2019 / 0148250 A1 and US 2012 / 0248621 A1.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this revelation are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, according to standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a cross-sectional view of an IC component. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. Figure 9 shows cross-sectional views of intermediate steps during a process for manufacturing integrated circuit packages according to some embodiments. Fig. Figure 10 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figure 11 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figure 12 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figure 13 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figure 14 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figure 15 is a cross-sectional view of an integrated circuit package according to some embodiments. Fig. Figures 16A to 16E are top views of integrated circuit packages according to different embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, only examples and are not to be understood as limiting. For example, the formation of a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements can be formed between the first and second elements, so that the first and second elements do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations explained.

[0007] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0008] In various embodiments, integrated circuit packages are formed by directly bonding IC components to a wafer that includes another device, such as an interposer. Voltage buffer layers are formed around the IC components before they are encapsulated. These voltage buffer layers are made of a material that helps protect the IC components during the expansion of the encapsulation material at high temperatures. This improves the yield and reliability of the integrated circuit packages.

[0009] Fig. Figure 1 is a cross-sectional view of an IC component 50. Several IC components 50 are packaged together in further processing to form integrated circuit packages. Each IC component 50 can be a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM die), static random access memory (SRAM die), etc.), a power management device (e.g., integrated power management circuit (PMIC die)), a radio frequency device (RF device), a sensor device, a microelectromechanical system device (MEMS device), a signal processing device (e.g., digital signal processing device (DSP die)), a front-end device (e.g., analog front-end die (AFE die)), the like, or combinations thereof (e.g., a system-on-a-chip (SoC) die).The IC component 50 can be formed on a wafer that may comprise various device regions, which are subsequently separated to form multiple IC components 50. The IC component 50 comprises a semiconductor substrate 52, an interconnect structure 54, die connectors 56, and a dielectric layer 58.

[0010] The semiconductor substrate 52 can be a silicon substrate, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as a multilayer or gradient substrate, can also be used. The semiconductor substrate 52 has an active area (e.g., the upward-facing area) and an inactive area (e.g., the downward-facing area). The devices are located on the active area of ​​the semiconductor substrate 52.The devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive area can be free of devices.

[0011] The interconnect structure 54 is located above the active area of ​​the semiconductor substrate 52 and serves to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 can comprise one or more dielectric layer(s) and one or more corresponding metallization structures within the dielectric layer(s). Acceptable dielectrics for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other dielectrics can also be used, e.g., a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, or the like.The metallization structures can include conductive vias and / or conductor tracks to interconnect the devices of the semiconductor substrate 52. The metallization structures can be formed from a conductive material, e.g., a metal such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure 54 can be formed by a damascus process, such as a simple damascus process, a dual damascus process, or the like.

[0012] The die connectors 56 are located on the front face 50F of the IC component 50. The die connectors 56 can be conductive pillars, pads, or the like, to which external connections are made. The die connectors 56 are located in and / or on the interconnect structure 54. For example, the die connectors 56 can be part of an upper metallization structure of the interconnect structure 54. The die connectors 56 can be made of a metal, such as copper, aluminum, or the like, and can be formed, for example, by plating or the like.

[0013] Optionally, solder regions (e.g., solder balls or solder bumps) can be placed on the die connectors 56 during the formation of the IC component 50. The solder balls can be used to perform chip probe (CP) tests on the IC component 50. The CP test can be performed on the IC component 50 to determine whether the IC component 50 is a "known good die" (KGD). Only IC components 50 that are KGDs are packaged further, and devices that fail the CP test are not packaged. After testing, the solder regions can be removed in subsequent processing steps.

[0014] A dielectric layer 58 is located on the front face 50F of the IC component 50. The dielectric layer 58 is located in and / or on the interconnect structure 54. The dielectric layer 58 can, for example, be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 encapsulates the die connectors 56 laterally. The dielectric layer 58 can be an oxide, a nitride, a carbide, a polymer, or the like, or a combination thereof. The dielectric layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. First, the dielectric layer 58 can encapsulate the die connectors 56, so that the upper surface of the dielectric layer 58 lies above the upper surfaces of the die connectors 56. The die connectors 56 are exposed through the dielectric layer 58 during the formation of the IC component 50.By exposing the die connectors 56, existing solder regions on the die connectors 56 can be removed. A removal process can be applied to the various layers to remove excess material above the die connectors 56. The removal process can be a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like. After planarization, the top surfaces of the die connectors 56 and the dielectric layer 58 are coplanar (within process variations) and are exposed on the front face 50F of the IC component 50. As described in more detail below, the planarized front face 50F of the IC component 50 is connected to another device, such as an interposer.

[0015] In some embodiments, the IC component 50 is a stacked device comprising multiple semiconductor substrates 52. For example, the IC component 50 may be a memory device comprising multiple memory dies, such as a hybrid memory cube device (HMC device), a high-bandwidth memory device (HBM device), or the like. In such embodiments, the IC component 50 comprises multiple semiconductor substrates 52 interconnected by vias or silicon vias (TSVs). Each of the semiconductor substrates 52 may (but need not) have a separate interconnect structure 54.

[0016] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. Figure 9 shows cross-sectional views of intermediate steps during a process for manufacturing integrated circuit packages according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. 8. Integrated circuit packages 100 are formed by bonding IC components 50 to a wafer 70. In one embodiment, the integrated circuit packages 100 are chip-on-wafer packages (CoW packages), and the embodiments can also be applied to other three-dimensional integrated circuit packages (3DIC packages). The wafer 70 has package regions 100A, 100B, each comprising devices formed therein, such as interposers. Fig. 9 are the package regions 100A, 100B isolated to form integrated circuit packages 100, each of which represents an isolated section of the wafer 70 (e.g. an interposer 140, see Fig. 9) and the IC components 50, which are connected to the isolated section of the wafer 70. The integrated circuit packages 100 are then mounted onto a package substrate 200. In one embodiment, the resulting device is a chip-on-wafer-on-substrate (CoWoS) package, although it is understood that the embodiments can also be applied to other 3DIC packages.

[0017] In Fig. 2 a wafer 70 will be obtained. The wafer 70 comprises devices in the package regions 100A, 100B, which are subsequently separated in order to be incorporated into the integrated circuit packages 100. The devices formed on the wafer 70 can be interposers, integrated circuit dies, or the like. The wafer 70 comprises a substrate 72, an interconnect structure 74, die connectors 76, a dielectric layer 78, and conductive vias 80.

[0018] Substrate 72 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. Substrate 72 can comprise a semiconductor material such as silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof. Other substrates, such as a multilayer or gradient substrate, can also be used. Substrate 72 can be doped or undoped.In embodiments where interposers are formed in the wafer 70, the substrate 72 generally does not include any active devices therein, although the interposers may include passive devices formed in and / or on a front face (e.g., the upward-facing face) of the substrate 72. In embodiments where IC components are formed in the wafer 70, active devices such as transistors, capacitors, resistors, diodes, and the like may be formed in and / or on the front face of the substrate 72.

[0019] The interconnect structure 74 is located above the front surface of the substrate 72 and serves to electrically connect the devices (if any) of the substrate 72. The interconnect structure 74 can comprise one or more dielectric layer(s) and one or more corresponding metallization structures within the dielectric layer(s). Acceptable dielectrics for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other dielectrics may also be used, e.g., a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, or the like.The metallization structures can include conductive vias and / or traces to connect any devices to each other and / or to an external device. The metallization structures can be formed from a conductive material, such as a metal like copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure 74 can be formed by a damascus process, such as a simple damascus process, a dual damascus process, or the like.

[0020] The die connectors 76 are located on a front face 70F of the wafer 70. The die connectors 76 can be conductive pillars, pads, or the like, to which external connections are made. The die connectors 76 are located in and / or on the interconnect structure 74. For example, the die connectors 76 can be part of an upper metallization structure of the interconnect structure 74. The die connectors 76 can be made of a metal, such as copper, aluminum, or the like, and can be formed, for example, by plating or the like.

[0021] The dielectric layer 78 is located on the front face 70F of the wafer 70. The dielectric layer 78 is located in and / or on the interconnect structure 74. The dielectric layer 78 can, for example, be an upper dielectric layer of the interconnect structure 74. The dielectric layer 78 encapsulates the die connectors 76 laterally. The dielectric layer 78 can be an oxide, a nitride, a carbide, a polymer, or the like, or a combination thereof. The dielectric layer 78 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. First, the dielectric layer 78 can bury the die connectors 76 so that the upper surface of the dielectric layer 78 lies above the upper surfaces of the die connectors 76. The die connectors 76 are exposed to the dielectric layer 78 during wafer formation.A removal process can be applied to the various layers to remove excess material over the die connectors 76. The removal process can be a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like. After planarization, the top surfaces of the die connectors 76 and the dielectric layer 78 are coplanar (within process variations) and are exposed on the front face 70F of the wafer 70. As described in more detail below, the planarized front face 70F of the wafer 70 is connected to other devices, such as IC components.

[0022] The conductive vias 80 extend into the interconnect structure 74 and / or the substrate 72. The conductive vias 80 are electrically coupled to metallization structures of the interconnect structure 74. The conductive vias 80 are sometimes also referred to as TSVs. To form the conductive vias 80, cutouts can be created in the interconnect structure 74 and / or the substrate 72, for example, by etching, milling, laser techniques, a combination thereof, and / or the like. A thin dielectric material can be formed in the cutouts, e.g., by an oxidation process. A thin barrier layer can be conformally deposited in the openings, e.g., by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like.The barrier layer can be formed from an oxide, a nitride, a carbide, a combination thereof, or the like. A conductive material can be applied over the barrier layer and in the openings. The conductive material can be formed by an electrochemical coating process, CVD, ALD, PVD, a combination thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excess conductive material and the barrier layer are removed from a surface of the interconnect structure 74 or the substrate 72, for example, by a CMP. Remaining sections of the barrier layer and the conductive material form the conductive vias 80.

[0023] IC components 50 are bonded to the wafer 70. In this embodiment, the IC components 50 comprise multiple IC components 50A, 50B, each arranged in one of the package regions 100A, 100B. The IC components 50A, 50B can each have a single function (e.g., a logic device, a memory device, etc.) or they can have multiple functions (e.g., a SoC). In one embodiment, the IC components 50A are logic devices and the IC components 50B are memory devices. In this embodiment, one IC component 50A (e.g., a logic device) and one IC component 50B (e.g., a memory device) are bonded in each of the package regions 100A, 100B. In another embodiment, a single IC component 50 is glued into each of the package regions 100A, 100B.

[0024] The IC components 50 and the wafer 70 are bonded directly face-to-face by hybrid bonding, so that the front faces 50F of the IC components 50 are connected to the front face 70F of the wafer 70. Specifically, the dielectric layers 58 of the IC component 50 are bonded to the dielectric layer 78 of the wafer 70 by dielectric-to-dielectric bonding without the use of an adhesive material (e.g., a die attach film), and the die connectors 56 of the IC components 50 are bonded to the die connectors 76 of the wafer 70 by metal-to-metal bonding without the use of a eutectic material (e.g., solder). The bonding process may include pre-bonding and annealing. During pre-bonding, a slight clamping force is applied to press the IC components 50 against the wafer 70. The pre-bonding is carried out at a low temperature, e.g. room temperature, e.g.At a temperature in the range of approximately 15 °C to approximately 30 °C, and after pre-bonding, the dielectric layers 58, 78 are bonded together. The adhesive strength is then improved in a subsequent tempering step, in which the dielectric layers 58, 78 are tempered at a high temperature, e.g., at a temperature in the range of approximately 100 °C to approximately 450 °C. After tempering, bonds, such as fusion bonds, are formed that connect the dielectric layers 58, 78. The bonds can be, for example, covalent bonds between the material of dielectric layers 58 and the material of dielectric layer 78. The die connectors 56, 76 are connected to each other with a one-to-one correspondence. The die connectors 56, 76 can be in physical contact after pre-connection or expand to be brought into physical contact during tempering.Furthermore, during annealing, the material of the die connectors 56, 76 (e.g., copper) mixes, resulting in the formation of metal-to-metal connections. Therefore, the resulting connections between the IC components 50 and the wafer 70 are hybrid connections, comprising both dielectric-to-dielectric and metal-to-metal bonds.

[0025] The width of each IC component 50 is less than the width of the wafer 70, allowing multiple IC components 50 to be bonded to the wafer 70. As described in more detail below, the IC components 50A can also have a different width than the IC components 50B. When the IC components 50 and the wafer 70 are bonded by hybrid bonding, the outer edges 50E and the inner edges 50N of the IC components 50 form an interface with the planarized surface of the dielectric layer 78. The outer edges 50E of the IC components 50 are the edges of the IC components 50 in each respective package region 100A, 100B that point away from other IC components 50 in the respective package region 100A, 100B. The inner edges 50N of the IC components 50 are the edges of the IC components 50 in each respective package region 100A, 100B that point towards other IC components 50 in the respective package region 100A, 100B. The outer edges 50E are subject to high stress, e.g.The stress on the outer edges 50E is greater than on the inner edges 50N, and this can be further increased if the IC components 50 are subsequently encapsulated with a material that has a high Young's modulus and / or a high coefficient of thermal expansion (CTE). Excessive stress on the outer edges 50E can damage the IC components 50 (e.g., the interconnect structures 54 and / or the dielectric layers 58), the wafer 70 (e.g., the interconnect structure 74 and / or the dielectric layer 78), or both. For example, delamination of the dielectric layers 58, 78 can occur. As described in more detail below, layers are formed around the outer edges 50E to buffer the stress on the outer edges 50E. This can improve the yield and reliability of the integrated circuit packages 100, especially if the IC components 50 are subsequently encapsulated.

[0026] In Fig. 3. Buffer layers 108 are applied to the front face 70F of the wafer 70 and around the IC components 50. Specifically, a buffer layer 108 is distributed around the IC components 50 in each of the package regions 100A, 100B. The buffer layers 108 are formed at locations subject to high stress (e.g., the outer edges 50E of the IC components 50). The buffer layers 108 are formed from a stress-reducing material that helps to buffer stresses at the outer edges 50E (see Fig. 2) The stress-reducing material comprises a polymer material and optionally includes fillers and / or a surfactant. The polymer material may be an epoxy, polyimide-based material, BCB-based material, silicone, acrylic, or the like. The fillers are formed from a material that provides mechanical strength and thermal dispersion for the buffer layers 108, such as silicon dioxide (SiO2) particles. The surfactant may be polyvinyl alcohol or the like. The stress-reducing material (comprising the polymer material, fillers, and / or surfactant) may be formed by printing (e.g., inkjet printing), deposition (e.g., standard deposition, tilt deposition, etc.), spin-on coating, lamination, deposition, or the like.

[0027] In this embodiment, the buffer layers 108 have fillet sections 108F and gap sections 108G. The gap sections 108G are arranged in the gaps between the IC components 50. The fillet sections 108F are arranged along the outer edges 50E of the IC components 50 and extend accordingly. In other embodiments, the gap sections 108G are omitted, and the buffer layers 108 have only the fillet sections 108F.

[0028] In this embodiment, the fillet sections 108F and the gap sections 108G have flat upper surfaces. In other embodiments, the fillet sections 108F and / or the gap sections 108G have concave upper surfaces. The types of upper surfaces can be determined by the amount (e.g., the volume) of the applied stress-reducing material and by whether a surfactant is included in the stress-reducing material. As described in more detail below, applying less stress-reducing material and / or including a surfactant can form concave upper surfaces.

[0029] In this embodiment, the buffer layers 108 extend completely over the sidewalls of the IC components 50, so that no sections of the sidewalls of the IC components 50 are exposed to (e.g., contacted by) a subsequently formed encapsulation material. In other embodiments, the buffer layers 108 can extend partially to the sidewalls of the IC components 50, so that sections of the sidewalls of the IC components 50 are exposed to the subsequently formed encapsulation material. As described in more detail below, applying less stress-reducing material can form the buffer layers 108 in such a way that they extend less over the sidewalls of the IC components 50.

[0030] In Fig. 4. An encapsulation material 110 is formed on the various components. The encapsulation material 110 is formed from a molding material or compound. The molding material comprises a polymer material and optionally includes filler materials. The polymer material can be an epoxy or the like. The filler materials are formed from a material that provides mechanical strength and thermal dispersion for the encapsulation material 110, such as silicon dioxide (SiO2) particles. The molding material (comprising the polymer material and / or the filler materials) can be formed by compression molding, injection molding, or the like. The polymer material of the encapsulation material 110 differs from the polymer material of the buffer layers 108 and is formed by a different process than the stress-reducing material of the buffer layers 108.The encapsulation material 110 can be formed over the front face 70F of the wafer 70, burying or covering the IC components 50 and the buffer layers 108. The encapsulation material 110 is then cured. A planarization process can be performed to planarize the top surface of the encapsulation material 110. The planarization process can be chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like. In the illustrated embodiment, the IC components 50 remain covered after planarizing the encapsulation material 110. In another embodiment, the IC components 50 are exposed by planarizing the encapsulation material 110.

[0031] The encapsulation material 110 surrounds and protects the IC components 50. However, the mold material of the encapsulation material 110 has a higher Young's modulus and a higher coefficient of thermal expansion (CTE) than the dielectric of the dielectric layers 58, 78. The expansion of the encapsulation material 110 at high temperatures can induce stresses on the IC components 50, particularly at the outer edges 50E, which can damage the IC components 50 and / or the wafer 70. The buffer layers 108 are formed from a stress-reducing material that is softer at high temperatures than the encapsulation material 110 and therefore helps to buffer stresses induced by the encapsulation material 110 at the outer edges 50E (see Figure 1). Fig. 2) are caused during expansion. The stress-reducing material of the buffer layers 108 has several properties that enable it to effectively buffer stresses from the mold material of the encapsulation material 110 at high temperatures. Specifically, the stress-reducing material of the buffer layers 108 has a different Young's modulus, a different CTE, a different filler material charge (e.g., amount of filler material), a different average filler particle size, and a different strain than the mold material of the encapsulation material 110.

[0032] The stress-reducing material of the buffer layers 108 has a lower Young's modulus than the molding material of the encapsulation material 110. In some embodiments, the Young's modulus of the stress-reducing material is approximately 5% to approximately 90% of the Young's modulus of the molding material. For example, the stress-reducing material may have a Young's modulus in the range of approximately 0.001 GPa to approximately 0.9 GPa, and the molding material may have a Young's modulus in the range of approximately 1 GPa to approximately 2.5 GPa.

[0033] The stress-reducing material of the buffer layers 108 has a similar or greater CTE than the molding material of the encapsulation material 110. In some embodiments, the CTE of the stress-reducing material is approximately 150% to approximately 500% of the CTE of the molding material. For example, the stress-reducing material can have a CTE in the range of approximately 15 ppm / °C to approximately 70 ppm / °C below its glass transition temperature (Tg). g) and a CTE in the range of approximately 50 ppm / °C to approximately 300 ppm / °C above its T g exhibit, and the molding material can have a CTE in the range of approximately 5 ppm / °C to approximately 22 ppm / °C below its T g and a CTE in the range of approximately 22 ppm / °C to approximately 60 ppm / °C above its T g exhibit.

[0034] The stress-reducing material of the buffer layers 108 has a lower filler charge than the molding material of the encapsulation material 110 (when both the stress-reducing material and the molding material include fillers). In some embodiments, the filler charge of the stress-reducing material is approximately 0% to approximately 90% of the filler charge of the molding material. For example, the stress-reducing material may have a filler charge in the range of approximately 0% to approximately 78%, and the molding material may have a filler charge in the range of approximately 75% to approximately 92%.

[0035] The stress-reducing material of the buffer layers 108 has a smaller average filler particle size than the molding material of the encapsulation material 110 (when both the stress-reducing material and the molding material include fillers). In some embodiments, the average filler particle size of the stress-reducing material is approximately 0.2% to approximately 60% of the average filler particle size of the molding material. For example, the stress-reducing material may have an average filler particle size in the range of approximately 0.01 µm to approximately 10 µm, and the molding material may have an average filler particle size in the range of approximately 5 µm to approximately 50 µm.

[0036] The stress-reducing material of the buffer layers 108 exhibits a greater strain than the mold material of the encapsulation material 110. In some embodiments, the strain of the stress-reducing material is approximately 120% to approximately 5000% of the strain of the mold material. For example, the stress-reducing material may exhibit a strain in the range of approximately 2% to approximately 100%, and the mold material may exhibit a strain in the range of approximately 1.2% to approximately 5%.

[0037] Forming the stress-reducing material of the buffer layers 108 and the molding material of the encapsulation material 110 with a Young's modulus, a coefficient of thermal expansion (CTE), a filler charge, an average filler particle size, and a strain within the ranges discussed above enables the buffer layers 108 to buffer sufficient stress from the encapsulation material 110 to prevent damage to the IC components 50 and / or the wafer 70 at the outer edges 50E. If the stress-reducing material of the buffer layers 108 and the molding material of the encapsulation material 110 are formed with a Young's modulus, a CTE, a filler charge, an average filler particle size, or a strain outside the ranges discussed above, the buffer layers 108 may not be able to buffer sufficient stress from the encapsulation material 110 to prevent damage to the IC components 50 and / or the wafer 70 at the outer edges 50E.

[0038] In addition to the different properties described above, the buffer layers 108 and the encapsulation material 110 exhibit different properties than the dielectric layers 58, 78. Specifically, the dielectric of the dielectric layers 58, 78 has a higher Young's modulus and a lower CTE than the voltage-reducing material of the buffer layers 108 and also the molding material of the encapsulation material 110. In some embodiments, the Young's modulus of the molding material is approximately 3% to approximately 50% of the Young's modulus of the dielectric, and the Young's modulus of the voltage-reducing material is approximately 6% to approximately 30% of the Young's modulus of the dielectric. In some embodiments, the CTE of the molding material is approximately 500% to approximately 2500% of the CTE of the dielectric, and the CTE of the voltage-reducing material is approximately 3000% to approximately 30000% of the CTE of the dielectric.Continuing the example above, the dielectric can have a Young's modulus in the range of about 30 GPa to about 300 GPa and a CTE in the range of about 0.3 ppm / °C to about 5 ppm / °C.

[0039] In Fig. 5. The intermediate structure is flipped (not illustrated) to prepare the back side 70B of the substrate 72 for processing. The intermediate structure can be placed on a support substrate 112 or another suitable support structure for subsequent processing. For example, the support substrate 112 can be attached to the encapsulation material 110. The support substrate 112 can be attached to the encapsulation material 110 by a release layer. The release layer can be formed from a polymer-based material that can be removed from the structure along with the support substrate 112 after processing. In some embodiments, the support substrate 112 is a substrate such as a bulk semiconductor or a glass substrate. In some embodiments, the release layer is a thermally removable epoxy-based material that loses its adhesive properties upon heating, such as a light-to-heat conversion release coating (LTHC release coating).

[0040] In Fig. 6. The substrate 72 is thinned to expose the conductive vias 80. Exposure of the conductive vias 80 can be achieved by a thinning process such as grinding, chemical-mechanical polishing (CMP), back-etching, combinations thereof, or the like. In the illustrated embodiment, a cutout process is performed to cut out the back side of the substrate 72 such that the conductive vias 80 protrude from the back side 70B of the wafer 70. The cutout process can be, for example, a suitable back-etching process, chemical-mechanical polishing (CMP), or the like. In some embodiments, the thinning process for exposing the conductive vias 80 includes CMP, and the conductive vias 80 protrude from the back side 70B of the wafer 70 due to the dishing occurring during the CMP.An insulating layer 114 is then formed on the back side of the substrate 72, surrounding the protruding sections of the conductive vias 80. In some embodiments, the insulating layer 114 is formed from a silicon-containing insulator, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and can be formed by a suitable deposition process, such as spin coating, CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), or the like. Initially, the insulating layer 114 can bury the conductive vias 80. A removal process can be applied to the various layers to remove excess material above the conductive vias 80. The removal process can be a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like.After planarization, the exposed areas of the conductive vias 80 and the insulating layer 114 are coplanar (within process variations) and are exposed on the back side 70B of the wafer 70. In another embodiment, the insulating layer 114 is omitted, and the exposed areas of the substrate 72 and the conductive vias 80 are coplanar (within process variations).

[0041] In Fig. Under Bump Metallurgies (UBMs) 132 are formed on the exposed areas of the conductive vias 80 and the insulating layer 114 (or the substrate 72 if the insulating layer 114 is omitted). As an example of UBM formation, a seed layer (not illustrated) is formed over the exposed areas of the conductive vias 80 and the insulating layer 114 / substrate 72. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer with several sublayers of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer.The photoresist can be formed by spin-on coating or similar processes and exposed to light for structuring. The structure of the photoresist corresponds to UBMs 132. The structuring creates openings through the photoresist for exposure of the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or similar processes. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, or similar. The photoresist and portions of the seed layer where the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ash removal or stripping process, such as using oxygen plasma or similar methods.Once the photoresist is removed, exposed sections of the seed layer are removed, for example by an acceptable etching process. The remaining sections of the seed layer and the conductive material form the UBMs 132.

[0042] Furthermore, conductive connectors 136 are formed on the UBMs 132. The conductive connectors 136 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connectors 136 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 136 are formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer has formed on the structure, melting can be performed to shape the material into the desired bump form. In another embodiment, the conductive connectors comprise 136 metal columns (e.g.B. copper columns), formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cover layer is formed on the upper surface of the metal columns. The metal cover layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0043] In Fig. 8. A support debonding process is carried out to separate (debonde) the support substrate 112 from the encapsulation material 110. In embodiments where the support substrate 112 is attached to the encapsulation material 110 by a release layer, the debonding process includes projecting light, e.g., laser light or ultraviolet (UV) light, onto the release layer, causing the release layer to decompose under the heat of the light and allowing the support substrate 112 to be removed. The structure is then turned over and placed on a tape (not illustrated).

[0044] The encapsulation material 110 is then thinned to expose the IC components 50. Exposure of the IC components 50 can be achieved through a thinning process, such as grinding, chemical-mechanical polishing (CMP), back-etching, combinations thereof, or the like. After the thinning process, the top surfaces of the encapsulation material 110 of the IC components 50 are coplanar (within process variations). The thinning is carried out until a desired amount of the encapsulation material 110 has been removed. Although the buffer layers 108 protect the outer edges 50E from stress, the encapsulation material 110 provides overall greater protection for the resulting integrated circuit packages 100 than the buffer layers 108.In this way, after thinning, enough of the encapsulation material 110 remains so that the integrated circuit packages 100 comprise more of the encapsulation material 110 (by volume) than the buffer layers 108. In some embodiments, the volume of the buffer layers 108 is about 2% to about 10% of the volume of the encapsulation material 110. For example, the buffer layers 108 in each integrated circuit package 100 can have a volume in the range of about 0.26 mm³. 3 up to about 1.3 mm 3 have, if the encapsulation material 110 has a volume of approximately 13 mm 3 exhibits. In this embodiment, the upper surfaces of the throat sections 108F and the gap sections 108G (see Fig. 3) and the encapsulation material 110 is also coplanar (within process variations). In other embodiments, some or all of the upper surfaces of the buffer layers 108 are arranged below the upper surface of the encapsulation material 110.

[0045] In Fig. 9. A singulation process is performed by cutting along scribed line regions, e.g., between package regions 100A and 100B. The singulation process may involve sawing, dicing, or the like. For example, the singulation process may involve sawing the insulating layer 114, the encapsulation material 110, the dielectric layer 78, the interconnect structure 74, and the substrate 72. The singulation process separates package regions 100A and 100B from each other. The resulting singulated integrated circuit package 100 originates from one of package regions 100A or 100B. The singulation process forms interposers 140 from the singulated sections of the wafer 70 and the insulating layer 114 (if present). Each of the integrated circuit packages 100 comprises one interposer 140.As a result of the singulation process, the outer side walls of the interposer 140 and the encapsulation material 110 are laterally congruent (within process variations).

[0046] The integrated circuit package 100 is then turned over and mounted on a package substrate 200 using the conductive connectors 136. The package substrate 200 comprises a substrate core 202, which may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, the substrate core 202 may be an SOI substrate. In general, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 202 is an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is fiberglass resin, such as FR4.Alternatives for the core material include bismaleimide triazine resin (BT resin) or, alternatively, other printed circuit board (PCB) materials or films. For the substrate core 202, a build-up film such as the Ajinomoto build-up film (ABF) or other laminates can be used.

[0047] The substrate core 202 can include active and passive devices (not illustrated). Devices such as transistors, capacitors, resistors, combinations thereof, and the like can be used to meet the structural and functional requirements of the system design. The devices can be formed using any method.

[0048] The substrate core 202 can also include metallization layers and vias (not illustrated) and bond pads 204 over the metallization layers and vias. The metallization layers can be formed over the active and passive devices and are designed to connect the various devices to form a functional circuit arrangement. The metallization layers can be formed from alternating layers of dielectric material (e.g., a dielectric with a low k-value) and conductive material (e.g., copper) with vias connecting the conductive material layers, and can be formed by any suitable method (e.g., deposition, damascening, dual damascening, or the like). In some embodiments, the substrate core 202 is essentially free of active and passive devices.

[0049] The conductive connectors 136 are melted to attach the UBMs 132 to the bond pads 204. The conductive connectors 136 connect the integrated circuit package 100, comprising the metallization structures of the interconnect structure 74, to the package substrate 200, comprising the metallization layers in the substrate core 202. Therefore, the package substrate 200 is electrically connected to the IC components 50. In some embodiments, passive devices (e.g., surface-mount devices (SMDs), not illustrated) can be attached to the integrated circuit package 100 prior to mounting it on the package substrate 200 (e.g., bonded to the UBMs 132). In such embodiments, the passive devices can be glued to the same surface of the integrated circuit package 100 as the conductive connectors 136. In some embodiments, passive devices (e.g., SMDs, not illustrated) can be attached to the package substrate 200, e.g.at the Bondpads 204.

[0050] In some embodiments, an underfill 206 is formed between the integrated circuit package 100 and the package substrate 200, surrounding the conductive connectors 136 and the UBMs 132. The underfill 206 can be formed by a capillary flow process after the integrated circuit package 100 has been attached or by a suitable deposition process before the integrated circuit package 100 has been attached. The underfill 206 can be a continuous material extending from the package substrate 200 to the interposer 140 (e.g., the insulating layer 114). The material of the underfill 206 differs from the stress-reducing material of the buffer layers 108 and is formed by a different process.

[0051] Optionally, a heat spreader 208 is attached to the integrated circuit package 100. The heat spreader 208 can be made of a material with high thermal conductivity, such as steel, stainless steel, copper, or the like, or combinations thereof. The heat spreader 208 protects the integrated circuit package 100 and forms a thermal path to dissipate heat from the various components of the integrated circuit package 100 (e.g., the IC components 50). The heat spreader 208 is in contact with the IC components 50, the encapsulation material 110, and optionally the buffer layers 108.

[0052] Fig. Figure 10 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the one in Fig. 9 described embodiment, except that the gap section 108G has a concave upper surface, while the throat sections 108F have flat upper surfaces. At least one portion of the upper surface of the gap section 108G is therefore located below and buried beneath the upper surface of the encapsulation material 110. The gap section 108G can be formed with a concave upper surface by using less stress-reducing buffer layer material 108 than in the embodiment of Fig. 9 is applied. For example, the volume of the buffer layer 108 in this embodiment can be approximately 70% to approximately 95% of the volume of the buffer layer 108 in the embodiment of Fig. 9.

[0053] Fig. Figure 11 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the embodiment described with reference to Fig. as described in Figure 10, except that the buffer layer 108 only partially extends over the sidewalls of the IC components 50, so that sections of the sidewalls of the IC components 50 are exposed to the encapsulation material 110. Specifically, the buffer layer 108 covers the sidewalls of the interconnect structure 54 and a section of the sidewalls of the semiconductor substrate 52 (see Figure 10). Fig. 1) The upper surfaces of the throat sections 108F and the gap section 108G are therefore arranged below and embedded in the upper surface of the encapsulation material 110. The buffer layer 108 can be formed such that it extends only partially upwards along the side walls of the IC components 50 by using less stress-reducing material of the buffer layer 108 than in the embodiment of Fig. 10 is applied. For example, the volume of the buffer layer 108 in this embodiment can be approximately 50% to approximately 80% of the volume of the buffer layer 108 in the embodiment of Fig. 10. Furthermore, the thickness T1 of the buffer layer 108 is greater than the thickness T2 of the dielectric layer 78, which can contribute to a further reduction of the voltage at the outer edges 50E.

[0054] Fig. Figure 12 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the embodiment described with reference to Fig. as described in Figure 10, except that the throat sections 108F and the gap section 108G each have concave upper surfaces. At least one portion of the upper surface of the gap section 108G is therefore located below and buried beneath the upper surface of the encapsulation material 110. The throat sections 108F and the gap section 108G can be formed with concave upper surfaces by using less stress-reducing material of the buffer layer 108 than in the embodiment described in Figure 10. Fig. 10 is applied and / or by incorporating a surfactant into the stress-reducing material. For example, the volume of the buffer layer 108 in this embodiment can be approximately 50% to approximately 70% of the volume of the buffer layer 108 in the embodiment of Fig. 10. In this embodiment as well, the buffer layer 108 extends completely over the sidewalls of the IC components 50, so that no sections of the sidewalls of the IC components 50 are exposed to the encapsulation material 110. Specifically, the buffer layer 108 covers the sidewalls of the interconnect structure 54 and the sidewalls of the semiconductor substrate 52 (see Fig. 1).

[0055] Fig. Figure 13 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the embodiment described with reference to Fig. as described in Figure 12, except that the buffer layer 108 only partially extends over the sidewalls of the IC components 50, so that sections of the sidewalls of the IC components 50 are exposed to the encapsulation material 110. Specifically, the buffer layer 108 covers the sidewalls of the interconnect structure 54 and a section of the sidewalls of the semiconductor substrate 52 (see Figure 12). Fig. 1) The upper surfaces of the throat sections 108F and the gap section 108G are therefore arranged below and embedded in the upper surface of the encapsulation material 110. The buffer layer 108 can be formed such that it extends only partially upwards along the side walls of the IC components 50 by using less stress-reducing material of the buffer layer 108 than in the embodiment of Fig. 12 is applied. For example, the volume of the buffer layer 108 in this embodiment can be approximately 50% to approximately 80% of the volume of the buffer layer 108 in the embodiment of Fig. 12. The thickness T1 of the buffer layer 108 is greater than the thickness T2 of the dielectric layer 78, which can contribute to a further reduction of the voltage at the outer edges 50E.

[0056] Fig. Figure 14 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the embodiment described with reference to Fig. 9 is described, except that the buffer layer 108 is at least partially arranged between the interposer 140 and each of the IC components 50. The IC components 50 have tapered sidewalls whose width increases in a direction extending from the back sides of the IC components 50 to the front sides of the IC components 50. The IC components 50 with tapered sidewalls can be formed by a cutting process at the edges of the semiconductor substrate 52 and / or the interconnect structure 54 (see Fig. 1) is performed before the IC components 50 are connected to the interposer 140. The cutting process may include a mechanical, laser, or plasma sawing process. Forming the IC components 50 with tapered sidewalls can help to further reduce stress on the outer edges 50E.

[0057] Fig. Figure 15 is a cross-sectional view of an integrated circuit package according to some embodiments. This embodiment is similar to the embodiment described with reference to Fig. as described in Figure 9, except that several integrated circuit packages 100 are mounted on the same package substrate 200 and the same heat spreader 208 is attached to each of the integrated circuit packages 100. In one embodiment, the resulting device is a multi-chip module package (MCM package), although the embodiments can also be applied to other 3DIC packages. An identical underfill 206 can be formed between the package substrate 200 and each of the integrated circuit packages 100.

[0058] Fig. Figures 16A to 16E are top views of integrated circuit packages according to various embodiments. Several layouts for the buffer layer 108 are illustrated. As shown in the top views, the IC components 50 have four corners 50C and four side walls 50S, with each side wall 50S extending between two corners 50C. As can also be seen more clearly, the IC components 50A can have greater widths than the IC components 50B in several directions.

[0059] In Fig. 16A both the throat sections 108F and the gap section 108G are exposed after thinning the encapsulation material 110 by the encapsulation material 110. Fig. 16A can show a top view of the embodiment of Fig. 9. In this embodiment, the exposed throat sections 108F extend around the corners 50C of the IC components 50 and extend continuously along the side walls 50S of the IC components 50.

[0060] In Fig. 16B some of the throat sections 108F are exposed through the encapsulation material 110 after dilution, but the gap section 108G remains covered after dilution of the encapsulation material 110. Fig. 16B can show a top view of the embodiment of Fig. 10. In this embodiment, the exposed throat sections 108F extend around the corners 50C of the IC components 50 and extend discontinuously along the side walls 50S of the IC components 50.

[0061] In Fig. 16C neither the throat sections 108F nor the gap section 108G are exposed through the encapsulation material 110, but remain covered after thinning of the encapsulation material 110. Fig. 16C can show a top view of the embodiments of the Fig. 11 and Fig. Be 13.

[0062] In Fig. 16D the gap section 108G is exposed after dilution of the encapsulation material 110 by the encapsulation material 110, but the throat sections 108F remain covered after dilution of the encapsulation material 110. Fig. 16D can show a top view of the embodiment of Fig. 9.

[0063] In Fig. 16E some of the throat sections 108F are exposed through the encapsulation material 110 after dilution, but the gap section 108G remains covered after dilution of the encapsulation material 110. Fig. 16E can show a top view of the embodiment of Fig. 10. In this embodiment, the buffer layer 108 comprises first sections 108A formed from a first polymer material and second sections 108B formed from a second polymer material. The first sections 108A can be the sections around the outer edges 50E of the IC components 50. The second sections 108B can be the sections around the inner edges 50N of the IC components 50. The first polymer material and the second polymer material are each similar to those described above for Fig. The three discussed stress-reducing materials are different from each other. For example, the first sections 108A may have a lower Young's modulus / CTE than the second sections 108B. In other words, in the embodiments of the Fig. In 16A to 16D, the buffer layer 108 comprises a single stress-reducing material, but in the embodiment of Fig.In 16E, the buffer layer 108 comprises several voltage-reducing materials. The voltage-reducing materials can be selected based on the desired degree of voltage buffering in the various regions of the integrated circuit packages 100.

[0064] Embodiments can offer advantages. If the IC components 50 are bonded directly to the wafer 70 by hybrid adhesive bonding, the expansion of the encapsulation material 110 at high temperatures can exert stresses on the IC components 50, particularly at the outer edges 50E, which can damage the IC components 50 and / or the wafer 70. For example, delamination of the dielectric layers 58, 78 can occur. The buffer layers 108 help to buffer stresses in regions of the integrated circuit packages 100 that are subject to high stresses, such as the outer edges 50E of the IC components 50. Specifically, the buffer layers 108 are formed from a stress-reducing material that expands less at high temperatures than the encapsulation material 110 and thus helps to buffer stresses caused by the encapsulation material 110 during expansion.The integrated circuit packages 100 can be repeatedly exposed to high temperatures during manufacturing, e.g., during testing. The formation of the buffer layers 108 helps to protect the integrated circuit packages 100 during high-temperature processing, thus improving the yield and reliability of the integrated circuit packages 100.

[0065] In one embodiment, a method comprises: connecting a first IC component and a second IC component with an interposer using dielectric-to-dielectric bonds and metal-to-metal bonds; forming a stress-reducing material around the first IC component and the second IC component, wherein the stress-reducing material has a first modulus of elasticity; encapsulating the stress-reducing material, the first IC component, and the second IC component with a molding material, wherein the molding material has a second modulus of elasticity, the first modulus of elasticity being smaller than the second modulus of elasticity; and thinning the molding material to expose the first IC component and the second IC component.

[0066] In some embodiments of the method, the stress-reducing material comprises a first polymer material and the molding material a second polymer material, wherein the first polymer material differs from the second polymer material. In some embodiments of the method, the stress-reducing material further comprises first filler materials and the molding material further comprises second filler materials. In some embodiments of the method, the stress-reducing material further comprises a surfactant. In some embodiments of the method, the first polymer material is a first epoxy, a polyimide-based material, a benzocyclobutene (BCB)-based material, a silicone material, or an acrylic material, and the second polymer material is a second epoxy.In some embodiments of the method, the stress-reducing material has a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, the fillet sections are arranged along the outer edges of the first IC component and the second IC component, wherein the gap section is exposed after thinning the mold material and wherein the fillet sections are exposed after thinning the mold material.In some embodiments of the method, the stress-reducing material has a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, the fillet sections are arranged along the outer edges of the first IC component and the second IC component, wherein the gap section remains covered after thinning the mold material, and wherein the fillet sections remain covered after thinning the mold material.In some embodiments of the method, the stress-reducing material has a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, the fillet sections are arranged along the outer edges of the first IC component and the second IC component, wherein the gap section is exposed after thinning the mold material and wherein the fillet sections remain covered after thinning the mold material.In some embodiments of the method, the stress-reducing material has a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, the fillet sections are arranged along the outer edges of the first IC component and the second IC component, wherein the gap section remains covered after thinning the mold material, and wherein the fillet sections are exposed after thinning the mold material.

[0067] In one embodiment, a device comprises: an interposer; a first IC component bonded to the interposer by dielectric-to-dielectric bonds and metal-to-metal bonds; a second IC component bonded to the interposer by dielectric-to-dielectric bonds and metal-to-metal bonds; a buffer layer around the first IC component and the second IC component, wherein the buffer layer comprises a stress-reducing material having a first Young's modulus; and an encapsulation material around the buffer layer, the first IC component, and the second IC component, wherein the encapsulation material comprises a molding material having a second Young's modulus, the first Young's modulus being smaller than the second Young's modulus.

[0068] In some embodiments of the device, the stress-reducing material has a first coefficient of thermal expansion and the molding material has a second coefficient of thermal expansion, wherein the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion. In some embodiments of the device, the stress-reducing material comprises first filler materials with a first filler charge and the molding material comprises second filler materials with a second filler charge, wherein the first filler charge is less than the second filler charge.In some embodiments of the device, the stress-reducing material comprises first filler materials with a first average filler particle size, and the molding material comprises second filler materials with a second average filler particle size, wherein the first average filler particle size is smaller than the second average filler particle size. In some embodiments of the device, the stress-reducing material has a first strain and the molding material has a second strain, wherein the first strain is smaller than the second strain.

[0069] In one embodiment, a device comprises: an interposer; a first IC component bonded to the interposer by dielectric-to-dielectric bonds and metal-to-metal bonds; a second IC component bonded to the interposer by dielectric-to-dielectric bonds and metal-to-metal bonds; a buffer layer with a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, and the fillet sections are arranged along outer edges of the first IC component and the second IC component; and an encapsulation material surrounding the buffer layer, the first IC component, and the second IC component, wherein the encapsulation material has a different modulus of elasticity, coefficient of thermal expansion, filler charge, average filler particle size, and strain than the buffer layer.

[0070] In some embodiments of the device, the gap section has a concave upper surface, and the fillet sections have concave upper surfaces. In some embodiments of the device, the gap section has a flat upper surface, and the fillet sections have flat upper surfaces. In some embodiments of the device, the gap section has a concave upper surface, and the fillet sections have flat upper surfaces. In some embodiments of the device, the buffer layer comprises a single stress-reducing material. In some embodiments of the device, the buffer layer comprises multiple stress-reducing materials.

Claims

[1] Procedure, encompassing: Connecting a first IC component and a second IC component with an interposer using dielectric-to-dielectric bonds and metal-to-metal bonds; Forming a stress-reducing material around the first IC component and the second IC component, wherein the stress-reducing material has a first Young's modulus; Encapsulating the stress-reducing material, the first IC component, and the second IC component with a molding material, wherein the molding material has a second Young's modulus, the first Young's modulus being smaller than the second Young's modulus; and Thinning the molding material to expose the first IC component and the second IC component, wherein the stress reduction material has first filler materials with a first average filler particle size and the molding material has second filler materials with a second average filler particle size, wherein the first average filler particle size is smaller than the second average filler particle size. [2] The method of claim 1, wherein the stress reduction material comprises a first polymer material and the molding material comprises a second polymer material, wherein the first polymer material is different from the second polymer material. [3] Method of claim 2, wherein the stress-reducing material further comprises a surfactant. [4] Method according to one of claims 2 or 3, wherein the first polymer material is a first epoxy, a polyimide-based material, a benzocyclobutene (BCB)-based material, a silicone material or an acrylic material, and the second polymer material is a second epoxy. [5] Method according to any one of claims 1 to 4, wherein the stress reduction material has a gap section and throat sections, wherein the gap section is arranged between the first IC component and the second integrated circuit device, wherein the throat sections are arranged along the outer edges of the first IC component and the second integrated circuit device, wherein the gap section is exposed after thinning the molding material and wherein the throat sections are exposed after thinning the molding material. [6] Method according to any one of claims 1 to 4, wherein the stress reduction material has a gap section and throat sections, wherein the gap section is arranged between the first IC component and the second integrated circuit device, wherein the throat sections are arranged along the outer edges of the first IC component and the second integrated circuit device, wherein the gap section remains covered after thinning the molding material and wherein the throat sections remain covered after thinning the molding material. [7] Method according to any one of claims 1 to 4, wherein the stress reduction material has a gap section and throat sections, wherein the gap section is arranged between the first IC component and the second integrated circuit device, wherein the throat sections are arranged along the outer edges of the first IC component and the second integrated circuit device, wherein the gap section is exposed after thinning the molding material and wherein the throat sections remain covered after thinning the molding material. [8] Method according to any one of claims 1 to 4, wherein the stress reduction material has a gap section and throat sections, wherein the gap section is arranged between the first IC component and the second integrated circuit device, wherein the throat sections are arranged along the outer edges of the first IC component and the second integrated circuit device, wherein the gap section remains covered after thinning the molding material and wherein the throat sections are exposed after thinning the molding material. [9] Device comprising: an interposer; a first IC component that is bonded to the interposer with dielectric-to-dielectric bonds and metal-to-metal bonds; a second IC component that is bonded to the interposer with dielectric-to-dielectric bonds and metal-to-metal bonds; a buffer layer around the first IC component and the second IC component, wherein the buffer layer comprises a stress-reducing material with a first Young's modulus; and an encapsulation material around the buffer layer, the first integrated circuit device and the second integrated circuit device, wherein the encapsulation material has a molding material with a second modulus of elasticity, wherein the first modulus of elasticity is smaller than the second modulus of elasticity. wherein the stress reduction material has first filler materials with a first average filler particle size and the molding material has second filler materials with a second average filler particle size, wherein the first average filler particle size is smaller than the second average filler particle size. [10] Device of claim 9, wherein the stress reduction material has a first coefficient of thermal expansion and the molding material has a second coefficient of thermal expansion, wherein the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion. [11] Device of claim 9 or 10, wherein the stress reduction material comprises first filling materials with a first filling material charge and the molding material comprises second filling materials with a second filling material charge, wherein the first filling material charge is smaller than the second filling material charge. [12] Device according to any one of claims 9 to 11, wherein the stress-reducing material has a first strain and the molding material has a second strain, wherein the first strain is smaller than the second strain. [13] Device comprising: an interposer; a first IC component that is bonded to the interposer with dielectric-to-dielectric bonds and metal-to-metal bonds; a second IC component that is bonded to the interposer with dielectric-to-dielectric bonds and metal-to-metal bonds; a buffer layer with a gap section and fillet sections, wherein the gap section is arranged between the first IC component and the second IC component, and wherein the fillet sections are arranged along outer edges of the first IC component and the second IC component; and an encapsulation material around the buffer layer, the first IC component and the second IC component, wherein the encapsulation material has a different modulus of elasticity, a different coefficient of thermal expansion, a different filler charge and a different average filler particle size and a different strain than the buffer layer, where the average filler particle size of the buffer layer is smaller than the average filler particle size of the encapsulation material. [14] Device of claim 13, wherein the gap section has a concave upper surface and the throat sections have concave upper surfaces. [15] Device of claim 13, wherein the gap section has a straight upper surface and the throat sections have straight upper surfaces. [16] Device of claim 13, wherein the gap section has a concave upper surface and the throat sections have straight upper surfaces. [17] Device according to any one of claims 13 to 16, wherein the buffer layer comprises a single stress-reducing material. [18] Device according to one of claims 13 to 17, wherein the buffer layer comprises several stress-reducing materials.

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