MEMORY ARRAY, SEMICONDUCTOR DEVICE AND METHOD

Abstract

Semiconductor device comprising: a first channel region (54) over a semiconductor substrate (50); a second channel region (54) located directly above the first channel region (54) in a vertical direction; a first gate structure (100, 102) enclosing the first channel region (54) and the second channel region (54); a third channel region (54) adjacent to the first channel region (54) in a horizontal direction; a first source / drain region (92A) electrically coupled to the first channel region (54) and the third channel region (54); and a second source / drain region (92B) electrically coupled to the second channel region (54) and insulated from the first source / drain region (92A), wherein a first dielectric material (96) extends between the first source / drain region (92A) and the second source / drain region (92B), wherein a second gate structure (100, 102) surrounds the third channel region (54), and the second gate structure (100, 102) is separated from the first gate structure (100, 102) by a second dielectric material (106).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers over a semiconductor substrate and patterning the various layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that need to be addressed.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2020 / 0 013 896 A1, US 2020 / 0 161 339 A1, US 2020 / 0 135 937 A1 and WO 2019 / 168 541 A1.

[0004] The invention is defined by the main claim and the subordinate claim. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of discussion. The Fig. 1A and Fig. 1B illustrate a perspective view and circuit diagram of a memory array according to some embodiments. The Fig. 2, Fig. 3, Fig. 4A, Fig. 4B, Fig. 4C, Fig. 5A, Fig. 5B, Fig. 5C, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 13D, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 15D, Fig. 15E, Fig. 15F, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 16D, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 18D, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 22D and Fig. 23 illustrate varying views of the fabrication of a semiconductor device including a memory array, according to some embodiments. The Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28A, Fig. 28B, Fig. 28C, Fig. 29A, Fig. 29B, Fig. 29C, Fig. 29D, Fig. 30A, Fig. 30B, Fig. 30C, Fig. 30D, Fig. 31A, Fig. 31B, Fig. 31C, Fig. 31D and Fig. 32 illustrate varying views of the fabrication of a semiconductor device including a memory array, according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments for implementing different features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely example embodiments and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The article may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0008] Various embodiments provide a 3D memory array in which epitaxially grown source / drain regions coalesce in a horizontal direction and are isolated in a vertical direction, as well as methods for forming the same. The method may include forming channel regions, which may be nanostructures or the like. Portions of the channel regions may be etched, and the source / drain regions may be epitaxially grown from remaining portions of the channel regions. The channel regions may be formed such that source / drain regions adjacent in a horizontal direction coalesce, while source / drain regions adjacent in a vertical direction remain uncoordinated.The source / drain regions can then be etched to form the stair-step structure, allowing separate connections to be made for each group of merged source / drain regions. The source / drain regions can be used as source lines and bit lines in a 3D memory array. This method for forming the 3D memory array is compatible with existing nanostructure field-effect transistor (nanoFET) processes and allows for the formation of a 3D memory array in a reduced area, thereby increasing device density and reducing costs.

[0009] Embodiments are described below in a specific context, namely a chip comprising nano-FETs. However, various embodiments may be applied to chips comprising other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with the nano-FETs.

[0010] The Fig. 1A and Fig. 1B illustrate examples of a memory array 200 according to some embodiments. Fig. 1A illustrates an example of a portion of the memory array 200 in a three-dimensional view according to some embodiments, and Fig. 1B illustrates a circuit diagram of the memory array 200. The memory array 200 includes a plurality of memory cells 202 that may be arranged in a grid of rows and columns. The memory cells 202 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. In some embodiments, the memory array 200 may be arranged in the back-end-of-line (BEOL) of a semiconductor chip. For example, the memory array 200 may be arranged in the interconnect layers of the semiconductor chip, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0011] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a transistor 204 having a gate dielectric layer 100. The gate dielectric layer 100 may serve as a gate dielectric. In some embodiments, a gate electrode 102 of each transistor 204 may correspond to or be electrically coupled to a respective word line. A first epitaxial source / drain region 92 of each transistor 204 may correspond to or be electrically coupled to a respective bit line, and a second epitaxial source / drain region 92 of each transistor 204 may correspond to or be electrically coupled to a respective source line.The memory cells 202 in the same horizontal row of the memory array 200 may share a common epitaxial source / drain region 92 corresponding to a common source line and a common epitaxial source / drain region 92 corresponding to a common bit line, while the memory cells 202 in the same vertical column of the memory array 200 may share a common gate electrode 102 corresponding to a common word line.

[0012] The memory array 200 includes a plurality of vertically stacked epitaxial source / drain regions 92, with a first ILD 96 disposed between vertically adjacent epitaxial source / drain regions 92. The epitaxial source / drain regions 92 extend in a direction parallel to a major surface of an underlying substrate 50. The epitaxial source / drain regions 92 may have a stepped configuration such that lower epitaxial source / drain regions 92 are longer than endpoints of upper epitaxial source / drain regions 92 and extend laterally beyond endpoints of the upper epitaxial source / drain regions. For example, in Fig. 1A illustrates multiple stacked layers of the epitaxial source / drain regions 92, with the topmost epitaxial source / drain regions 92 being the shortest and the bottommost epitaxial source / drain regions 92 being the longest. The respective lengths of the epitaxial source / drain regions 92 may increase in a direction toward the underlying substrate. In this way, a portion of each of the epitaxial source / drain regions 92 may be accessed from above the memory array 200, and conductive contacts may be made to an exposed portion of each of the epitaxial source / drain regions 92.

[0013] The memory array 200 further includes a plurality of gate electrodes 102. The gate electrodes 102 may each extend in a direction perpendicular to the epitaxial source / drain region 92. Dielectric materials 106 are disposed between and insulate adjacent ones of the gate electrodes 102. Pairs of the epitaxial source / drain regions 92, together with the intersecting gate electrode 102, define boundaries for each memory cell 202, and the dielectric materials 106 are disposed between and insulate adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, alternating stacks of the epitaxial source / drain regions 92 may be electrically coupled to ground and voltage sources.

[0014] The memory array 200 may also include nanostructures 54. The nanostructures 54 may provide channel regions for the transistors 204 of the memory cells 202. For example, a nanostructure 54 intersecting the gate electrode 102 may allow a current to flow from a first epitaxial source / drain region 92 on a first side of the nanostructure 54 to a second epitaxial source / drain region 92 on a second side of the nanostructure 54, opposite the first side of the nanostructure 54, when a suitable voltage (e.g., above a respective threshold voltage (V th ) of a corresponding transistor 204) is applied via a gate electrode 102.

[0015] The gate dielectric layers 100 are disposed between the gate electrodes 102 and the nanostructures 54, and the gate dielectric layers 100 provide gate dielectrics for the transistors 204. In some embodiments, the gate dielectric layers 100 comprise ferroelectric (FE) materials, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, the memory array 200 may therefore be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the gate dielectric layers 100 may be multilayer structures, other ferroelectric materials, other types of memory layers (e.g., capable of storing one bit), or the like.The use of ferroelectric materials for the gate dielectric layers 100 can result in a shift in the threshold voltage (Vt) and provide memory reliability and improved performance.

[0016] In embodiments where the gate dielectric layers 100 comprise FE materials, the gate dielectric layers 100 may be polarized in one of two different directions. The polarization direction may be changed by applying a suitable voltage difference across the gate dielectric layers 100 and generating a suitable electric field. Depending on the polarization direction of a particular gate dielectric layer 100, a threshold voltage of a corresponding transistor 204 varies, and a digital value (e.g., 0 or 1) may be stored. For example, the corresponding transistor 204 may have a relatively low threshold voltage when a gate dielectric layer 100 has a first electrical polarization direction, and the corresponding transistor 204 may have a relatively high threshold voltage when the gate dielectric layer 100 has a second electrical polarization direction.The difference between the two threshold voltages can be referred to as the threshold voltage shift. A larger threshold voltage shift makes reading the digital value stored in the corresponding memory cell 202 easier (e.g., less error-prone).

[0017] To perform a write operation on a memory cell 202, a write voltage is applied to a gate dielectric layer 100 corresponding to the memory cell 202. The write voltage may be applied, for example, by applying appropriate voltages to a gate electrode 102 (e.g., via a corresponding word line) and to the corresponding epitaxial source / drain regions 92 (e.g., via corresponding bit lines and source lines). A polarization direction of the gate dielectric layer 100 may be changed by applying the write voltage to the gate dielectric layer 100. As a result, the corresponding threshold voltage of the corresponding transistor 204 may be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value may be stored in the memory cell 202.Since the gate electrodes 102 cross the epitaxial source / drain regions 92, individual memory cells 202 can be selected for the write operation.

[0018] To perform a read operation on the memory cell 202, a read voltage (e.g., a voltage between the low and high threshold voltages) is applied to the corresponding gate electrode 102 (e.g., through the corresponding word line). Depending on the polarization direction of the corresponding gate dielectric layer 100, the transistor 204 of the memory cell 202 may or may not be turned on. As a result, the corresponding epitaxial source / drain region 92 (e.g., the corresponding epitaxial source / drain region electrically coupled to the source line) may or may not be discharged through the corresponding epitaxial source / drain region 92 (e.g., the corresponding epitaxial source / drain region electrically coupled to ground), and the digital value stored in the memory cell 202 may be determined.Since the gate electrodes 102 cross the epitaxial source / drain regions 92, individual memory cells 202 can be selected for the read operation.

[0019] Fig. 1A further illustrates reference cross-sections of the memory array 200 used in subsequent figures. Cross-section AA' extends along longitudinal axes of the nanostructures 54 and in a direction parallel to the direction of current flow through the nanostructures 54 of the transistors 204. Cross-section BB' is perpendicular to cross-section AA' and extends through the gate electrodes 102 in a direction parallel to longitudinal axes of the epitaxial source / drain regions 92. Cross-section CC' is parallel to cross-section BB' and extends through the epitaxial source / drain regions 92. For clarity, subsequent figures refer to these reference cross-section planes.

[0020] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or aspects used in fin field-effect transistors (FinFETs).

[0021] The Fig. 2 to 32 are cross-sectional and top views of intermediate stages in manufacturing the memory array 200 according to some embodiments. Fig. 2, Fig. 3, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A, Fig. 30A and Fig. 31A illustrate the Fig. 1A illustrated reference cross section A-A'. The Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 15E, Fig. 15F, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B and Fig. 31B illustrate the reference cross section B-B' shown in Fig. 1A. The Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 29C, Fig. 30C and Fig. 31C illustrate the reference cross section C-C', as in Fig. 1A. The Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 10D, Fig. 11D, Fig. 12D, Fig. 13D, Fig. 14D, Fig. 15D, Fig. 16D, Fig. 17D, Fig. 18D, Fig. 19D, Fig. 20D, Fig. 21D, Fig. 22D, Fig. 23, Fig. 24C, Fig. 25C, Fig. 26C, Fig. 27C, Fig. 28D, Fig. 29D, Fig. 30D, Fig. 31D and Fig. 32 illustrate a top-down view.

[0022] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be an integrated circuit chip such as a logic chip, a memory chip, an ASIC chip, or the like. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) chip and may be referred to as a CMOS bottom array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulation layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer or the like.The insulation layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0023] Fig. 2 further illustrates circuits that may be formed over the substrate 50. The circuits include transistors on a top surface of the substrate 50. The transistors may include gate dielectric layers 302 over top surfaces of the substrate 50 and gate electrodes 304 over the gate dielectric layers 302. Source / drain regions 306 are disposed in the substrate 50 on opposite sides of the gate dielectric layers 302 and the gate electrodes 304. Gate spacers 308 are formed along the sidewalls of the gate dielectric layers 302 and separate the source / drain regions 306 from the gate electrodes 304 by suitable lateral distances. The transistors may be fin field-effect transistors (FinFETs), nanostructures (e.g.,Nanofoil, nanowire, gate-all-around or the like), FETs (nano-FETs), planar FETs, the like, or combinations thereof and can be formed by gate-first (first) process or gate-last (last) process.

[0024] A first ILD 310 surrounds and insulates the source / drain regions 306, the gate dielectric layers 302, and the gate electrodes 304, with a second ILD 312 disposed over the first ILD 310. Source / drain contacts 314 extend through the second ILD 312 and the first ILD 310 and are electrically coupled to the source / drain regions 306, and gate contacts 316 extend through the second ILD 312 and are electrically coupled to the gate electrodes 304. An interconnection structure 320 comprising one or more stacked dielectric layers 324 and conductive features 322 formed in the one or more dielectric layers 324 overlies the second ILD 312, the source / drain contacts 314, and the gate contacts 316. The interconnection structure 320 may be electrically connected to the gate contacts 316 and the source / drain contacts 314 to form functional circuits.In some embodiments, the functional circuits formed by interconnect structure 320 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, and the like, or combinations thereof. Although. Fig. 2 discusses transistors formed over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuitry. For simplicity and clarity, the transistors, ILDs, and interconnection structure 320 formed over the substrate 50 may be omitted from the following figures. The substrate 50, together with the transistors (e.g., the source / drain regions 306, the gate dielectric layers 302, and the gate electrodes 304), the gate spacers 308, the first ILD 310, the second ILD 312, and the interconnection structure 320, may be a CMOS bottom array (CUA), a logic chip, or the like.

[0025] In some embodiments, substrate 50 may include an n-type region and a p-type region (not separately illustrated). The n-type region may be used to form n-type devices, such as NMOS transistors such as n-nanoFETs, while the p-type region may be used to form p-type devices, such as PMOS transistors such as p-nanoFETs. The n-type region may be physically separated from the p-type region, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region and the p-type region. Any number of n-type regions and p-type regions may be provided.

[0026] In Fig. 3 is a multi-layer stack 64 over the structure of Fig. 2. For simplicity and clarity, the transistors, ILDs, and interconnect structure 320 may be omitted from the following figures. Although the multilayer stack 64 is illustrated as contacting the substrate 50, any number of interlayers may be disposed between the substrate 50 and the multilayer stack 64. For example, one or more interconnect layers comprising conductive features in isolation layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 64. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines for the active devices on the substrate 50 and / or the memory array 200 (see Fig. 1A and Fig. 1B). In some embodiments, the multilayer stack 64 may be formed directly over the substrate 50.

[0027] The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layers 51 are removed and the second semiconductor layers 53 are patterned to form channel regions of nano-FETs in both the p-type region and the n-type region. In some embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the n-type region, the p-type region, or both the n-type region and the p-type region.In embodiments where the channel regions are formed from the first semiconductor layers 51 or the second semiconductor layers 53 in both the n-type region and the p-type region, the channel regions in both the n-type region and the p-type region may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

[0028] For illustrative purposes, the multilayer stack 64 is illustrated as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In some embodiments, the first semiconductor layers 51 may be formed from first semiconductor materials, such as silicon germanium or the like, and the second semiconductor layers 53 may be formed from second semiconductor materials, such as silicon, silicon carbon, silicon germanium, germanium, or the like.In embodiments where the first semiconductor materials and the second semiconductor materials are formed of silicon germanium, the first semiconductor materials and the second semiconductor materials may have different concentrations of silicon and germanium from one another, such that the first semiconductor materials and the second semiconductor materials may be selectively etched with respect to one another. For illustrative purposes, the multilayer stack 64 is shown with one of the first semiconductor layers 51 as a bottommost semiconductor layer. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is one of the second semiconductor layers 53.

[0029] The first semiconductor materials and the second semiconductor materials may be materials that have a high etch selectivity to each other. In this way, the first semiconductor layers 51 may be removed from the first semiconductor materials without substantially removing the second semiconductor layers 53 from the second semiconductor materials, allowing the second semiconductor layers 53 to be patterned to form channel regions of the nano-FETs. Similarly, in embodiments where the second semiconductor layers 53 are removed from the second semiconductor material, the second semiconductor layers 53 may be removed from the second semiconductor material without substantially removing the first semiconductor layers 51 from the first semiconductor material, allowing the second semiconductor layers 51 to be patterned to form channel regions of the nano-FETs.

[0030] The first semiconductor layers 51 may be formed with thicknesses T1 in the range of about 100 nm to about 500 nm, while the second semiconductor layers 53 may be formed with thicknesses T2 in the range of about 10 nm to about 50 nm. In some embodiments, a ratio of the thicknesses T1 of the first semiconductor layers 51 to the thicknesses T2 of the second semiconductor layers 53 may be in a range of about 2 to about 10. Forming the first semiconductor layers 51 and the second semiconductor layers 53 with the prescribed thicknesses may help to horizontally connect adjacent epitaxial source / drain regions of the subsequently formed epitaxial source / drain regions (such as the epitaxial source / drain regions 92 described below with reference to the Fig. 10A to 10D) to coalesce, while vertically adjacent epitaxial source / drain regions of the subsequently formed epitaxial source / drain regions do not coalesce. This allows the horizontally coalesced epitaxial source / drain regions to be used as source lines and bit lines and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the coalesced epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0031] In Fig. 4A to 4C, nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 may be formed in the multilayer stack 64 by etching trenches in the multilayer stack 64. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etch (NBE), or the like, or combinations thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 may define first nanostructures 52A-C from the first semiconductor layers 51 (collectively referred to as first nanostructures 52) and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from the second semiconductor layers 53. The first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55.

[0032] The nanostructures 55 may be patterned by any suitable method. For example, the nanostructures 55 may be patterned using one or more photolithography processes, including double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography and self-aligned processes, enabling the fabrication of structures with smaller dimensions than is achievable, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructures 55.

[0033] In some embodiments, the nanostructures 55 may have substantially equal widths in the n-type region and the p-type region; however, the widths of the nanostructures 55 may be larger in the n-type region or the p-type region. Further, although each of the nanostructures 55 is illustrated as having a uniform width, in some embodiments, the nanostructures 55 may have tapered sidewalls such that a width of each of the nanostructures 55 continuously increases in the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and may have a trapezoidal shape.

[0034] The nanostructures 55 may have widths W1 in a range of about 10 nm to about 50 nm. The nanostructures 55 may be separated by distances D1 in a range of about 50 nm to about 100 nm. Forming the first nanostructures 55 with the prescribed width and spacing may help to horizontally separate adjacent epitaxial source / drain regions in subsequently formed epitaxial source / drain regions (such as the epitaxial source / drain regions 92 described with reference to FIG. Fig. 10A to 10D discussed below) while preventing vertically adjacent epitaxial source / drain regions from merging in the subsequently formed epitaxial source / drain regions. This allows the horizontally merging epitaxial source / drain regions to be used as source lines and bit lines and prevents short circuits between vertically merging epitaxial source / drain regions. Using the merging epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0035] The above with regard to Fig. The process described in Figures 3 through 4C is merely an example of how the nanostructures 55 may be formed. In some embodiments, the nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the nanostructures 55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth, thereby avoiding prior and / or subsequent implantations, but in situ and implantation doping may also be used together.

[0036] Additionally, for illustrative purposes only, the first semiconductor layers 51 (and the resulting first nanostructures 52) and the second semiconductor layers 53 (and the resulting second nanostructures 54) are illustrated and discussed herein as comprising the same materials in the p-type region and the n-type region. Accordingly, in some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be formed from different materials or in a different order in the p-type region and the n-type region.

[0037] Furthermore, Fig. 4A to 4C, suitable wells (not separately illustrated) may be formed in the nanostructures 55. In embodiments with different well types, different implantation steps for the n-type region and the p-type region may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the nanostructures 55 and the substrate 50 in the n-type region and the p-type region. The photoresist is patterned to expose the p-type region. The photoresist may be formed using a spin-on technique and patterned using acceptable photolithography techniques. After the photoresist is patterned, an n-type impurity implantation is performed in the p-type region, and the photoresist may serve as a mask that substantially prevents n-type impurities from being implanted into the n-type region.The n-impurities may be phosphorus, arsenic, antimony, or the like, implanted in the region at a concentration ranging from about 10 13 atoms / cm 3 up to about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process. This process can then be repeated to perform a p-type impurity implantation in the n-type region while a photoresist is formed and patterned to substantially prevent p-type impurities from being implanted into the p-type region. The p-type impurities can be boron, boron fluoride, indium, or the like, implanted in the region at a concentration ranging from about 10 13 atoms / cm 3 up to about 10 14 atoms / cm 3After the n-type and p-type implantations, an annealing step may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the grown epitaxial fin materials may be doped in situ during growth, thereby avoiding the implantations; however, in situ and implantation doping may also be used together.

[0038] In Fig. 5A to 5C, a dummy dielectric layer 70 is formed on the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to any acceptable technique. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited over the dummy gate layer 72.The dummy gate layer 72 may be made of a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials with high etch selectivity toward etching the isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region and the p-type region.It should be noted that the dummy dielectric layer 70 is shown covering only the nanostructures 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the substrate 50 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the substrate 50.

[0039] In Fig. 6A to 6C, the mask layer 74 (cf. Fig. 5A to 5C) using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the nanostructures 55. The pattern of the masks 78 can be used to physically separate the individual dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective nanostructures 55.

[0040] Furthermore, Fig. 6A to 6C, first spacers 80 are formed adjacent to the dummy gate dielectrics 71, the dummy gates 76, and the masks 78 over the nanostructures 55. The first spacers 80 may act as spacers for forming self-aligned source / drain regions. The first spacers 80 may be formed by depositing a first spacer layer (not separately illustrated) on top surfaces of the substrate 50; top surfaces and sidewalls of the nanostructures 55 and the masks 78; and sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The first spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation or deposition by CVD, ALD, or the like.

[0041] After the first spacer layer is formed, implantations for lightly doped source / drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the embodiments described above with reference to Fig. 4A to Fig. 4C, a mask, such as a photoresist, may be formed over the n-type region while exposing the p-type region, and impurities of a suitable type (e.g., p-type) may be implanted into the exposed nanostructures 55 in the p-type region. The mask may then be removed. Thereafter, a mask, such as a photoresist, may be formed over the p-type region while exposing the n-type region, and impurities of a suitable type (e.g., n-type) may be implanted into the exposed nanostructures 55 in the n-type region. The mask may then be removed. The n-type impurities may be any of the previously discussed n-type impurities, and the p-type impurities may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have an impurity concentration in a range of approximately 1 × 10 15 atoms / cm 3 up to about 1 × 10 19 atoms / cm 3An annealing step can be used to repair implantation damage and activate the implanted foreign materials.

[0042] The first spacer layer may then be etched to form the first spacers 80. As discussed in more detail below, the first spacers 80 serve to allow the subsequently formed source / drain regions to be self-aligned and to protect the sidewalls of the nanostructure 55 during subsequent processing. The first spacer layer may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. As described in Fig. 6A, the first spacers 80 may be arranged on sidewalls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 71. As shown in Fig. 6C, the first spacers 80 may further be arranged on sidewalls of the nanostructures 55.

[0043] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different sequences of steps may be used, additional spacers may be formed and removed, and / or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps.

[0044] In Fig. 7A to 7C, first recesses 86 are formed in the nanostructures 55. In some embodiments, the first recesses 86 may also extend at least partially into the substrate 50. Thereafter, epitaxial source / drain regions are formed in the first recesses 86. The first recesses 86 may extend through the first nanostructures 52 and the second nanostructures 54. As shown in Fig. 7A, the first recesses 86 may extend to upper surfaces of the substrate 50. The first recesses 86 may be formed by etching the nanostructures 55 using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 80 and the masks 78 mask portions of the nanostructures 55 during the etching processes used to form the first recesses 86. A single etching process or multiple etching processes may be used to etch each layer of the nanostructures 55. Timed etching processes may be used to stop the etching of the first recesses 86 after the first recesses 86 reach a desired depth.

[0045] In Fig. 8, portions of the sidewalls of the layers of the multilayer stack 64 formed from the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86 are etched to form sidewall recesses 88. Although the sidewalls of the first nanostructures 52 are adjacent to the sidewall recesses 88 in Fig. 8 as straight, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In embodiments where the first nanostructures 52 comprise, for example, silicon germanium and the second nanostructures 54 comprise, for example, silicon or silicon carbide, a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the first nanostructures 52.

[0046] In Fig. 9A and Fig. 9B, first inner spacers 90 are formed in the sidewall recess 88. The first inner spacers 90 may be formed by depositing an inner spacer layer (not separately illustrated) over the Fig. 8. The first internal spacers 90 act as isolation features between subsequently formed source / drain regions and a gate structure. As discussed in more detail below, the source / drain regions are formed in the first recesses 86, while the first nanostructures 52 are replaced with corresponding gate structures.

[0047] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as low dielectric constant (low-k) materials having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form the first inner spacers 90. Although the outer sidewalls of the first inner spacers 90 are illustrated as being flush with sidewalls of the second nanostructures 54, the outer sidewalls of the first inner spacers 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54.

[0048] Although the outer side walls of the first inner spacers 90 in Fig. 9A are illustrated as straight, the outer side walls of the first inner spacers 90 may be concave or convex. As an example, Fig. 9B illustrates an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the sidewalls of the second nanostructures 54. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, or the like. The first inner spacers 90 may be used to prevent damage to subsequently formed source / drain regions (e.g., the epitaxial source / drain regions 92 described below with reference to FIG. Fig. 10A to 10D) by subsequent etching processes, for example, etching processes used to form gate structures.

[0049] In Fig. 10A to 10D, epitaxial source / drain regions 92A-C are formed in the first recesses 86. The epitaxial source / drain regions 92A-C may be collectively referred to as epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 may exert a strain on the second nanostructures 54, thereby improving performance. As shown in Fig. 10A, the epitaxial source / drain regions 92 are formed in the first recesses 86 such that each dummy gate 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the first nanostructures 52 by appropriate lateral distances such that the epitaxial source / drain regions 92 are not short-circuited to gates of the resulting nano-FETs that are subsequently formed.

[0050] As in Fig. 10A, Fig. 10C and Fig. 10D, the epitaxial source / drain regions 92A-C (collectively referred to as epitaxial source / drain regions 92) may be epitaxially grown from the second nanostructures 54A-C, respectively. The epitaxial source / drain regions 92 may be grown such that horizontally adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 adjacent to each other in a direction parallel to a main surface of the substrate 50), exemplified by the epitaxial source / drain regions 92A.i and 92A.ii, the epitaxial source / drain regions 92B.i and 92B.ii, and the epitaxial source / drain regions 92C.i and 92C.ii, and corresponding dashed lines, grow together.On the other hand, vertically adjacent epitaxial source / drain regions 92, exemplified by epitaxial source / drain regions 92A-C (e.g., epitaxial source / drain regions 92 arranged directly on top of / below each other in a direction perpendicular to the main surface of substrate 50), remain separated from each other. Epitaxial source / drain regions 92 may extend from sidewalls of second nanostructures 54 and may extend along sidewalls of first inner spacers 90 and first spacers 80.

[0051] The epitaxial source / drain regions 92 may be epitaxially grown with thicknesses T3 ranging from about 30 nm to about 200 nm. The epitaxial source / drain regions 92 may have heights H1 ranging from about 50 nm to about 400 nm and may be separated from each other by gaps 93 with heights H2 ranging from about 50 nm to about 200 nm. The spacing and dimensions of the first nanostructures 52 and the second nanostructures 54 may be selected in conjunction with the thickness T3 to allow horizontally adjacent epitaxial source / drain regions 92 to grow together while vertically adjacent epitaxial source / drain regions 92 remain ungrown.In some embodiments, this may be achieved by forming the first semiconductor layers 51 to have thicknesses T1 that are greater than the distances D1 between adjacent nanostructures in the nanostructures 55, such that horizontally adjacent nanostructures in the second nanostructures 54 are spaced closer than vertically adjacent nanostructures in the second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated by distances D1 that are in the range of about 50 nm to about 200 nm, and vertically adjacent second nanostructures 54 may be separated by distances D2 that are greater than the distances D1 and are in the range of about 100 nm to about 500 nm.This allows the horizontally grown-together epitaxial source / drain regions 92 to be used as source lines and bit lines and prevents short circuiting between vertically adjacent epitaxial source / drain regions 92. Using the grown-together epitaxial source / drain regions 92 as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0052] Although the epitaxial source / drain regions 92 in the Fig. 10A illustrated cross-sectional view rectangular and in the Fig. 10C, the epitaxial source / drain regions 92 may have any suitable sectional representation shape, such as hexagonal, octagonal, or others. In some embodiments, the epitaxial source / drain regions 92 may have facets. In some embodiments, the epitaxial source / drain regions 92 may include materials in both the n-type region and the p-type region, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like.

[0053] The epitaxial source / drain regions 92 in the n-type region, e.g., the NMOS region, may be formed by masking the p-type region, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the n-type region. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 may comprise materials that exert tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0054] The epitaxial source / drain regions 92 in the p-type region, e.g., the PMOS region, may be formed by masking the n-type region, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the p-type region. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for p-type nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 may comprise materials that exert compressive stress on the second nanostructures 54, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like.

[0055] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing step. The source / drain regions may have an impurity concentration between about 1 × 10 19 atoms / cm 3 and about 1 × 10 21 atoms / cm 3 The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0056] In Fig. 11A to 11D, a first interlayer dielectric (ILD) 96 is respectively disposed over the Fig. 10A to 10D. The first ILD 96 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), ALD, or the like. The dielectric materials may include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon carbide, silicon oxynitride, or the like. Other insulating materials formed by any acceptable process may be used. As shown in Fig. 11A and Fig. 11C, the first ILD 96 may be formed around the epitaxial source / drain regions 92 and fill the gaps 93. The first ILD 96 may be formed along the top, side, and bottom surfaces of the epitaxial source / drain regions 92; side surfaces of the first inner spacers 90; side surfaces and top surfaces of the first spacers 80; and top surfaces of the masks 78.

[0057] In Fig. 12A to 12D, a planarization process, such as CMP, may be performed to cause the top surface of the first ILD 96 to be in the same plane as the top surfaces of the dummy gates 76 or the masks 78. The planarization process may also remove the masks 78 on the dummy gates 76 and portions of the first spacers 80 along sidewalls of the masks 78. After the planarization process, top surfaces of the dummy gates 76, the first spacers 80, and the first ILD 96 are in a plane, within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 may be retained, in which case the planarization process causes the top surfaces of the first ILD 96 to be aligned with the top surfaces of the masks 78 and the first spacers 80.

[0058] In Fig. 13A to 13D, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps such that second recesses 98 are formed. Portions of the dummy gate dielectrics 71 in the second recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 71 are removed by an anisotropic dry etching process. The etching process may, for example, comprise a dry etching process using a reactive gas(es) that etch the dummy gates 76 at a faster rate than the first ILD 96 or the first spacers 80. Each second recess 98 exposes and / or covers portions of the nanostructures 55 that act as channel regions in later completed nano-FETs. Portions of the nanostructures 55 acting as the channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 71 can be used as etch stop layers when the dummy gates 76 are etched. Then, the dummy gate dielectrics 71 can be removed after the removal of the dummy gates 76.

[0059] In Fig. 14A to 14D, the first nanostructures 52 are removed, with the second recesses 98 extending. The first nanostructures 52 may be removed by performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 58 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 comprise, for example, silicon germanium and the second nanostructures 54A-C comprise, for example, silicon or silicon carbide, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the first nanostructures 52. After removing the first nanostructures 52, the adjacent second nanostructures 54 may be etched in a vertical direction (e.g.,a direction perpendicular to a main surface of the substrate 50) have distances from each other that are equal to the thicknesses (e.g., the thicknesses T1) of the first nanostructures.

[0060] In Fig. 15A to 15D, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. The gate dielectric layers 100 are conformally deposited in the second recesses 98. The gate dielectric layers 100 may be formed on the top surfaces of the substrate 50 and the top, side, and bottom surfaces of the second nanostructures 54. The gate dielectric layers 100 may also be deposited on the top surfaces of the first ILD 96, the top and side surfaces of the first spacers 80, and the side surfaces of the first inner spacers 90. The gate dielectric layers 100 may be deposited by CVD, PVD, ALD, molecular beam deposition (MBD), PECVD, or the like.

[0061] In some embodiments, the gate dielectric layers 100 may comprise materials that can switch between two different polarization directions by applying a suitable voltage difference across the gate dielectric layers 100. The gate dielectric layers 100 may be high-k dielectric materials, such as a hafnium (Hf)-based dielectric material or the like. In some embodiments, the gate dielectric layers 100 may comprise ferroelectric (FE) materials, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In some embodiments, the gate dielectric layers 100 may comprise different ferroelectric materials or different types of dielectric materials.In some embodiments, the gate dielectric layers 100 may be multilayer dielectric structures (e.g., ONO structures) comprising a SiN. x -layer between two SiO x -layers. The structure of the gate dielectric layers 100 may be the same or different in the n-type region and the p-type region. The gate dielectric layers 100 may have thicknesses ranging from about 5 nm to about 20 nm. Forming the gate dielectric layers 100 with thicknesses less than 5 nm may degrade performance, while forming the gate dielectric layers 100 with thicknesses greater than 20 nm may take up too much space.

[0062] The gate electrodes 102 are deposited on the gate dielectric layers 100 and fill the remaining portions of the second recesses 98. The gate electrodes 102 may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Although, for example, in Fig. 15A to 15D illustrate single-layer gate electrodes 102. The gate electrodes 102 may include any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers forming the gate electrodes 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50.

[0063] The formation of the gate dielectric layers 100 in the n-type region and the p-type region may occur simultaneously, such that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 may occur simultaneously, such that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes, such that the gate dielectric layers 100 may be different materials and / or have a different number of layers, and / or the gate electrodes 102 in each region may be formed by different processes, such that the gate electrodes 102 may be different materials and / or have a different number of layers.When different processes are used, different masking steps can be used to mask or reveal appropriate areas.

[0064] After filling the second recesses 98, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the gate electrode material 102 that overlie the top surfaces of the first ILD 96 and the first spacers 80. The remaining portions of the gate electrode material 102 and the gate dielectric layers 100 thus form replacement gate structures of the resulting nano-FETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as "gate structures."

[0065] Although the second nanostructures 54 in Fig. 14B and Fig. 15B are illustrated as having rectangular cross-sectional shapes, after removal of the dummy gate dielectrics 71, the dummy gates 76, and the first nanostructures 52, the second nanostructures 54 may have a round, circular, square, or other cross-sectional shape. As examples, Fig. 15E shows an embodiment in which the second nanostructures 54 have circular shapes in a cross-sectional view, and Fig. 15F illustrates an embodiment in which the second nanostructures 54 have square shapes in a cross-sectional view. The shapes of the second nanostructures 54 can be controlled by controlling the thicknesses of the second semiconductor layers 53, the widths of the second nanostructures 54, and the parameters of the etching processes used to pattern the second nanostructures 54, to remove the dummy gate dielectrics 71, the dummy gates 76, and the first nanostructures 52. The gate dielectric layers 100 are conformally formed, thus having cross-sectional shapes similar to the cross-sectional shapes of the second nanostructures 54. For example, the gate dielectric layers 100 in the Fig. 15E have circular shapes in a cross-sectional view, and the gate dielectric layers 100 have Fig. 15E illustrated embodiment has square shapes in a cross-sectional view.

[0066] In Fig. 16A to 16D, trenches 104 are patterned through the gate electrodes 102, the gate dielectric layers 100, and the first spacers 80. The trenches 104 may also be patterned through the second nanostructures 54. The trenches 104 may be patterned by a combination of photolithography and etching. The etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or a combination thereof. The etching may be anisotropic. The trenches 104 may be disposed between opposing sidewalls of the first ILD 96 and the epitaxial source / drain regions 92, and the trenches 104 may physically connect adjacent stacks of the memory cells 202 in the memory array 200 (see FIG. Fig. 1A). The trenches 104 may also be patterned in portions of the structure through the gate electrodes 102, the gate dielectric layers 100, the first spacers 80 and the second nanostructures 54, in which a stair structure is subsequently formed (such as the stair structure 110 as described below with reference to the Fig. 21A to 21D).

[0067] In Fig. 17A to 17D, dielectric materials 106 are deposited in and fill the trenches 104. The dielectric materials 106 may include, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon carbide, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric materials 106 may fill the trenches 104 and may be deposited to extend along top surfaces of the first ILD 96, the first spacers 80, the gate dielectric layers 100, the gate electrodes 102, and the substrate 50, as well as along sidewalls of the gate dielectric layers 100, the gate electrodes 102, the first ILD 96, and the epitaxial source / drain regions 92. After deposition, a planarization process (e.g., CMP, etchback, or the like) may be performed to remove excess portions of the dielectric materials 106.In the resulting structure, the top surfaces of the first ILD 96, the first spacers 80, the gate dielectric layers 100, the gate electrodes 102, and the dielectric materials 106 may be substantially aligned with each other (e.g., within process variations).

[0068] The Fig. 18A to 21D illustrate patterning of the first ILD 96 and the epitaxial source / drain regions 92 to form a staircase structure 110 (In Fig. 21A to 21D). In Fig. 18A to 18D, a photoresist 108 is formed over the first ILD 96, the dielectric materials 106, the first spacers 80, the gate dielectric layers 100, and the gate electrodes 102. The photoresist 108 may be formed using a spin-on technique and patterned using acceptable photolithography techniques. Patterning the photoresist 108 may expose portions of the first ILD 96 and the dielectric materials 106 in a region 111 while masking remaining portions of the first ILD 96, the dielectric materials 106, the first spacers 80, the gate dielectric layers 100, and the gate electrodes 102.

[0069] Furthermore, Fig. 18A to 18D, the exposed portions of the first ILD 96 in the region 111 are etched using the photoresist 108 as a mask, and portions of the epitaxial source / drain regions 92C underlying the exposed portions of the first ILD 96 in the region 111 are etched using the first ILD 96 as a mask. The etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. The etching may be anisotropic. The etching may remove portions of the first ILD 96 and the epitaxial source / drain regions 92C in the region 111 and define an opening 109. Because the first ILD 96 and the epitaxial source / drain regions 92C have different material compositions, the etchants used to remove the exposed portions of these layers may be different.In some embodiments, the epitaxial source / drain regions 92C act as an etch stop layer when the first ILD 96 is etched, and the first ILD 96 acts as an etch stop layer when the epitaxial source / drain regions 92C are etched. As a result, portions of the first ILD 96 and the epitaxial source / drain regions 92C can be selectively removed without removing remaining portions of the first ILD 96 and the epitaxial source / drain regions 92, and the opening 109 can extend to a desired depth. Alternatively, a timed etch process can be used to stop the etching of the opening 109 after the opening 109 reaches a desired depth. In the resulting structure, a portion of the first ILD 96 is exposed above the epitaxial source / drain regions 92B in the region 111.

[0070] In Fig. 19A through 19D, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric materials 106. The photoresist 108 may be trimmed using acceptable photolithography techniques. As a result of the trimming, a width of the photoresist 108 decreases, and portions of the first ILD 96 and the dielectric materials 106 in the region 111 and a region 113 are exposed. For example, the top surfaces of the first ILD 96 and the dielectric materials 106 in the region 113 and in the region 111 may be exposed.

[0071] The exposed portions of the first ILD 96 and the epitaxial source / drain regions 92 may then be etched using the photoresist 108, along with the portions of the first ILD 96 and the epitaxial source / drain regions 92C, as masks. The etching may be any suitable etching process, such as wet or dry etching, RIE, NBE, the like, or a combination thereof. The etching process may be anisotropic. The etching may extend the opening 109 further into the first ILD 96 and the epitaxial source / drain regions 92. Because the first ILD 96 and the epitaxial source / drain regions 92 have different material compositions, the etchants used to remove the exposed portions of these layers may be different.In some embodiments, the epitaxial source / drain regions 92B-C act as etch stop layers while portions of the first ILD 96 are etched, and portions of the first ILD 96 act as etch stop layers while the epitaxial source / drain regions 92B-C are etched. As a result, the first ILD 96 and the epitaxial source / drain regions 92B-C may be selectively etched without etching the remaining portions of the first ILD 96 and the epitaxial source / drain regions 92B-C, and the opening 109 may extend to a desired depth. Alternatively, timed etch processes may be used to stop the etching of the opening 109 after the opening 109 reaches a desired depth. Furthermore, the unetched portions of the first ILD 96 and the epitaxial source / drain regions 92 act as masks for underlying layers during the etching process, and as a result, a previous structure (see . Fig. 18A to 18D) of the first ILD 96 and the epitaxial source / drain regions 92C are transferred to the underlying first ILD 96 and the underlying epitaxial source / drain regions 92B. In the resulting structure, a portion of the first ILD 96 is exposed over the epitaxial source / drain regions 92A in region 111, and a portion of the first ILD 96 is exposed over the epitaxial source / drain regions 92B in region 113.

[0072] In Fig. 20A through 20D, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric materials 106. The photoresist 108 may be trimmed using acceptable photolithography techniques. As a result of the trimming, a width of the photoresist 108 decreases, and portions of the first ILD 96 and the dielectric materials 106 in the region 111, the region 113, and a region 115 are exposed. For example, the top surfaces of the first ILD 96 and the dielectric materials 106 in the region 115, the region 113, and the region 111 may be exposed.

[0073] The exposed portions of the first ILD 96 and the epitaxial source / drain regions 92 may then be etched using the photoresist 108, portions of the first ILD 96, the epitaxial source / drain regions 92C, and the epitaxial source / drain regions 92B as masks. The etching may be any suitable etching process, such as wet or dry etching, RIE, NBE, the like, or a combination thereof. The etching process may be anisotropic. The etching may extend the opening 109 further into the first ILD 96 and the epitaxial source / drain regions 92. Because the first ILD 96 and the epitaxial source / drain regions 92 have different material compositions, the etchants used to remove the exposed portions of these layers may be different.In some embodiments, the epitaxial source / drain regions 92A-C act as etch stop layers while portions of the first ILD 96 are etched, and portions of the first ILD 96 act as etch stop layers while the epitaxial source / drain regions 92A-C are etched. As a result, the first ILD 96 and the epitaxial source / drain regions 92A-C may be selectively etched without etching remaining portions of the first ILD 96, and the opening 109 may extend to a desired depth. Alternatively, timed etch processes may be used to stop the etching of the opening 109 after the opening 109 reaches a desired depth. Furthermore, the unetched portions of the first ILD 96 and the epitaxial source / drain regions 92 act as masks for the underlying layers during the etching process, and as a result, a previous structure (cf. . Fig. 19A to 19D) of the first ILD 96 and the epitaxial source / drain regions 92B-C are transferred to the underlying first ILD 96 and the underlying epitaxial source / drain regions 92A-B. In the resulting structure, a portion of the first ILD 96 is exposed above the substrate 50 in region 111, a portion of the first ILD 96 is exposed above the epitaxial source / drain regions 92A in region 113, and a portion of the first ILD 96 is exposed above the epitaxial source / drain regions 92B in region 115.

[0074] In Fig. 21A to 21D, the photoresist 108 is removed by an acceptable ashing or wet exfoliation process. Thus, a stair structure 110 is formed. The stair structure 110 comprises a stack of alternating layers of the first ILD 96 and the epitaxial source / drain regions 92. As shown in Fig. 21C, the lengths of the epitaxial source / drain regions 92 increase toward the substrate 50, such that the epitaxial source / drain regions 92A are longer and extend laterally beyond the epitaxial source / drain regions 92B, and the epitaxial source / drain regions 92B are longer and extend laterally beyond the epitaxial source / drain regions 92C. As a result, in subsequent processing steps, conductive contacts may be formed from above the stair structure 110 to each of the epitaxial source / drain regions 92.

[0075] In Fig. 22A to 22D, an intermetal dielectric (IMD) 112 is deposited over the structure of the Fig. 21A to 21D. The IMD 112 may be formed along the top surfaces of the first ILD 96, the first spacers 80, the gate dielectric layers 100, the gate electrodes 102, the dielectric materials 106, and the epitaxial source / drain regions 92A-C, and along side surfaces of the first ILD 96 and the epitaxial source / drain regions 92A-C. The IMD 112 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the IMD 112 may comprise an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), a combination thereof, or the like.Other dielectric materials formed by any acceptable process may be used.

[0076] Furthermore, Fig. 22A to 22D, contacts 114 and contacts 116 are formed, each extending to and electrically coupled to the epitaxial source / drain regions 92 and the gate electrodes 102. The stair-step shape of the epitaxial source / drain regions 92 provides areas on each epitaxial source / drain region 92 for the contacts 114 to land. Forming the contacts 114 and 116 may include patterning openings in the IMD 112 to expose portions of the epitaxial source / drain regions 92 and the gate electrodes 102, for example, using a combination of photolithography and etching. In some embodiments, the openings in the IMD 112 may be formed by a process having high etch selectivity to materials of the IMD 112. Thus, the openings can be formed in the IMD 112 without substantially removing materials from the epitaxial source / drain regions 92 and the gate electrodes 102.

[0077] In some embodiments, openings exposing each of the epitaxial source / drain regions 92A-C may be formed simultaneously. Due to variations in the thickness of the IMD 112 covering each of the epitaxial source / drain regions 92A-C, the epitaxial source / drain regions 92C may be exposed to etching for a longer duration than the epitaxial source / drain regions 92B, which are exposed for a longer duration than the epitaxial source / drain regions 92A. Exposure to the etch may cause some material loss, pitting, or other damage in the epitaxial source / drain regions 92, such that the epitaxial source / drain regions 92C are damaged to a maximum degree, the epitaxial source / drain regions 92B are damaged to a reduced degree, and the epitaxial source / drain regions 92A are damaged to a minimum degree.The openings exposing the gate electrodes 102 may be formed simultaneously with the openings exposing the epitaxial source / drain regions 92, or may be formed by separate etching processes similar or identical to those used to form the openings exposing the epitaxial source / drain regions 92.

[0078] A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, or the like. The contacts 114 and the contacts 116 may be formed simultaneously or separately. A planarization process, such as CMP, may be performed to remove excess material from a surface of the IMD 112. The remaining liner and the conductive material form the contacts 114 and the contacts 116 in the openings. As shown in Fig. 22C, the contacts 114 may extend to each of the epitaxial source / drain regions 92A-C. As illustrated in Fig. 22B, the contacts 116 extend to each of the gate electrodes 102.

[0079] In Fig. 23, conductive lines 118 and conductive lines 120 are formed on and electrically coupled to contacts 114 and contacts 116, respectively. Conductive lines 118 and conductive lines 120 may be formed over IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed in additional IMD layers formed over IMD 112 using processes and materials that are the same or similar to those used for IMD 112. In some embodiments, the conductive lines 118 and the conductive lines 120 may be formed using a damascene process in which an additional IMD layer is patterned over the IMD 112 using a combination of photolithography and etching techniques to form trenches that correspond to the desired structure of the conductive lines 118 and the conductive lines 120.An optional diffusion barrier layer and / or an optional adhesion layer may be deposited in the trenches, and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives. Suitable materials for the conductive material include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, or the like. In one embodiment, the conductive lines 118 and 120 may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches with electroplating.A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from surfaces of the additional IMD layer and to planarize surfaces of the conductive lines 118 and the conductive lines 120 and the additional IMD layer for subsequent processing.

[0080] As in Fig. As illustrated in Figure 23, the gate electrodes 102 adjacent in a direction perpendicular to longitudinal directions of the epitaxial source / drain regions 92 may be electrically coupled to various conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive lines 118. In some embodiments, the gate electrodes 102 may be word lines connected to word signals through the contacts 116 and the conductive lines 120. The epitaxial source / drain regions 92 on a first side of the stair structure 110 may be source lines electrically coupled to a voltage source through the contacts 114 and the conductive lines 118, and the epitaxial source / drain regions 92 on a first side of the stair structure 110 may be bit lines electrically coupled to ground through the contacts 114 and the conductive lines 118.

[0081] Forming the epitaxial source / drain regions 92 that grow together horizontally and are vertically isolated from each other enables separate connections for each of the epitaxial source / drain regions 92A-C in the stair structure 110. This increases the number of devices that can be provided in a given area (e.g., increases the device density) and reduces costs.

[0082] The Fig. 24A to 32 illustrate an embodiment in which the second nanostructures 54 of adjacent gate structures are offset from each other. Fig. 24A to 24C illustrate nanostructures 55 after similar or identical steps as those in Fig. 3 to 4C and explained above. The nanostructures 55 may be formed with a different width and a different spacing than those described above in connection with the embodiment of the Fig. 3 to 4C. The nanostructures 55 may, for example, have widths W2 in a range of about 10 nm to about 50 nm. The nanostructures 55 may be separated by distances D3 ranging from about 20 nm to about 300 nm. Forming the first nanostructures 55 with the prescribed width and spacing may help to horizontally separate adjacent epitaxial source / drain regions in subsequently formed epitaxial source / drain regions (such as the epitaxial source / drain regions 92 described with reference to FIGS. Fig. 29A to 29D discussed below) while not allowing vertically adjacent epitaxial source / drain regions to coalesce in the subsequently formed epitaxial source / drain regions. This allows the horizontally coalesced epitaxial source / drain regions to be used as source lines and bit lines and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the coalesced epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0083] The nanostructures 55 may include first nanostructures 52A-C (collectively referred to as first nanostructures 52) and second nanostructures 54A-C (collectively referred to as second nanostructures 54) similar or identical to those described above. The first nanostructures 52 may be formed with heights H3 ranging from about 100 nm to about 500 nm, while the second nanostructures 54 may be formed with heights H4 ranging from about 10 nm to about 50 nm. In some embodiments, a ratio of the heights H3 of the first nanostructures 52 to the heights H4 of the second nanostructures 54 may be between about 2 and about 10.Forming the first nanostructures 52 and the second nanostructures 54 with the prescribed thicknesses may help to horizontally define adjacent epitaxial source / drain regions of the subsequently formed epitaxial source / drain regions (such as the epitaxial source / drain regions 92 described below with reference to FIG. Fig. 29A to 29D) while vertically adjacent epitaxial source / drain regions of the subsequently formed epitaxial source / drain regions do not coalesce. This allows the horizontally coalesced epitaxial source / drain regions to be used as source lines and bit lines and prevents short circuits between vertically adjacent epitaxial source / drain regions. Using the coalesced epitaxial source / drain regions as source lines and bit lines reduces device size, increases device density, and reduces cost.

[0084] In Fig. 25A to 25C, the nanostructures 55 are patterned to form gaps 130 in each of the nanostructures 55. The gaps 130 may extend through the second nanostructures 54A-C and the first nanostructures 52A-C and expose surfaces of the substrate 50. The nanostructures 55 may be patterned using the same or similar processes as described above in connection with the Fig. 4A to 4C. In some embodiments, the nanostructures 55 may be formed and patterned in a single processing step to form the gaps 130. As in Fig. 25C, the gaps 130 formed in adjacent nanostructures 55 may be offset, and the remaining portions of the adjacent nanostructures 55 may also be offset. Portions of the remaining portions of adjacent nanostructures 55 may overlap each other. Forming the nanostructures 55 in an offset configuration may simplify connections of the second nanostructures 54 in subsequent steps, thereby reducing costs and mitigating device defects. After patterning the nanostructures 55, portions of the nanostructures 55 that subsequently form the channel regions of the transistors 204 may be separated from each other in a direction perpendicular to long axes of the nanostructures 55 by a distance D4 that ranges from about 50 nm to about 200 nm.

[0085] In Fig. 26A to 26C, a dummy dielectric layer 70 is formed on the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to any acceptable technique. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited over the dummy gate layer 72.The dummy gate layer 72 may be made of a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials with high etch selectivity toward etching the isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region and the p-type region.It should be noted that the dummy dielectric layer 70 is shown covering only the nanostructures 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the substrate 50 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the substrate 50.

[0086] In Fig. 27A to 27C, the mask layer 74 (cf. Fig. 26A to 26C) may be patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 may then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the nanostructures 55. The pattern of the masks 78 may be used to physically separate the individual dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective nanostructures 55.

[0087] Furthermore, Fig. 27A to 27C, first spacers 80 are formed adjacent to the dummy gate dielectrics 71, the dummy gates 76, and the masks 78 over the nanostructures 55. The first spacers 80 may act as spacers for forming self-aligned source / drain regions. The first spacers 80 may be formed by depositing a first spacer layer (not separately illustrated) on top surfaces of the substrate 50; top surfaces and sidewalls of the nanostructures 55 and the masks 78; and sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The first spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation or deposition by CVD, ALD, or the like.

[0088] The first spacer layer may then be etched to form the first spacers 80. As discussed in more detail below, the first spacers 80 serve to allow the subsequently formed source / drain regions to be self-aligned and to protect the sidewalls of the nanostructure 55 during subsequent processing. The first spacer layer may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. As described in Fig. 27A, the first spacers 80 may be arranged on sidewalls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 71. As shown in Fig. 27C, the first spacers 80 may further be arranged on sidewalls of the nanostructures 55.

[0089] As in Fig. 27A, the first spacers 80 may be formed to extend along the end surfaces of the first nanostructures 52 and the second nanostructures 54. In some embodiments, the dummy gates 76 may be formed to extend along the end surfaces of the first nanostructures 52 and the second nanostructures 54, and the first spacers 80 may be formed over the second nanostructures 54C.

[0090] Although the nanostructures 55 are described as being patterned before forming and patterning the dummy gates 76, the dummy gate dielectrics 71, and the masks 78 to form the columns 130, in some embodiments, the nanostructures 55 may be patterned after forming and patterning the dummy gates 76, the dummy gate dielectrics 71, and the masks 78 to form the columns 130. Furthermore, the nanostructures 55 may be patterned to form the columns 130 before or after forming the first spacers 80.

[0091] In Fig. 28A to 28C, first recesses 86 are formed in the nanostructures 55. In some embodiments, the first recesses 86 may also extend at least partially into the substrate 50. Thereafter, epitaxial source / drain regions are formed in the first recesses 86. The first recesses 86 may extend through the first nanostructures 52 and the second nanostructures 54. As shown in Fig. 28A, the first recesses 86 may extend to upper surfaces of the substrate 50. The first recesses 86 may be formed by etching the nanostructures 55 using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 80 and the masks 78 mask portions of the nanostructures 55 during the etching processes used to form the first recesses 86. A single etching process or multiple etching processes may be used to etch each layer of the nanostructures 55. Timed etching processes may be used to stop the etching of the first recesses 86 after the first recesses 86 reach a desired depth.

[0092] Furthermore, Fig. 28A to 28C, the sidewall portions of the first nanostructures 52 exposed by the first recesses 86 are replaced by the first inner spacers 90. The first nanostructures 52 may be etched using the same or similar processes as those described above with respect to Fig. 8. Then, the same or similar processes and materials as those discussed above with reference to the Fig. 9A or Fig. 9B, to form the first inner spacers 90.

[0093] In Fig. 29A to 29D, epitaxial source / drain regions 92A-C are formed in the first recesses 86. The epitaxial source / drain regions 92A-C may be collectively referred to as epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 may exert a strain on the second nanostructures 54, thereby improving performance. As shown in Fig. 29A, the epitaxial source / drain regions 92 are formed in the first recesses 86 such that each dummy gate 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the first nanostructures 52 by appropriate lateral distances such that the epitaxial source / drain regions 92 are not shorted to gates of the resulting nano-FETs that are subsequently formed.

[0094] As in Fig. 29A, Fig. 29C and Fig. 29D, the epitaxial source / drain regions 92A-C may be epitaxially grown from the second nanostructures 54A-C, respectively. The epitaxial source / drain regions 92 may be grown such that horizontally adjacent epitaxial source / drain regions 92 (e.g., epitaxial source / drain regions 92 adjacent to each other in a direction parallel to a main surface of the substrate 50), exemplified by the epitaxial source / drain regions 92A.i and 92A.ii, the epitaxial source / drain regions 92B.i and 92B.ii, and the epitaxial source / drain regions 92C.i and 92C.ii, and corresponding dashed lines, grow together.On the other hand, vertically adjacent epitaxial source / drain regions 92, exemplified by epitaxial source / drain regions 92A-C (e.g., epitaxial source / drain regions 92 arranged directly on top of / below each other in a direction perpendicular to the main surface of substrate 50), remain separated from each other. Epitaxial source / drain regions 92 may extend from sidewalls of second nanostructures 54 and may extend along sidewalls of first inner spacers 90 and first spacers 80.

[0095] The epitaxial source / drain regions 92 may be epitaxially grown with thicknesses T4 ranging from about 30 nm to about 200 nm. The epitaxial source / drain regions 92 may have heights H5 ranging from about 50 nm to about 400 nm and may be separated from each other by gaps 93 with heights H6 ranging from about 50 nm to about 200 nm. The spacing and dimensions of the first nanostructures 52 and the second nanostructures 54 may be selected in conjunction with the thickness T4 to allow horizontally adjacent epitaxial source / drain regions 92 to grow together while vertically adjacent epitaxial source / drain regions 92 remain ungrown.In some embodiments, this may be achieved by forming the first nanostructures 52 with heights H3 that are greater than the distances D4 between adjacent nanostructures 55, such that horizontally adjacent nanostructures in the second nanostructures 54 are spaced closer than vertically adjacent nanostructures in the second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated by distances D4 that range from about 50 nm to about 200 nm, and vertically adjacent second nanostructures 54 may be separated by distances D5 that are greater than the distances D4 and range from about 100 nm to about 500 nm. This allows the horizontally grown epitaxial source / drain regions 92 to be used as source lines and bit lines and prevents shorting between vertically adjacent epitaxial source / drain regions 92.The use of the merged epitaxial source / drain regions 92 as source lines and bit lines reduces device size, increases device density, and reduces costs.

[0096] Although the epitaxial source / drain regions 92 in the Fig. 29A illustrated cross-sectional view rectangular and in the Fig. 29C, the epitaxial source / drain regions 92 may have any suitable sectional representation shape, such as hexagonal, octagonal, or others. In some embodiments, the epitaxial source / drain regions 92 may have facets. In some embodiments, the epitaxial source / drain regions 92 may include materials in both the n-type region and the p-type region, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like.

[0097] The epitaxial source / drain regions 92 in the n-type region, e.g., the NMOS region, may be formed by masking the p-type region, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the n-type region. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 may comprise materials that exert tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0098] The epitaxial source / drain regions 92 in the p-type region, e.g., the PMOS region, may be formed by masking the n-type region, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the p-type region. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for p-type nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 may comprise materials that exert compressive stress on the second nanostructures 54, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like.

[0099] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing step. The source / drain regions may have an impurity concentration between about 1 × 10 19 atoms / cm 3 and about 1 × 10 21 atoms / cm 3 The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0100] Fig. 30A to 30D illustrate the structures after the Fig. 11A to 21D, the steps illustrated in FIGS. 11A to 21D were performed as discussed above. Specifically, a first ILD 96 is formed around the epitaxial source / drain regions 92, the dummy gate structures are replaced with gate structures including the gate electrodes 102 and the gate dielectric layers 100, portions of the gate structure are replaced with dielectric materials 106, and a stair structure 110 is formed in the epitaxial source / drain regions 92 and the first ILD 96.

[0101] In Fig. 31A to 31D, an intermetal dielectric (IMD) 112 is deposited over the structure of the Fig. 30A to 30D. The IMD 112 may be formed along the top surfaces of the first ILD 96, the first spacers 80, the gate dielectric layers 100, the gate electrodes 102, the dielectric materials 106, and the epitaxial source / drain regions 92A-C, and along side surfaces of the first ILD 96 and the epitaxial source / drain regions 92A-C. The IMD 112 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the IMD 112 may comprise an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), a combination thereof, or the like.Other dielectric materials formed by any acceptable process may be used.

[0102] Furthermore, Fig. 31A to 31D, contacts 114 and contacts 116 are formed, each extending to and electrically coupled to the epitaxial source / drain regions 92 and the gate electrodes 102. The stair-step shape of the epitaxial source / drain regions 92 provides areas on each epitaxial source / drain region 92 for the contacts 114 to land. Forming the contacts 114 and 116 may include patterning openings in the IMD 112 to expose portions of the epitaxial source / drain regions 92 and the gate electrodes 102, for example, using a combination of photolithography and etching. In some embodiments, the openings in the IMD 112 may be formed by a process having high etch selectivity to materials of the IMD 112. Thus, the openings can be formed in the IMD 112 without substantially removing materials from the epitaxial source / drain regions 92 and the gate electrodes 102.

[0103] In some embodiments, openings exposing each of the epitaxial source / drain regions 92A-C may be formed simultaneously. Due to variations in the thickness of the IMD 112 covering each of the epitaxial source / drain regions 92A-C, the epitaxial source / drain regions 92C may be exposed to etching for a longer duration than the epitaxial source / drain regions 92B, which are exposed for a longer duration than the epitaxial source / drain regions 92A. Exposure to the etch may cause some material loss, pitting, or other damage in the epitaxial source / drain regions 92, such that the epitaxial source / drain regions 92C are damaged to a maximum degree, the epitaxial source / drain regions 92B are damaged to a reduced degree, and the epitaxial source / drain regions 92A are damaged to a minimum degree.The openings exposing the gate electrodes 102 may be formed simultaneously with the openings exposing the epitaxial source / drain regions 92, or may be formed by separate etching processes similar or identical to those used to form the openings exposing the epitaxial source / drain regions 92.

[0104] A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, or the like. The contacts 114 and the contacts 116 may be formed simultaneously or separately. A planarization process, such as CMP, may be performed to remove excess material from a surface of the IMD 112. The remaining liner and the conductive material form the contacts 114 and the contacts 116 in the openings. As shown in Fig. 22C, the contacts 114 may extend to each of the epitaxial source / drain regions 92A-C. As illustrated in Fig. 31B, the contacts 116 extend to each of the gate electrodes 102.

[0105] In Fig. 32, the conductive lines 118 and the conductive lines 120 are formed on and electrically coupled to the contacts 114 and the contacts 116, respectively. The conductive lines 118 and the conductive lines 120 may be formed over the IMD 112. In some embodiments, the conductive lines 118 and the conductive lines 120 may be formed in additional IMD layers formed over the IMD 112 using processes and materials that are the same or similar to those used for the IMD 112. In some embodiments, the conductive lines 118 and the conductive lines 120 may be formed using a damascene process in which an additional IMD layer is patterned over the IMD 112 using a combination of photolithography and etching techniques to form trenches that correspond to the desired structure of the conductive lines 118 and the conductive lines 120.An optional diffusion barrier layer and / or an optional adhesion layer may be deposited in the trenches, and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives. Suitable materials for the conductive material include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, or the like. In one embodiment, the conductive lines 118 and 120 may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches with electroplating.A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from surfaces of the additional IMD layer and to planarize surfaces of the conductive lines 118 and the conductive lines 120 and the additional IMD layer for subsequent processing.

[0106] As in Fig. 32 illustrates, the (in Fig. 24A to 24C) formed from each of the stacks of first nanostructures 52 may be electrically coupled to the same conductive lines 120. The gate electrodes 102 formed from the adjacent first nanostructures 52 are connected to adjacent ones of the conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive lines 118. In some embodiments, the gate electrodes 102 may be word lines connected to word signals through the contacts 116 and the conductive lines 120.The epitaxial source / drain regions 92 on a first side of the stair structure 110 may be source lines electrically coupled to a voltage source through the contacts 114 and the conductive lines 118, and the epitaxial source / drain regions 92 on a first side of the stair structure 110 may be bit lines electrically coupled to ground through the contacts 114 and the conductive lines 118. Forming the nanostructures 55 in the staggered configuration of the . Fig. 25A to 25C allows single conductive lines 120 to be electrically coupled to the gate electrodes 102 formed from each stack of the first nanostructures 52, simplifying the interconnect arrangement, reducing costs, and reducing device defects.

[0107] Embodiments may achieve various advantages. For example, forming the epitaxial source / drain regions 92 that grow together horizontally and are vertically isolated from each other enables separate interconnection for each of the epitaxial source / drain regions 92A-C in the stair structure 110. This increases the number of devices that can be provided in a given area (e.g., increases device density) and reduces cost.

[0108] According to one embodiment, a memory array comprises a first channel region above a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly above the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.In one embodiment, the memory array further comprises a second channel region directly above the first channel region in the direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region, and the gate dielectric further surrounding the second channel region. In one embodiment, a ratio of a distance between the first channel region and the second channel region to heights of the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is 2 to 10.In one embodiment, the memory array further comprises a second channel region directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and a third channel region adjacent to the first channel region in a direction parallel to the main surface of the semiconductor substrate, the third channel region being electrically coupled to the first epitaxial region. In one embodiment, a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is greater than a distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate.In one embodiment, a distance between the second epitaxial region and the semiconductor substrate is greater than a distance between the first epitaxial region and the semiconductor substrate, and the length of the second epitaxial region is less than a length of the first epitaxial region. In one embodiment, the gate dielectric comprises a ferroelectric material.

[0109] According to another embodiment, a semiconductor device comprises a first channel region above a semiconductor substrate; a second channel region directly above the first channel region in the vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region adjacent to the first channel region in the horizontal direction; a first source / drain region electrically coupled to the first channel region and the third channel region; and a second source / drain region electrically coupled to the second channel region and insulated from the first source / drain region, wherein a first dielectric material extends between the first source / drain region and the second source / drain region.In one embodiment, a second gate structure surrounds the third channel region, wherein the second gate structure is separated from the first gate structure by a second dielectric material. In one embodiment, a length of the second source / drain region is less than a length of the first source / drain region. In one embodiment, the first source / drain region and the second source / drain region are bit lines or source lines, while the first gate structure is a word line. In one embodiment, the memory array further comprises a third source / drain region electrically coupled to the first channel region and the third channel region, wherein the third source / drain region is arranged on a side of the first channel region and the third channel region opposite the first source / drain region, wherein the first source / drain region is a source line and the third source / drain region is a bit line.In one embodiment, the memory array further comprises a fourth channel region electrically coupled to the first source / drain region, wherein a longitudinal axis of the fourth channel region is aligned with a longitudinal axis of the first channel region; a second gate structure surrounding the fourth channel region; a first conductive line electrically coupled to the first gate structure, wherein the first conductive line is arranged on a first side of the first channel region and the fourth channel region in the horizontal direction; and a second conductive line electrically coupled to the second gate structure, wherein the second conductive line is arranged on a second side of the first channel region and the fourth channel region opposite the first side in a horizontal direction.In one embodiment, the memory array further comprises a fourth channel region electrically coupled to the first source / drain region opposite the first channel region, wherein a longitudinal axis of the fourth channel region is aligned with the first gate structure; and a second gate structure surrounding the fourth channel region, wherein a longitudinal axis of the first channel region is aligned with the second gate structure.

[0110] According to yet another embodiment, a method comprises forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising a first nanostructure, a second nanostructure adjacent to the first nanostructure in a direction parallel to a major surface of the semiconductor substrate, and a third nanostructure directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure over the multilayer stack; etching the multilayer stack,to form a first recess adjacent to the gate structure; and epitaxially growing source / drain regions from the second plurality of nanostructures, wherein a first source / drain region epitaxially grown from the first nanostructure and a second source / drain region epitaxially grown from the second nanostructure grow together, and wherein a third source / drain region epitaxially grown from the third nanostructure is isolated from the first source / drain region after the epitaxial growth of the source / drain regions. In one embodiment, longitudinal axes of the first plurality of nanostructures and longitudinal axes of the second plurality of nanostructures extend parallel to a first direction, and after patterning the multilayer stack, the first plurality of nanostructures and the second plurality of nanostructures form a first stack and a second stack,which is separated from the first stack in the first direction. In one embodiment, after patterning the multilayer stack, the first plurality and the second plurality of nanostructures further form a third stack that is separated from the first stack and the second stack in a second direction perpendicular to the first direction, wherein a first end face of the third stack lies between opposite end faces of the first stack in the first direction and a second end face of the third stack, opposite the first end face, lies between opposite end faces of the second stack in the first direction. In one embodiment, the method further comprises removing the first plurality of nanostructures and the gate structure to form a second recess; and forming a replacement gate structure in the second recess. In one embodiment, the method further comprises patterning the replacement gate structure,to form a third recess separating a first replacement gate structure from a second replacement gate structure; and forming a dielectric material in the third recess. In one embodiment, the method further comprises forming a dielectric material between the first source / drain region and the third source / drain region, the dielectric material isolating the first source / drain region from the third source / drain region.

Claims

[1] A semiconductor device comprising: a first channel region (54) over a semiconductor substrate (50); a second channel region (54) located directly above the first channel region (54) in a vertical direction; a first gate structure (100, 102) enclosing the first channel region (54) and the second channel region (54); a third channel region (54) adjacent to the first channel region (54) in a horizontal direction; a first source / drain region (92A) electrically coupled to the first channel region (54) and the third channel region (54); and a second source / drain region (92B) electrically coupled to the second channel region (54) and insulated from the first source / drain region (92A), wherein a first dielectric material (96) extends between the first source / drain region (92A) and the second source / drain region (92B), wherein a second gate structure (100, 102) surrounds the third channel region (54), and the second gate structure (100, 102) is separated from the first gate structure (100, 102) by a second dielectric material (106). [2] The semiconductor device according to claim 1, wherein a length of the second source / drain region (92B) is less than a length of the first source / drain region (92A). [3] A semiconductor device according to any one of the preceding claims 1 or 2, wherein the first source / drain region (92A) and the second source / drain region (92B) are bit lines or source lines, and wherein the first gate structure (100, 102) is a word line. [4] The semiconductor device according to any one of the preceding claims 1 to 3, further comprising a third source / drain region electrically coupled to the first channel region (54) and the third channel region (54), wherein the third source / drain region is arranged on a side of the first channel region (54) and the third channel region (54) opposite to the first source / drain region (92A), wherein the first source / drain region (92A) is a source line and wherein the third source / drain region is a bit line. [5] A semiconductor device according to any one of the preceding claims 1 to 4, further comprising: a fourth channel region (54) electrically coupled to the first source / drain region (92A), wherein a longitudinal axis of the fourth channel region (54) is aligned with a longitudinal axis of the first channel region (54); a third gate structure (100, 102) surrounding the fourth channel region (54); a first conductive line electrically coupled to the first gate structure (100, 102), the first conductive line being arranged on a first side of the first channel region (54) and the fourth channel region (54) in the horizontal direction; and a second conductive line electrically coupled to the third gate structure (100, 102), the second conductive line being disposed on a second side of the first channel region (54) and the fourth channel region (54) opposite the first side in the horizontal direction. [6] Method comprising: Forming a multilayer stack (64) over a semiconductor substrate (50), the multilayer stack (64) comprising alternating layers of a first semiconductor material (51) and a second semiconductor material (53); Structuring the multilayer stack (64) to form a first plurality of nanostructures (52) comprising the first semiconductor material (51) and a second plurality of nanostructures (54) comprising the second semiconductor material (53), wherein the second plurality of nanostructures (54) comprises a first nanostructure (54A), a second nanostructure (54A) adjacent to the first nanostructure (54A) in a direction parallel to a major surface of the semiconductor substrate (50), and a third nanostructure (54B) directly above the first nanostructure (54A) in a direction perpendicular to the major surface of the semiconductor substrate (50); Forming a gate structure (71, 76) over the multilayer stack (64); Etching the multilayer stack (64) to form a first recess (86) adjacent to the gate structure (71, 76); and epitaxial growth of source / drain regions (92) from the second plurality of nanostructures (54), wherein a first source / drain region (92A.i) epitaxially grown from the first nanostructure (54A) and a second source / drain region (92A.ii) epitaxially grown from the second nanostructure (54A) grow together, and wherein a third source / drain region (92B.i) epitaxially grown from the third nanostructure (54B) is isolated from the first source / drain region (92A.i) after the epitaxial growth of the source / drain regions (92). [7] The method of claim 6, wherein longitudinal axes of the first plurality of nanostructures (52) and longitudinal axes of the second plurality of nanostructures (54) extend parallel to a first direction, and wherein the first plurality of nanostructures (52) and the second plurality of nanostructures (54) form a first stack and a second stack spaced apart from the first stack in the first direction after patterning the multilayer stack (64). [8] The method of claim 7, wherein after patterning the multilayer stack (64), the first plurality of nanostructures (52) and the second plurality of nanostructures (54) further form a third stack separated from the first stack and the second stack in a second direction perpendicular to the first direction, wherein a first end face of the third stack lies between opposite end faces of the first stack in the first direction, and wherein a second end face of the third stack, opposite the first end face, lies between opposite end faces of the second stack in the first direction. [9] Method according to one of the preceding claims 6 to 8, further comprising: Removing the first plurality of nanostructures (52) and the gate structure (71, 76) to form a second recess (98); and Forming a replacement gate structure (102) in the second recess. [10] The method of claim 9, further comprising: Patterning the replacement gate structure to form a third recess (104) separating a first replacement gate structure from a second replacement gate structure; and Forming a dielectric material (106) in the third recess (104). [11] The method of any one of the preceding claims 6 to 10, further comprising forming a dielectric material (96) between the first source / drain region (92A.i) and the third source / drain region (92B.i), the dielectric material (96) isolating the first source / drain region (92A.i) from the third source / drain region (92B.i).

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